500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Search Stock

Shift+Click on the column header for multi-column sorting 
Part
Manufacturer
Supplier
Stock
Best Price
Price Each
Ordering
Part : HFE7-3-1HDS-L2 Supplier : Hongfa Electroacoustic Manufacturer : Future Electronics Stock : - Best Price : $2.74 Price Each : $3.29
Part : JE8-3-1HDS-L2 Supplier : Hongfa Electroacoustic Manufacturer : Chip One Exchange Stock : 49 Best Price : - Price Each : -
Shipping cost not included. Currency conversions are estimated. 

HDSL2 Datasheet

Part Manufacturer Description PDF Type
HDSL2 DT Magnetics International Transformer Approved for use with ADIs AD930 Chipset Original
HDSL2 Intel HDSL2 Modem Chip Set Original
HDSL2 Pulse Engineering LINE TRANSFORMER For Use with GlobeSpan Chipset Original

HDSL2

Catalog Datasheet MFG & Type PDF Document Tags

fireberd 6000a manual

Abstract: ttc fireberd 6000A reference manual for E1. The MCLK source is selected through the HDSL2 software. The HDSL2-T1 Evaluation system is , TTC Fireberd 6000A for HDSL2-Framed mode using the digital interface. Power supply and COM port , HDSL2 Evaluation System for T1 Applications - LXDHDSL2-T1 Developer Manual January 2001 As of January 15, 2001, this document replaces the Level One document known as HDSL2 Evaluation System , respective owners. HDSL2 Evaluation System for T1 Applications - LXDHDSL2-T1 Developer Manual
Intel
Original
fireberd 6000a manual ttc fireberd 6000A reference manual rj11 to db9 rj11 to db25 fireberd zener DB3 C209 CON10A CON10C CON10B CSB25

sk70743

Abstract: HDSL2 combine POTS and HDSL2? HDSL2's PSD, known as OPTIS, is designed around T1 transport applications. As , is growing at 20-30% per year ­ so we will continue to see business in HDSL2. 6 Frequently , used for HDSL2? The framing structure is currently based on ANSI contribution T1E1.418-2000. Q13 , HDSL2 Frequently Asked Questions January 2001 Order Number: 249381-001 As of January 15, 2001, this document replaces the Level One document known as HDSL2 - FAQ. Information in this document is
Intel
Original
sk70743 SK70742 adsl psd mask SK70740 SK70741 SK70744

PAM16

Abstract: Metalink MtH2405 SDSL2/HDSL2 Dual Transceiver (Product Brief) Advanced Multi-Mode DSLTM Integration Key Features : Dual SDSL2/HDSL2 Transceiver Metalink's MtH2405 Chipset Solution implements a low power Dual SDSL2/HDSL2 transceiver. Each transceiver implements PAM 4, 8, 16 line codes with trellis coded , power consumption and a small real estate. Superior Performance The Metalink Dual SDSL2/HDSL2 , Voice and Data With a minimal transmission delay of less than 0.5 msec., Metalink's SDSL2/HDSL2 Dual
MetaLink
Original
PAM16 Metalink PAM-16 MTH2405 SDSL AFE H2405 H2446 H2435

PAM16

Abstract: PAM-16 product brief Intel SK70740, SK70741, SK70742 ® HDSL2 Data Pump and Framer Chip Set Product Overview Intel Internet Exchange Architecture ® Intel® has developed an HDSL2 data pump and , three-chip solution supports the ANSI HDSL2 standard and is capable of delivering 10 -7 BER performance in , HDSL2 modulation scheme. The power spectral density (PSD) of the transmit signal conforms to the OPTIS template, which ensures that HDSL2 does not interfere with preexisting services such as T1, ISDN, HDSL
Intel
Original
INTEL CLOCK AND DATA RECOVERY USA/0101/1K/ASI/DC

DSX Access Systems

Abstract: The result is HDSL2. HDSL2 is the acronym for High-bit-rate (high-speed) Digital Subscriber Line, generation 2. In a nutshell, HDSL2 provides the same performance as its predecessor HDSL, but on a single , coding are not supported by any standard and fall short of HDSL2's 12,000 feet of reach. The Intel , application brief HDSL2 High-speed Digital Subscriber Line, generation 2 Product Description , delivery. The new technology requirements were to: The performance expectations for HDSL2 presented
Intel
Original
DSX Access Systems
Abstract: T1 over HDSL2_4.qxd 8/3/00 12:58 PM Page 1 T1 over HDSL2 The future of Digital Subscriber Line technology T1 over HDSL2_4.qxd 8/3/00 12:58 PM Page 2 T1 over HDSL2: The , over HDSL2_4.qxd 8/3/00 12:58 PM Page 3 T1 over HDSL2: The future of Digital Subscriber , , connecting to the CSU used to terminate the T1. 3 T1 over HDSL2_4.qxd 8/3/00 12:58 PM Page 4 , regular T1 interface. A typical HDSL T1 over HDSL2_4.qxd 8/3/00 12:58 PM Page 5 T1 over -
Original
0700/OC/AO/SK/PP/2 NP1745

4148NX

Abstract: SK70741 DATA SHEET MARCH 2000 Revision 2.3 SK70742 HDSL2 FEC/Framer General Description Features Level One's HDSL2 chip set provides synchronous fullduplex transmission over a single twisted pair. The SK70742 combines the functions of HDSL2 Frame Mapping and Forward Error Correction (FEC) in , · · · Meets requirements for ANSI T1E1.418 · HDSL2 Frame Correction Mapping and , 5 Volt tolerant input pins · Data buffering and rate adaption between the T1 and HDSL2 line rate
Intel
Original
4148NX 500E 80C51 SK70742QE EOC17 Viterbi Decoder SK70742-R2

intel batch MARKING

Abstract: intel i960 batch MARKING HDSL2 Product Family Specification Update September 2001 The HDSL2 products may contain design , changes to them. The HDSL2 products may contain design defects or errors known as errata which may cause , Specification Update HDSL2 Product Family Contents Contents Revision History , . 14 HDSL2 Product Family Specification Update 3 Revision History Revision History , . Specification Update HDSL2 Product Family Preface Preface This document is an update to the
Intel
Original
intel batch MARKING intel i960 batch MARKING intel DOC SK70740HE SK70741HE SK70744HE SK70740/41/42

pam modulator demodulator circuit

Abstract: HDSL2 product brief Intel SK70740/SK70744 HDSL2 Modem Chip Set ® Product Overview The Intel® SK70740/SK70744 chip set is an ANSI HDSL2 modem that provides symmetric full-duplex, T1 transmission , Interlocking Spectrum (OPTIS) power spectral density (PSD). This HDSL2 modem solution consists of two chips , within the HDSL2 frame. A synchronous TDM interface allows the chip set to be used with common T1 , CS JTAS D/A WR, DS REGISTERS PAM PROCESSOR ALE, A RSER DESCRAMBLER HDSL2
Intel
Original
pam modulator demodulator circuit Trellis regenerator USA/0101/7K/ASI/DC

D link schematic circuit diagram adsl modem board

Abstract: tms 3874 provides frame mapping, transceiver, and line interface functions for single pair HDSL2. The SK70740/44 , SK70740/44 HDSL2 Modem Chip Set Datasheet The SK70740 and SK70744 chip set provide full-duplex , consists of two ICs that provide the HDSL2 modem solution: s SK70740HE - Analog Front End (AFE) s , Coded PAM modulator/demodulator. HDSL2 utilizes shaped PAM-16 modulation to minimize interference into , other services. The frame mapping function inserts and recovers the HDSL2 overhead. Interrupt alarms
Intel
Original
D link schematic circuit diagram adsl modem board tms 3874 schematic circuit diagram adsl modem board water level control block diagram fec 34 afe 1000 MO-112

smd ND

Abstract: TH101 51264R 50517R Appl i cati on Orio n IDSL Analo g fro nt e nd Analo g fro nt e nd HDSL2 HDSL2 MDSL MDSL IDSL HDSL2 HDSL2 IDSL-M2B1Q MSDL-HMS g . SHDSL Turns Rati on PRI :SEC 5. 4: 1 2: 1 2: 1 2: 1 2. 2: 1
Midcom
Original
smd ND TH101 IEC950 50711R 50864R 51081R 51074R 51128R

PAIRGAIN

Abstract: HDSL2 of the various services was compared when disturbed by either HDSL or HDSL2. Table 2 shows the , HDSL2 Overcomes the Impairments of the Local Loop White Paper January 2001 Order Number: 249346-001 As of January 15, 2001, this document replaces the Level One document HDSL2 Overcomes the , whatsoever for conflicts or incompatibilities arising from future changes to them. The HDSL2 may contain , owners. White Paper HDSL2 Overcomes the Impairments of the Local Loop Contents 1.0
Intel
Original
PAIRGAIN Adtran T1.413 ADSL standard T1E1 trellis 5/6 decoder trellis code modulation 5/6 decoder scheme HDSL 120

automatic water level controller circuit diagram

Abstract: water level controller circuit diagram SK70742 HDSL2 FEC/Framer Datasheet Intel's HDSL2 chip set provides full-duplex transmission over a single twisted pair. The SK70742 combines the functions of HDSL2 Frame Mapping and Forward , ANSI T1E1.418 HDSL2 Frame Mapping and Forward Error Correction Operates from a single 3.3 V supply 5 Volt tolerant input pins Data buffering and rate adaption between the T1 and HDSL2 line rate , January 15, 2001, this document replaces the Level One document SK70742 - HDSL2 FEC/Framer. Order
Intel
Original
automatic water level controller circuit diagram water level controller circuit diagram water level control circuit diagram water level indicator using microcontroller WATER LEVEL CONTROLLER Xm-19

hdsl modem chipset

Abstract: SK70740 product brief Intel SK70740/SK70744 HDSL2 Modem Chipset ® Product Description The Intel® SK70740/SK70744 chipset is an ANSI HDSL2 modem that provides symmetric full-duplex, T1 transmission over , Interlocking Spectrum (OPTIS) power spectral density (PSD). This HDSL2 modem solution consists of two chips: s The core of the transceiver/framer is a Trellis Coded PAM modulator/demodulator. HDSL2 , access devices s Wireless access systems SK70744 TFSYNC TCLK TSER HDSL2 TX FRAMER
Intel
Original
hdsl modem chipset USA/0301/1K/ASI/DC

gs2237-208-001p

Abstract: GS3137-08T UTOPIA Level 2 or single-channel ATM over UTOPIA Level 1 is supported for SHDSL, SDSL 2B1Q, and HDSL2. , ) G2237-208-041PT B2 (SHDSL/HDSL2) G2237-208-041PT C1 (SHDSL/HDSL2) XDSL2TM SDSL, HDSL2, or SHDSL - , including SDSL, HDSL2, and SHDSL, using population options for optimization. · · Data Sheet The , T1.418 for HDSL2 and ITU-T G.991.2 for SHDSL Reference design compatible with Bellcore GR-1089, IEC , SDSL, HDSL2, and SHDSL - ILD2 Data Sheet Introduction The GlobespanVirata DSL chip sets support
GlobespanVirata
Original
GS3137-08T gs2237-208-001p gs3137 gs2237 SHDSL gs3137 GS2237-208 G2216-208-041PF G2214-208-041DF 208-001P GS2237-208-001P GS2216-208-001P

g991

Abstract: HDSL2 DSL Access Modem using the Aluminum Digitally Tuned Analog Front End HDSL2/G.shdsl/2B1Q SDSL , the PAM transceiver, HDSL2 framer, and 512 state Trellis encoder and decoder with a high performance , . Aluminum is optimized for the ANSI HDSL2 standard for T1 transport. It can also be used for testing and , is used for T1 transport in HDSL2 mode. Aluminum also supports 2B1Q SDSL. The Power Spectral , DSL Access Multiplexers (DSLAMs) s T1 HDSL2 CSU/DSUs Ordering Information s T1 HDSL2
Virata
Original
g991 bd3800 ECHO line canceller IC phone VIRATA VC7220 P0800V1 17F-2

DSL Line TRANSFORMER and Hybrid

Abstract: transformer interface with 8051 Multi-Mode Transceiver M28976 Two Full-Rate T1/E1 Payloads Over a Single G.shdsl/HDSL2/SDSL Link , operation and guaranteed interoperability with legacy software control. systems including HDSL2, SDSL , and software handle the extended tion. In addition, it complies with the ANSI HDSL2 standard , and HDSL2 supports data rates from 192 Kbps to 4.6 Mbps, and requires only frame formats and EOC , for high density and manufacturability ­ HDSL2 (ANSI T1.418) ­ SDSL/2B1Q (AutoBaud) ­ Option A
Mindspeed Technologies
Original
DSL Line TRANSFORMER and Hybrid transformer interface with 8051 TR-28 M28975

RJ48 pin out

Abstract: SK70742 HDSL2 - System Design and Chip Set Overview Application Note January 2001 Order Number , and names are the property of their respective owners. Application Note HDSL2 - System Design , .12 1 2 3 4 5 6 7 8 9 10 11 12 HDSL2 Block Diagram , Tables Application Note 3 HDSL2 - System Design and Chip Set Overview 1.0 General Description Intel's HDSL2 chip set provides synchronous, full duplex transmission over a single twisted pair
Intel
Original
AN110 RJ48 pin out 741i 48c60 AD8016 AD8016ARB

TC-PAM

Abstract: Modulation TC-PAM LXT776 also includes an integrated line driver that supports G.SHDSL, ETSI SDSL, and HDSL2 standards , Error Correction G.SHDSL: International Symmetric High-speed DSL standard (developed by ITU) HDSL2 , supports G.SHDSL, ETSI SDSL, and HDSL2 digital subscriber line applications, and data rates from 192Kbps , HDSL2 REMOTE TERMINAL T1 SERVICE DSX-1 Figure 3: HDSL ACCESS BAY INTEROFFICE NETWORK DSX-1 HDSL2 ACCESS BAY HDSL SPAN LEVEL ONE PARTS = HDSL2 DATA PUMP = T1 TRANSCEIVER (LIU
Intel
Original
TC-PAM Modulation TC-PAM tcpam encoder G.SHDSL LOOP modems G.SHDSL PAM time division multiplexing PB-1013 USA/0600/7K/ASI/CR

Campus Italia Vol 1

Abstract: ZipWire2 . . . . . . . . . . . . . . . . . . . . . . . 14-3 HDSL2-Single Pair . . . . . . . . . . . . . . . , parametric information contains target parameters that are subject to change. CN8980 ZipWire2 HDSL2/SDSL , for HDSL2 T1 transport and meets all the current requirements of the emerging ETSI standards for SDSL , OPTIS-based HDSL2 through software modifications. The ZipWire2 device has a two- or three-chip architecture , almost any frame format. In particular, it supports the ANSI HDSL2 and ETSI HDSL1 frame formats. It
Conexant Systems
Original
Campus Italia Vol 1 ZipWire2 071 0039 adc interfacing with 8051 asm code satellite l300 P2A13 RS8973/8953B

AFE1230

Abstract: AFE1230E q q q q q E1, T1, AND SUBRATE OPERATION COMPLIES WITH G.SHDSL AND HDSL2 16-BIT, DELTA-SIGMA , and cost of G.SHDSL and HDSL2 application designs. It provides a transceiver as the line interface , power into a 135 line for HDSL2 operation. With an appropriate DSP, the transmitted Power Spectral Density (PSD) complies with either the G.SHDSL standard or with the HDSL2 standard (via an OPA2677 used , HDSL2 operation) and an operation temperature range of ­40°C to +85°C. Programmable SC LPF
Texas Instruments
Original
AFE1230 SSOP-28 AFE1230E SBWS015A

circuit diagram of PAM transmitter and receiver

Abstract: motorola 68000 microprocessor datasheet SK70741 HDSL2 PAM Transceiver Datasheet Intel's HDSL2 chip set provides full-duplex transmission over a single twisted pair. The SK70741 is the heart of the HDSL2 chip set and supports the ANSI T1E1.418 HDSL2 standard for T1 transport. PAM-16 modulation is used to achieve this rate over standard , crosstalk and interference to other systems. This allows HDSL2 to coexist with other transport technologies , - HDSL2 PAM Transceiver. Order Number: 249238-001 January 2001 Information in this document
Intel
Original
circuit diagram of PAM transmitter and receiver motorola 68000 microprocessor datasheet motorola 68000 intel 68000 INSTRUCTION SET
Showing first 20 results.