HD66717 HD66717A03TA0 TCP-153 HD66717A03TA1L TCP-149 HD66717A03TA2L HCD66717A03 - Datasheet Archive

 

(Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver) Description The HD66717 dot-matrix liquid crystal display

 

HD66717 HD66717 (Low-Power Dot-Matrix Liquid Crystal Display Controller/Driver) Description The HD66717 HD66717 dot-matrix liquid crystal display controller and driver LSI displays alphanumerics, katakana, hiragana, and symbols. It can be configured to drive a dot-matrix liquid crystal display under the control of an I2C bus, a clock-synchronized serial, or a 4- or 8-bit microprocessor. A single HD66717 HD66717 is capable of displaying a maximum of four 12-character lines, 40 segments, and 10 annunciators. The HD66717 HD66717 incorporates all the functions required for driving a dot-matrix liquid crystal display such as display RAM, character generator, and liquid crystal drivers, and a booster for LCD power supply. The HD66717 HD66717 provides various functions to reduce the power consumption of an LCD system such as lowvoltage operation of 2.4V or less, a booster for generating a maximum of triple LCD drive voltage from the supplied voltage, and voltage-followers for decreasing the direct current flow in the LCD drive bleederresistors. Combining these hardware functions with software functions such as standby and sleep modes allows a fine power control. The HD66717 HD66717, with the above functions, is suitable for any portable batterydriven product requiring long-term driving capabilities and small size. Features · 5 × 8-dot matrix LCD drive · Four 12-character lines, 40 segments, and 10 annunciators · Low-power operation support: 2.4 to 5.5V (low voltage) Double or triple booster for liquid crystal drive voltage Electron volume function and voltage-followers for decreasing the direct current flow in the LCD drive bleeder-resistors Standby mode and sleep mode Displays up to 10 static annunciators · I2C bus or clock-synchronized serial interface; 4- or 8-bit parallel bus interface · 60 × 8-bit display data RAM (60 characters max) · 9,600-bit character generator ROM 240 characters (5 × 8 dots) 1 HD66717 HD66717 · 32 × 5-bit character generator RAM 4 characters (5 × 8 dots) · 8 × 5-bit segment RAM 40 segment-icons and marks max · 60-segment × 34-common liquid crystal display driver · Programmable display sizes and duty ratios (see List1) · Vertical smooth scroll · Double-height display · Wide range of instruction functions: Display clear, display on/off, icon and mark control, character blink, white-black inverting blinking cursor, icon and mark blink, cursor home, cursor on/off, white-black inverting raster-row · Hardware reset · Internal oscillation with an external resistor · Wide range of LCD drive voltages 3.0V to 13.0V · Slim chip with/without bump (for COB) and tape carrier package (TCP) List 1 Programmable Display Sizes and Duty Ratios Display Size Duty Ratio Oscillation Frequency Current Consumption Multi-plexed-Drive Segments Static-Drive Annunciators 1 line × 12 characters 1/10 40 kHz 8 µA 40 10 2 lines × 12 characters 1/18 80 kHz 15 µA 40 10 3 lines × 12 characters 1/26 120 kHz 23 µA 40 10 4 lines × 12 characters 1/34 160 kHz 30 µA 40 10 Note: Current consumption excludes that for LCD power supply source; V CC = 3V. 2 HD66717 HD66717 Ordering Information Type Name External Dimension Special spec. Internal Font HD66717A03TA0 HD66717A03TA0 TCP-153 TCP-153 HD66717A03TA1L HD66717A03TA1L TCP-149 TCP-149 1/4 bias driving HD66717A03TA2L HD66717A03TA2L TCP-149 TCP-149 1/6 bias driving HCD66717A03 HCD66717A03 Bare chip HCD66717A03BP HCD66717A03BP Au-bumped chip HD66717LA03TA0 HD66717LA03TA0 TCP-153 TCP-153 Built-in Low power opamp. HCD66717LA03 HCD66717LA03 Bare chip Built-in Low power opamp. HCD66717LA03BP HCD66717LA03BP Au-bumped chip Built-in Low power opamp. HD66717A13TA0L HD66717A13TA0L TCP-153 TCP-153 HCD66717A13BP HCD66717A13BP Au-bumped chip HCD66717LA13BP HCD66717LA13BP Au-bumped chip HD66717A02TA0L HD66717A02TA0L TCP-153 TCP-153 European font HCD66717A02 HCD66717A02 Bare chip (ROM code : A02) HCD66717A02BP HCD66717A02BP Au-bumped chip HD66717A12TA0L HD66717A12TA0L TCP-153 TCP-153 HCD66717A12BP HCD66717A12BP Au-bumped chip Japanese and European fonts Up-side-down pattern of A03 Built-in Low power opamp. Up-side-down pattern of A02 3 HD66717 HD66717 LCD-II Family Comparison Item Power supply voltage LCD-II (HD44780U HD44780U) 2.7V to 5.5V Liquid crystal drive voltage Maximum display characters per chip 3.0 to 11.0V HD66702R HD66702R 5V ± 10% (standard) 2.7V to 5.5V (low voltage) 3.0V to 8.3V 8 characters × 2 lines 20 characters × 2 lines Segment display Display duty ratio None 1/8, 1/11, and 1/16 9,920 bits (208 5-×-8 dot characters and 32 5-×-10 dot characters) 64 bytes 80 bytes None 40 16 A None 1/8, 1/11, and 1/16 7,200 bits (160 5-×-7 dot characters and 32 5-×-10 dot characters) 64 bytes 80 bytes None 100 16 B External resistor or external clock 270 kHz ± 30% None External resistor or external clock 320 kHz ± 30% None None None External resistor or external clock 270 kHz ± 30% Double or triple booster circuit None External External External External None None None None None Independent control signal None Independent control signal None Independent control signal Internal reset circuit Impossible Internal reset circuit Impossible None Used in common with a driver output pin Internal reset circuit Dot unit Impossible 1 or 2 None 4 or 8 bits 80-pin QFP1420 QFP1420 80-pin TQFP1414 TQFP1414 80-pin bare chip Impossible 1 or 2 None 4 or 8 bits 144-pin FQFP2020 FQFP2020 144-pin bare chip CGROM CGRAM DDRAM SEGRAM Segment signals Common signals Liquid crystal drive waveform Clock source Rf oscillation frequency Liquid crystal voltage booster circuit Liquid crystal drive operational amplifier Bleeder-resistor for liquid crystal drive Liquid crystal contrast adjuster Key scan circuit Extension driver control signal Reset function Horizontal smooth scroll Vertical smooth scroll Number of displayed lines Low power control Bus interface Package 4 HD66710 HD66710 2.7V to 5.5V HD66712U HD66712U 2.7V to 5.5V 3.0 to 13.0V 2.7 to 11.0V 16 characters × 2 lines/ 8 characters × 4 lines 40 1/17 and 1/33 24 characters × 2 lines/ 12 characters × 4 lines 60 (extended to 80) 1/17 and 1/33 9,600 bits (240 5-×-8 dot characters) 9,600 bits (240 5-×-8 dot characters) 64 bytes 80 bytes 8 bytes 40 33 B 64 bytes 80 bytes 16 bytes 60 34 B External resistor or external clock 270 kHz ± 30% Double or triple booster circuit None Impossible 1, 2, or 4 Low power mode 4 or 8 bits 100-pin QFP1420 QFP1420 100-pin TQFP1414 TQFP1414 100-pin bare chip Internal reset circuit or reset input Dot unit and line unit Impossible 1, 2, or 4 Low power mode Serial, 4, or 8 bits 128-pin TCP 128-pin bare chip HD66717 HD66717 LCD-II Family Comparison (cont) Item Power supply voltage Liquid crystal drive voltage Maximum display characters per chip Segment display Display duty ratio CGROM CGRAM DDRAM SEGRAM Segment signals Common signals Liquid crystal drive waveform Clock source Rf oscillation frequency Liquid crystal voltage booster circuit Liquid crystal drive operational amplifier Bleeder-resistor for liquid crystal drive Liquid crystal contrast adjuster Key scan circuit Extension driver control signal Reset function HD66720 HD66720 2.7V to 5.5V 3.0 to 11.0V HD66717 HD66717 2.4V to 5.5V 3.0 to 13.0V HD66727 HD66727 2.4V to 5.5V 3.0 to 13.0V 10 characters × 1 line/ 8 characters × 2 lines 42 (extended to 80) 1/9 and 1/17 9,600 bits (240 5-×-8 dot characters) 64 bytes 40 bytes 16 bytes 42 17 B 12 characters × 1 line/2 lines/3 lines/4 lines 12 characters × 1 line/2 lines/3 lines/4 lines 40 (and 10 annunciators) 1/10, 1/18, 1/26, and 1/34 9,600 bits (240 5-×-8 dot characters) 32 bytes 60 bytes 8 bytes 60 34 B 40 (and 12 annunciators) 1/10, 1/18, 1/26, and 1/34 11,520 bits (240 6-×-8 dot characters) 32 bytes 60 bytes 8 bytes 60 34 B External resistor or external clock 160 kHz ± 30% External resistor or external clock 1-line mode: 40 kHz ± 30% 2-line mode: 80 kHz ± 30% 3-line mode: 120 kHz ± 30% 4-line mode: 160 kHz ± 30% Double or triple booster circuit Built-in for each V1 to V5 External resistor or external clock 1-line mode: 40 kHz ± 30% 2-line mode: 80 kHz ± 30% 3-line mode: 120 kHz ± 30% 4-line mode: 160 kHz ± 30% Double or triple booster circuit Built-in for each V1 to V5 Internal 1/4 and 1/6 bias resistors Incorporated Internal 1/4 and 1/6 bias resistors Incorporated None None 4 × 8 = 32 keys None Reset input Reset input Impossible Impossible Dot (raster-row) unit 1, 2, 3, or 4 Standby mode and sleep mode I2C, serial, 4, or 8 bits Slim chip with/without bumps TCP Dot (raster-row) unit 1, 2, 3, or 4 Standby mode and sleep mode I2C or clock-synchronized serial Slim chip with/without bumps TCP Double or triple booster circuit None External None 5 × 6 = 30 keys Independent control signal Internal reset circuit or reset input Horizontal smooth scroll Dot unit and line unit Vertical smooth scroll Impossible Number of displayed lines 1 or 2 Low power control Low power mode and sleep mode Bus interface Serial Package 100-pin QFP1420 QFP1420 100-pin TQFP1414 TQFP1414 100-pin bare chip 5 HD66717 HD66717 HD66717 HD66717 Block Diagram OSC1 SFT OSC2 EXM AGND CPG Timing generator RESET* ASEG1­ ASEG10 ASEG10 TEST Instruction register (IR) Instruction decoder Annunciator driver 7 COM1­ COM32 COM32 Display data RAM (DDRAM) 60 × 8 bits 8 IM1/0 ACOM 34-bit Common signal shift register driver Address counter COMS1/2 7 RS/CS* E/SCL RW/SDA System interface · I 2C bus · Clocksynchronized serial · 4 bits · 8 bits 7 8 DB7­DB6 DB5/ID5 ­DB0/ID0 Input/ output buffer 8 Data register (DR) 60-bit shift register 8 5 5 Segment RAM (SEGRAM) 8 bytes Character generator RAM (CGRAM ) 32 bytes Character generator ROM (CGROM) 9,600 bits 7 LCD drive voltage selector Cursor and blink controller Vci C1 C2 V5OUT2 5 5 Booster V5OUT3 Parallel/serial converter VCC GND +­ R OPOFF 6 +­ R V1OUT +­ 2R V2 SEG1­ Segment SEG60 SEG60 signal driver 8 3 Busy flag 60-bit latch circuit V2OUT V3 + ­ +­ R V3OUT R V4OUT VR V5OUT VEE HD66717 HD66717 HD66717 HD66717 Pin Arrangement COM17 COM17 COM18 COM18 COM19 COM19 COM20 COM20 COM21 COM21 COM22 COM22 COM23 COM23 COM24 COM24 COM25 COM25 COM26 COM26 COM27 COM27 COM28 COM28 COM29 COM29 COM30 COM30 COM31 COM31 COM32 COM32 COMS1 Dummy Dummy Dummy Dummy VCC VCC V1OUT V2OUT V3OUT V4OUT V5OUT VREFP VREF VREFM V2 V3 VEE VEE V5OUT3 V5OUT3 V5OUT2 V5OUT2 C1 C1 C2 C2 Vci Vci GND GND Dummy VCC VCC VCC OSC2 OSC1 EXM SFT IM1 IM0 OPOFF TEST RESET* RS/CS* E/SCL RW/SDA HD66717 HD66717 (Top View) Y X DB0/ID0 DB1/ID1 DB2/ID2 DB3/ID3 DB4/ID4 DB5/ID5 DB6 DB7 GND GND GND GND GND GND VCC VCC AGND AGND Dummy Dummy Dummy Dummy Dummy Dummy SEG60 SEG60 SEG59 SEG59 SEG58 SEG58 SEG57 SEG57 SEG56 SEG56 SEG55 SEG55 SEG54 SEG54 SEG53 SEG53 SEG52 SEG52 SEG51 SEG51 SEG50 SEG50 SEG49 SEG49 SEG48 SEG48 SEG47 SEG47 SEG46 SEG46 SEG45 SEG45 SEG44 SEG44 SEG43 SEG43 SEG42 SEG42 SEG41 SEG41 SEG40 SEG40 SEG39 SEG39 SEG38 SEG38 SEG37 SEG37 SEG36 SEG36 SEG35 SEG35 SEG34 SEG34 SEG33 SEG33 SEG32 SEG32 SEG31 SEG31 SEG30 SEG30 SEG29 SEG29 SEG28 SEG28 SEG27 SEG27 SEG26 SEG26 SEG25 SEG25 SEG24 SEG24 SEG23 SEG23 SEG22 SEG22 SEG21 SEG21 SEG20 SEG20 SEG19 SEG19 SEG18 SEG18 SEG17 SEG17 SEG16 SEG16 SEG15 SEG15 SEG14 SEG14 SEG13 SEG13 SEG12 SEG12 SEG11 SEG11 SEG10 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 ASEG10 ASEG10 ASEG9 ASEG8 ASEG7 ASEG6 ASEG5 ASEG4 ASEG3 ASEG2 ASEG1 ACOM1 Dummy Dummy Dummy Dummy Dummy COMS2 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM10 COM11 COM11 COM12 COM12 COM13 COM13 COM14 COM14 COM15 COM15 COM16 COM16 7 No. - - - - 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 - 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pad Name Dummy Dummy Dummy Dummy VCC VCC V1OUT V2OUT V3OUT V4OUT V5OUT VREFP VREF VREM V2 V3 VEE VEE V5OUT3 V5OUT3 V5OUT2 V5OUT2 C1 C1 C2 C2 Vci Vci GND GND Dummy VCC VCC VCC OSC2 OSC1 EXM SFT IM1 IM0 OPOFF TEST RESET* RS/CS* E/SCL X ­5191 ­4891 ­4767 ­4643 ­4439 ­4315 ­4034 ­3913 ­3793 ­3672 ­3552 ­3432 ­3311 ­3191 ­3045 ­2924 ­2803 ­2683 ­2526 ­2406 ­2225 ­2105 ­1955 ­1834 ­1683 ­1562 ­1411 ­1290 ­1139 ­1018 ­898 ­777 ­656 ­536 ­391 ­183 21 225 429 633 837 1041 1245 1449 1653 Y ­1260 ­1260 ­1260 ­1260 ­1244 ­1244 ­1169 ­1169 ­1169 ­1169 ­1169 ­1169 ­1169 ­1169 ­1168 ­1168 ­1168 ­1168 ­1168 ­1168 ­1168 ­1168 ­1168 ­1168 ­1168 ­1168 ­1168 ­1168 ­1168 ­1168 ­1168 ­1168 ­1168 ­1168 ­1192 ­1192 ­1192 ­1192 ­1192 ­1192 ­1192 ­1192 ­1192 ­1192 ­1192 No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 - 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 - - - - - 77 78 79 Pad Name RW/SDA DB0/ID0 DB1/ID1 DB2/ID2 DB3/ID3 DB4/ID4 DB5/ID5 DB6 DB7 GND GND GND GND GND GND VCC VCC AGND AGND Dummy COM16 COM16 COM15 COM15 COM14 COM14 COM13 COM13 COM12 COM12 COM11 COM11 COM10 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COMS2 Dummy Dummy Dummy Dummy Dummy ACOM ASEG1 ASEG2 X 1861 2073 2290 2507 2723 2940 3157 3374 3590 3809 3930 4079 4200 4349 4474 4627 4752 4905 5029 5191 5191 5191 5191 5191 5191 5191 5191 5191 5191 5191 5191 5191 5191 5191 5191 5191 5191 5191 4939 4815 4690 4566 4442 4317 4193 Y ­1192 ­1192 ­1192 ­1192 ­1192 ­1192 ­1192 ­1192 ­1192 ­1201 ­1201 ­1201 ­1201 ­1201 ­1201 ­1201 ­1201 ­1201 ­1201 ­1201 ­1020 ­896 ­772 ­647 ­523 ­398 ­274 ­149 ­25 100 224 348 473 597 722 846 971 1191 1191 1191 1191 1191 1191 1191 1191 No. Pad Name 80 ASEG3 81 ASEG4 82 ASEG5 83 ASEG6 84 ASEG7 85 ASEG8 86 ASEG9 87 ASEG10 ASEG10 88 SEG1 89 SEG2 90 SEG3 91 SEG4 92 SEG5 93 SEG6 94 SEG7 95 SEG8 96 SEG9 97 SEG10 SEG10 98 SEG11 SEG11 99 SEG12 SEG12 100 SEG13 SEG13 101 SEG14 SEG14 102 SEG15 SEG15 103 SEG16 SEG16 104 SEG17 SEG17 105 SEG18 SEG18 106 SEG19 SEG19 107 SEG20 SEG20 108 SEG21 SEG21 109 SEG22 SEG22 110 SEG23 SEG23 111 SEG24 SEG24 112 SEG25 SEG25 113 SEG26 SEG26 114 SEG27 SEG27 115 SEG28 SEG28 116 SEG29 SEG29 117 SEG30 SEG30 118 SEG31 SEG31 119 SEG32 SEG32 120 SEG33 SEG33 121 SEG34 SEG34 122 SEG35 SEG35 123 SEG36 SEG36 124 SEG37 SEG37 X 4068 3944 3819 3695 3571 3446 3322 3197 2948 2824 2699 2575 2451 2326 2202 2077 1953 1828 1704 1579 1455 1331 1206 1082 957 833 708 584 460 335 211 86 ­38 ­163 ­287 ­412 ­536 ­660 ­785 ­909 ­1034 ­1158 ­1283 ­1407 ­1532 Y 1191 1191 1191 1191 1191 1191 1191 1191 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 1196 No. Pad Name 125 SEG38 SEG38 126 SEG39 SEG39 127 SEG40 SEG40 128 SEG41 SEG41 129 SEG42 SEG42 130 SEG43 SEG43 131 SEG44 SEG44 132 SEG45 SEG45 133 SEG46 SEG46 134 SEG47 SEG47 135 SEG48 SEG48 136 SEG49 SEG49 137 SEG50 SEG50 138 SEG51 SEG51 139 SEG52 SEG52 140 SEG53 SEG53 141 SEG54 SEG54 142 SEG55 SEG55 143 SEG56 SEG56 144 SEG57 SEG57 145 SEG58 SEG58 146 SEG59 SEG59 147 SEG60 SEG60 - Dummy - Dummy - Dummy - Dummy - Dummy 148 COM17 COM17 149 COM18 COM18 150 COM19 COM19 151 COM20 COM20 152 COM21 COM21 153 COM22 COM22 154 COM23 COM23 155 COM24 COM24 156 COM25 COM25 157 COM26 COM26 158 COM27 COM27 159 COM28 COM28 160 COM29 COM29 161 COM30 COM30 162 COM31 COM31 163 COM32 COM32 164 COMS1 X Y ­1656 1196 ­1780 1196 ­1905 1196 ­2029 1196 ­2154 1196 ­2278 1196 ­2403 1196 ­2527 1196 ­2651 1196 ­2776 1196 ­2900 1196 ­3025 1196 ­3149 1196 ­3274 1196 ­3398 1196 ­3523 1196 ­3647 1196 ­3771 1196 ­3896 1196 ­4020 1196 ­4145 1196 ­4269 1196 ­4394 1196 ­4518 1196 ­4643 1196 ­4767 1196 ­4891 1196 ­5191 1196 970 ­5191 845 ­5191 721 ­5191 596 ­5191 472 ­5191 348 ­5191 223 ­5191 99 ­5191 ­26 ­5191 ­5191 ­150 ­5191 ­275 ­5191 ­399 ­5191 ­524 ­5191 ­648 ­5191 ­772 ­5191 ­897 ­5191 ­1021 Die Specification Chip size : 10.88 × 2.89mm2 Coordinate : Pad center Origin : Chip center Bump size : 70 × 70 µm2 Pad size : 90 × 90 µm2 Target Information Target shape : Cross ("+") Target center coordinate : X = ­5110, Y = ­1206 X = +5115, Y = ­1206 X = ­5110, Y = +1206 X = +5115, Y = 1206 Target AL length : 26 µm Target AL width : 8 µm HD66717 HD66717 8 HD66717 HD66717 Pad Coordinate HD66717 HD66717 TCP Dimensions (TA0) 0.50P × (44­1) = 21.50mm HD66717 HD66717 I/O, Power supply 0.50mm pitch Dummy Dummy COMS1 COM32 COM32 COM17 COM17 SEG60 SEG60 0.22 mm pitch LCD Driver Outputs 0.22P × (109­1) = 23.76 mm SEG1 ASEG10 ASEG10 HITACHI NC VCC V1OUT V2OUT V3OUT V4OUT V5OUT VREFP VREF VREFM V2 V3 VEE V5OUT3 V5OUT2 C1 C2 Vci GND VCC OSC2 OSC1 EXM SFT IM1 IM0 OPOFF TEST RESET* RS/CS* E/SCL RW/SDA DB0/ID0 DB1/ID1 DB2/ID2 DB3/ID3 DB4/ID4 DB5/ID5 DB6 DB7 GND VCC AGND NC ASEG1 ACOMS COMS2 COM1 COM16 COM16 Dummy Dummy 9 HD66717 HD66717 TCP Dimensions (TA1, TA2) HD66717 HD66717 0.65mm pitch HITACHI VCC V1OUT V2OUT V3OUT V4OUT V5OUT VREFP VREF VREFM VEE V5OUT3 V5OUT2 C1 C2 Vci GND VCC OSC2 I/O, Power Supply OSC1 EXM SFT 0.65P × (39­1) IM1 =24.70mm IM0 OPOFF TEST RESET* RS/CS* E/SCL RW/SDA DB0/ID0 DB1/ID1 DB2/ID2 DB3/ID3 DB4/ID4 DB5/ID5 DB6 DB7 GND AGND Dummy Dummy COMS1 COM32 COM32 ­ ­ ­ ­ ­ ­ ­ COM17 COM17 Dummy SEG60 SEG60 ­ ­ ­ ­ 0.24mm ­ pitch ­ ­ ­ ­ ­ ­ ­ ­ ­ LCD Driver Outputs ­ ­ ­ ­ ­ 0.24P × (110­1) ­ ­ =26.16mm ­ ­ ­ ­ ­ ­ ­ ­ SEG1 ASEG10 ASEG10 ­ ­ ­ ASEG1 ACOMS COMS2 COM1 ­ ­ ­ ­ ­ COM16 COM16 Dummy Dummy Note : TA1: V2 and V3 pins are short-circuited (1/4 bias driving) TA2: V2 and V3 pins are open (1/6 bias driving) 10 HD66717 HD66717 Pin Functions Table 1 Pin Functional Description Signal Number of Pins I/O Device Interfaced with Function IM1, IM0 2 I VCC or GND Selects interface mode with the MPU: IM1, IM0 = GND, GND: I2C bus mode (receive) IM1, IM0 = GND, VCC: Clock-synchronized serial mode (receive) IM1, IM0 = VCC, GND: 8-bit bus mode IM1, IM0 = VCC, VCC: 4-bit bus mode RS/CS* 1 I MPU Selects the HD66717 HD66717 during clock-synchronized serial mode: Low: HD66717 HD66717 is selected and can be accessed High: HD66717 HD66717 is not selected and cannot be accessed Selects the registers during 4- or 8-bit bus mode: Low: Instruction register (write); busy flag and address counter (read) High: Data registers (write/read) Must be grounded when I 2C bus mode RW/SDA 1 I/O, I MPU Inputs serial (receive) data and outputs the acknowledge bit during I2C bus mode; Inputs serial (receive) data during clock-synchronous serial mode; selects read/write during 4or 8-bit bus mode: Low: Write High: Read E/SCL 1 I Inputs serial clock pulses during I 2C bus mode and clocksynchronized serial mode; enables data read/write during 4or 8-bit bus mode DB7, DB6, DB5/ID5 DB4/ID4 4 I, I/O MPU Inputs the HD66717 HD66717's identification code (ID5, ID4) during I 2C bus mode and clock-synchronized serial mode;must be fixed to high or low (DB7 and DB6.). Four high-order bidirectional data bus pins for tristate data transfer during 8-bit bus mode. Bidirectional data bus pins during 4-bit bus mode. DB3/ID3, DB2/ID2, DB1/ID1, DB0/ID0, 4 I, I/O MPU Inputs the HD66717 HD66717's identification code (ID3 to ID0) during I2C bus mode and clock-synchronized serial mode; must be fixed to high or low. Four low-order bidirectional data bus pins for tristate data transfer during 8-bit bus mode. Must be left disconnected during 4-bit bus mode since they are not used. COMS1, COMS2 2 O Common output signals for segment icon display. MPU LCD 11 HD66717 HD66717 Table 1 Pin Functional Description (cont) Signal Number of Pins I/O Device Interfaced with Function COM1 to COM32 COM32 32 O LCD Common output signals for character display: COM1 to COM8 for the first line, COM9 to COM16 COM16 for the second line, COM17 COM17 to COM24 COM24 for the third line, and COM25 COM25 to COM32 COM32 for the fourth line. All the unused pins output deselection waveforms. During sleep mode (SLP= 1) or standby mode (STB = 1), all pins output VCC level. SEG1 to SEG60 SEG60 60 O LCD Segment output signals for segment icon display and character display. During sleep mode (SLP = 1) or standby mode (STB = 1), all pins output VCC level. ACOM 1 O LCD Common output signal for annunciator display; can drive display statically between VCC and AGND levels; outputs VCC level while annunciator display is turned off (DA = 0). ASEG1 to ASEG10 ASEG10 10 O LCD Segment output signals for annunciator display; can drive display statically between VCC and AGND levels; output VCC level while annunciator display is turned off (DA = 0). V2/V3 2 I Open or Short-circuited V2/V3 are voltage levels for the internal operational amplifiers; can drive LCD with 1/4 bias when V2 and V3 are short-circuited and with 1/6 bias when they are left disconnected. V1OUT to V5OUT 5 I or O - Used for output from the internal operational amplifiers when they are used (OPOFF = GND); when amplifiers' driving capability is insufficient, attach a capacitor to stabilize the output. Especially these capacitors for V1OUT and V4OUT must be attached in 1/26 duty and 1/34 duty. When the amplifiers are not used (OPOFF = VCC); V1 to V5 voltages can be supplied to these pins externally. VREFP, VREF, VREFM 3 I Adjusts the driving capability of the internal operational amplifiers according to the LCD power supply voltage. Open or Short-circuited LCD Power Supply Voltage (VCC­VEE) Pin Settings VREF, VREFP, and VREFM VCC­VEE: 3V­5V Only VREF and VREFP shorted VCC­VEE: 4V­6V All pins open VCC­VEE: 5V­8V All pins shorted VCC­VEE: 7V or more Only VREF and VREFM shorted VEE 2 - Power supply GND power supply for LCD drive VCC­VEE = 13V max. VCC/GND 10 - Power supply VCC: +2.4V to +5.5V, GND (logic): 0V AGND 2 - Power supply Low level power supply for annunciator display; can adjust contrast of annunciators; AGND GND. OSC1/ OSC2 2 - Oscillation resistor/clock For R-C oscillation, connect an external resistor For external clock supply, input clock pulses to OSC1. 12 HD66717 HD66717 Table 1 Pin Functional Description (cont) Signal Number of Pins I/O Device Interfaced with Function Vci 2 I Power supply V5OUT2 1 O VEE pin/ Booster Voltage input to the Vci pin is boosted twice and output. capacitance When the voltage is boosted three times, the same capacitance as that of C1­C2 should be connected here. V5OUT3 1 O VEE pin Voltage input to the Vci pin is boosted three times and output. C1/C2 2 - Booster capacitance External capacitance should be connected here when using the booster. RESET* 1 I - Reset pin. Initializes the LSI when low. EXM 1 I MPU External alternating signal used for annunciator display during standby mode. If annunciator display is not used, EXM must be fixed to VCC or GND. SFT 1 I VCC or GND Selects the SEG output pin arrangement: when SFT = GND, SEG1 is connected to the far left of the LCD panel and when SFT = VCC, SEG60 SEG60 is connected to the far left of the LCD panel OPOFF 1 I VCC or GND Turns the internal operational amplifier off when OPOFF = VCC, and turns it on when OPOFF = GND. If the amplifier is turned off (OPOFF = VCC), V1 to V5 must be supplied to the V1OUT to V5OUT pins. TEST 1 I GND Test pin. Must be grounded. Inputs a reference voltage and supplies power to the booster; generates the liquid crystal display drive voltage from the operating voltage. 13 HD66717 HD66717 Block Function Description System Interface The HD66717 HD66717 has four types of system interfaces: I2C bus, clock-synchronized serial, 4-bit bus, and 8-bit bus. The interface mode is selected by the IM1 and IM0 pins. The HD66717 HD66717 has two 8-bit registers: an instruction register (IR) and a data register (DR). The IR stores instruction codes, such as display clear, return home, and display control, and address information for the display data RAM (DDRAM), the character generator RAM (CGRAM), and the segment RAM (SEGRAM). The IR can only be written to by MPU and cannot be read from. The DR temporarily stores data to be written into DDRAM, CGRAM, SEGRAM, or annunciator. Data written into the DR from the MPU is automatically written into DDRAM, CGRAM, SEGRAM, or annunciator by an internal operation. The DR is also used for data storage when reading data from DDRAM, CGRAM, or SEGRAM. When address information is written into the IR, data is read and then stored into the DR from DDRAM, CGRAM, or SEGRAM by an internal operation. Data transfer between the MPU is then completed when the MPU reads the DR. After the read, data in DDRAM, CGRAM, or SEGRAM at the next address is sent to the DR for the next read from the MPU. These two registers can be selected by the register select (RS) signal in the 4/8-bit bus interface, and by the RS bit in I2C bus or clock-synchronized serial interface (Table 2). Busy Flag (BF) When the busy flag is 1, the HD66717 HD66717 is in the internal operation mode, and the next instruction will not be accepted. When RS = low and R/W = high in 4/8-bit bus mode (Table 2), the busy flag is output from DB7. The next instruction must be written after ensuring that the busy flag is 0. The busy flag cannot be read in I 2 C bus mode or clock-synchronized serial mode; data must be transferred in appropriate timing considering instruction execution times. Address Counter (AC) The address counter (AC) assigns addresses to DDRAM, CGRAM, or SEGRAM. When the address set instruction is written into the IR, the address information is sent from the IR to the AC. Selection of DDRAM, CGRAM, and SEGRAM is also determined concurrently by the instruction. After writing into (reading from) DDRAM, CGRAM, or SEGRAM, the AC is automatically incremented by 1 (or decremented by 1). The AC contents are then output to DB0 to DB6 when RS = low and R/W = high in 4/8-bit bus mode (Table 2). 14 HD66717 HD66717 Table 2 Register Selection RS R/W Operation 0 0 IR write as an internal operation (display clear, etc.) 0 1 Read busy flag (DB7) read and address counter (DB0 to DB6) (4/8-bit bus interface) 1 0 DR write as an internal operation (DR to DDRAM, CGRAM, SEGRAM, or annunciator) 1 1 DR read as an internal operation (DDRAM, CGRAM, or SEGRAM to DR) (4/8-bit bus interface) Display Data RAM (DDRAM) Display data RAM (DDRAM) stores display data represented in 8-bit character codes. Its capacity is 60 × 8 bits, or 60 characters, which is equivalent to an area of 12 characters × 5 lines. Any number of display lines (LCD drive duty ratio) from 1 to 4 can be selected by software. Here, assignment of DDRAM addresses is the same for all display modes (Table 3). The line to be displayed at the top of the display (display-start line) can also be selected by register settings. See Table 4. MSB Address counter (AC) LSB AC 6 AC5 AC4 AC3 AC2 AC1 AC0 Example : DDRAM address 4A 1 0 0 1 0 1 0 Figure 1 Address Counter and DDRAM Address Table 3 DDRAM Addresses and Display Positions Display Line 1st Char. 2nd 3rd 4th 5th 6th 7th 8th 9th 10th 11th 12th Char. Char. Char. Char. Char. Char. Char. Char. Char. Char. Char. 1st 00 01 02 03 04 05 06 07 08 09 0A 0B 2nd 10 11 12 13 14 15 16 17 18 19 1A 1B 3rd 20 21 22 23 24 25 26 27 28 29 2A 2B 4th 30 31 32 33 34 35 36 37 38 39 3A 3B 5th 40 41 42 43 44 45 46 47 48 49 4A 4B Note: Char. indicates character position. 15 HD66717 HD66717 Table 4 Display-Line Modes, Display-Start Line, and DDRAM Addresses Display-Start Lines DisplayLine Mode Duty Ratio Common Pins 1st Line (SN = 000) 2nd Line (SN = 001) 3rd Line (SN = 010) 4th Line (SN = 011) 5th Line (SN = 100) 1-line (NL = 00) 1/10 COM1­COM8 00H­0BH 10H­1BH 20H­2BH 30H­3BH 40H­4BH 2-line (NL = 01) 1/18 COM1­COM8 COM9­COM16 COM16 00H­0BH 10H­1BH 10H­1BH 20H­2BH 20H­2BH 30H­3BH 30H­3BH 40H­4BH 40H­4BH 00H­0BH 3-line (NL = 10) 1/26 COM1­COM8 00H­0BH COM9­COM16 COM16 10H­1BH COM17 COM17­COM24 COM24 20H­2BH 10H­1BH 20H­2BH 30H­3BH 20H­2BH 30H­3BH 40H­4BH 30H­3BH 40H­4BH 00H­0BH 40H­4BH 00H­0BH 10H­1BH 4-line (NL = 11) 1/34 COM1­COM8 COM9­COM16 COM16 COM17 COM17­COM24 COM24 COM25 COM25­COM32 COM32 00H­0BH 10H­1BH 20H­2BH 30H­3BH 10H­1BH 20H­2BH 30H­3BH 40H­4BH 20H­2BH 30H­3BH 40H­4BH 00H­0BH 30H­3BH 40H­4BH 00H­0BH 10H­1BH 40H­4BH 00H­0BH 10H­1BH 20H­2BH Character Generator ROM (CGROM) The character generator ROM generates 5 × 8-dot character patterns from 8-bit character codes (Table 5). It can generate 240 5 × 8-dot character patterns. User-defined character patterns are also available using a mask-programmed ROM (see the Modifying Character Patterns section.) Character Generator RAM (CGRAM) The character generator RAM of 32 × 5 bits allows the user to redefine the character patterns for user fonts. In the case of 5 × 8-dot characters, up to four fonts may be redefined. Write the character codes at addresses 00H to 03H into DDRAM to display the character patterns stored in CGRAM. Segment RAM (SEGRAM) The segment RAM is used to enable control of segments such as an icon and a mark by the user program. Segments and characters are driven by a multiplexing drive method. SEGRAM has a capacity of 8 × 5 bits, for controlling the display of a maximum of 40 icons and marks. While COMS1 and COMS2 outputs are being selected, SEGRAM is read and segments (icons and marks) are displayed by a multiplexing drive method (20 segments each during COMS1 and COMS2 selection). Bits in SEGRAM corresponding to segments to be displayed are directly set by the MPU, regardless of the contents of DDRAM and CGRAM. 16 HD66717 HD66717 Timing Generation Circuit The timing generation circuit generates timing signals for the operation of internal circuits such as DDRAM, CGROM, CGRAM, and SEGRAM. RAM read timing for display and internal operation timing by MPU access are generated separately to avoid interfering with each other. Therefore, when writing data to DDRAM, for example, there will be no undesirable interferences, such as flickering, in areas other than the display area. Cursor/Blink Control Circuit The cursor/blink (or white-black inversion) control is used to produce a cursor or a flashing area on the display at a position corresponding to the location stored in the address counter (AC). For example (Figure 2), when the address counter is 08H, a cursor is displayed at a position corresponding to DDRAM address (08)H. Multiplexing Liquid Crystal Display Driver Circuit The multiplexing liquid crystal display driver circuit consists of 34 common signal drivers (COM1 to COM32 COM32, COMS1, COMS2) and 60 segment signal drivers (SEG1 to SEG60 SEG60). When the number of lines are selected by a program, the required common signal drivers automatically output drive waveforms, while the other common signal drivers continue to output deselection waveforms. Character pattern data is sent serially through a 60-bit shift register and latched when all needed data has arrived. The latched data then enables the segment signal drivers to generate drive waveform outputs. The shift direction of 60-bit data can be selected by the SFT pin; select the direction appropriate to the device mounting configuration. When multiplexing drive is not used, or during standby or sleep mode, all common and segment signal drivers output the VCC level, halting display. Annunciator Driver Circuit The static annunciator drivers, which are specially used for displaying icons and marks, consists of 1 common signal driver (ACOM) and 10 segment signal drivers (ASEG1 to ASEG10 ASEG10). Since this driver circuit operates at the logic operating voltage (V CC­AGND), the LCD drive power supply circuit is not necessary, and low-power consumption can be achieved. It is suitable for mark indication during system standby because of its drive capability during standby and sleep modes. When multiplexing drive is not used, or during standby or sleep mode, all common and segment signal drivers output the VCC level, halting display. 17 HD66717 HD66717 Booster The booster doubles or triples a voltage input to the Vci pin. With this function, both the internal logic units and LCD drivers can be controlled with a single power supply. Oscillator The HD66717 HD66717 can provide R-C oscillation simply by adding an external oscillation resistor between the OSC1 and OSC2 pins. The appropriate oscillation frequency for operating voltage, display size, and frame frequency can be obtained by adjusting the external-resistor value. Clock pulses can also be supplied externally. Since R-C oscillation is halted during standby mode, current consumption can be reduced. V-Pin Voltage-Followers A voltage-follower for each voltage level (V1 to V5) reduces current consumption by the LCD drive power supply circuit. No external resistors are required because of the internal bleeder-resistor, which generates different levels of LCD drive voltage. The voltage-followers can be turned off while multiplexing drive is not being used. Contrast-Adjuster The contrast-adjuster can adjust LCD contrast by varying LCD drive voltage by software. This function is suitable for selecting appropriate brightness of the LCD or for temperature compensation. 1 2 3 4 5 6 7 8 9 10 11 12 Display position 00 01 02 03 04 05 06 07 08 09 0A 0B DDRAM address Cursor position Note: The cursor/blink or white-black inversion control is also active when the address counter indicates the CGRAM or SEGRAM. However, it has no effect on the display. Figure 2 Cursor Position and DDRAM Address 18 HD66717 HD66717 Table 5 Lower bits Upper bits Relation between Character Codes and Character Patterns (ROM code : A02) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 xxxx0000 CG RAM (1) xxxx0001 CG RAM (2) xxxx0010 CG RAM (3) xxxx0011 CG RAM (4) xxxx0100 CG RAM (5) xxxx0101 CG RAM (6) xxxx0110 CG RAM (7) xxxx0111 CG RAM (8) xxxx1000 CG RAM (1) xxxx1001 CG RAM (2) xxxx1010 CG RAM (3) xxxx1011 CG RAM (4) xxxx1100 CG RAM (5) xxxx1101 CG RAM (6) xxxx1110 CG RAM (7) xxxx1111 CG RAM (8) 19 HD66717 HD66717 Table 6 Relation between Character Codes and Character Patterns (ROM code: A03) Upper Lower bits bits xxxx 0000 CG RAM (1) xxxx 0001 CG RAM (2) xxxx 0010 CG RAM (3) xxxx 0011 CG RAM (4) xxxx 0100 CG RAM (1) xxxx 0101 CG RAM (2) xxxx 0110 CG RAM (3) xxxx 0111 CG RAM (4) xxxx 1000 CG RAM (1) xxxx 1001 CG RAM (2) xxxx 1010 CG RAM (3) xxxx 1011 CG RAM (4) xxxx 1100 CG RAM (1) xxxx 1101 CG RAM (2) xxxx 1110 CG RAM (3) xxxx 1111 20 0000 CG RAM (4) 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 HD66717 HD66717 Table 7 Relation between Character Codes and Character Patterns (ROM code: A13) Lower bits Upper bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 CG xxxx 0000 RAM (1) CG xxxx 0001 RAM (2) CG xxxx 0010 RAM (3) CG xxxx 0011 RAM (4) CG xxxx 0100 RAM (1) CG xxxx 0101 RAM (2) CG xxxx 0110 RAM (3) CG xxxx 0111 RAM (4) CG xxxx 1000 RAM (1) CG xxxx 1001 RAM (2) CG xxxx 1010 RAM (3) CG xxxx 1011 RAM (4) CG xxxx 1100 RAM (1) CG xxxx 1101 RAM (2) CG xxxx 1110 RAM (3) CG xxxx 1111 RAM (4) Note : This A13 font pattern is an upside-down pattern of A03. 21 HD66717 HD66717 Modifying Character Patterns · Character pattern development procedure The following operations correspond to the numbers listed in Figure 3: 1. Determine the correspondence between character codes and character patterns. 2. Create a listing indicating the correspondence between EPROM addresses and data. 3. Program the character patterns into an EPROM. 4. Send the EPROM to Hitachi. 5. Computer processing of the EPROM is performed at Hitachi to create a character pattern listing, which is sent to the user. 6. If there are no problems within the character pattern listing, a trial LSI is created at Hitachi and samples are sent to the user for evaluation. When it is confirmed by the user that the character patterns are correctly written, mass production of the LSI will proceed at Hitachi. 22 HD66717 HD66717 Hitachi User Start Computer processing Evaluate character patterns No Create EPROM address data listing 2 Write EPROM 5 1 3 EPROM Hitachi Create character pattern listing Determine character patterns 4 OK? Yes Art work M/T Masking Trial Sample Sample evaluation OK? 6 No Yes Mass production Figure 3 Character Pattern Development Procedure 23 HD66717 HD66717 Programming Character Patterns This section explains the correspondence between addresses and data used to program character patterns in EPROM. · Programming to EPROM The HD66717 HD66717 character generator ROM can generate 240 5 × 8-dot character patterns. Table 8 shows correspondence between the EPROM address data and the character pattern. Handling Unused Character Patterns 1. EPROM data outside the character pattern area: This is ignored by the character generator ROM for display operation so any data is acceptable. 2. EPROM data in CGRAM area: Always fill with zeros. 3. Treatment of unused user patterns in the HD66717 HD66717 EPROM: According to the user application, these are handled in either of two ways: a. When unused character patterns are not programmed: If an unused character code is written into DDRAM, all its dots are lit, because the EPROM is filled with 1s after it is erased. b. When unused character patterns are programmed as 0s: Nothing is displayed even if unused character codes are written into DDRAM. (This is equivalent to a space.) Table 8 Example of Correspondence between EPROM Address Data and Character Pattern (5 × 8 Dots) EPROM Address Data MSB A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 LSB O4 O3 O2 O1 O0 Character code 1 1 0 0 0 1 1 0 0 0 1 0 1 0 1 0 0 0 1 0 1 1 0 1 0 1 0 1 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 0 0 0 1 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 "0" Line position Notes: 1. EPROM addresses A11 to A4 correspond to a character code. 2. EPROM addresses A2 to A0 specify the line position of the character pattern. EPROM address A3 should be set to 0. 3. EPROM data O4 to O0 correspond to character pattern data. 4. Areas which are lit (indicated by shading) are stored as 1, and unlit areas as 0. 5. The eighth raster-row is also stored in the CGROM, and should also be programmed. If the eighth raster-row is used for a cursor, this data should all be set to zero. 6. EPROM data bits O7 to O5 are invalid. 0 should be written in all bits. 24 HD66717 HD66717 Table 9 Example of Relationships between Character Code (DDRAM) and Character Pattern (CGRAM Data) CGRAM address Character code (DDRAM data) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 * * * * 0 1 0 1 MSB A4 A3 A2 A1 A0 O7 O6 O5 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 * * * (Don't care) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 * * * (Don't care) 1 0 1 CGRAM data LSB O4 O3 O2 O1 O0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 Character pattern (1) Character pattern (4) Notes: 1. The lower 2 bits of the character code correspond to the upper two bits of the CGRAM address (2 bits: 4 types). 2. CGRAM address bits 0 to 2 designate the character pattern raster-row position. The 8th rasterrow is the cursor position and its display is formed by a logical OR with the cursor. 3. The upper three bits of the CGRAM data are invalid; use the lower five bits. 4. When the upper four bits (bits 7 to 4) of the character code are 0, CGRAM is selected. Bits 3 and 2 of the character code are invalid (*). Therefore, for example, the character codes (00)H and (08)H correspond to the same CGRAM address. 5. A set bit in the CGRAM data corresponds to display selection, and 0 to non-selection. * Indicates no effect. 25 HD66717 HD66717 Table 10 Correspondence between Segment Display SEGRAM Addresses (ASEG) and Driver Signals Segment Signals ASEG Address MSB LSB D7 D6 D5 D4 D3 D2 D1 D0 Common Signal 1 0 0 0 * * * SEG1, SEG21 SEG21, SEG41 SEG41 SEG2, SEG22 SEG22, SEG42 SEG42 SEG3, SEG23 SEG23, SEG43 SEG43 SEG4, SEG24 SEG24, SEG44 SEG44 SEG5, SEG25 SEG25, SEG45 SEG45 COMS1 1 0 0 1 * * * SEG6, SEG26 SEG26, SEG46 SEG46 SEG7, SEG27 SEG27, SEG47 SEG47 SEG8, SEG28 SEG28, SEG48 SEG48 SEG9, SEG29 SEG29, SEG49 SEG49 SEG10 SEG10, SEG30 SEG30, SEG50 SEG50 COMS1 1 0 1 0 * * * SEG11 SEG11, SEG31 SEG31, SEG51 SEG51 SEG12 SEG12, SEG32 SEG32, SEG52 SEG52 SEG13 SEG13, SEG33 SEG33, SEG53 SEG53 SEG14 SEG14, SEG34 SEG34, SEG54 SEG54 SEG15 SEG15, SEG35 SEG35, SEG55 SEG55 COMS1 1 0 1 1 * * * SEG16 SEG16, SEG36 SEG36, SEG56 SEG56 SEG17 SEG17, SEG37 SEG37, SEG57 SEG57 SEG18 SEG18, SEG38 SEG38, SEG58 SEG58 SEG19 SEG19, SEG39 SEG39, SEG59 SEG59 SEG20 SEG20, SEG40 SEG40, SEG60 SEG60 COMS1 1 1 0 0 * * * SEG1, SEG21 SEG21, SEG41 SEG41 SEG2, SEG22 SEG22, SEG42 SEG42 SEG3, SEG23 SEG23, SEG43 SEG43 SEG4, SEG24 SEG24, SEG44 SEG44 SEG5, SEG25 SEG25, SEG45 SEG45 COMS2 1 1 0 1 * * * SEG6, SEG26 SEG26, SEG46 SEG46 SEG7, SEG27 SEG27, SEG47 SEG47 SEG8, SEG28 SEG28, SEG48 SEG48 SEG9, SEG29 SEG29, SEG49 SEG49 SEG10 SEG10, SEG30 SEG30, SEG50 SEG50 COMS2 1 1 1 0 * * * SEG11 SEG11, SEG31 SEG31, SEG51 SEG51 SEG12 SEG12, SEG32 SEG32, SEG52 SEG52 SEG13 SEG13, SEG33 SEG33, SEG53 SEG53 SEG14 SEG14, SEG34 SEG34, SEG54 SEG54 SEG15 SEG15, SEG35 SEG35, SEG55 SEG55 COMS2 1 1 1 1 * * * SEG16 SEG16, SEG36 SEG36, SEG56 SEG56 SEG17 SEG17, SEG37 SEG37, SEG57 SEG57 SEG18 SEG18, SEG38 SEG38, SEG58 SEG58 SEG19 SEG19, SEG39 SEG39, SEG59 SEG59 SEG20 SEG20, SEG40 SEG40, SEG60 SEG60 COMS2 Notes: 1. When the SFT pin is grounded, the SEG1 pin output is connected to the far left of the LCD panel, and when the SFT pin is high, the SEG60 SEG60 pin output is connected to the far left. 2. SEG1 to SEG20 SEG20 data is identical to SEG21 SEG21 to SEG40 SEG40 and SEG41 SEG41 to SEG60 SEG60 data. 3. The lower five bits (D4 to D0) of SEGRAM data determine on or off display of each segment. A segment is selected (turned on) when the corresponding data is 1, and is deselected (turned off) when the corresponding data is 0. The upper three bits (D7 to D5) are invalid. 26 HD66717 HD66717 Table 11 Correspondence between Annunciator Display Addresses (AAN) and Driver Signals AAN Address MSB LSB D7 Annunciator Segment Signals D6 D5 D4 D3 D2 D1 D0 Common Signal 0 0 0 0 ASEG1 Blink ASEG1 Data ASEG2 Blink ASEG2 Data ASEG3 Blink ASEG3 Data ASEG4 Blink ASEG4 Data ACOM 0 0 0 1 ASEG5 Blink ASEG5 Data ASEG6 Blink ASEG6 Data ASEG7 Blink ASEG7 Data ASEG8 Blink ASEG8 Data ACOM 0 0 1 0 ASEG9 Blink ASEG9 Data ASEG10 ASEG10 ASEG10 ASEG10 - Blink Data * - * - * - * ACOM Notes: 1. The annunciator is turned on when the corresponding even bit (data) is 1, and is turned off when 0. 2. The turned-on annunciator blinks when the corresponding odd bit (blink) is 1. Blinking is provided by repeatedly turning on the annunciator for 32 frames and then turning it off for the next 32 frames. 27 HD66717 HD66717 Instructions Outline Only the instruction register (IR) and the data register (DR) of the HD66717 HD66717 can be controlled by the MPU. Before starting internal operation of the HD66717 HD66717, control information is temporarily stored in these registers to allow interfacing with various peripheral control devices or MPUs which operate at different speeds. The internal operation of the HD66717 HD66717 is determined by signals sent from the MPU. These signals, which include register selection (RS), read/write (R/W), and the data bus (DB0 to DB7), make up the HD66717 HD66717 instructions (Table 18). There are four categories of instructions that: · · · · Control display Control power management Set internal RAM addresses Perform data transfer with internal RAM Normally, instructions that perform data transfer with internal RAM are used the most. However, autoincrementation by 1 (or auto-decrementation by 1) of internal HD66717 HD66717 RAM addresses after each data write can lighten the program load of the MPU. While an instruction is being executed for internal operation, or during reset, no instruction other than the busy flag/address read instruction can be executed. Because the busy flag is set to 1 while an instruction is being executed, check it to make sure it is 0 before sending another instruction from the MPU. If an instruction is sent without checking the busy flag, the time between the first instruction issue and next instruction issue must be longer than the instruction execution time itself. Refer to Table 16 for the list of each instruction execution cycles (clock pulses). The execution time depends on the operating clock frequency (oscillation frequency). 28 HD66717 HD66717 Instruction Description Status Read The status read instruction (Figure 4) reads the busy flag (BF) indicating that the system is now internally operating on a previously received instruction. If BF is 1, the internal operation is in progress. The next instruction will not be accepted until BF is reset to 0. Check the BF status before the next write operation. At the same time, the value of the address counter in binary AAAAAAA is read out. This address counter is used by both CGRAM, DDRAM, and SEGRAM addresses, and its value is determined by the previous instruction. Clear Display The clear display instruction (Figure 5) writes space code (20)H (character pattern for character code (20)H must be a blank pattern) into all DDRAM addresses. It then sets DDRAM address 0 into the address counter. It also sets I/D to 1 (increment mode) in entry mode. RS R/W DB7 0 1 BF DB0 A A A A A A A Figure 4 Status Read Instruction RS R/W DB7 0 0 0 DB0 0 0 0 0 0 0 1 Figure 5 Clear Display Instruction 29 HD66717 HD66717 Return Home The return home instruction (Figure 6) sets DDRAM address 0 into the address counter. The DDRAM contents do not change.The cursor or blinking goes to the top left of the display. Start Oscillator The start oscillator instruction (Figure 7) re-starts the oscillator from a halt state in standby mode. After issuing this instruction, wait at least 10 ms for oscillation to become stable before issuing the next instruction. (Refer to the Standby Mode section.) Entry Mode The entry mode instruction (Figure 8) includes the I/D and OSC bits. I/D: Increments (I/D = 1) or decrements (I/D = 0) the DDRAM address by 1 when a character code is written into or read from DDRAM.The cursor or blinking moves to the right when incremented by 1 and to the left when decremented by 1. The same applies to writing and reading of CGRAM and SEGRAM. OSC: Divides the external clock frequency by four (OSC = 1) using the resulting clock as an internal operating clock. The execution time for this instruction and subsequent ones is therefore quadrupled. The execution time of clearing this bit (OSC = 0) is also quadrupled. (For application of this instruction, refer to the Partial-Display-Off Function section.) RS R/W DB7 0 0 0 DB0 0 0 0 0 0 1 0 Figure 6 Return Home Instruction RS R/W DB7 0 0 0 DB0 0 0 0 0 0 1 Figure 7 Start Oscillator Instruction 30 1 HD66717 HD66717 Cursor Control The cursor control (Figure 9) includes the B/W, C, and B bits. B/W: When B/W is 1, the character at the cursor position is cyclically (every 32 frames) displayed with black-white inversion. C: The cursor is displayed on the 8th raster-row when C is 1. The cursor is displayed using 5 dots in the 8th raster-row for 5 × 8-dot character font. B: The character indicated by the cursor blinks when B is 1. The blinking is displayed as switching between all black dots and displayed characters every 32 frames. The cursor and blinking can be set to display simultaneously. When LC and B = 1, the blinking is displayed as switching between all white dots and displayed characters. Figure 10 shows cursor control examples. RS R/W DB7 0 0 0 DB0 0 0 0 0 1 I/D OSC Figure 8 Entry Mode Instruction RS R/W DB7 0 0 0 DB0 0 0 0 1 B/W C B Figure 9 Cursor Control Instruction 31 HD66717 HD66717 Display On/Off Control The display on/off control instruction (Figure 11) includes DC, DS, and LC bits. DC: The character display is on when DC is 1 and off when DC is 0. When off, the display data remains in DDRAM, and can be displayed instantly by setting DC to 1. DS: When DS = 1, segment display for icons and marks that is controlled by the multiplexing drive method is turned on and when DS = 0, it is turned off. When both DC and DS = 0, multiplexing drive is halted, setting the outputs from SEG1 to SEG60 SEG60, COM1 to COM32 COM32, and COMS1 and COMS2 to V CC level to turn off the display. This can suppress current for LCD charging or discharging due to LCD driving operations. LC: When LC = 1, a cursor attribute is assigned to the line that contains the address counter (AC) value. Cursor mode can be selected with the B/W, C, and B bits. Refer to the Line-Cursor Display section. Alternating display (every 32 frames) i) White-black inverting display example Alternating display ii) Blink display example ii) 8th raster-row cursor display Figure 10 Cursor Control Examples RS R/W DB7 0 0 0 DB0 0 0 1 0 DC DS LC Figure 11 Display On/Off Instruction 32 HD66717 HD66717 Power Control The cursor control instruction (Figure 12) includes the AMP, SLP, and STB bits. AMP: When AMP = 1, each voltage-follower for V1 to V5 pins and the booster are turned on. When AMP = 0, current consumption can be reduced while character or segment display controlled by the multiplexing drive method is not being used. SLP: When SLP = 1, the HD66717 HD66717 enters sleep mode, where all the internal operations are halted except for annunciator display function and the R-C oscillator, thus reducing current consumption. Refer to the Sleep Mode section. Only the following instructions can be executed during sleep mode. a. b. c. d. e. f. Annunciator address set (AAN) Annunciator data write Annunciator display on or off (DA = 1 or 0) Voltage-follower on or off (AMP = 1 or 0) Standby mode set (STB = 1) Sleep mode cancel (SLP = 0) During sleep mode, other RAM data and instructions cannot be updated but they are retained. STB: When STB = 1, the HD66717 HD66717 enters standby mode, where the device completely stops, halting all the internal operations including the internal R-C oscillator and no external clock pulses are supplied. However, annunciator display alone is available when the alternating signal for annunciator-driving signals is supplied to the EXM pin. When the annunciator display is not needed, make sure to turn off display (DA = 0). Refer to the Standby Mode section. Only the following instructions can be executed during standby mode. a. b. c. d. e. f. Annunciator address set (AAN) Annunciator data write Annunciator display on or off (DA = 1 or 0) Voltage-follower on or off (AMP = 1 or 0) Start oscillator Standby mode cancel (STB = 0) During standby mode, RAM data and other instructions may be lost; they must be set again after standby mode is cancelled. RS R/W DB7 0 0 0 DB0 0 0 1 1 AMP SLP STB Figure 12 Power Control Instruction 33 HD66717 HD66717 Display Control The display control instruction (Figure 13) includes the NL and DL bits. NL1, NL0: Designates the number of display lines. This value determines the LCD drive multiplexing duty ratio (Table 12). The address assignment is the same for all display line modes. DL3­DL1: Doubles the height of characters on a specified line. The first, second, or third line is doubled in height when DL1, DL2, or DL3 = 1, respectively. Two lines can be simultaneously doubled in a 4-line display. Refer to the Double-Height Display section. RS R/W DB7 0 0 0 DB0 0 1 NL1 NL0 DL3 DL2 DL1 Figure 13 Display Control Instruction Table 12 NL Bits and Display Lines NL1 NL0 Number of Display Lines LCD Drive Multiplexing Duty Ratio 0 0 1 1/10 0 1 2 1/18 1 0 3 1/26 1 1 4 1/34 34 HD66717 HD66717 Contrast Control The contrast control instruction (Figure 14) includes the SN and CT bits. SN2: Combined with the SN1 and SN0 bits described in the Scroll Control section to select the first line to be scrolled (display-start line). CT3­CT0: Controls the LCD drive voltage (potential difference between VCC and V5) to adjust contrast (Figure 15 and Table 13). Refer to the Contrast Adjuster section. RS R/W DB7 0 0 0 DB0 1 0 SN2 CT3 CT2 CT1 CT0 Figure 14 Contrast Control Instruction HD66717 HD66717 VCC V1 R V2 R R V3 R V4 R V5 R + ­ + ­ + ­ + ­ + ­ VR VEE Figure 15 Contrast Adjuster 35 HD66717 HD66717 Scroll Control The scroll control instruction (Figure 16) includes the SN and SL bits. SN1, SN0: Combined with the SN2 bit described in the Contrast Control section to select the top line to be displayed (display-start line) through the data output from the COM1 pin (Table 14). After first five lines are displayed from the top line, the cycle is repeated and scrolling continues. Table 13 CT Bits and Variable Resistor Value of Contrast Adjuster CT3 CT2 CT1 CT0 Variable Resistor Value (VR) 0 0 0 0 6.4 x R 0 0 0 1 6.0 x R 0 0 1 0 5.6 x R 0 0 1 1 5.2 x R 0 1 0 0 4.8 x R 0 1 0 1 4.4 x R 0 1 1 0 4.0 x R 0 1 1 1 3.6 x R 1 0 0 0 3.2 x R 1 0 0 1 2.8 x R 1 0 1 0 2.4 x R 1 0 1 1 2.0 x R 1 1 0 0 1.6 x R 1 1 0 1 1.2 x R 1 1 1 0 0.8 x R 1 1 1 1 0.4 x R RS R/W DB7 0 0 0 DB0 1 1 SN1 SN0 SL2 SL1 SL0 Figure 16 Scroll Control Instruction 36 HD66717 HD66717 SL2­SL0: Selects the top raster-row to be displayed (display-start raster-row) in the display-start line specified by SN2 to SN0. Any raster-row from the first to eighth can be selected (Table 15). This function is used to perform vertical smooth scroll together with SN2 to SN0. Refer to the Vertical Smooth Scroll section. Table 14 SN Bits and Display-Start Lines SN2 SN1 SN0 Display-Start Line 0 0 0 1st line 0 0 1 2nd line 0 1 0 3rd line 0 1 1 4th line 1 0/1 0/1 5th line Table 15 SN Bits and Display-Start Raster-Rows SL2 SN1 SL0 Display-Start Raster-Row 0 0 0 1st raster-row 0 0 1 2nd raster-row 0 1 0 3rd raster-row 0 1 1 4th raster-row 1 0 0 5th raster-row 1 0 1 6th raster-row 1 1 0 7th raster-row 1 1 1 8th raster-row 37 HD66717 HD66717 Annunciator/SEGRAM Address Set The annunciator/SEGRAM address set instruction (Figure 17) includes the DA and A bits. DA: Turns annunciator display on or off. When DA = 1, annunciator display is turned on and driven statically. When DA = 0, annunciator display is turned off with ASEG1 to ASEG10 ASEG10 and ACOM pins held to VCC level. The internal operating clock supply is halted during standby mode; make sure to turn off display (DA = 0) if the external alternating signal is not supplied. Refer to the Segment Display and Annunciator Display section and the Standby Mode section. AAAA: Used for setting the SEGRAM address in the address counter (AC) or for setting an annunciator address. The SEGRAM addresses range from 1000H 1000H to 1111H 1111H (8 addresses), while the annunciator addresses range from 0000H 0000H to 0010H 0010H (3 addresses). The annunciator address is directly set without using the address counter, and consequently must be updated for each access. The annunciator address can be set even during sleep and standby modes. Once the SEGRAM address is set, data in the SEGRAM can be accessed consecutively since the address counter is automatically incremented or decremented by one according to the I/D bit setting after each access. The SEGRAM address cannot be set during sleep or standby mode. RS R/W DB7 0 0 1 DB0 0 0 DA A A A A Figure 17 Annunciator/SEGRAM Address Set Instruction 38 HD66717 HD66717 CGRAM Address Set The CGRAM address set instruction (Figure 18) includes the A bits. AAAAA: Used for setting the CGRAM address in the address counter (AC). The CGRAM addresses range from 00H to 1FH (32 addresses) (Table 16). Once the CGRAM address is set, data in the CGRAM can be accessed consecutively since the address counter is automatically incremented or decremented according to the I/D bit setting after each access. The CGRAM address cannot be set during sleep or standby mode. RS R/W DB7 0 0 1 DB0 0 1 A A A A A Figure 18 CGRAM Address Set Instruction Table 16 CGRAM Addresses and Character Codes Displayed Character CGRAM Address Character Codes 1st character 00H to 07H 00H 2nd character 08H to 0FH 01H 3rd character 10H to 17H 02H 4th character 18H to 1FH 03H 39 HD66717 HD66717 DDRAM Address Set The DDRAM address set instruction (Figure 19) includes the A bits. AAAAAAA: Used for setting the DDRAM address in the address counter (AC). The DDRAM addresses range from 00H to 4BH (60 addresses) (Table 17). Once the DDRAM address is set, data in the DDRAM can be accessed consecutively since the address counter is automatically incremented or decremented according to the I/D bit setting after each access. Here, invalid addresses are automatically skipped. The DDRAM address cannot be set during sleep or standby mode. RS R/W DB7 DB0 0 0 1 1 0 0 0 0 A A Upper bits 0 0 1 1 1 A A A A A Lower bits Figure 19 DDRAM Address Set Instruction Table 17 DDRAM Addresses and Invalid Addresses Displayed Line DDRAM Address Invalid Addresses 1st line 00H to 0BH 0CH to 0FH 2nd line 10H to 1BH 1CH to 1FH 3rd line 20H to 2BH 2CH to 2FH 4th line 30H to 3BH 3CH to 3FH 5th line 40H to 4BH 4CH and subsequent addresses 40 HD66717 HD66717 Write Data to RAM The write data to RAM instruction (Figure 20) writes 8-bit data to annunciator or DDRAM, or lower 5-bit data to SEGRAM or CGRAM that is selected by the previous specification of the address set instruction (annunciator/SEGRAM address set, CGRAM address set, or DDRAM address set). After a write, the address is automatically incremented or decremented by 1 according to the I/D bit setting in the entry mode instruction. The annunciator address is not automatically updated; it must be specifically updated to write data to a different address. During sleep and standby modes, DDRAM, CGRAM, or SEGRAM cannot be accessed. Read Data from RAM The read data from RAM instruction (Figure 21), reads 8-bit data from DDRAM, or 5-bit binary data from CGRAM or SEGRAM that is selected by the previous specification of the address set instruction (SEGRAM address set, CGRAM address set, or DDRAM address set). The unused upper three bits of CGRAM or SEGRAM data are read as 000; annunciator data cannot be read. If no address is specified by the address set instruction just before this instruction, the first data read will be invalid. When executing serial read instructions, the next address is normally read from the next address. After a read, the address is automatically incremented or decremented by 1 according to the I/D bit setting in the entry mode instruction. Table 18 lists the above instructions. RS R/W DB7 1 0 D DB0 D D D D D D D Figure 20 Write Data to RAM Instruction RS R/W DB7 1 1 D DB0 D D D D D D D Figure 21 Read Data from RAM Instruction 41 HD66717 HD66717 Table 18 Instruction List Code Instruction No. R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Execution Cycle * 1 Status SR 1 0 BF AC AC AC AC AC AC AC Reads busy flag (BF), which indicates internal operations are being performed, and reads address counter (AC). 0 Clear display CL 0 0 0 0 0 0 0 0 0 1 Clears entire display and 310 sets DDRAM address 0 in address counter. Return home CH 0 0 0 0 0 0 0 0 1 0 Sets DDRAM address 0 in 10 address counter. Start oscillator OS 0 0 0 0 0 0 0 0 1 1 Starts oscillation during standby mode. Entry mode set EM 0 0 0 0 0 0 0 1 I/D OSC Sets address update 10 direction after RAM access (I/D), and system clock division (OSC). Cursor control CR 0 0 0 0 0 0 1 B/W C B Sets black-white inverting cursor (B/W), 8th rasterrow cursor (C), and blink cursor (B). 10 Display on/off control DO 0 0 0 0 0 1 0 DC LC Sets character display on/off (DC), segment display on/off (DS), and line-cursor on/off (LC). 10 Power control PW 0 0 0 0 0 1 1 AMP SLP STB Turns on voltage-follower 10 and booster (AMP), and sets sleep mode (SLP) and standby mode (STB). Display control DC 0 0 0 0 1 NL1 NL0 DL3 Contrast control CN 0 0 0 1 0 SN2 CT3 CT2 CT1 CT0 Sets the display-start line (SN2) and contrastadjusting value (CT). 10 Scroll control SC 0 0 0 1 1 SN1 SN0 SL2 10 Annunciator AS /SEGRAM address set 0 0 1 0 0 DA CGRAM CA address set 0 0 1 0 1 ACG4 ACG3 ACG2 ACG1 ACG0 Sets the initial CGRAM address to the address counter. 10 DDRAM DA address set (upper bits) 0 0 1 1 0 0 ADD6 ADD5 Sets the initial higher DDRAM address to the address counter. 10 DDRAM DA address set (lower bits) 0 0 1 1 1 ADD4 ADD3 ADD2 ADD1 ADD0 Sets the initial lower DDRAM address to the address counter. 10 42 DS DL2 SL1 DL1 SL0 Sets the number of display 10 lines (NL) and the line to be doubled in height. Sets the display-start line (SN) and display-start raster-row (SL). AAN/ AAN/ AAN/ AAN/ Turns on annunciator ASEG3 ASEG2 ASEG1 ASEG0 display and sets annunciator/SEGRAM address. 0 0 - 10 HD66717 HD66717 Table 18 Instruction List (cont) Code DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description Execution Cycle * 1 Instruction No. R/W RS Write data to RAM WD 0 1 Write data Writes data to DDRAM, CGRAM, SEGRAM, or annunciator. Read data from RAM RD 1 1 Read data Reads data from DDRAM, 10 CGRAM, or SEGRAM. 10 BF = 1: I/D = 1: OSC = 1: B/W = 1: B = 1: D = 1: DC = 1: LC = 1: AMP = 1: STB = 1: NL1,NL0: Internally operating AC: Address counter Increment I/D = 0: Decrement System clock divided by four Black-white inverting cursor on C = 1: 8th raster-row cursor on Blink cursor on Display on Character display on DS = 1: Segment display on Line containing AC given cursor attribute Voltage-follower and booster on SLP = 1: Sleep mode Standby mode Number of display lines [00: 1line (1/10 duty ratio), 01: 2 lines (1/18 duty ratio), 10: 3 lines (1/26 duty ratio),11:4 lines (1/34 duty ratio)] DL3 ­ DL1: Double-height lines (DL1 = 1: 1st line, DL2 = 1: 2nd line, DL3 = 1: 3rd line) CT3­CT0: Contrast adjustment SN2 ­ SN0: Display-start line (000: 1st line, 001: 2nd line, 010: 3rd line, 011: 4th line, 100: 5th line) SL2 ­ SL0: Display-start raster-row (000: 1st raster-row. 111: 8th raster-row) DA = 1: Annunciator display on AAN/ASEG = 0000­0010: Annunciator address AAN/ASEG = 1000­1111: SEGRAM address ACG4­ACG0: CGRAM address (00000­11111) ADD6­ADD0: DDRAM address (0000000­1001011) Note: 1. Represented by the number of operating clock pulses; the execution time depends on the supplied clock frequency or the internal oscillation frequency. 43 HD66717 HD66717 Reset Function Initializing by Internal Reset Circuit The HD66717 HD66717 is internally initialized by RESET input. During reset, the system executes the instructions as described below. Here, the busy flag (BF) therefore indicates a busy state (BF = 1), accepting no instruction or RAM data access from the MPU. Here, reset input must be held at least 10 ms. After releasing power-on reset, clear display instruction is operated, so wait for 1,000 clock-cycles or more. Make sure to reset the HD66717 HD66717 immediately after power-on reset in I2C bus mode. 1. Instruction set initialization a. Clear display: Writes 20H to DDRAM after releasing reset b. Return home Sets the address counter (AC) to 00H to select the DDRAM c. Start oscillator d. Entry mode I/D = 1: Increment by 1 OSC = 0: Clock frequency not divided e. Cursor control B/W = 0: White-black inverting cursor off C = 0: 8th raster-row cursor off B = 0: Blink cursor off f. Display on/off control DC = 0: Character display off DS = 0: Segment display off LC = 0: Line-cursor off g. Power control AMP = 0: LCD power supply off SLP = 0: Sleep mode off STB = 0: Standby mode off h. Display control NL1, NL0 = 11: 4-line display (1/34 multiplexing duty ratio) DL3­DL1 = 000: Double-height display off i. Contrast adjust CT = 0000: Weak contrast j. Scroll control SN2­SN0 = 000: First line displayed at the top SL2­SL0 = 000: First raster-row displayed at the top of the first line 44 HD66717 HD66717 k. Annunciator control DA = 0: Annunciator display off 2. RAM data initialization a. DDRAM All addresses are initialized to 20H by the clear display instruction b. CGRAM/SEGRAM Not automatically initialized by reset input; must be initialized by software while display is off (DC and DS = 0) c. Annunciator data Not automatically initialized by reset input; must be initialized by software while display is off (DA= 0) 3. Output pin initialization a. LCD driver output pins (SEG/COM, ASEG/ACOM): Outputs VCC level b. Booster output pins (V5OUT2 and V5OUT3): Outputs GND level c. Oscillator output pin (OSC2): Outputs oscillation signal 45 HD66717 HD66717 Transferring Serial Data I2C Bus Interface Grounding the IM1 and IM0 pins (interface mode pins) allows serial data transfer conforming to the I2C bus interface over the serial data line (SDA) and serial transfer clock line (SCL). Here, the HD66717 HD66717 operates in an exclusive-receive slave mode. The HD66717 HD66717 initiates serial data transfer by transferring the first byte when a high SCL level at the falling edge of the SDA input is sampled; it ends serial data transfer when a high SCL level at the rising edge of the SDA input is sampled. The HD66717 HD66717 is selected when the higher six bits of the 7-bit slave address in the first byte transferred from the master device match the 6-bit device identification code assigned to the HD66717 HD66717. The HD66717 HD66717, when selected, receives the subsequent data strings. Any identification code can be assigned by the DB5/ID5 to DB0/ID0 pins; select an appropriate code that is not assigned to any other slave device. The higher four bits (ID5 to ID2) of this identification code is recommended as 0111. Two different slave addresses must be assigned to a single HD66717 HD66717 because the least significant bit (LSB) of the slave address is used as a register select bit (RS): when RS = 0, an instruction can be issued and when RS = 1, data can be written to a RAM. The eighth bit of the first byte (R/W bit) must be 0 since the HD66717 HD66717 exclusively receives data. The ninth bit of the first byte is a receive-data acknowledge bit (ACK). When the received slave address matches the device ID code, the HD66717 HD66717 pulls down the ACK bit to a low level. Therefore, the ACK output buffer is an open-drain structure, only allowing low-level output. However, the ACK bit is undetermined immediately after power-on; make sure to initialize the LSI using the RESET* input. After identifying the address in the first byte, the HD66717 HD66717 receives the subsequent data as an HD66717 HD66717 instruction or as RAM data. Having received 8-bit data normally, the HD66717 HD66717 pulls down the ninth bit (ACK) to a low level. Therefore, if the ACK is not returned, the data must be transferred again. Multiple bytes of data can be consecutively transferred until the transfer-end condition is satisfied. Here, when the serial data transfer rate is longer than that of the HD66717 HD66717 instruction execution cycle, effective data transfer is possible without retransmission (see Table 18, Instruction List). Note that the display-clear instruction alone requires longer execution time than the others. Table 19 illustrates the first bytes of I 2C bus interface data and Figure 22 shows the I2C bus interface timing sequence . 46 HD66717 HD66717 First Bytes of I 2C Bus Interface Data Table 19 Transferred Bit String First Byte S Bit 1 Bit 2 Bit 3 2 Bit 5 Bit 6 Bit 7 A1 A0 I C slave address A5 A3 ID4 ID3 ID2 1 Transfer start ID5 A4 1 A2 Bit 9 ACK 0 ACK 1 Device ID code 0 Bit 8 R/W 2 I C bus system Transfer start A6 HD66717 HD66717 Bit 4 ID1 RS ID0 Transfer end Transfer start 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 SCL (input) MSB (0) (1) (1) (1) SDA (input) MSB ID5 ID4 ID3 ID2 ID1 ID0 RS "0" Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack D7 D6 D5 D4 D3 D2 D1 D0 Ack Device ID code RS 1st instruction Slave address 2nd instruction Acknowledge Acknowledge 1st byte Acknowledge Instructions a) Basic data transfer (receive) timing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 SCL (input) SDA (input) S Start 1st byte A C K Instruction 1 A C K Instruction 2 Instruction 1 execution time A C K Instrucation 3 Instruction 2 execution time A C K P End b) Consecutive data transfer timing Note: Transfer the instruction 2 ACK after instruction 1 has been executed. Figure 22 I2C Bus Interface Timing Sequence 47 HD66717 HD66717 Clock-Synchronized Serial Interface Setting the IM1 and IM0 pins (interface mode pins) to the GND and high levels, respectively, allows standard clock-synchronized serial data transfer, using the chip select (CS*), SDA, and SCL lines. Here, the HD66717 HD66717 exclusively receives data. The HD66717 HD66717 initiates serial data transfer by transferring the start byte at the falling edge of the CS* input. It ends serial data transfer at the rising edge of the CS* input. The HD66717 HD66717 is selected when the 6-bit chip address in the start byte transferred from the transmitting device matches the 6-bit (device) identification code assigned to the HD66717 HD66717. The HD66717 HD66717, when selected, receives the subsequent data strings. Any identification code can be assigned by the DB5/ID5 to DB0/ID0 pins. Two different chip addresses must be assigned to a single HD66717 HD66717 because the seventh bit of the start byte is used as a register select bit (RS): when RS = 0, an instruction can be issued and when RS = 1, data can be written to a RAM. The eighth bit of the start byte must be 0. After receiving the start byte, the HD66717 HD66717 receives the subsequent data as an HD66717 HD66717 instruction or as RAM data. Data is transferred with the MSB first. To transfer data consecutively, adjust the data transfer rate so that the HD66717 HD66717 can complete the current instruction before the eighth bit of the next instruction is transferred. See Table 18, Instruction List. If the next instruction is received during execution of the previous instruction, the next instruction will be ignored. Note that the display-clear instruction alone requires longer execution time than the others. Figure 23 shows the clock-synchronised serial interface timing sequence. 48 HD66717 HD66717 Transfer start Transfer end CS* (Input) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SCL (Input) MSB SDA ID5 ID4 ID3 ID2 ID1 ID0 RS 0 (Input) Device ID code D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 RS 1st instruction Start byte 2nd instruction Instruction (a) Basic data transfer (receive) timing CS* (Input) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Instruction 1 Instruction 2 Instruction 3 Instruction 1 execution time Instruction 2 execution time SCL (Input) SDA (Input) 1st byte Start End (b) Consecutive data transfer timing Note: Adjust the transfer rate so that the HD66717 HD66717 can complete instruction 1 before the 8th bit of instruction 2 is transferred. Figure 23 Clock-Synchronized Serial Interface Timing Sequence 49 HD66717 HD66717 Transferring Parallel Data Interface with an 8-Bit MPU Eight-bit data can be transferred in parallel by setting the IM1 and IM0 pins to the VCC and GND levels, respectively (Figure 24). The HD66717 HD66717 can interface directly with an 8-bit bus synchronized with the E clock, or with an 8-bit MCU through an I/O port (Figure 25). When the number of I/O lines or chip packaging size is limited, a 4-bit bus interface or even serial data transfer should be used. RS R/W E Internal operation Internal signal DB7 Data Busy Instruction write Not Busy Busy Busy flag check Busy flag check Busy flag check Figure 24 8-Bit Parallel Data Transfer Timing Sequence I/O port interface H8/325 H8/325 C0 C1 C2 E RS R/W HD66717 HD66717 8 A0 - A7 DB0 - DB7 Figure 25 8-Bit MPU Interface 50 Data Instruction write HD66717 HD66717 Interface with a 4-Bit MPU Four-bit data can be transferred in parallel by setting both the IM1 and IM0 pins to the VCC level (Figure 26). Four-bit data representing higher or lower bits of 8-bit instructions or 8-bit RAM data can be transferred in that order. The HD66717 HD66717 can forcibly reset the counter that counts the number of higher and lower 4-bit data transfers in a 4-bit bus interface. This function, called transfer-syncronization, can be performed by writing a special instruction containing 0000 four consecutive times after return home (Figure 27). For example, when a data transfer sequence becomes disordered due to noise or some undesired factor, this function resets the counter and thus enables resuming data transfer from the higher 4 bits. Using this function at specified intervals prevents display-system crash. This transfer-synchronization must be performed after power-on reset. RS Internal operation R/W E Internal signal DB7 IR7 IR3 Instruction write Busy AC3 Busy flag check Not Busy AC3 Busy flag check D7 D3 Instruction write Figure 26 4-Bit Parallel Data Transfer Timing Sequence 51 HD66717 HD66717 RS R/W E 0000 0000 0000 0000 (1) DB7­ DB0 (2) (3) Higher Lower (4) (4-bit data transfer synchronized) R/W RS DB7 DB6 DB5 DB4 0 0 0 0 0 0 wait 10 clock cycles 0 0 0 0 1 0 Return home 0 1st 0 2nd 0 3rd 0 4th wait 10 clock cycles 0 0 0 0 0 wait 10 clock cycles 0 0 0 0 0 wait 10 clock cycles 0 0 0 0 0 wait 10 clock cycles 0 0 0 0 0 wait 10 clock cycles Figure 27 4-Bit Data Transfer Synchronization 52 HD66717 HD66717 Oscillator Circuit The HD66717 HD66717 can either be supplied with operating clock pulses externally (external clock mode) or oscillate using an internal R-C oscillator and an external oscillator-resistor (internal oscillation mode), as shown in Figure 28. An appropriate oscillator-resistor must be used to obtain the optimum clock frequency according to the number of display lines (Table 20). Instruction execution times change in proportion to the operating clock frequency or R-C oscillation frequency; MPU data transfer rate must be appropriately adjusted (see Table 18, Instruction List). Figure 29 shows a sample LCD drive output waveform, where 4lines are displayed with 1/34 multiplexing duty ratio. 1) When an external clock is used Clock OSC1 2) When an internal oscillator is used Rf OSC1 OSC2 HD66717 HD66717 HD66717 HD66717 The oscillator frequency can be adjusted by oscillator resistance (Rf). If Rf is increased or power supply voltage is decreased, the oscillator frequency decreases. Figure 28 Oscillator Circuit Table 20 Oscillation Frequency and LCD Frame Frequency Item 1-Line Display NL1, NL0 = 00 2-Line Display 3-Line Display NL1, NL0 = 01 NL1, NL0 = 10 4-Line Display NL1, NL0 = 11 Multiplexing duty ratio 1/10 1/18 1/26 1/34 620 k 300 k 200 k 150 k CR oscillator frequency 40 kHz 85 kHz 120 kHz 160 kHz Frame frequency 67 Hz 79 Hz 77 Hz 78Hz Oscillator resistance (Rf) VCC = 3V 53 HD66717 HD66717 1-line selection period 1 2 3 4 33 34 1 2 3 33 34 VCC V1 COM1 V4 V5 VCC V1 COM2 V4 V5 VCC V1 COMS2 V4 V5 VCC V1 COMS1 V4 V5 1 frame 1 frame Figure 29 LCD Drive Output Waveform Example (4-line display with 1/34 multiplexing duty ratio) 54 HD66717 HD66717 Power Supply for Liquid Crystal Display Drive When External Power Supply and Internal Operational Amplifiers are Used To supply LCD drive voltage directly from the external power supply without using the internal booster, circuits should be connected as shown in Figure 30. Here, contrast can be adjusted through the CT bits of the contrast-control instruction. The HD66717 HD66717 incorporates a voltage-follower operational amplifier for each of V1 to V5 to reduce current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive voltages. Thus, potential differences between VCC and V1 and between V EE and V5 must be 0.4V or greater. Note that the OPOFF pin must be grounded when using the operational amplifiers. OPOFF = GND HD66717 HD66717 VCC VCC R V2 + ­ V3 R V3 + ­ + ­ R V2 + ­ R R V1 + ­ R V4 SEG1­SEG60 SEG60 LCD multiplexing driver COM1­COM32 COM32 COMS1­COMS2 V5 VR VEE V EE LCD static driver AGND ASEG1­ASEG10 ASEG10 ACOM GND a) 3- or 4-line display with 1/6 bias OPOFF = GND HD66717 HD66717 VCC VCC R Short-circuited V3 R + ­ R V2 + ­ R R R + ­ + ­ + ­ V1 SEG1­SEG60 SEG60 V2 V3 LCD multiplexing driver COM1­COM16 COM16 V4 COMS1­COMS2 V5 VR V EE VEE AGND LCD static driver ASEG1­ASEG10 ASEG10 ACOM GND b) 1- or 2-line display with 1/4 bias Note: 1. Potential differences between VCC and V1 and between V5 and VEE must be 0.4V or greater, particularly for low-duty drive such as 1-line display. 2. When the internal operational amplifiers cannot fully drive the LCD panel used, an appropriate capacitor must be inserted between each output of V1OUT to V5OUT and VCC to stabilize the operational amplifier output. Figure 30 External Power Supply Circuit Example for LCD Drive Voltage Generation 55 HD66717 HD66717 When an Internal Booster and Internal Operational Amplifiers are Used To supply LCD drive voltage using the internal booster, circuits should be connected as shown in Figure 31. Here, contrast can be adjusted through the CT bits of the contrast-control instruction. Temperature can be compensated either through the CT bits or by controlling the reference voltage for the booster (Vci pin) using a thermistor. Note that Vci is both a reference voltage and power supply for the booster; the reference voltage must therefore be adjusted using an emitter-follower or a similar element so that sufficient current can be supplied. In this case, Vci must be equal to or smaller than the V CC level. The HD66717 HD66717 incorporates a voltage-follower operational amplifier for each of V1 to V5 to reduce current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive voltages. Thus, potential differences between VCC and V1 and between V EE and V5 must be 0.4V or greater. Note that the OPOFF pin must be grounded when using the operational amplifiers. b) Triple boosting a) Double boosting OPOF = GND OPOFF = GND VCC VCC HD66717 HD66717 R V2 Short-circuited for 1-or 2-line display R R V3 + ­ + ­ + ­ + ­ + ­ V3 R V2 V2 Short-circuited for 1-or 2-line display V3 R V5 + ­ + ­ V1 + ­ + ­ + ­ V3 R R V4 VR V2 V4 V5 VR VEE Vci Vci C1 C1 0.47 µF C2 to 1 µF + 0.47 µF to 1 µF + C2 Booster GND R R VEE 0.47 µF to 1 µF + HD66717 HD66717 R V1 R R VCC VCC V5OUT2 V5OUT3 V5OUT2 Booster 0.47 µF + to 1 µF GND V5OUT3 + GND Note: 1. The reference voltage input (Vci) must be adjusted so that the output voltage after boosting will not exceed the absolute maximum rating of the liquid-crystal power supply voltage (15V). Particularly, Vci must be 5 V or less for triple boosting. 2. Vci is both a reference voltage and power supply for the booster; connect it to VCC directly or combine it with a transistor so that sufficient current can be obtained. 3. Vci must be smaller than VCC. 4. To operate the voltage-follower correctly, potential differences between VCC and V1 and between V5 and VEE must be 0.4V or greater, particularly for low-duty drive such as 1-line display. 5. Polarized capacitors must be connected correclty. 6. Circuits for temperature compensation should be designed based on the sample circuit shown in Figure 32. Figure 31 Internal Power Supply Circuit Example for LCD Drive Voltage Generation 56 HD66717 HD66717 HD66717 HD66717 VCC VCC Tr Thermistor Vci GND Figure 32 Temperature Compensation Circuit Example 57 HD66717 HD66717 The HD66717 HD66717's internal operational amplifiers have a reduced drive current to save current consumption; when the internal operational amplifiers cannot fully drive the LCD panel used, an appropriate capacitors must be inserted between each output of V1OUT to V5OUT and V CC to stabilize the operational amplifier output (Figure 33). Especially, the capacitors for V1OUT and V4OUT must be inserted when 1/26 duty or 1/34 duty drives. The L version (HD66717L HD66717L) saves the driving current. OPOFF = GND 0.1 µF to 0.5 µF* VCC HD66717 HD66717 VCC + + + + + VCC R + ­ V2 V2OUT V1 + ­ V1OUT V2 R R V3 V3OUT SEG1­SEG60 SEG60 LCD multiplexing driver R + ­ V3 + ­ V4 + ­ V5 COM1­COM32 COM32 R V4OUT COMS1­COMS2 R V5OUT VEE VR Vci C1 0.47 µF to 1 µF + C2 V5OUT2 Booster + 0.47 µF to 1 µF GND V5OUT3 + GND 0.47 µF to 1 µF Note : The capacitors for V1OUT and V4OUT must be inserted when 1/26 duty or 1/34 duty drives. Figure 33 Operational Amplifier Output Stabilization Circuit Example 58 HD66717 HD66717 When 1/10, 1/18-duty drive (1 line, 2 lines) When 1/26, 1/34-duty drive (3 lines, 4 lines) When I EE 15 µA Capacitors for V1OUT to V5OUT must be inserted. Capacitors for V1OUT to V5OUT must be inserted. When 15 µA IEE 40 µA Capacitors for V1OUT and V4OUT Capacitors for V1OUT and V4OUT must be inserted. must be inserted. When I EE 40 µA Capacitors for V1OUT and V4OUT And additional capacitors for other may be inserted after confirming the VnOUTs may be inserted after display quality. confirming the display quality. LCD driving current (IEE)*2 Notes: 1. These relationships between LCD driving current (I EE ) and the external capacitors are applied to designing LCM, but they cannot guarantee the practical display quality. This display quality depends on LCD panel size and LCD material used, and it must be checked and confirmed with your LCD panel. 2. These LCD driving currents (I EE ) depend on the LCD driving voltage between VCC and VEE, and setting of VREF, VREFP and VREFP pins. 3. Especially the capacitors for V1OUT and V4OUT are most efficient for display quality. 4. This condition is an example when the frame frequency is 60Hz to 100Hz. If higher frame frequency is used, these external capacitors should be enhanced to prevent the cross-talk. 59 HD66717 HD66717 When an Internal Booster and External Bleeder-Resistors are Used When the internal operational amplifiers cannot fully drive the LCD panel used, V1 to V5 voltages can be supplied through external bleeder-resistors (Figure 34). Here, the OPOFF pin must be set to the VCC level to turn off the internal operational amplifiers. Since the internal contrast adjuster is disabled in this case, contrast must be adjusted externally. Double- and triple-boosters can be used as they are. OPOFF = VCC VCC VCC HD66717 HD66717 VCC V1OUT + ­ V1 V2OUT + ­ V2 V3OUT + ­ V3 V4OUT + ­ V4 R V5OUT + ­ V5 VR VEE R R 2R R 0.47 µF to 1 µF Vci C1 + C2 V5OUT2 Booster 0.47 µF + to 1 µF GND V5OUT3 0.47 µF + to 1 µF GND Note: 1. Resistance of each external bleeder resistor should be 5 k to 15 k. 2. The bias current value for driving liquid-crystals can be varied by adjusting the resistance (2R) between the V2OUT and V3OUT pins. 3. The internal contrast-adjuster is disabled; contrast must be adjusted either by controlling the external variable resistor between VEE and V5OUT or Vci for the booster. 4. Vci is both a reference voltage and power supply for the booster; connect it to VCC directly or combine it with a transistor so that sufficient current can be obtained. 5. Vci must be smaller than VCC. Figure 34 External Bleeder-Resistor Example for LCD Drive Voltage Generation Power Supply Circuit 60 HD66717 HD66717 Contrast Adjuster Multiplexing Drive System Contrast for an LCD controlled by the multiplexing drive method can be adjusted by varying the liquidcrystal drive voltage (potential difference between V CC and V5) through the CT bits of the contrast control instruction (electron volume function). See Figure 35 and Table 20. The value of a variable resistor (VR) can be adjusted within the range from 0.4R through 6.4R, where R is a reference resistance obtained by dividing the total resistance between VCC and V5. The HD66717 HD66717 incorporates a voltage-follower operational amplifier for each of V1 to V5 to reduce current flowing through the internal bleeder-resistors, which generate different levels of liquid-crystal drive voltages. Thus, potential differences between VCC and V1 and between V EE and V5 must be 0.4V or greater. Note that the OPOFF pin must be grounded when using the operational amplifiers. · 1/6 bias (V2 and V3 pins left open) LCD drive voltage VLCD: 6R × (VCC ­ VEE)/(6R + VR) (VR = a value within the range from 0.4R to 6.4R) VLCD adjustable range: 0.484 × (VCC ­ VEE) VLCD 0.938 × (VCC ­ VEE) Potential difference between VCC and V1: R × (VCC ­ VEE)/(6R + VR) 0.4 (V) Potential difference between V5 and VEE: VR × (VCC ­ VEE)/(6R + VR) 0.4 (V) · 1/4 bias (V2 and V3 pins short-circuited) LCD drive voltage VLCD: 4R × (VCC ­ VEE)/(4R + VR) (VR = a value within the range from 0.4R to 6.4R) VLCD adjustable range: 0.385 × (VCC ­ VEE) VLCD 0.909 × (VCC ­ VEE) Potential difference between VCC and V1: R × (VCC ­ VEE)/(4R + VR) 0.4 (V) Potential difference between V5 and VEE: VR × (VCC ­ VEE)/(4R + VR) 0.4 (V) Static Drive System Contrast for a statically-driven LCD, that is, annunciator display, can be adjusted through the AGND pin. The annunciators are driven statically by the potential difference between V CC and AGND. The AGND pin level must be equal to or greater than the GND level. 61 HD66717 HD66717 HD66717 HD66717 VCC VCC R R V3 V1 + ­ V2 + ­ V3 + ­ V4 V5 R R R VEE + ­ + ­ V2 R VR CT Figure 35 Contrast Adjuster Table 21 Contrast-Adjust Bits (CT) and Variable Resistor Values CT Register CT3 CT2 CT1 CT0 Variable Resistor Value (VR) 0 0 0 0 6.4 R 0 0 0 1 6.0 R 0 0 1 0 5.6 R 0 0 1 1 5.2 R 0 1 0 0 4.8 R 0 1 0 1 4.4 R 0 1 1 0 4.0 R 0 1 1 1 3.6 R 1 0 0 0 3.2 R 1 0 0 1 2.8 R 1 0 1 0 2.4 R 1 0 1 1 2.0 R 1 1 0 0 1.6 R 1 1 0 1 1.2 R 1 1 1 0 0.8 R 1 1 1 1 0.4 R 62 HD66717 HD66717 LCD Module Interface Segment data output pins SEG1 to SEG60 SEG60 can be connected either from left to right or right to left of an LCD panel according to the SFT pin level. When the SFT pin is grounded, SEG1 is connected to the far left of the panel, and when it is at the VCC level, SEG60 SEG60 is connected to the far left. Either connection mode can be selected according to the LCD module layout and routing on a printed-circuit board. Figures 36 shows two examples. 63 HD66717 HD66717 a) 12-character x 3-line display (SEG line above the panel : SFT = GND) SEG60 SEG60 SEG59 SEG59­2 SEG1 COMS1 GND HD66717 HD66717 SFT COM1 ­ COM8 COM9 ­ COM16 COM16 COM17 COM17 ­ COM24 COM24 COMS2 ON MODE 2ndF Clock DATE TIME KEY ACOM ASEG1­ ASEG10 ASEG10 b) 12-character x 4-line display (SEG line below the panel : SFT = VCC) ASEG1­ ASEG10 ASEG10 ACOM VCC HD66717 HD66717 COMS1 SFT COM1 ­ COM8 ON MODE 2ndF Clock DATE TIME KEY COM9 ­ COM16 COM16 COM17 COM17 ­ COM24 COM24 COM25 COM25 ­ COM32 COM32 COMS2 SEG60 SEG60 SEG59 SEG59­2 SEG1 Figure 36 LCD Module Interface Examples 64 HD66717 HD66717 Segment Display and Annunciator Display The HD66717 HD66717 provides both segment display, which is driven by the multiplexing method, and annunciator display, which is driven statically. Annunciator display is driven at a logic operating voltage (V CC ­ AGND) and is thus also available while the LCD drive power supply is turned off. Accordingly, annunciator display is suitable for displaying marks during system standby, when it is desirable to reduce current consumption. It is available in sleep mode, where internal multiplexing operations for character or segment display are halted. If an alternating signal is supplied to the EXM pin, it is also available in standby mode, where the internal R-C oscillator is halted. Here, AGND must be equal to or above the GND level. Note that annunciator display cannot share character display drivers SEG and COM but require special drivers ASEG and ACOM that require long routing. Tables 22 to 24 illustrates segment display and annunciator display. Table 22 Comparison between Segment Display and Annunciator Display Item Segment Display Annunciator Display Number of driven elements 20 each by COMS1 and COMS2 10 Blinking Impossible Possible Segment drivers SEG1­SEG60 SEG60 (shared with character display) ASEG1­ASEG10 ASEG10 (independent of character display) Common drivers COMS1, COMS2 ACOM LCD power supply VCC ­ V5 (LCD power supply necessary) VCC ­ AGND (LCD power supply unnecessary) Normal mode display Display possible together with character display by multiplexing drive Display possible by static drive Sleep mode display Impossible (SEG and COM output VCC) Possible by static drive Standby mode display (without oscillation) Impossible (SEG and COM output VCC) Possible by supplying alternating signal to the EXM pin 65 HD66717 HD66717 Table 23 Correspondence between Segment Display SEGRAM Addresses (ASEG) and Driver Signals ASEG Address Segment Signals LSB MSB Common Signal Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1 0 0 0 COMS1 SEG1/21/41 SEG1/21/41 SEG2/22/42 SEG2/22/42 SEG3/23/43 SEG3/23/43 SEG4/24/44 SEG4/24/44 SEG5/25/45 SEG5/25/45 1 0 0 1 COMS1 SEG6/26/46 SEG6/26/46 SEG7/27/47 SEG7/27/47 SEG8/28/48 SEG8/28/48 SEG9/29/49 SEG9/29/49 SEG10/30/50 SEG10/30/50 1 0 1 0 COMS1 SEG11/31/51 SEG11/31/51 SEG12/32/52 SEG12/32/52 SEG13/33/53 SEG13/33/53 SEG14/34/54 SEG14/34/54 SEG15/35/55 SEG15/35/55 1 0 1 1 COMS1 SEG16/36/56 SEG16/36/56 SEG17/37/57 SEG17/37/57 SEG18/38/58 SEG18/38/58 SEG19/39/59 SEG19/39/59 SEG20/40/60 SEG20/40/60 1 1 0 0 COMS2 SEG1/21/41 SEG1/21/41 SEG2/22/42 SEG2/22/42 SEG3/23/43 SEG3/23/43 SEG4/24/44 SEG4/24/44 SEG5/25/45 SEG5/25/45 1 1 0 1 COMS2 SEG6/26/46 SEG6/26/46 SEG7/27/47 SEG7/27/47 SEG8/28/48 SEG8/28/48 SEG9/29/49 SEG9/29/49 SEG10/30/50 SEG10/30/50 1 1 1 0 COMS2 SEG11/31/51 SEG11/31/51 SEG12/32/52 SEG12/32/52 SEG13/33/53 SEG13/33/53 SEG14/34/54 SEG14/34/54 SEG15/35/55 SEG15/35/55 1 1 1 1 COMS2 SEG16/36/56 SEG16/36/56 SEG17/37/57 SEG17/37/57 SEG18/38/58 SEG18/38/58 SEG19/39/59 SEG19/39/59 SEG20/40/60 SEG20/40/60 Table 24 Correspondence between Annunciator Display Addresses (AAN) and Driver Signals AAN Address Segment Signals LSB MSB Common Signal Bits 7, 6 Bits 5, 4 Bits 3, 2 Bits 1, 0 0 0 0 0 ACOM ASEG1 ASEG2 ASEG3 ASEG4 0 0 0 1 ACOM ASEG5 ASEG6 ASEG7 ASEG8 0 0 1 0 ACOM ASEG9 ASEG10 ASEG10 - - Note: The annunciator is turned on when the corresponding even bit (bit 6, 4, 2, or 0) is 1, and the turnedon annunciator blinks when the corresponding odd bit (bit 7, 5, 3, or 1) is 1. 66 HD66717 HD66717 Annunciator Drive Figure 37 shows annunciator drive output waveforms in two modes. i) Normal mode and sleep mode VCC level VCC level ACOM AGND level VCC level VCC level ASEG1 Display off AGND level VCC level VCC level ASEG2 AGND level Display on 1 frame ii) Standby mode (without oscillation) 1 frame VCC level EXM (Input) VCC level AGND level VCC level VCC level AGND level ACOM VCC level VCC level Display off AGND level ASEG1 VCC level ASEG2 AGND level AGND level Display on Note: If annunciator display is unnecessary during standby mode, make sure to fix the EXM pin to the VCC or GND level and set the annunciator display ON bit (DA) to 0. This will prevent dark display and liquid-cell deterioration due to DC bias application on liquid crystal cells. Figure 37 Annunciator Drive Output Waveforms 67 HD66717 HD66717 Vertical Smooth Scroll The HD66717 HD66717 can scroll in the vertical direction in units of raster-rows. This function is achieved by writing character codes into the DDRAM area that is not being used for display. In other words, since the DDRAM corresponds to a 5-line × 12-character display, one of the lines can be used to achieve continuous smooth vertical scroll even in a 4-line display. Here, after the fifth line is displayed, the first line is displayed again. Specifically, this function is controlled by incrementing or decrementing the value in the scroll-start line bits (SL2 to SL0) and scroll-start raster-row bits (SN2 to SN0) by 1. For example, to smoothly scroll up, first set SN2 to SN0 to 000, and increment SL2 to SL0 by 1 from 000 to 111 to scroll seven raster-rows. Then increment SN2 to SN0 to 001, and again increment SL2 to SL0 by 1 from 000 to 111. To start displaying and scrolling from the first raster-row of the second line, update the first line of DDRAM data as desired during its non-display period. Figure 38 shows an example of vertical smooth scrolling and Figure 39 shows an example of setting instructions for vertically scrolling upward in a 4-line display (NL1 and NL0 = 11). 68 HD66717 HD66717 Set initial data to all DDRAM addresses 1) Not scrolled · SN2­0 = 000 · SL2­0 = 000 9) 8 raster-row scrolled up · SN2­0 = 001 · SL2­0 = 000 Update the first line of DDRAM data 2) 1 raster-row scrolled up 10) 9 raster-row scrolled up · SL2­0 = 001 · SL2­0 = 001 3) 2 raster-row scrolled up 11) 10 raster-row scrolled up · SL2­0 = 010 · SL2­0 = 010 4) 3 raster-row scrolled up 12) 11 raster-row scrolled up · SL2­0 = 011 · SL2­0 = 011 5) 4 raster-row scrolled up 13) 12 raster-row scrolled up · SL2­0 = 100 · SL2­0 = 100 6) 5 raster-row scrolled up 14) 13 raster-row scrolled up · SL2­0 = 101 · SL2­0 = 101 7) 6 raster-row scrolled up 15) 14 raster-row scrolled up · SL2­0 = 110 · SL2­0 = 110 8) 7 raster-row scrolled up 16) 15 raster-row scrolled up · SL2­0 = 111 · SL2­0 = 111 Figure 38 Example of Vertical Smooth Scrolling 69 HD66717 HD66717 Scroll up display R/W RS DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 1 0 0 0 0 1 1 0 CT 0 0 0 SN2= 0 0 SN1/0 = 00 and SL2­SL0 = 000 (1st raster-row of 1st line displayed at the top) Set initial character codes of 5 lines to all DDRAM addresses 0 0 0 1 1 0 0 0 0 1 Scroll up 1 raster-row (2nd raster-row of 1st line displayed at the top) 0 1 0 Scroll up 2 raster-rows (3rd raster-row of 1st line displayed at the top) 0 1 1 Scroll up 3 raster-rows (4th raster-row of 1st line displayed at the top) 1 0 0 Scroll up 4 raster-rows (5th raster-row of 1st line displayed at the top) 1 1 1 Scroll up 7 raster-rows (8th raster-row of 1st line displayed at the top) 0 0 0 Scroll up 8 raster-rows (1st raster-row of 2nd line displayed at the top) CPU Wait 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 CPU Wait 1 0 0 CPU Wait 1 0 0 CPU Wait 0 0 0 1 1 0 0 CPU Wait 0 0 0 1 1 0 1 CPU Wait Update 1st-line (address 00H to 1BH) character co