H8/3397 HD6433397 H8/3396 HD6433396 H8/3394 HD6433394 H8/3337 H8/3337Y - Datasheet Archive

 

H8/3397 Series H8/3397 HD6433397 H8/3396 HD6433396 H8/3394 HD6433394 H8/3337 Series H8/3337Y HD6473337Y, HD6433337Y H8/3336Y

 

Hitachi Single­Chip Microcomputer H8/3397 H8/3397 Series H8/3397 H8/3397 HD6433397 HD6433397 H8/3396 H8/3396 HD6433396 HD6433396 H8/3394 H8/3394 HD6433394 HD6433394 H8/3337 H8/3337 Series H8/3337Y H8/3337Y HD6473337Y HD6473337Y, HD6433337Y HD6433337Y H8/3336Y H8/3336Y HD6433336Y HD6433336Y H8/3334Y H8/3334Y HD6473334Y HD6473334Y, HD6433334Y HD6433334Y H8/3337W H8/3337W HD6433337W HD6433337W H8/3336W H8/3336W HD6433336W HD6433336W H8/3337YF-ZTATTM H8/3337YF-ZTATTM HD64F3337Y HD64F3337Y H8/3337SF-ZTATTM H8/3337SF-ZTATTM HD64F3337S HD64F3337S H8/3334YF-ZTATTM H8/3334YF-ZTATTM HD64F3334Y HD64F3334Y Hardware Manual ADE-602-078D ADE-602-078D Rev. 5.0 2/01/99 Hitachi, Ltd. Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products. Notes on S-Mask Model (Single-Power-Supply Specification) There are two versions of the H8/3337F H8/3337F with on-chip flash memory: a dual-power-supply version and a single-power-supply (S-mask) version. Points to be noted when using the H8/3337F H8/3337F singlepower-supply S-mask model are given below. 1. Notes on Voltage Application 12 V must not be applied to the S-mask model (single-power-supply specification), as this may permanently damage the device. The flash memory programming power supply for the S-mask model (single-power-supply specification) is VCC. The programming power supply for the dual-power-supply model is the FVPP pin (12 V), but the single-power-supply model (S-mask model) does not have an FVPP pin. Also, in boot mode, 12 V has to be applied to the MD1 pin in the dual-power-supply model, but 12 V application is not necessary in the single-power-supply model (S-mask model). The maximum rating of the MD1 pin is VCC +0.3 V. Applying a voltage in excess of the maximum rating will permanently damage the device. Do not select the HN28F101 HN28F101 programmer setting for the S-mask model (single-power-supply specification). If this setting is made by mistake, 12 V will be applied to the STBY pin, possibly causing permanent damage to the device. When using a PROM programmer to program the on-chip flash memory in the S-mask model (single-power-supply specification), use a PROM programmer that supports Hitachi microcomputer devices with 64-kbyte on-chip flash memory. Also, only use the specified socket adapter. Using the wrong PROM programmer or socket adapter may damage the device. The following PROM programmers support the S-mask model (single-power-supply specification). DATA I/O: UNISITE, 2900, 3900, etc. Minato: 1892, 1891, 1890, etc. 2. Product Type Names and Markings Table 1 shows examples of product type names and markings for the H8/3337YF H8/3337YF (dual-powersupply specification) and H8/3337SF H8/3337SF (single-power-supply specification), and the differences in flash memory programming power supply. Table 1 Differences in H8/3337YF H8/3337YF and H8/3337F H8/3337F S-Mask Model Markings Dual-Power-Supply Model: H8/3337YF H8/3337YF Product type name Single-Power-Supply Model: H8/3337F H8/3337F S-Mask Model HD64F3337YF16/TF16 HD64F3337YF16/TF16 HD64F3337SF16/TF16 HD64F3337SF16/TF16 Sample markings H8/3337 H8/3337 8M3 HD 64F3337F16 64F3337F16 JAPAN H8/3337 H8/3337 8M3 S HD 64F3337F16 64F3337F16 JAPAN "S" is printed above the type name Flash memory programming power supply VPP power supply VCC power supply (12.0 V ±0.6 V) (5.0 V ±10%) 3. Differences in S-Mask Model Table 2 shows the differences between the H8/3337F H8/3337F (dual-power-supply specification) and H8/3337SF H8/3337SF (single-power-supply specification). Table 2 Differences between H8/3337F H8/3337F and H8/3337F H8/3337F S-Mask Model Item Program/ erase voltage Dual-Power-Supply Model: H8/3337F H8/3337F Single-Power-Supply Model: H8/3337F H8/3337F S-Mask Model 12 V must be applied from off-chip 12 V application not required VPP (12.0 V ±0.6 V) VCC single-power-supply programming VCC (5.0 V ±10%) FV PP (FWE) pin function Dual function as FV PP power supply and STBY function No programming control pin Programming modes · · Writer mode On-board Boot mode User programming mode (See section 21 for the use of these modes) Writer mode (See section 21 for the use of these modes) Operating · modes allowing · on-board · programming Boot mode User programming mode On-board programming unit 1-byte-unit programming 32-byte-unit programming Programming with PROM programmer Select Hitachi stand-alone flash memory HN28F101 HN28F101 setting Special programming mode setting required. Use of PROM programmer that supports Hitachi microcomputer device types with 64-kbyte on-chip flash memory. (128-byte-unit fast page programming) Boot mode setting method Reset release after MD 1 = FVPP /STBY = 12 V application Pin Setting level MD1 MD0 P92 0 0 1 P91 P90 1 1 Reset release after above pin settings User program mode setting method FV PP = 12 V application Control bits set by software Table 2 Differences between H8/3337F H8/3337F and H8/3337F H8/3337F S-Mask Model (cont) Item Dual-Power-Supply Model: H8/3337F H8/3337F Single-Power-Supply Model: H8/3337F H8/3337F S-Mask Model Programming mode timing RES RES MD0 MD1, MD1 tMDS tMDS MD1 12 V Min 0 µs 12 V VPP P92, P91, P90 tMDS: 4tcyc (min.) tMDS: 4tcyc (min.) Prewrite processing Required before erasing Not required Programming processing Block corresponding to programming address must be set in EBR1/EBR2 registers before programming Settings at left not required EBR register configuration EBR1, EBR2 EBR2 Memory map (block configuration) SB0 (128 bytes) EB0 (1 kbyte) SB1 (128 bytes) EB1 (1 kbyte) SB2 (128 bytes) SB3 (128 bytes) EB2 (1 kbyte) SB4 (512 bytes) EB3 (1 kbyte) SB5 (1 kbyte) SB6 (1 kbyte) SB7 (1 kbyte) LB0 (4 kbytes) 60 kbytes EB4 (24 kbytes) 60 kbytes LB1(8 kbytes) LB2 (8 kbytes) LB3 (8 kbytes) LB4 (8 kbytes) EB5 (16 kbytes) LB5 (8 kbytes) EB6 (12 kbytes) LB6 (12 kbytes) LB7 (2 kbytes) Reset during operation Drive RES pin low for at least 10 system clock cycles (10ø). (RES pulse width tRESW = min. 10tcyc) EB7 (2 kbytes) Drive RES pin low for at least 20 system clock cycles (20ø). (RES pulse width tRESW = min. 20tcyc) Table 2 Differences between H8/3337F H8/3337F and H8/3337F H8/3337F S-Mask Model (cont) Item MDCR Dual-Power-Supply Model: H8/3337F H8/3337F 7 - 6 - 5 - 4 - 3 - 2 - Single-Power-Supply Model: H8/3337F H8/3337F S-Mask Model 1 0 MDS1 MDS0 7 EXPE 6 - 5 - 4 - 3 - 2 - 1 0 MDS1 MDS0 Bit 7: Expanded mode enable (EXPE) WSCR 7 6 5 RAMS RAM0 CKDBL 4 - 3 2 1 0 WMS1WMS0 WC1 WC0 7 - 6 - 5 4 3 2 1 0 CKDBL FLSHE WMS1 WMS0 WC1 WC0 Bit 4: Flash memory control register enable (FLSHE) FLMCR1 7 VPP 6 - 5 - 4 - 3 EV 2 PV 1 E 0 P 7 6 FWE SWE 5 - 4 - 3 EV 2 PV 1 E 0 P Bit 7: Flash write enable (FWE) Bit 6: Software write enable (SWE) FLMCR2 - 7 FLER 6 - 5 - 4 - 3 - 2 - 1 ESU 0 PSU Bit 7: Flash memory error (FLER) Bit 1: Erase setup (ESU) Bit 0: Program setup (PSU) EBR1 7 LB7 6 LB6 5 LB5 4 LB4 3 LB3 2 LB2 1 LB1 0 LB0 EBR2 7 SB7 6 SB6 5 SB5 4 SB4 3 SB3 2 SB2 1 SB1 0 SB0 - This address is not used. 7 EB7 6 EB6 5 EB5 4 EB4 3 EB3 2 EB2 1 EB1 0 EB0 Erase block register (EBR2) EB0 (1 kbyte): H'0000 to H'03FF EB1 (1 kbyte): H'0400 to H'07FF EB2 (1 kbyte): H'0800 to H'0BFF EB3 (1 kbyte): H'0C00 to H'0FFF EB4 (28 kbytes): H'1000 to H'7FFF EB5 (16 kbytes): H'8000 to H'BFFF EB6 (12 kbytes): H'C000 to H'EF7F EB7 (2 kbytes): H'EF00 to H'F77F Details concerning flash memory See section 20, ROM (Dual-PowerSupply 60-Kbyte Flash Memory Version) See section 21, ROM (Single-PowerSupply 60-Kbyte Flash Memory Version) Electrical characteristics See section 23, Electrical Characteristics See section 23, Electrical Characteristics Registers See Appendix B, Registers See Appendix B, Registers Table 3 shows differences in the development environments of the H8/3337YF H8/3337YF (dual-powersupply specification) and H8/3337SF H8/3337SF (single-power-supply specification). Table 3 H8/3337YF H8/3337YF and H8/3337F H8/3337F S-Mask Model Development Environments Dual-Power-Supply Model: H8/3337YF H8/3337YF Item E6000 E6000 Emulator Hitachi emulator unit HS3008EPI60H HS3008EPI60H User cable Single-Power-Supply Model: H8/3337F H8/3337F S-Mask Model Hitachi HS3008EPI60H HS3008EPI60H Hitachi HS3437ECH61H HS3437ECH61H Hitachi HS3437ECH61H HS3437ECH61H Programming socket adapter Hitachi HS3434ESHF1H HS3434ESHF1H Minato DATA I/O Adapter board Hitachi HS0008EASF1H/2H HS0008EASF1H/2H Hitachi HS0008EASF3H HS0008EASF3H Windows interface software Hitachi HS6400FWIW2SF HS6400FWIW2SF Hitachi HS6400FWIW2SF HS6400FWIW2SF Table 4 shows differences in the pin settings of the H8/3337YF H8/3337YF (dual-power-supply specification) and H8/3337SF H8/3337SF (single-power-supply specification). Table 4 H8/3337YF H8/3337YF and H8/3337F H8/3337F S-Mask Model Pin Settings Item Dual-Power-Supply Model: H8/3337YF H8/3337YF Boot mode Single-Power-Supply Model: H8/3337F H8/3337F S-Mask Model H8/3337SF H8/3337SF H8/3337YF H8/3337YF VCC (5 V) 12 V 8 FVPP/STBY 5 23 24 25 MD1 VSS (GND) User programming mode H8/3337YF H8/3337YF 12 V 8 FVPP/STBY P92 P91 P90 5 6 MD1 MD0 There are no state transitions due to pin states. Transitions should be implemented by means of register settings by software. Preface The H8/3337 H8/3337 Series and H8/3397 H8/3397 Series are series of high-performance microcontrollers with a fast H8/300 H8/300 CPU core and a set of on-chip supporting functions optimized for embedded control. These include ROM, RAM, four types of timers, a serial communication interface, I 2C bus interface, host interface, A/D converter, D/A converter, I/O ports, and other functions needed in control system configurations, so that compact, high-performance systems can be implemented easily. The H8/3397 H8/3397 Series is a subset of the H8/3337 H8/3337 Series and does not include a host interface and D/A converter. H8/3337 H8/3337 Series includes the H8/3337Y H8/3337Y with 60-kbyte ROM and 2-kbyte RAM, the H8/3336Y H8/3336Y with 48-kbyte ROM and 2-kbyte RAM, and the H8/3334Y H8/3334Y with 32-kbyte ROM and 1-kbyte RAM. H8/3397 H8/3397 Series includes the H8/3397 H8/3397 with 60-kbyte ROM and 2-kbyte RAM, the H8/3396 H8/3396 with 48-kbyte ROM and 2-kbyte RAM, and the H8/3394 H8/3394 with 32-kbyte ROM and 1-kbyte RAM. The H8/3337Y H8/3337Y, and H8/3334Y H8/3334Y are available in mask-ROM versions and in ZTATTM *1 (zero turnaround time) versions, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently-changing specifications. In addition, the H8/3334Y H8/3334Y and H8/3337Y H8/3337Y have an F-ZTATTM*2 (flexible-ZTAT) version with on-board programmability. This manual describes the hardware of the H8/3337 H8/3337 Series and H8/3397 H8/3397 Series. Refer to the H8/300 H8/300 Series Programming Manual for a detailed description of the instruction set. Notes: 1. ZTAT is a trademark of Hitachi, Ltd. 2. F-ZTAT is a trademark of Hitachi, Ltd. Contents Section 1 1.1 1.2 1.3 Overview . Overview. Block Diagram. Pin Assignments and Functions. 1.3.1 Pin Arrangement . 1.3.2 Pin Functions. 1 1 6 8 8 12 Section 2 CPU . 25 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Overview. 2.1.1 Features . 2.1.2 Address Space . 2.1.3 Register Configuration . Register Descriptions. 2.2.1 General Registers. 2.2.2 Control Registers. 2.2.3 Initial Register Values . Data Formats. 2.3.1 Data Formats in General Registers. 2.3.2 Memory Data Formats. Addressing Modes . 2.4.1 Addressing Mode. 2.4.2 Calculation of Effective Address. Instruction Set. 2.5.1 Data Transfer Instructions . 2.5.2 Arithmetic Operations . 2.5.3 Logic Operations . 2.5.4 Shift Operations. 2.5.5 Bit Manipulations . 2.5.6 Branching Instructions. 2.5.7 System Control Instructions . 2.5.8 Block Data Transfer Instruction . CPU States . 2.6.1 Overview . 2.6.2 Program Execution State . 2.6.3 Exception-Handling State . 2.6.4 Power-Down State. Access Timing and Bus Cycle. 2.7.1 Access to On-Chip Memory (RAM and ROM) . 2.7.2 Access to On-Chip Supporting Modules and External Devices . 25 25 26 26 27 27 27 28 29 30 31 32 32 34 38 40 42 43 44 45 50 52 53 55 55 56 56 57 57 57 59 i Section 3 MCU Operating Modes and Address Space . 63 3.1 3.2 3.3 3.4 Overview. 63 3.1.1 Mode Selection. 63 3.1.2 Mode and System Control Registers . 63 System Control Register (SYSCR). 64 Mode Control Register (MDCR) . 66 Address Space Map in Each Operating Mode. 66 Section 4 Exception Handling . 71 4.1 4.2 4.3 4.4 Overview. 71 Reset . 71 4.2.1 Overview . 71 4.2.2 Reset Sequence. 71 4.2.3 Disabling of Interrupts after Reset . 74 Interrupts. 74 4.3.1 Overview . 74 4.3.2 Interrupt-Related Registers . 76 4.3.3 External Interrupts. 80 4.3.4 Internal Interrupts . 80 4.3.5 Interrupt Handling . 81 4.3.6 Interrupt Response Time . 86 4.3.7 Precaution . 86 Note on Stack Handling. 87 Section 5 Wait-State Controller . 89 5.1 5.2 5.3 Overview. 89 5.1.1 Features . 89 5.1.2 Block Diagram. 89 5.1.3 Input/Output Pins. 90 5.1.4 Register Configuration . 90 Register Description . 90 5.2.1 Wait-State Control Register (WSCR) . 90 Wait Modes. 92 Section 6 Clock Pulse Generator . 95 6.1 6.2 6.3 6.4 ii Overview. 6.1.1 Block Diagram. 6.1.2 Wait-State Control Register (WSCR) . Oscillator Circuit . Duty Adjustment Circuit. Prescaler . 95 95 96 97 101 101 Section 7 I/O Ports . 103 7.1 7.2 Overview. Port 1. 7.2.1 Overview . 7.2.2 Register Configuration and Descriptions . 7.2.3 Pin Functions in Each Mode . 7.2.4 Input Pull-Up Transistors . 7.3 Port 2. 7.3.1 Overview . 7.3.2 Register Configuration and Descriptions . 7.3.3 Pin Functions in Each Mode . 7.3.4 Input Pull-Up Transistors . 7.4 Port 3. 7.4.1 Overview . 7.4.2 Register Configuration and Descriptions . 7.4.3 Pin Functions in Each Mode . 7.4.4 Input Pull-Up Transistors . 7.5 Port 4. 7.5.1 Overview . 7.5.2 Register Configuration and Descriptions . 7.5.3 Pin Functions. 7.6 Port 5. 7.6.1 Overview . 7.6.2 Register Configuration and Descriptions . 7.6.3 Pin Functions. 7.7 Port 6. 7.7.1 Overview . 7.7.2 Register Configuration and Descriptions . 7.7.3 Pin Functions. 7.7.4 Input Pull-Up Transistors . 7.8 Port 7. 7.8.1 Overview . 7.8.2 Register Configuration and Descriptions. 7.9 Port 8. 7.9.1 Overview . 7.9.2 Register Configuration and Descriptions . 7.9.3 Pin Functions. 7.10 Port 9. 7.10.1 Overview . 7.10.2 Register Configuration and Descriptions . 7.10.3 Pin Functions. 103 108 108 109 111 113 114 114 115 117 119 119 119 121 123 125 125 125 127 129 131 131 131 133 134 134 134 137 139 140 140 140 141 141 142 144 147 147 148 150 iii Section 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 16-Bit Free-Running Timer . Overview. 8.1.1 Features . 8.1.2 Block Diagram. 8.1.3 Input and Output Pins. 8.1.4 Register Configuration . Register Descriptions. 8.2.1 Free-Running Counter (FRC). 8.2.2 Output Compare Registers A and B (OCRA and OCRB). 8.2.3 Input Capture Registers A to D (ICRA to ICRD) . 8.2.4 Timer Interrupt Enable Register (TIER) . 8.2.5 Timer Control/Status Register (TCSR) . 8.2.6 Timer Control Register (TCR) . 8.2.7 Timer Output Compare Control Register (TOCR) . CPU Interface . Operation . 8.4.1 FRC Increment Timing . 8.4.2 Output Compare Timing . 8.4.3 FRC Clear Timing. 8.4.4 Input Capture Timing . 8.4.5 Timing of Input Capture Flag (ICF) Setting . 8.4.6 Setting of Output Compare Flags A and B (OCFA and OCFB) . 8.4.7 Setting of Timer Overflow Flag (OVF). Interrupts. Sample Application . Application Notes. Section 9 9.1 9.2 9.3 iv 8-Bit Timers . Overview. 9.1.1 Features . 9.1.2 Block Diagram. 9.1.3 Input and Output Pins. 9.1.4 Register Configuration . Register Descriptions. 9.2.1 Timer Counter (TCNT) . 9.2.2 Time Constant Registers A and B (TCORA and TCORB). 9.2.3 Timer Control Register (TCR) . 9.2.4 Timer Control/Status Register (TCSR) . 9.2.5 Serial/Timer Control Register (STCR) . Operation . 9.3.1 TCNT Increment Timing. 9.3.2 Compare-Match Timing . 9.3.3 External Reset of TCNT. 153 153 153 154 155 156 157 157 157 158 160 162 164 166 168 171 171 173 174 174 177 177 178 179 180 181 187 187 187 188 189 189 190 190 190 191 194 196 197 197 199 201 9.4 9.5 9.6 9.3.4 Setting of Overflow Flag (OVF) . Interrupts. Sample Application . Application Notes. 9.6.1 Contention between TCNT Write and Clear . 9.6.2 Contention between TCNT Write and Increment . 9.6.3 Contention between TCOR Write and Compare-Match . 9.6.4 Contention between Compare-Match A and Compare-Match B . 9.6.5 Increment Caused by Changing of Internal Clock Source . 201 202 202 203 203 204 205 206 206 Section 10 PWM Timers. 209 10.1 Overview. 10.1.1 Features . 10.1.2 Block Diagram. 10.1.3 Input and Output Pins. 10.1.4 Register Configuration . 10.2 Register Descriptions. 10.2.1 Timer Counter (TCNT) . 10.2.2 Duty Register (DTR) . 10.2.3 Timer Control Register (TCR) . 10.3 Operation . 10.3.1 Timer Incrementation . 10.3.2 PWM Operation. 10.4 Application Notes. 209 209 210 210 211 211 211 212 213 215 215 216 217 Section 11 Watchdog Timer . 219 11.1 Overview. 11.1.1 Features . 11.1.2 Block Diagram. 11.1.3 Register Configuration . 11.2 Register Descriptions. 11.2.1 Timer Counter (TCNT) . 11.2.2 Timer Control/Status Register (TCSR) . 11.2.3 System Control Register (SYSCR) . 11.2.4 Register Access . 11.3 Operation . 11.3.1 Watchdog Timer Mode . 11.3.2 Interval Timer Mode . 11.3.3 Setting the Overflow Flag . 11.4 Application Notes. 11.4.1 Contention between TCNT Write and Increment . 11.4.2 Changing the Clock Select Bits (CKS2 to CKS0). 11.4.3 Recovery from Software Standby Mode . 219 219 220 220 221 221 221 223 224 225 225 226 226 227 227 227 227 v 11.4.4 Switching between Watchdog Timer Mode and Interval Timer Mode. 228 11.4.5 Detection of Program Runaway . 228 Section 12 Serial Communication Interface . 229 12.1 Overview. 12.1.1 Features . 12.1.2 Block Diagram. 12.1.3 Input and Output Pins. 12.1.4 Register Configuration . 12.2 Register Descriptions. 12.2.1 Receive Shift Register (RSR). 12.2.2 Receive Data Register (RDR) . 12.2.3 Transmit Shift Register (TSR). 12.2.4 Transmit Data Register (TDR) . 12.2.5 Serial Mode Register (SMR). 12.2.6 Serial Control Register (SCR). 12.2.7 Serial Status Register (SSR). 12.2.8 Bit Rate Register (BRR). 12.2.9 Serial/Timer Control Register (STCR) . 12.3 Operation . 12.3.1 Overview . 12.3.2 Asynchronous Mode . 12.3.3 Synchronous Mode. 12.4 Interrupts. 12.5 Application Notes. 229 229 230 231 232 233 233 233 233 234 234 236 239 242 252 253 253 255 268 274 274 Section 13 I2C Bus Interface (H8/3337 H8/3337 Series Only) [Option] . 277 13.1 Overview. 13.1.1 Features . 13.1.2 Block Diagram. 13.1.3 Input/Output Pins. 13.1.4 Register Configuration . 13.2 Register Descriptions. 13.2.1 I2C Bus Data Register (ICDR). 13.2.2 Slave Address Register (SAR) . 13.2.3 I2C Bus Mode Register (ICMR) . 13.2.4 I2C Bus Control Register (ICCR) . 13.2.5 I2C Bus Status Register (ICSR). 13.2.6 Serial/Timer Control Register (STCR) . 13.3 Operation . 13.3.1 I2C Bus Data Format. 13.3.2 Master Transmit Operation . 13.3.3 Master Receive Operation . vi 277 277 279 280 280 281 281 281 282 283 286 290 291 291 292 294 13.3.4 Slave Transmit Operation. 13.3.5 Slave Receive Operation . 13.3.6 IRIC Set Timing and SCL Control. 13.3.7 Noise Canceler. 13.3.8 Sample Flowcharts . 13.4 Application Notes. 296 298 299 300 301 305 Section 14 Host Interface (H8/3337 H8/3337 Series Only) . 307 14.1 Overview. 14.1.1 Block Diagram. 14.1.2 Input and Output Pins. 14.1.3 Register Configuration . 14.2 Register Descriptions. 14.2.1 System Control Register (SYSCR) . 14.2.2 Host Interface Control Register (HICR) . 14.2.3 Input Data Register 1 (IDR1) . 14.2.4 Output Data Register 1 (ODR1) . 14.2.5 Status Register 1 (STR1). 14.2.6 Input Data Register 2 (IDR2) . 14.2.7 Output Data Register 2 (ODR2) . 14.2.8 Status Register 2 (STR2). 14.2.9 Serial/Timer Control Register (STCR) . 14.3 Operation . 14.3.1 Host Interface Operation . 14.3.2 Control States . 14.3.3 A20 Gate . 14.4 Interrupts. 14.4.1 IBF1, IBF2. 14.4.2 HIRQ11 HIRQ11, HIRQ1, and HIRQ12 HIRQ12 . 14.5 Application Note. 307 308 309 310 311 311 311 312 313 313 314 315 315 317 318 318 318 319 322 322 322 323 Section 15 A/D Converter . 325 15.1 Overview. 15.1.1 Features . 15.1.2 Block Diagram. 15.1.3 Input Pins. 15.1.4 Register Configuration . 15.2 Register Descriptions. 15.2.1 A/D Data Registers A to D (ADDRA to ADDRD). 15.2.2 A/D Control/Status Register (ADCSR). 15.2.3 A/D Control Register (ADCR). 15.3 CPU Interface . 15.4 Operation . 325 325 326 327 328 329 329 330 332 332 334 vii 15.4.1 Single Mode (SCAN = 0) . 15.4.2 Scan Mode (SCAN = 1) . 15.4.3 Input Sampling and A/D Conversion Time. 15.4.4 External Trigger Input Timing . 15.5 Interrupts. 15.6 Useage Notes . 15.6.1 Setting Ranges of Analog Power Supply Pins, Etc. . 15.6.2 Notes on Board Design . 15.6.3 Notes on Noise . 15.6.4 A/D Conversion Accuracy Definitions . 15.6.5 Allowable Signal-Source Impedance . 15.6.6 Effect on Absolute Accuracy. 334 336 338 339 340 340 340 340 340 341 343 344 Section 16 D/A Converter (H8/3337 H8/3337 Series Only) . 345 16.1 Overview. 16.1.1 Features . 16.1.2 Block Diagram. 16.1.3 Input and Output Pins. 16.1.4 Register Configuration . 16.2 Register Descriptions. 16.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) . 16.2.2 D/A Control Register (DACR). 16.3 Operation . 345 345 346 347 347 348 348 348 350 Section 17 RAM . 351 17.1 Overview. 17.1.1 Block Diagram. 17.1.2 RAM Enable Bit (RAME) in System Control Register (SYSCR) . 17.2 Operation . 17.2.1 Expanded Modes (Modes 1 and 2). 17.2.2 Single-Chip Mode (Mode 3) . 351 351 352 352 352 352 Section 18 ROM (Mask ROM Version/ZTAT Version). 353 18.1 Overview. 18.1.1 Block Diagram. 18.2 Writer Mode (H8/3337Y H8/3337Y, H8/3334Y H8/3334Y) . 18.2.1 Writer Mode Setup . 18.2.2 Socket Adapter Pin Assignments and Memory Map . 18.3 PROM Programming . 18.3.1 Programming and Verification . 18.3.2 Notes on Programming. 18.3.3 Reliability of Programmed Data . 18.3.4 Erasing Data . viii 353 354 354 354 355 358 358 363 363 364 18.4 Handling of Windowed Packages. 18.4.1 Glass Erasing Window . 18.4.2 Handling after Programming. 18.4.3 84-Pin LCC Package . 365 365 365 365 Section 19 ROM (32-Kbyte Dual-Power-Supply Flash Memory Version) . 367 19.1 Flash Memory Overview . 19.1.1 Flash Memory Operating Principle . 19.1.2 Mode Programming and Flash Memory Address Space. 19.1.3 Features . 19.1.4 Block Diagram. 19.1.5 Input/Output Pins. 19.1.6 Register Configuration . 19.2 Flash Memory Register Descriptions . 19.2.1 Flash Memory Control Register (FLMCR). 19.2.2 Erase Block Register 1 (EBR1). 19.2.3 Erase Block Register 2 (EBR2). 19.2.4 Wait-State Control Register (WSCR) . 19.3 On-Board Programming Modes . 19.3.1 Boot Mode. 19.3.2 User Programming Mode . 19.4 Programming and Erasing Flash Memory. 19.4.1 Program Mode. 19.4.2 Program-Verify Mode . 19.4.3 Programming Flowchart and Sample Program . 19.4.4 Erase Mode. 19.4.5 Erase-Verify Mode . 19.4.6 Erasing Flowchart and Sample Program . 19.4.7 Prewrite Verify Mode. 19.4.8 Protect Modes. 19.4.9 Interrupt Handling during Flash Memory Programming and Erasing . 19.5 Flash Memory Emulation by RAM . 19.6 Flash Memory Writer Mode (H8/3334YF H8/3334YF) . 19.6.1 Writer Mode Setting . 19.6.2 Socket Adapter and Memory Map . 19.6.3 Operation in Writer Mode . 19.7 Flash Memory Programming and Erasing Precautions . 367 367 368 368 369 370 370 371 371 372 373 374 377 378 384 386 386 387 388 390 390 391 404 404 405 407 410 410 410 412 420 Section 20 ROM (60-Kbyte Dual-Power-Supply Flash Memory Version) . 427 20.1 Flash Memory Overview . 20.1.1 Flash Memory Operating Principle . 20.1.2 Mode Programming and Flash Memory Address Space. 20.1.3 Features . 427 427 428 428 ix 20.2 20.3 20.4 20.5 20.6 20.7 20.1.4 Block Diagram. 20.1.5 Input/Output Pins. 20.1.6 Register Configuration . Flash Memory Register Descriptions . 20.2.1 Flash Memory Control Register (FLMCR). 20.2.2 Erase Block Register 1 (EBR1). 20.2.3 Erase Block Register 2 (EBR2). 20.2.4 Wait-State Control Register (WSCR) . On-Board Programming Modes . 20.3.1 Boot Mode. 20.3.2 User Programming Mode . Programming and Erasing Flash Memory. 20.4.1 Program Mode. 20.4.2 Program-Verify Mode . 20.4.3 Programming Flowchart and Sample Program . 20.4.4 Erase Mode. 20.4.5 Erase-Verify Mode . 20.4.6 Erasing Flowchart and Sample Program . 20.4.7 Prewrite Verify Mode. 20.4.8 Protect Modes. 20.4.9 Interrupt Handling during Flash Memory Programming and Erasing . Flash Memory Emulation by RAM . Flash Memory Writer Mode (H8/3337YF H8/3337YF) . 20.6.1 Writer Mode Setting . 20.6.2 Socket Adapter and Memory Map . 20.6.3 Operation in Writer Mode . Flash Memory Programming and Erasing Precautions . 429 430 430 431 431 432 433 434 437 438 444 446 446 447 448 450 450 451 464 464 465 467 470 470 470 472 480 Section 21 ROM (60-Kbyte Single-Power-Supply Flash Memory Version) . 489 21.1 Flash Memory Overview . 21.1.1 Mode Pin Settings and ROM Space . 21.1.2 Features . 21.1.3 Block Diagram. 21.1.4 Input/Output Pins. 21.1.5 Register Configuration . 21.1.6 Mode Control Register (MDCR). 21.1.7 Flash Memory Operating Modes. 21.2 Flash Memory Register Descriptions . 21.2.1 Flash Memory Control Register 1 (FLMCR1). 21.2.2 Flash Memory Control Register 2 (FLMCR2). 21.2.3 Erase Block Register 2 (EBR2). 21.2.4 Wait-State Control Register (WSCR) . x 489 489 490 491 492 492 493 494 498 498 500 501 502 21.3 On-Board Programming Modes . 21.3.1 Boot Mode. 21.3.2 User Programming Mode . 21.4 Programming and Erasing Flash Memory. 21.4.1 Program Mode. 21.4.2 Program-Verify Mode . 21.4.3 Erase Mode. 21.4.4 Erase-Verify Mode . 21.4.5 Protect Modes. 21.4.6 Interrupt Handling during Flash Memory Programming and Erasing . 21.5 Flash Memory Writer Mode (H8/3437SF H8/3437SF). 21.5.1 Writer Mode Setting . 21.5.2 Socket Adapter and Memory Map. 21.5.3 Operation in Writer Mode . 21.6 Flash Memory Programming and Erasing Precautions . 503 503 509 510 510 511 513 513 515 517 518 518 518 519 530 Section 22 Power-Down State. 533 22.1 Overview. 22.1.1 System Control Register (SYSCR) . 22.2 Sleep Mode. 22.2.1 Transition to Sleep Mode . 22.2.2 Exit from Sleep Mode . 22.3 Software Standby Mode . 22.3.1 Transition to Software Standby Mode. 22.3.2 Exit from Software Standby Mode. 22.3.3 Clock Settling Time for Exit from Software Standby Mode. 22.3.4 Sample Application of Software Standby Mode. 22.3.5 Application Notes. 22.4 Hardware Standby Mode . 22.4.1 Transition to Hardware Standby Mode . 22.4.2 Recovery from Hardware Standby Mode. 22.4.3 Timing Relationships in Hardware Standby Mode . 533 534 536 536 536 537 537 537 538 539 539 541 541 541 542 Section 23 Electrical Specifications . 543 23.1 Absolute Maximum Ratings. 23.2 Electrical Characteristics . 23.2.1 DC Characteristics. 23.2.2 AC Characteristics. 23.2.3 A/D Converter Characteristics . 23.2.4 D/A Converter Characteristics (H8/3337 H8/3337 Series Only). 23.2.5 Flash Memory Characteristics. 23.3 MCU Operational Timing. 23.3.1 Bus Timing . 543 544 544 555 563 564 565 567 567 xi 23.3.2 23.3.3 23.3.4 23.3.5 23.3.6 23.3.7 23.3.8 23.3.9 23.3.10 Control Signal Timing. 16-Bit Free-Running Timer Timing . 8-Bit Timer Timing . Pulse Width Modulation Timer Timing . Serial Communication Interface Timing. I/O Port Timing . Host Interface Timing (H8/3337 H8/3337 Series Only) . I2C Bus Timing (Option) (H8/3337 H8/3337 Series Only). External Clock Output Timing . 568 568 571 572 573 574 574 575 576 Appendix A CPU Instruction Set . 577 A.1 A.2 A.3 Instruction Set List . 577 Operation Code Map. 585 Number of States Required for Execution. 587 Appendix B Interrupt I/O Register . 593 B.1 B.2 Addresses. B.1.1 Addresses for H8/3337 H8/3337 Series . B.1.2 Addresses for H8/3397 H8/3397 Series . Function . 593 593 598 603 Appendix C I/O Port Block Diagrams . 660 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 Port 1 Block Diagram. Port 2 Block Diagram. Port 3 Block Diagram. Port 4 Block Diagrams . Port 5 Block Diagrams . Port 6 Block Diagrams . Port 7 Block Diagrams . Port 8 Block Diagrams . Port 9 Block Diagrams . 660 661 662 663 667 670 674 675 681 Appendix D Port States in Each Processing State . 687 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode . 689 Appendix F Option List . 688 Appendix G Product Code Lineup . 692 Appendix H Package Dimensions . 694 xii Section 1 Overview 1.1 Overview The H8/3337 H8/3337 Series and the H8/3397 H8/3397 Series of single-chip microcomputers feature an H8/300 H8/300 CPU core and a complement of on-chip supporting modules implementing a variety of system functions. The H8/300 H8/300 CPU is a high-speed processor with an architecture featuring powerful bitmanipulation instructions, ideally suited for realtime control applications. The on-chip supporting modules implement peripheral functions needed in system configurations. These include ROM, RAM, four types of timers (a 16-bit free-running timer, 8-bit timers, PWM timers, and a watchdog timer), a serial communication interface (SCI), an I2C bus interface (option), a host interface (HIF), an A/D converter, a D/A converter, and I/O ports. The H8/3397 H8/3397 Series is a subset of the H8/3337 H8/3337 Series and does not include an I 2C bus interface, host interface, and D/A converter. The H8/3337 H8/3337 Series can operate in single-chip mode or in two expanded modes, depending on the requirements of the application. Besides the mask-ROM versions of the H8/3337 H8/3337 Series, there are ZTATTM versions with on-chip PROM, and F-ZTATTM versions with on-chip flash memory. The F-ZTATTM version can be programmed or reprogrammed on-board in application systems. Notes: 1. ZTATTM (zero turn-around time) is a trademark of Hitachi, Ltd. 2. F-ZTATTM (flexible-ZTAT) is a trademark of Hitachi, Ltd. The H8/3397 H8/3397 Series is only available in a mask-ROM version. For applications with ZTAT, F-ZTAT, and emulator versions, use the H8/3337 H8/3337 Series instead. In such cases, do not access registers of deleted functions. Also, do not write 1 to the following bits: HIE bit of SYSCR; IICS, IICD, IICX, IICE and STAC bits of STCR; RAMS and RAM0 bits of WSCR. Table 1.1 lists the features of the H8/3337 H8/3337 Series. 1 Table 1.1 Features Item Specification CPU Two-way general register configuration · Eight 16-bit registers, or · Sixteen 8-bit registers High-speed operation · Maximum clock rate (ø clock): 16 MHz at 5 V, 12MHz at 4 V or 10 MHz at 3 V · 8- or 16-bit register-register add/subtract: 125 ns (16 MHz), 167 ns (12MHz), 200 ns (10 MHz) · 8 × 8-bit multiply: 875 ns (16 MHz), 1167 ns (12MHz), 1400 ns (10 MHz) · 16 ÷ 8-bit divide: 875 ns (16 MHz), 1167 ns (12MHz), 1400 ns (10 MHz) Streamlined, concise instruction set · Instruction length: 2 or 4 bytes · Register-register arithmetic and logic operations · MOV instruction for data transfer between registers and memory Instruction set features · Multiply instruction (8 bits × 8 bits) · Divide instruction (16 bits ÷ 8 bits) · Bit-accumulator instructions · Register-indirect specification of bit positions Memory · · · H8/3337Y H8/3337Y, H8/3397 H8/3397: 60-kbyte ROM; 2-kbyte RAM H8/3336Y H8/3336Y, H8/3396 H8/3396: 48-kbyte ROM; 2-kbyte RAM H8/3334Y H8/3334Y, H8/3394 H8/3394: 32-kbyte ROM; 1-kbyte RAM 16-bit free-running timer (1 channel) · · · One 16-bit free-running counter (can also count external events) Two output-compare lines Four input capture lines (can be buffered) 8-bit timer (2 channels) Each channel has · One 8-bit up-counter (can also count external events) · Two time constant registers PWM timer (2 channels) · · Duty cycle can be set from 0 to 100% Resolution: 1/250 Watchdog timer (WDT) (1 channel) · · Overflow can generate a reset or NMI interrupt Also usable as interval timer 2 Table 1.1 Features (cont) Item Specification Serial communication · interface (SCI) · (2 channels) · Asynchronous or synchronous mode (selectable) Full duplex: can transmit and receive simultaneously On-chip baud rate generator I 2C bus interface · (1 channel) (option) · (H8/3337 H8/3337 Series only) Conforms to Philips I2C bus interface Includes single master mode and slave mode Host interface (HIF) · (H8/3337 H8/3337 Series only) · · · 8-bit host interface port Three host interrupt requests (HIRQ 1, HIRQ11 HIRQ11, HIRQ12 HIRQ12) Regular and fast A 20 gate output Two register sets, each with two data registers and a status register Keyboard with controller · Controls a matrix-scan keyboard by providing a keyboard scan function wake-up interrupts and sense ports A/D converter · · · · 10-bit resolution Eight channels: single or scan mode (selectable) Start of A/D conversion can be externally triggered Sample-and-hold function D/A converter · (H8/3337 H8/3337 Series only) · 8-bit resolution Two channels I/O ports · · 58 input/output lines (16 of which can drive LEDs) 8 input-only lines Interrupts · · Nine external interrupt lines: NMI, IRQ0 to IRQ7 26 on-chip interrupt sources Wait control · Three selectable wait modes Operating modes · · · Expanded mode with on-chip ROM disabled (mode 1) Expanded mode with on-chip ROM enabled (mode 2) Single-chip mode (mode 3) Power-down modes · · · Sleep mode Software standby mode Hardware standby mode Other features · On-chip oscillator 3 Table 1.1 Item Features (cont) Specification Series lineup Part Number Product Name 5-V Version (16 MHz) 4-V Version (12 MHz) 3-V Version (10 MHz) Package ROM H8/3337Y H8/3337Y F-ZTAT HD64F3337YF16 HD64F3337YF16 HD64F3337YFLH16 HD64F3337YFLH16 HD64F3337YF16 HD64F3337YF16 HD64F3337YFLH16 HD64F3337YFLH16 80-pin QFP (FP-80A FP-80A) HD64F3337YTF16 HD64F3337YTF16 HD64F3337YTFLH16 HD64F3337YTFLH16 HD64F3337YTF16 HD64F3337YTF16 HD64F3337YTFLH16 HD64F3337YTFLH16 80-pin TQFP (TFP-80C TFP-80C) Flash memory (dual-powersupply product) HD64F3337YCP16 HD64F3337YCP16 HD64F3337YCP16 HD64F3337YCP16 84-pin PLCC (CP-84 CP-84) HD64F3337SF16 HD64F3337SF16 HD64F3337SF16 HD64F3337SF16 80-pin QFP (FP-80A FP-80A) HD64F3337STF16 HD64F3337STF16 HD64F3337STF16 HD64F3337STF16 80-pin TQFP (TFP-80C TFP-80C) HD6473337YF16 HD6473337YF16 HD6473337YF16 HD6473337YF16 80-pin QFP (FP-80A FP-80A) HD6473337YTF16 HD6473337YTF16 HD6473337YTF16 HD6473337YTF16 80-pin TQFP (TFP-80C TFP-80C) HD6473337YCP16 HD6473337YCP16 HD6473337YCP16 HD6473337YCP16 84-pin PLCC (CP-84 CP-84) HD6473337YCG16 HD6473337YCG16 HD6473337YCG16 HD6473337YCG16 84-pin LCC (CG-84 CG-84) HD6433337YF16 HD6433337YF16 HD6433337YF12 HD6433337YF12 HD6433397F16 HD6433397F16 HD6433397F12 HD6433397F12 HD6433337YVF10 HD6433337YVF10 HD6433397VF10 HD6433397VF10 80-pin QFP (FP-80A FP-80A) HD6433337YTF16 HD6433337YTF16 HD6433337YTF12 HD6433337YTF12 HD6433397TF16 HD6433397TF16 HD6433397TF12 HD6433397TF12 HD6433337YVTF10 HD6433337YVTF10 HD6433397VTF10 HD6433397VTF10 80-pin TQFP (TFP-80C TFP-80C) HD6433337YCP16 HD6433337YCP16 HD6433337YCP12 HD6433337YCP12 HD6433397CP16 HD6433397CP16 HD6433397CP12 HD6433397CP12 HD6433337YVCP10 HD6433337YVCP10 HD6433397VCP10 HD6433397VCP10 84-pin PLCC (CP-84 CP-84) HD6433336YF16 HD6433336YF16 HD6433336YF12 HD6433336YF12 HD6433396F16 HD6433396F16 HD6433396F12 HD6433396F12 HD6433336YVF10 HD6433336YVF10 HD6433396VF10 HD6433396VF10 80-pin QFP (FP-80A FP-80A) HD6433336YTF16 HD6433336YTF16 HD6433336YTF12 HD6433336YTF12 HD6433396TF16 HD6433396TF16 HD6433396TF12 HD6433396TF12 HD6433336YVTF10 HD6433336YVTF10 HD6433396VTF10 HD6433396VTF10 80-pin TQFP (TFP-80C TFP-80C) HD6433336YCP16 HD6433336YCP16 HD6433336YCP12 HD6433336YCP12 HD6433396CP16 HD6433396CP16 HD6433396C12 HD6433396C12 HD6433336YVCP10 HD6433336YVCP10 HD6433396VCP10 HD6433396VCP10 84-pin PLCC (CP-84 CP-84) H8/3337Y H8/3337Y ZTAT H8/3337Y H8/3337Y H8/3397 H8/3397 H8/3336Y H8/3336Y H8/3396 H8/3396 4 Flash memory (single-powersupply product) PROM Mask ROM Mask ROM Table 1.1 Item Features (cont) Specification Series lineup Part Number Product Name 5-V Version (16 MHz) 4-V Version (12 MHz) 3-V Version (10 MHz) Package ROM H8/3334Y H8/3334Y F-ZTAT HD64F3334YF16 HD64F3334YF16 HD64F3334YFLH16 HD64F3334YFLH16 HD64F3334YF16 HD64F3334YF16 HD64F3334YFLH16 HD64F3334YFLH16 80-pin QFP (FP-80A FP-80A) Flash memory HD64F3334YTF16 HD64F3334YTF16 HD64F3334YTFLH16 HD64F3334YTFLH16 HD64F3334YTF16 HD64F3334YTF16 HD64F3334YTFLH16 HD64F3334YTFLH16 80-pin TQFP (TFP-80C TFP-80C) HD64F3334YCP16 HD64F3334YCP16 HD64F3334YCP16 HD64F3334YCP16 84-pin PLCC (CP-84 CP-84) HD6473334YF16 HD6473334YF16 HD6473334YF16 HD6473334YF16 80-pin QFP (FP-80A FP-80A) HD6473334YTF16 HD6473334YTF16 HD6473334YTF16 HD6473334YTF16 80-pin TQFP (TFP-80C TFP-80C) HD6473334YCP16 HD6473334YCP16 HD6473334YCP16 HD6473334YCP16 84-pin PLCC (CP-84 CP-84) HD6433334YF16 HD6433334YF16 HD6433334YF12 HD6433334YF12 HD6433394F16 HD6433394F16 HD6433394F12 HD6433394F12 HD6433334YVF10 HD6433334YVF10 HD6433394VF10 HD6433394VF10 80-pin QFP (FP-80A FP-80A) HD6433334YTF16 HD6433334YTF16 HD6433334YTF12 HD6433334YTF12 HD6433394TF16 HD6433394TF16 HD6433394TF12 HD6433394TF12 HD6433334YVTF10 HD6433334YVTF10 HD6433394VTF10 HD6433394VTF10 80-pin TQFP (TFP-80C TFP-80C) HD6433334YCP16 HD6433334YCP16 HD6433334YCP12 HD6433334YCP12 HD6433394CP16 HD6433394CP16 HD6433394CP12 HD6433394CP12 HD6433334YVCP10 HD6433334YVCP10 HD6433394VCP10 HD6433394VCP10 84-pin PLCC (CP-84 CP-84) H8/3334Y H8/3334Y ZTAT H8/3334Y H8/3334Y H8/3394 H8/3394 PROM Mask ROM Notes: The I2C bus interface is an available option. Please note the following points regarding this option. 1. Contact your local Hitachi representative to order the I2C bus interface. 2. In mask ROM versions, the Y in the part number becomes a W in products in which this optional function is used. Example: HD6433337WF HD6433337WF, HD6433334WF HD6433334WF 3. Although ZTAT and F-ZTAT chips have identical part numbers, inform your local Hitachi representative when ordering the I 2C bus interface. 5 1.2 Block Diagram Figure 1.1 (a) shows a block diagram of the H8/3337 H8/3337 Series. Figure 1.1 (b) shows a block diagram of the H8/3397 H8/3397 Series. Data bus (low) 8-bit timer (2 channels) 10-bit A/D converter (8 channels) PWM timer (2 channels) 8-bit D/A converter (2 channels) Port 7 P50/TxD0 P51/RxD0 P52/SCK0 P52/SCK0 P70/AN0 P70/AN0 P71/AN1 P71/AN1 P72/AN2 P72/AN2 P73/AN3 P73/AN3 P74/AN4 P74/AN4 P75/AN5 P75/AN5 P76/AN6/DA0 P76/AN6/DA0 P77/AN7/DA1 P77/AN7/DA1 Note: * In the case of the CP-84 CP-84 and CG-84 CG-84 Memory Sizes H8/3337Y H8/3337Y H8/3336Y H8/3336Y H8/3334Y H8/3334Y ROM 60 kbytes 48 kbytes 32 kbytes Figure 1.1 (a) Block Diagram for H8/3337 H8/3337 Series 6 P80/HA0 P80/HA0 P81/GA20 P81/GA20 P82/CS1 P82/CS1 P83/IOR P83/IOR P84/TxD1/IRQ3/IOW P85/RxD1/IRQ4/CS2 P86/SCK1/IRQ5/SCL P86/SCK1/IRQ5/SCL Port 5 AVCC AVSS Port 4 P30/D0/HDB0 P30/D0/HDB0 P31/D1/HDB1 P31/D1/HDB1 P32/D2/HDB2 P32/D2/HDB2 P33/D3/HDB3 P33/D3/HDB3 P34/D4/HDB4 P34/D4/HDB4 P35/D5/HDB5 P35/D5/HDB5 P36/D6/HDB6 P36/D6/HDB6 P37/D7/HDB7 P37/D7/HDB7 Port 8 Port 9 Serial communication interface (2 channels) I2C bus interface (1 channel) (option) P90/ADTRG/IRQ2/ECS2 P90/ADTRG/IRQ2/ECS2 P91/IRQ1/EIOW P91/IRQ1/EIOW P92/IRQ0 P92/IRQ0 P93/RD P93/RD P94/WR P94/WR P95/AS P95/AS P96/ø P97/WAIT/SDA P97/WAIT/SDA Port 3 16-bit free-running timer Port 1 Host interface P40/TMCI0 P40/TMCI0 P41/TMO0 P41/TMO0 P42/TMRI0 P42/TMRI0 P43/TMCI1/HIRQ11 P43/TMCI1/HIRQ11 P44/TMO1/HIRQ1 P44/TMO1/HIRQ1 P45/TMRI1/HIRQ12 P45/TMRI1/HIRQ12 P46/PW0 P46/PW0 P47/PW1 P47/PW1 P60/FTCI/KEYIN0 P60/FTCI/KEYIN0 P61/FTOA/KEYIN1 P61/FTOA/KEYIN1 P62/FTIA/KEYIN2 P62/FTIA/KEYIN2 P63/FTIB/KEYIN3 P63/FTIB/KEYIN3 P64/FTIC/KEYIN4 P64/FTIC/KEYIN4 P65/FTID/KEYIN5 P65/FTID/KEYIN5 P66/FTOB/IRQ6/KEYIN6 P66/FTOB/IRQ6/KEYIN6 P67/IRQ7/KEYIN7 P67/IRQ7/KEYIN7 RAM H8/3337Y H8/3337Y: 2 kbytes H8/3336Y H8/3336Y: 2 kbytes H8/3334Y H8/3334Y: 1 kbyte Watchdog timer Port 2 P20/A8 P20/A8 P21/A9 P21/A9 P22/A10 P22/A10 P23/A11 P23/A11 P24/A12 P24/A12 P25/A13 P25/A13 P26/A14 P26/A14 P27/A15 P27/A15 ROM Flash memory, PROM or mask ROM H8/3337Y H8/3337Y: 60 kbytes H8/3336Y H8/3336Y: 48 kbytes H8/3334Y H8/3334Y: 32 kbytes Port 6 P10/A0 P10/A0 P11/A1 P11/A1 P12/A2 P12/A2 P13/A3 P13/A3 P14/A4 P14/A4 P15/A5 P15/A5 P16/A6 P16/A6 P17/A7 P17/A7 Address bus RES STBY NMI MD0 MD1 VCC VCC VSS VSS VSS VSS VSS VSS VSS CPU H8/300 H8/300 Data bus (high) XTAL EXTAL Clock pulse generator * RAM 2 kbytes 2 kbytes 1 kbyte Port 9 P30/D0 P30/D0 P31/D1 P31/D1 P32/D2 P32/D2 P33/D3 P33/D3 P34/D4 P34/D4 P35/D5 P35/D5 P36/D6 P36/D6 P37/D7 P37/D7 Port 8 Port 1 16-bit free-running timer Serial communication interface (2 channels) 8-bit timer (2 channels) P80 P81 P82 P83 P84/TxD1/IRQ3 P85/RxD1/IRQ4 P86/SCK1/IRQ5 P86/SCK1/IRQ5 10-bit A/D converter (8 channels) PWM timer (2 channels) Port 7 P50/TxD0 P51/RxD0 P52/SCK0 P52/SCK0 P70/AN0 P70/AN0 P71/AN1 P71/AN1 P72/AN2 P72/AN2 P73/AN3 P73/AN3 P74/AN4 P74/AN4 P75/AN5 P75/AN5 P76/AN6 P76/AN6 P77/AN7 P77/AN7 Port 5 AVCC AVSS Port 4 P40/TMCI0 P40/TMCI0 P41/TMO0 P41/TMO0 P42/TMRI0 P42/TMRI0 P43/TMCI1 P43/TMCI1 P44/TMO1 P44/TMO1 P45/TMRI1 P45/TMRI1 P46/PW0 P46/PW0 P47/PW1 P47/PW1 P60/FTCI/KEYIN0 P60/FTCI/KEYIN0 P61/FTOA/KEYIN1 P61/FTOA/KEYIN1 P62/FTIA/KEYIN2 P62/FTIA/KEYIN2 P63/FTIB/KEYIN3 P63/FTIB/KEYIN3 P64/FTIC/KEYIN4 P64/FTIC/KEYIN4 P65/FTID/KEYIN5 P65/FTID/KEYIN5 P66/FTOB/IRQ6/KEYIN6 P66/FTOB/IRQ6/KEYIN6 P67/IRQ7/KEYIN7 P67/IRQ7/KEYIN7 P90/ADTRG/IRQ2 P90/ADTRG/IRQ2 P91/IRQ1 P91/IRQ1 P92/IRQ0 P92/IRQ0 P93/RD P93/RD P94/WR P94/WR P95/AS P95/AS P96/ø P97/WAIT P97/WAIT RAM H8/3397 H8/3397: 2 kbytes H8/3396 H8/3396: 2 kbytes H8/3394 H8/3394: 1 kbyte Watchdog timer Port 2 P20/A8 P20/A8 P21/A9 P21/A9 P22/A10 P22/A10 P23/A11 P23/A11 P24/A12 P24/A12 P25/A13 P25/A13 P26/A14 P26/A14 P27/A15 P27/A15 ROM (Mask ROM) H8/3397 H8/3397: 60 kbytes H8/3396 H8/3396: 48 kbytes H8/3394 H8/3394: 32 kbytes Port 6 P10/A0 P10/A0 P11/A1 P11/A1 P12/A2 P12/A2 P13/A3 P13/A3 P14/A4 P14/A4 P15/A5 P15/A5 P16/A6 P16/A6 P17/A7 P17/A7 Port 3 Data bus (low) Address bus RES STBY NMI MD0 MD1 VCC VCC VSS VSS VSS VSS VSS VSS VSS CPU H8/300 H8/300 Data bus (high) XTAL EXTAL Clock pulse generator * Memory Sizes Note: * In the case of the CP-84 CP-84 and CG-84 CG-84 H8/3397 H8/3397 H8/3396 H8/3396 H8/3394 H8/3394 ROM 60 kbytes 48 kbytes 32 kbytes RAM 2 kbytes 2 kbytes 1 kbyte Figure 1.1 (b) Block Diagram for H8/3397 H8/3397 Series 7 1.3 Pin Assignments and Functions 1.3.1 Pin Arrangement Figure 1.2 (a) shows the pin arrangement of the FP-80A FP-80A and TFP-80C TFP-80C packages for the H8/3337 H8/3337 Series, and figure 1.2 (b) shows the packages for the H8/3397 H8/3397 Series. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 1 60 2 59 3 58 4 57 5 56 6 55 7 54 8 53 H8/3337 H8/3337 Series FP-80A FP-80A, TFP-80C TFP-80C (top view) 9 10 11 52 51 50 40 39 38 37 36 35 34 33 32 31 30 41 29 42 20 28 43 19 27 44 18 26 45 17 25 46 16 24 47 15 23 48 14 22 49 13 21 12 P14/A4 P14/A4 P15/A5 P15/A5 P16/A6 P16/A6 P17/A7 P17/A7 VSS P20/A8 P20/A8 P21/A9 P21/A9 P22/A10 P22/A10 P23/A11 P23/A11 P24/A12 P24/A12 P25/A13 P25/A13 P26/A14 P26/A14 P27/A15 P27/A15 VCC P47/PW1 P47/PW1 P46/PW0 P46/PW0 P45/TMRI1/HIRQ12 P45/TMRI1/HIRQ12 P44/TMO1/HIRQ1 P44/TMO1/HIRQ1 P43/TMCI1/HIRQ11 P43/TMCI1/HIRQ11 P42/TMRI0 P42/TMRI0 KEYIN0/FTCI/P60 KEYIN0/FTCI/P60 KEYIN1/FTOA/P61 KEYIN1/FTOA/P61 KEYIN2/FTIA/P62 KEYIN2/FTIA/P62 KEYIN3/FTIB/P63 KEYIN3/FTIB/P63 KEYIN4/FTIC/P64 KEYIN4/FTIC/P64 KEYIN5/FTID/P65 KEYIN5/FTID/P65 IRQ6/KEYIN6/FTOB/P66 IRQ6/KEYIN6/FTOB/P66 IRQ7/KEYIN7/P67 IRQ7/KEYIN7/P67 AVCC AN0/P70 AN0/P70 AN1/P71 AN1/P71 AN2/P72 AN2/P72 AN3/P73 AN3/P73 AN4/P74 AN4/P74 AN5/P75 AN5/P75 DA0/AN6/P76 DA0/AN6/P76 DA1/AN7/P77 DA1/AN7/P77 AVSS TMCI0/P40 TMCI0/P40 TMO0/P41 TMO0/P41 RES XTAL EXTAL MD1 MD0 NMI STBY/FVPP* VCC SCK0/P52 SCK0/P52 RxD0/P51 TxD0/P50 VSS WAIT/SDA/P97 WAIT/SDA/P97 ø/P96 AS/P95 AS/P95 WR/P94 WR/P94 RD/P93 RD/P93 IRQ0/P92 IRQ0/P92 EIOW/IRQ1/P91 EIOW/IRQ1/P91 ADTRG/ECS2/IRQ2/P90 ADTRG/ECS2/IRQ2/P90 79 80 P86/IRQ5/SCK1/SCL P86/IRQ5/SCK1/SCL P85/CS2/IRQ4/RxD1 P84/IOW/IRQ3/TxD1 P83/IOR P83/IOR P82/CS1 P82/CS1 P81/GA20 P81/GA20 P80/HA0 P80/HA0 VSS P37/HDB7/D7 P37/HDB7/D7 P36/HDB6/D6 P36/HDB6/D6 P35/HDB5/D5 P35/HDB5/D5 P34/HDB4/D4 P34/HDB4/D4 P33/HDB3/D3 P33/HDB3/D3 P32/HDB2/D2 P32/HDB2/D2 P31/HDB1/D1 P31/HDB1/D1 P30/HDB0/D0 P30/HDB0/D0 P10/A0 P10/A0 P11/A1 P11/A1 P12/A2 P12/A2 P13/A3 P13/A3 Figure 1.3 (a) shows the pin arrangement of the CP-84 CP-84 and CG-84 CG-84 packages for the H8/3337 H8/3337 Series, and figure 1.3 (b) shows the packages for the H8/3397 H8/3397 Series. Note: * In the S-mask model (single-power-supply model), pin 7 functions only as the STBY pin. Figure 1.2 (a) Pin Arrangement for H8/3337 H8/3337 Series (FP-80A FP-80A, TFP-80C TFP-80C, Top View) 8 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 P86/IRQ5/SCK1 P86/IRQ5/SCK1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 P83 P82 P81 P80 VSS P37/D7 P37/D7 P36/D6 P36/D6 P35/D5 P35/D5 P34/D4 P34/D4 P33/D3 P33/D3 P32/D2 P32/D2 P31/D1 P31/D1 P30/D0 P30/D0 P10/A0 P10/A0 P11/A1 P11/A1 P12/A2 P12/A2 P13/A3 P13/A3 79 80 1 60 2 59 3 58 4 57 5 56 6 55 7 54 53 8 H8/3397 H8/3397 Series FP-80A FP-80A, TFP-80C TFP-80C (top view) 9 10 11 52 51 50 40 39 38 37 36 35 34 33 32 31 30 41 29 42 20 28 43 19 27 44 18 26 45 17 25 46 16 24 47 15 23 48 14 22 49 13 21 12 P14/A4 P14/A4 P15/A5 P15/A5 P16/A6 P16/A6 P17/A7 P17/A7 VSS P20/A8 P20/A8 P21/A9 P21/A9 P22/A10 P22/A10 P23/A11 P23/A11 P24/A12 P24/A12 P25/A13 P25/A13 P26/A14 P26/A14 P27/A15 P27/A15 VCC P47/PW1 P47/PW1 P46/PW0 P46/PW0 P45/TMRI1 P45/TMRI1 P44/TMO1 P44/TMO1 P43/TMCI1 P43/TMCI1 P42/TMRI0 P42/TMRI0 KEYIN0/FTCI/P60 KEYIN0/FTCI/P60 KEYIN1/FTOA/P61 KEYIN1/FTOA/P61 KEYIN2/FTIA/P62 KEYIN2/FTIA/P62 KEYIN3/FTIB/P63 KEYIN3/FTIB/P63 KEYIN4/FTIC/P64 KEYIN4/FTIC/P64 KEYIN5/FTID/P65 KEYIN5/FTID/P65 IRQ6/KEYIN6/FTOB/P66 IRQ6/KEYIN6/FTOB/P66 IRQ7/KEYIN7/P67 IRQ7/KEYIN7/P67 AVCC AN0/P70 AN0/P70 AN1/P71 AN1/P71 AN2/P72 AN2/P72 AN3/P73 AN3/P73 AN4/P74 AN4/P74 AN5/P75 AN5/P75 AN6/P76 AN6/P76 AN7/P77 AN7/P77 AVSS TMCI0/P40 TMCI0/P40 TMO0/P41 TMO0/P41 RES XTAL EXTAL MD1 MD0 NMI STBY VCC SCK0/P52 SCK0/P52 RxD0/P51 TxD0/P50 VSS WAIT/P97 WAIT/P97 ø/P96 AS/P95 AS/P95 WR/P94 WR/P94 RD/P93 RD/P93 IRQ0/P92 IRQ0/P92 IRQ1/P91 IRQ1/P91 ADTRG/IRQ2/P90 ADTRG/IRQ2/P90 Figure 1.2 (b) Pin Arrangement for H8/3397 H8/3397 Series (FP-80A FP-80A, TFP-80C TFP-80C, Top View) 9 75 76 77 78 79 80 81 82 83 1 84 2 3 4 5 6 7 8 9 P86/IRQ5/SCK1/SCL P86/IRQ5/SCK1/SCL P85/CS2/IRQ4/RxD1 P84/IOW/IRQ3/TxD1 P83/IOR P83/IOR P82/CS1 P82/CS1 P81/GA20 P81/GA20 P80/HA0 P80/HA0 VSS P37/HDB7/D7 P37/HDB7/D7 VSS P36/HDB6/D6 P36/HDB6/D6 P35/HDB5/D5 P35/HDB5/D5 P34/HDB4/D4 P34/HDB4/D4 P33/HDB3/D3 P33/HDB3/D3 P32/HDB2/D2 P32/HDB2/D2 P31/HDB1/D1 P31/HDB1/D1 P30/HDB0/D0 P30/HDB0/D0 P10/A0 P10/A0 P11/A1 P11/A1 P12/A2 P12/A2 P13/A3 P13/A3 10 11 12 74 13 73 14 72 15 71 16 70 17 69 18 68 19 67 20 66 H8/3337 H8/3337 Series CP-84 CP-84, CG-84 CG-84 (top view) 21 22 23 65 64 63 53 52 51 50 49 48 47 46 45 44 43 42 54 41 55 32 40 56 31 39 57 30 38 58 29 37 59 28 36 60 27 35 61 26 34 62 25 33 24 P14/A4 P14/A4 P15/A5 P15/A5 P16/A6 P16/A6 P17/A7 P17/A7 VSS P20/A8 P20/A8 P21/A9 P21/A9 P22/A10 P22/A10 P23/A11 P23/A11 P24/A12 P24/A12 VSS P25/A13 P25/A13 P26/A14 P26/A14 P27/A15 P27/A15 VCC P47/PW1 P47/PW1 P46/PW0 P46/PW0 P45/TMRI1/HIRQ12 P45/TMRI1/HIRQ12 P44/TMO1/HIRQ1 P44/TMO1/HIRQ1 P43/TMCI1/HIRQ11 P43/TMCI1/HIRQ11 P42/TMRI0 P42/TMRI0 KEYIN0/FTCI/P60 KEYIN0/FTCI/P60 KEYIN1/FTOA/P61 KEYIN1/FTOA/P61 KEYIN2/FTIA/P62 KEYIN2/FTIA/P62 KEYIN3/FTIB/P63 KEYIN3/FTIB/P63 KEYIN4/FTIC/P64 KEYIN4/FTIC/P64 KEYIN5/FTID/P65 KEYIN5/FTID/P65 IRQ6/KEYIN6/FTOB/P66 IRQ6/KEYIN6/FTOB/P66 IRQ7/KEYIN7/P67 IRQ7/KEYIN7/P67 VSS AVCC AN0/P70 AN0/P70 AN1/P71 AN1/P71 AN2/P72 AN2/P72 AN3/P73 AN3/P73 AN4/P74 AN4/P74 AN5/P75 AN5/P75 DA0/AN6/P76 DA0/AN6/P76 DA1/AN7/P77 DA1/AN7/P77 AVSS TMCI0/P40 TMCI0/P40 TMO0/P41 TMO0/P41 RES XTAL EXTAL MD1 MD0 NMI STBY/FVPP* VCC SCK0/P52 SCK0/P52 RxD0/P51 TxD0/P50 VSS VSS WAIT/SDA/P97 WAIT/SDA/P97 ø/P96 AS/P95 AS/P95 WR/P94 WR/P94 RD/P93 RD/P93 IRQ0/P92 IRQ0/P92 EIOW/IRQ1/P91 EIOW/IRQ1/P91 ADTRG/ECS2/IRQ2/P90 ADTRG/ECS2/IRQ2/P90 Note: * In the S-mask model (single-power-supply model), pin 18 functions only as the STBY pin. Figure 1.3 (a) Pin Arrangement for H8/3337 H8/3337 Series (CP-84 CP-84, CG-84 CG-84, Top View) 10 75 76 77 78 79 80 81 82 83 1 84 2 3 4 5 6 7 8 9 P86/IRQ5/SCK1 P86/IRQ5/SCK1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 P83 P82 P81 P80 VSS P37/D7 P37/D7 VSS P36/D6 P36/D6 P35/D5 P35/D5 P34/D4 P34/D4 P33/D3 P33/D3 P32/D2 P32/D2 P31/D1 P31/D1 P30/D0 P30/D0 P10/A0 P10/A0 P11/A1 P11/A1 P12/A2 P12/A2 P13/A3 P13/A3 10 11 12 74 13 73 14 72 15 71 16 70 17 69 18 68 67 19 20 66 H8/3397 H8/3397 Series CP-84 CP-84 (top view) 21 22 23 65 64 63 53 52 51 50 49 48 47 46 45 44 43 42 54 41 55 32 40 56 31 39 57 30 38 58 29 37 59 28 36 60 27 35 61 26 34 62 25 33 24 P14/A4 P14/A4 P15/A5 P15/A5 P16/A6 P16/A6 P17/A7 P17/A7 VSS P20/A8 P20/A8 P21/A9 P21/A9 P22/A10 P22/A10 P23/A11 P23/A11 P24/A12 P24/A12 VSS P25/A13 P25/A13 P26/A14 P26/A14 P27/A15 P27/A15 VCC P47/PW1 P47/PW1 P46/PW0 P46/PW0 P45/TMRI1 P45/TMRI1 P44/TMO1 P44/TMO1 P43/TMCI1 P43/TMCI1 P42/TMRI0 P42/TMRI0 KEYIN0/FTCI/P60 KEYIN0/FTCI/P60 KEYIN1/FTOA/P61 KEYIN1/FTOA/P61 KEYIN2/FTIA/P62 KEYIN2/FTIA/P62 KEYIN3/FTIB/P63 KEYIN3/FTIB/P63 KEYIN4/FTIC/P64 KEYIN4/FTIC/P64 KEYIN5/FTID/P65 KEYIN5/FTID/P65 IRQ6/KEYIN6/FTOB/P66 IRQ6/KEYIN6/FTOB/P66 IRQ7/KEYIN7/P67 IRQ7/KEYIN7/P67 VSS AVCC AN0/P70 AN0/P70 AN1/P71 AN1/P71 AN2/P72 AN2/P72 AN3/P73 AN3/P73 AN4/P74 AN4/P74 AN5/P75 AN5/P75 AN6/P76 AN6/P76 AN7/P77 AN7/P77 AVSS TMCI0/P40 TMCI0/P40 TMO0/P41 TMO0/P41 RES XTAL EXTAL MD1 MD0 NMI STBY VCC SCK0/P52 SCK0/P52 RxD0/P51 TxD0/P50 VSS VSS WAIT/P97 WAIT/P97 ø/P96 AS/P95 AS/P95 WR/P94 WR/P94 RD/P93 RD/P93 IRQ0/P92 IRQ0/P92 IRQ1/P91 IRQ1/P91 ADTRG/IRQ2/P90 ADTRG/IRQ2/P90 Figure 1.3 (b) Pin Arrangement for H8/3397 H8/3397 Series (CP-84 CP-84, Top View) 11 1.3.2 Pin Functions Pin Assignments in Each Operating Mode: Table 1.2 (a) and table 1.2 (b) lists the assignments of the pins of the FP-80A FP-80A, TFP-80 TFP-80, CP-84 CP-84, and CG-84 CG-84 packages in each operating mode. Table 1.2 (a) Pin Assignments for H8/3337 H8/3337 Series in Each Operating Mode Pin No. Expanded Modes Single-Chip Mode FP-80A FP-80A, CP-84 CP-84, TFP-80C TFP-80C CG-84 CG-84 Mode 1 Mode 2 HIF Disabled HIF Enabled Flash EPROM Memory Writer Writer Mode Mode 1 12 RES RES RES RES VPP RES 2 13 XTAL XTAL XTAL XTAL NC XTAL 3 14 EXTAL EXTAL EXTAL EXTAL NC EXTAL 4 15 MD1 MD1 MD1 MD1 VSS VSS 5 16 MD0 MD0 MD0 MD0 VSS VSS 6 17 NMI NMI NMI NMI EA9 FA 9 7 18 STBY STBY/FVPP STBY/FVPP STBY/FVPP VSS FV PP 8 19 VCC VCC VCC VCC VCC VCC 9 20 P52/SCK0 P52/SCK0 P52/SCK0 P52/SCK0 P52/SCK0 P52/SCK0 P52/SCK0 P52/SCK0 NC NC 10 21 P51/RxD0 P51/RxD0 P51/RxD0 P51/RxD0 NC NC 11 22 P50/TxD0 P50/TxD0 P50/TxD0 P50/TxD0 NC NC 12 23 VSS VSS VSS VSS VSS VSS - 24 VSS VSS VSS VSS VSS VSS 13 25 P97/WAIT/SDA P97/WAIT/SDA P97/WAIT/SDA P97/WAIT/SDA P97/SDA P97/SDA P97/SDA P97/SDA NC VCC 14 26 ø ø P96/ø P96/ø NC NC 15 27 AS AS P95 P95 NC FA 16 16 28 WR WR P94 P94 NC FA 15 17 29 RD RD P93 P93 NC WE 18 30 P92/IRQ0 P92/IRQ0 P92/IRQ0 P92/IRQ0 P92/IRQ0 P92/IRQ0 P92/IRQ0 P92/IRQ0 PGM VSS 19 31 P91/IRQ1 P91/IRQ1 when HIF is disabled or STAC bit is 0 in STCR; EIOW/IRQ1 when HIF is enabled and STAC bit is 1 EA15 VCC 20 32 P90/IRQ2/ADTRG P90/IRQ2/ADTRG when HIF is disabled or STAC bit is 0 in STCR; ECS2/IRQ2 when HIF is enabled and STAC bit is 1 EA16 VCC 21 33 P60/FTCI/ P60/FTCI/ KEYIN0 NC NC Mode 3 12 P60/FTCI/ P60/FTCI/ KEYIN0 P60/FTCI/ P60/FTCI/ KEYIN0 P60/FTCI/ P60/FTCI/ KEYIN0 Table 1.2 (a) Pin Assignments for H8/3337 H8/3337 Series in Each Operating Mode (cont) Pin No. Expanded Modes Single-Chip Mode Mode 3 FP-80A FP-80A, CP-84 CP-84, TFP-80C TFP-80C CG-84 CG-84 Mode 1 Mode 2 HIF Disabled HIF Enabled Flash EPROM Memory Writer Writer Mode Mode 22 34 P61/FTOA/ P61/FTOA/ KEYIN1 P61/FTOA/ P61/FTOA/ KEYIN1 P61/FTOA/ P61/FTOA/ KEYIN1 P61/FTOA/ P61/FTOA/ KEYIN1 NC NC 23 35 P62/FTIA/ P62/FTIA/ KEYIN2 P62/FTIA/ P62/FTIA/ KEYIN2 P62/FTIA/ P62/FTIA/ KEYIN2 P62/FTIA/ P62/FTIA/ KEYIN2 NC NC 24 36 P63/FTIB/ P63/FTIB/ KEYIN3 P63/FTIB/ P63/FTIB/ KEYIN3 P63/FTIB/ P63/FTIB/ KEYIN3 P63/FTIB/ P63/FTIB/ KEYIN3 VCC VCC 25 37 P64/FTIC/ P64/FTIC/ KEYIN4 P64/FTIC/ P64/FTIC/ KEYIN4 P64/FTIC/ P64/FTIC/ KEYIN4 P64/FTIC/ P64/FTIC/ KEYIN4 VCC VCC 26 38 P65/FTID/ P65/FTID/ KEYIN5 P65/FTID/ P65/FTID/ KEYIN5 P65/FTID/ P65/FTID/ KEYIN5 P65/FTID/ P65/FTID/ KEYIN5 NC NC 27 39 P66/FTOB/ P66/FTOB/ IRQ6/KEYIN6 P66/FTOB/ P66/FTOB/ IRQ6/KEYIN6 P66/FTOB/ P66/FTOB/ P66/FTOB/ P66/FTOB/ NC IRQ6/KEYIN6 IRQ6/KEYIN6 NC 28 40 P67/IRQ7/ P67/IRQ7/ KEYIN7 P67/IRQ7/ P67/IRQ7/ KEYIN7 P67/IRQ7/ P67/IRQ7/ KEYIN7 P67/IRQ7/ P67/IRQ7/ KEYIN7 NC VSS - 41 VSS VSS VSS VSS VSS VSS 29 42 AVCC AVCC AVCC AVCC VCC VCC 30 43 P70/AN0 P70/AN0 P70/AN0 P70/AN0 P70/AN0 P70/AN0 P70/AN0 P70/AN0 NC NC 31 44 P71/AN1 P71/AN1 P71/AN1 P71/AN1 P71/AN1 P71/AN1 P71/AN1 P71/AN1 NC NC 32 45 P72/AN2 P72/AN2 P72/AN2 P72/AN2 P72/AN2 P72/AN2 P72/AN2 P72/AN2 NC NC 33 46 P73/AN3 P73/AN3 P73/AN3 P73/AN3 P73/AN3 P73/AN3 P73/AN3 P73/AN3 NC NC 34 47 P74/AN4 P74/AN4 P74/AN4 P74/AN4 P74/AN4 P74/AN4 P74/AN4 P74/AN4 NC NC 35 48 P75/AN5 P75/AN5 P75/AN5 P75/AN5 P75/AN5 P75/AN5 P75/AN5 P75/AN5 NC NC 36 49 P76/AN6/DA0 P76/AN6/DA0 P76/AN6/DA0 P76/AN6/DA0 P76/AN6/DA0 P76/AN6/DA0 P76/AN6/DA0 P76/AN6/DA0 NC NC 37 50 P77/AN7/DA1 P77/AN7/DA1 P77/AN7/DA1 P77/AN7/DA1 P77/AN7/DA1 P77/AN7/DA1 P77/AN7/DA1 P77/AN7/DA1 NC NC 38 51 AVSS AVSS AVSS AVSS VSS VSS 39 52 P40/TMCI0 P40/TMCI0 P40/TMCI0 P40/TMCI0 P40/TMCI0 P40/TMCI0 P40/TMCI0 P40/TMCI0 NC NC 40 53 P41/TMO0 P41/TMO0 P41/TMO0 P41/TMO0 P41/TMO0 P41/TMO0 P41/TMO0 P41/TMO0 NC NC 41 54 P42/TMRI0 P42/TMRI0 P42/TMRI0 P42/TMRI0 P42/TMRI0 P42/TMRI0 P42/TMRI0 P42/TMRI0 NC NC 42 55 P43/TMCI1/ P43/TMCI1/ HIRQ11 HIRQ11* P43/TMCI1/ P43/TMCI1/ HIRQ11 HIRQ11* P43/TMCI1 P43/TMCI1 HIRQ11/ HIRQ11/ TMCI1 NC NC 13 Table 1.2 (a) Pin Assignments for H8/3337 H8/3337 Series in Each Operating Mode (cont) Pin No. Expanded Modes Single-Chip Mode Mode 3 FP-80A FP-80A, CP-84 CP-84, TFP-80C TFP-80C CG-84 CG-84 Mode 1 Mode 2 HIF Disabled HIF Enabled Flash EPROM Memory Writer Writer Mode Mode 43 56 P44/TMO1/ P44/TMO1/ HIRQ1* P44/TMO1/ P44/TMO1/ HIRQ1* P44/TMO1 P44/TMO1 HIRQ1/TMO1 NC NC 44 57 P45/TMRI1/ P45/TMRI1/ HIRQ12 HIRQ12* P45/TMRI1/ P45/TMRI1/ HIRQ12 HIRQ12* P45/TMRI1 P45/TMRI1 HIRQ12/ HIRQ12/ TMRI1 NC NC 45 58 P46/PW0 P46/PW0 P46/PW0 P46/PW0 P46/PW0 P46/PW0 P46/PW0 P46/PW0 NC NC 46 59 P47/PW1 P47/PW1 P47/PW1 P47/PW1 P47/PW1 P47/PW1 P47/PW1 P47/PW1 NC NC 47 60 VCC VCC VCC VCC VCC VCC 48 61 A15 P27/A P27/A 15 P27 P27 CE CE 49 62 A14 P26/A P26/A 14 P26 P26 EA14 FA 14 50 63 A13 P25/A P25/A 13 P25 P25 EA13 FA 13 - 64 VSS VSS VSS VSS VSS VSS 51 65 A12 P24/A P24/A 12 P24 P24 EA12 FA 12 52 66 A11 P23/A P23/A 11 P23 P23 EA11 FA 11 53 67 A10 P22/A P22/A 10 P22 P22 EA10 FA 10 54 68 A9 P21/A P21/A 9 P21 P21 OE OE 55 69 A8 P20/A P20/A 8 P20 P20 EA8 FA 8 56 70 VSS VSS VSS VSS VSS VSS 57 71 A7 P17/A P17/A 7 P17 P17 EA7 FA 7 58 72 A6 P16/A P16/A 6 P16 P16 EA6 FA 6 59 73 A5 P15/A P15/A 5 P15 P15 EA5 FA 5 60 74 A4 P14/A P14/A 4 P14 P14 EA4 FA 4 61 75 A3 P13/A P13/A 3 P13 P13 EA3 FA 3 62 76 A2 P12/A P12/A 2 P12 P12 EA2 FA 2 63 77 A1 P11/A P11/A 1 P11 P11 EA1 FA 1 64 78 A0 P10/A P10/A 0 P10 P10 EA0 FA 0 65 79 D0 D0 P30 HDB0 EO0 FO0 66 80 D1 D1 P31 HDB1 EO1 FO1 67 81 D2 D2 P32 HDB2 EO2 FO2 68 82 D3 D3 P33 HDB3 EO3 FO3 14 Table 1.2 (a) Pin Assignments for H8/3337 H8/3337 Series in Each Operating Mode (cont) Pin No. Expanded Modes Single-Chip Mode FP-80A FP-80A, CP-84 CP-84, TFP-80C TFP-80C CG-84 CG-84 Mode 1 Mode 2 HIF Disabled HIF Enabled Flash EPROM Memory Writer Writer Mode Mode 69 83 D4 D4 P34 HDB4 EO4 FO4 70 84 D5 D5 P35 HDB5 EO5 FO5 71 1 D6 D6 P36 HDB6 EO6 FO6 - 2 VSS VSS VSS VSS VSS VSS 72 3 D7 D7 P37 HDB7 EO7 FO7 73 4 VSS VSS VSS VSS VSS VSS 74 5 P80/HA0 P80/HA0* P80/HA0 P80/HA0* P80 HA 0 NC NC 75 6 P81/GA P81/GA 20 * P81/GA P81/GA 20 * P81 P81/GA P81/GA 20 NC NC 76 7 P82/CS1 P82/CS1* P82/CS1 P82/CS1* P82 CS 1 NC NC 77 8 P83/IOR P83/IOR* P83/IOR P83/IOR* P83 IOR NC NC 78 9 P84/IRQ3/TxD1 when HIF is disabled or STAC bit is 1 in STCR; IOW/IRQ3 when HIF is enabled and STAC bit is 0 NC NC 79 10 P85/IRQ4/RxD1 when HIF is disabled or STAC bit is 1 in STCR; CS2/IRQ4 when HIF is enabled and STAC bit is 0 NC NC 80 11 P86/SCK1/ P86/SCK1/ IRQ5/SCL NC NC Mode 3 P86/SCK1/ P86/SCK1/ IRQ5/SCL P86/SCK1/ P86/SCK1/ IRQ5/SCL P86/SCK1/ P86/SCK1/ IRQ5/SCL Notes: 1. Pins marked NC should be left unconnected. 2. For details on witer mode, refer to 18.2, Writer Mode, 19.6 Flash Memory Writer Mode (H8/3334YF H8/3334YF), 20.6 Flash Memory Writer Mode (H8/3337YF H8/3337YF) and 21.5, Flash Memory Writer Mode (H8/3337SF H8/3337SF). 3. In this chip, except for the S-mask model (single-power-supply specification), the same pin is used for STBY and FV PP . When this pin is driven low, a transition is made to hardware standby mode. This happens not only in the normal operating modes (modes 1, 2, and 3), but also when programming the flash memory with a PROM writer. When using a PROM programmer to program dual-power-supply flash memory, therefore, the PROM programmer specifications should provide for this pin to be held at the V CC level except when programming (FVPP = 12 V). * Differs as in mode 3, depending on whether the host interface is enabled or disabled. 15 Table 1.2 (b) Pin Assignments for H8/3397 H8/3397 Series in Each Operating Mode Pin No. Expanded Modes Single-Chip Mode FP-80A FP-80A, TFP-80C TFP-80C CP-84 CP-84, CG-84 CG-84 Mode 1 Mode 2 Mode 3 1 12 RES RES RES 2 13 XTAL XTAL XTAL 3 14 EXTAL EXTAL EXTAL 4 15 MD1 MD1 MD1 5 16 MD0 MD0 MD0 6 17 NMI NMI NMI 7 18 STBY STBY STBY 8 19 VCC VCC VCC 9 20 P52/SCK0 P52/SCK0 P52/SCK0 P52/SCK0 P52/SCK0 P52/SCK0 10 21 P51/RxD0 P51/RxD0 P51/RxD0 11 22 P50/TxD0 P50/TxD0 P50/TxD0 12 23 VSS VSS VSS - 24 VSS VSS VSS 13 25 P97/WAIT P97/WAIT P97/WAIT P97/WAIT P97 14 26 ø