H8/3048 HD6473048 HD6433048 H8/3047 HD6433047 H8/3045 HD6433045 H8/3044 - Datasheet Archive

 

H8/3048 Series H8/3048 HD6473048, HD6433048 H8/3047 HD6433047 H8/3045 HD6433045 H8/3044 HD6433044 H8/3048F-ZTATTM H8/3048F

 

Hitachi Single-Chip Microcomputer H8/3048 H8/3048 Series H8/3048 H8/3048 HD6473048 HD6473048, HD6433048 HD6433048 H8/3047 H8/3047 HD6433047 HD6433047 H8/3045 H8/3045 HD6433045 HD6433045 H8/3044 H8/3044 HD6433044 HD6433044 H8/3048F-ZTATTM H8/3048F-ZTATTM H8/3048F H8/3048F HD64F3048 HD64F3048 Hardware Manual ADE-602-073E ADE-602-073E Rev. 6.0 9/3/2002 Hitachi, Ltd. Cautions 1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products. Preface The H8/3048 H8/3048 Series is a series of high-performance microcontrollers that integrate system supporting functions together with an H8/300H H8/300H CPU core. The H8/300H H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. The on-chip supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller (DMAC), a refresh controller, and other facilities. Of the two SCI channels, one has been expanded to support the ISO/IEC7816-3 ISO/IEC7816-3 smart card interface. Functions have also been added to reduce power consumption in battery-powered applications: individual modules can be placed in standby, and the frequency of the system clock supplied to the chip can be divided down under software control. The address space is divided into eight areas. The data bus width and access cycle length can be selected independently in each area, simplifying the connection of different types of memory. Seven operating modes (modes 1 to 7) are provided, offering a choice of data bus width and address space size. With these features, the H8/3048 H8/3048 Series can be used to implement compact, high-performance systems easily. In addition to its mask ROM versions, the H8/3048 H8/3048 Series has a ZTATTM* version with user2 programmable on-chip PROM and an F-ZTATTM* version with on-chip flash memory that can be programmed on-board. These versions enable users to respond quickly and flexibly to changing application specifications. 1 The on-chip emulator (E10T) is installed on the H8/3048F-ONE H8/3048F-ONE in the H8/3048 H8/3048 series microcomputer. Refer to the H8/3048F-ONE H8/3048F-ONE Hardware Manual for details. This manual describes the H8/3048 H8/3048 Series hardware. For details of the instruction set, refer to the H8/300H H8/300H Series Programming Manual. Notes: *1 ZTATTM (Zero Turn-Around-Time) is a trademark of Hitachi, Ltd. *2 F-ZTATTM (Flexible ZTAT) is a trademark of Hitachi, Ltd. Rev. 6.0, 09/02, page iii of xxxii Rev. 6.0, 09/02, page iv of xxxii List of Items Revised or Added for This Version Section Page All Comparison of H8/3048 H8/3048 Series Product Specifications Descriptions Description of H8/3048F-ONE H8/3048F-ONE deleted. xvii, xviii Description amended. Hardware Manual ROM Type H8/3048 H8/3048 Series (Rev. 6.0) ZTAT H8/3048F-ONE H8/3048F-ONE (Rev. 1.0) Mask ROM F-ZTAT Model Type H8/3048 H8/3048 H8/3048 H8/3048 mask ROM version H8/3048F H8/3048F H8/3047 H8/3047 mask ROM version H8/3045 H8/3045 mask ROM version H8/3044 H8/3044 mask ROM version H8/3048F-ONE H8/3048F-ONE Model Spec PROM model Mask ROM model Dual power supply, flash memory is installed Single power supply, flash memory installed, internal step-down, high-speed operation model Refer to 1.4, Differences between H8/3048F H8/3048F and H8/3048F-ONE H8/3048F-ONE. Refer to 1.4.3, Differences between H8/3048F H8/3048F and H8/3048F-ONE H8/3048F-ONE. HD64F3048 HD64F3048 HD64F3048B HD64F3048B Model Type No. HD6473048 HD6473048 HD6433048 HD6433048 HD6433047 HD6433047 HD6433045 HD6433045 HD6433044 HD6433044 Pin Assignment Refer to figure 1.2, Pin Arrangement of H8/3048ZTAT H8/3048ZTAT, H8/3048 H8/3048 Mask ROM Version, H8/3047 H8/3047 Mask ROM Version, H8/3045 H8/3045 Mask ROM Version, H8/3044 H8/3044 Mask ROM Version, and H8/3048F H8/3048F (FP-100B FP-100B or TFP-100B TFP-100B, Top View), in section 1. 5-V operation models have a VCL pin and an external capacitor must be connected. Refer to figure 1.3, H8/3048F-ONE H8/3048F-ONE Pin Arrangement (FP-100B FP-100B or TFP-100B TFP-100B, Top View), in section 1. RAM Capacity 4 kbytes Hardware Manual ROM Type ROM Capacity Flash Memory Clock Pulse Generator Power-Down State H8/3048 H8/3048: 4 kbytes H8/3047 H8/3047: 4 kbytes H8/3045 H8/3045: 2 kbytes H8/3044 H8/3044: 2 kbytes 4 kbytes 4 kbytes H8/3048 H8/3048 Series (Rev. 6.0) ZTAT 128 kbytes H8/3048 H8/3048: 128 kbytes H8/3047 H8/3047: 96 kbytes H8/3045 H8/3045: 64 kbytes H8/3044 H8/3044: 32 kbytes H8/3048F-ONE H8/3048F-ONE (Rev. 1.0) Mask ROM - - F-ZTAT 128 kbytes 128 kbytes Refer to section 19, ROM (H8/3048F H8/3048F). Refer to section 18, Flash Memory (H8/3048F-ONE H8/3048F-ONE Single Power Supply). Refer to section 20, Clock Pulse Generator. Refer to section 19, Clock Pulse Generator. List of Registers Refer to section 20, Power-Down State. Clock oscillator settling time: Waiting time of up to 262144 states Refer to table 22.1, Electrical Characteristics of H8/3048 H8/3048 Series Products, in section 22. Refer to table 21.1, Electrical Characteristics of H8/3048 H8/3048 Series Products, in section 21. 1 to 18 MHz Electrical Characteristics (Clock Rate) Refer to section 21, Power-Down State. Clock oscillator settling time: Waiting time of up to 131072 states 5 V operation models: 2 to 25 MHz, 3 V operation models: 2 to 25 MHz. 1 to 16 MHz Refer to table B.1, Comparison of H8/3048 H8/3048 Series Internal I/O Register Specifications, in appendix B. Refer to appendix B.1, Addresses. Notes on Usage - - - Refer to section 1.4, Notes on H8/3048FONE H8/3048FONE (Single Power Supply). On-chip Emulator (E10T) - - - On-chip emulator (E10T) Rev. 6.0, 09/02, page v of xxxii Section Page Descriptions 1.1 Overview 2 to 6 Feature of CPU, memory, and product lineup: Description of H8/3048F-ONE H8/3048F-ONE deleted. Table 1.1 Features CPU description added (also usable as sixteen 8-bit registers + eight 16-bit registers or eight 32-bit registers) 1.2 Block Diagram 7 Description of H8/3048F-ONE H8/3048F-ONE deleted. 8 Description of H8/3048F-ONE H8/3048F-ONE deleted. Figure 1.1 Block Diagram 1.3.1 Pin Arrangement Table 1.2 Table 1.2 Comparison of H8/3048 H8/3048 Series Pin Arrangements Description of H8/3048F-ONE H8/3048F-ONE deleted. Figure 1.2 Figure 1.2 Connection of Pin 1 1.3.1 Pin Arrangement Deleted. 9 Note Description of FWE terminal deleted. Figure 1.2 Pin Arrangement of H8/3048ZTAT H8/3048ZTAT, H8/3048 H8/3048 Mask ROM Version, H8/3047 H8/3047 Mask ROM Version, H8/3045 H8/3045 Mask ROM Version, H8/3044 H8/3044 Mask ROM Version, and H8/3048F H8/3048F (FP-100B FP-100B or TFP-100B TFP-100B, Top View) Figure 1.3(2) Arrangement (FP-100B FP-100B or TFP-100B TFP-100B, Top View) 1.3.2 Pin Assignments in Each Mode - 10, 14 Deleted. Pin No. 1 and 10: Description deleted "Flash memory version with single power supply" Notes: Description of *4 amended, *3 and *4 deleted. Table 1.3 Pin Assignments in Each Mode (FP-100B FP-100B or TFP100B TFP100B) 1.3.3 Pin Functions *4 For the H8/3048 H8/3048 ZTAT version, H8/3048F H8/3048F version, H8/3048 H8/3048 mask ROM version, H8/3047 H8/3047 mask ROM version, H8/3045 H8/3045 mask ROM version, and H8/3044 H8/3044 mask ROM version, this pin is used as the RESO terminal. 15 to 19 Description of H8/3048F-ONE H8/3048F-ONE deleted. Table 1.4 Pin Functions The following types of description deleted. Internal step-down pin and system control of FWE pin Notes deleted. 1.4 Notes on H8/3048F- H8/3048F- ONE (Single Power Supply) Deleted. 1.5 Setting Oscillation Settling Wait Time - Deleted. 1.6 Caution on Crystal Resonator Connection - Deleted. 1.4 Differences between H8/3048F H8/3048F and H8/3048FONE H8/3048FONE 20 to 23 Newly added. Rev. 6.0, 09/02, page vi of xxxii Section Page Descriptions 2.1.1 Features 25, 26 High-speed operation: Description of H8/3048F-ONE H8/3048F-ONE deleted. · Maximum clock frequency: 25MHz description deleted. · The following description deleted. - - - - - 2.7.2 Effective Address Calculation 56 8/16/32-bit register-register add/subtract: 80 ns @ 25 MHz 8 - 8-bit register-register multiply: 560 ns @ 25 MHz 16 ÷ 8-bit register-register divide: 560 ns @ 25 MHz 16 - 16-bit register-register multiply: 880 ns @ 25 MHz 32 ÷ 16-bit register-register divide: 880 ns @ 25 MHz Description of normal mode added. · Normal mode Table 2.13 Effective Address Calculation op abs 23 87 H'0000 0 abs 0 15 Memory contents 3.2 Mode Control Register 66 (MDCR) 68 84 0 Bits 6 to 4 2. For the H8/3048F-ONE H8/3048F-ONE version deleted. 4.2.2 Reset Sequence 16 15 H'00 Note deleted. 3.3 System Control Register (SYSCR) 23 Description of Flash memory version deleted. For the flash memory version with single power supply (H8/3048F-ONE H8/3048F-ONE), hold the RES pin low for at least 20 system clock () cycles. 4.3 Interrupts 88 5.1.1 Features 91 Note deleted. Note deleted. 5.1.3 Pin Configuration 93 Note deleted. 105 Notes deleted. 5.4.1 Interrupt Handling Process 110 Note deleted. 5.5.4 Usage Notes on External Interrupts 118 Description amended. Table 5.1 Interrupt Pins 5.3.1 External Interrupts NMI The IRQnF flag specification calls for the flag to be cleared by writing 0 to it after it has been read while set to 1. However, it is possible for the IRQnF flag to be cleared by mistake simply by writing 0 to it, irrespective of whether it has been read while set to 1, with the result that interrupt exception handling is not executed. This occurs when the following conditions are fulfilled. · Setting conditions 1. Multiple external interrupts (IRQa, IRQb) are being used. 2. Different clearing methods are being used: clearing by writing 0 for the IRQaF flag, and clearing by hardware for the IRQbF flag. 3. A bit manipulation instruction is used on the IRQ status register to clear the IRQaF flag, or else ISR is read as a byte unit, the IRQaF flag bit is cleared, and the values read in the other bits are written as a byte unit. Rev. 6.0, 09/02, page vii of xxxii Section Page Descriptions 5.5.4 Usage Notes on External Interrupts 120 Description amended. Countermeasure 1: When clears IRQaF flag, do not use the bit manipulation instruction, read the ISR in bytes. Then write a value in bytes which sets IRQnF flag to 0 and other bits to 1. Countermeasure 6.1.1 Features 123 Description amended. · Bus arbitration function - A built-in bus arbiter arbitrates the bus right to the CPU, DMAC, refresh controller, or an external bus master. 6.3.6 Interconnections with 152 Memory (Example) Description amended. EPROM A19 to A 1 Figure 6.18 Interconnections with Memory (Example) A 18 to A 0 I/O 15 to I/O8 I/O 7 to I/O 0 9.1 Overview 259, Table 9.1 Port Functions 260 Description amended and deleted. Port 8 Description amended Port Description Pins Port 8 · 5-bit I/O port P84/ Mode 1 · P82 to P80 have Schmitt inputs P83/ 1/ P82/ S2/ P81/ 3/ P80/ Mode 2 Mode 3 DDR = 1 (after reset): , , 3 3 2 / to 1 input, DDR = 1: 0 0 input, 1 to 3 · Schmitt inputs output Description amended PB6/TP14/DREQ0/CS7 PB6/TP14/DREQ0/CS7 Description of pin amended. P60/WAIT P60/WAIT 295 Description amended. Figure 9.10 Port A Pin Configuration Port A: Output deleted PA6/TP6/TIOCA2/A21/CS4 PA6/TP6/TIOCA2/A21/CS4 PA5/TP5/TIOCB1/A22/CS5 PA5/TP5/TIOCB1/A22/CS5 PA4/TP4/TIOCA1/A23/CS6 PA4/TP4/TIOCA1/A23/CS6 Pin function in modes 3, 4, and 6: Output added A20 (output) Rev. 6.0, 09/02, page viii of xxxii Mode 6 output to 3 output, and generic input output output, and generic input/output Port B 9.11.1 Overview 0 1 Description deleted. Table 9.11 Port 6 Pin Functions in Modes 1 to 6 Mode 5 DDR = 0 (after reset): generic input 1 Port A 9.7.2 Register Descriptions 281 Mode 4 DDR = 0: generic input 0 Mode 7 Generic input/ output 3 to 0 input and generic input/ output Section Page Descriptions 9.11.3 Pin Functions 298, 300, 303 PA7/TP7/TIOCB2/A20 PA7/TP7/TIOCB2/A20 Table 9.19 Port A Pin Functions ITU channel 2 settings amended. Mode 1, 2, 5, 7 3, 4, 6 ITU channel 2 settings (1) in table below PA7DDR - 0 1 1 NDER7 - - 0 1 - TIOCB2 output PA7 input PA7 output TP7 output A20 output Pin function (2) in table below - - TIOCB2 input* Note: * TIOCB2 input when IOB2 = 1 and PWM2 = 0. PA5/TP5/TIOCB1/A22/CS5 PA5/TP5/TIOCB1/A22/CS5 Description amended. CS5 output PA1/TP1/TCLKB/TEND1 Pin function amended. DMAC channel 1 settings (1) in table below (2) in table below PA1DDR - 0 1 1 NDER1 - - 0 1 PA1 output TP1 output Pin function 1 output PA1 input TCLKB input* Note: * TCLKB input when MDF = 1 in TMDR, or when TPSC2 = 1, TPSC1 = 0, and TPSC0 = 1 in any of TCR4 to TCR0. PA0/TP0/TCLKA/TEND0 Pin function amended. DMAC channel 0 settings (1) in table below PA0DDR - 0 1 1 NDER0 - - 0 1 PA0 output TP0 output Pin function 0 output (2) in table below PA0 input TCLKA input* Note: * TCLKA input when MDF = 1 in TMDR, or when TPSC2 = 1 and TPSC1 = 0 in any of TCR4 to TCR0. 10.2.4 Timer Function Control Register (TFCR) 332 12.1.1 Features 435 Description amended. When these bits select complementary PWM mode or reset-synchronized PWM mode, they take precedence over the setting of the PWM mode bits (PWM4 and PWM3) in TMDR. Settings of complementary PWM mode or reset-synchronized PWM mode and settings of timer sync bits SYNC4 and SYNC3 in TSNC are valid simultaneously, however, when complementary PWM mode is selected, channels 3 and 4 must not be synchronized (do not set bits SYNC3 and SYNC4 both to 1 in TSNC). Description of H8/3048F-ONE H8/3048F-ONE amended. · Watchdog timer reset signal resets the entire chip internally, and can also be output externally. 12.1.3 Pin Configuration 436 Description of H8/3048F-ONE H8/3048F-ONE deleted. 440 Description of H8/3048F-ONE H8/3048F-ONE deleted. Table 12.1 WDT Pin 12.2.3 Reset Control/ Status Register (RSTCSR) Rev. 6.0, 09/02, page ix of xxxii Section Page Descriptions 12.3.1 Watchdog Timer Operation 443 Description of H8/3048F-ONE H8/3048F-ONE deleted. 13.2.8 Bit Rate Register (BRR) 469, 470, Table 13.3 Examples of 472, 473 Bit Rates and BRR Table amended. Description of 20 and 25 MHz deleted. Settings in Asynchronous Mode Table 13.4 Examples of Bit Rates and BRR Settings in Synchronous Mode Table 13.5 Maximum Bit Rates for Various Frequencies (Asynchronous Mode) Table 13.6 Maximum Bit Rates with External Clock Input (Asynchronous Mode) Table 13.7 Maximum Bit Rates with External Clock Input (Synchronous Mode) 13.3.2 Operation in Asynchronous Mode 482 Description amended. PER FER ORER = 1? · Receiving Serial Data (Asynchronous Mode) Figure 13.7 Sample Flowchart for Receiving Serial Data (1) 13.3.3 Multiprocessor Communication 489 Description amended. Transmitting and Receiving Data · Receiving Multiprocessor Serial Data Figure 13.12 Sample Flowchart for Receiving Multiprocessor Serial Data (1) Rev. 6.0, 09/02, page x of xxxii FER ORER = 1 Section Page Descriptions 13.3.4 Synchronous Operation 494 Description of 1 amended. 1. SCI initialization: the transmit data output function of the TxD pin is selected automatically. Transmitting and Receiving Data · Transmitting Serial Data (Synchronous Mode) Figure 13.16 Sample Flowchart for Serial Transmitting 13.5 Usage Notes 503 Restrictions on Usage of the Serial Clock 14.3.5 Clock Table 14.5 Bit Rates (bits/s) for Different BRR Settings (when n = 0) Description amended. When transmitting data using an external clock as the serial clock, an interval of at least 5 states is necessary between clearing the TDRE bit in SSR and the Start (falling edge) of the first transmit clock pulse corresponding to each frame (see figure 13.22). This condition is also needed for continuous transmission. If ti is not fulfilled, operational error will occur. 520, 521 Description of 20 and 25 MHz deleted. 533 · High-speed conversion Table 14.6 BRR Settings for Typical Bit Rate (bits/s) (when n = 0) 15.1.1 Features Description of 18MHz amended and 25MHz deleted Conversion time: Minimum 7.45 µs per channel (with 18 MHz system clock) 15.1.4 Register Configuration 536 Description of H8/3048F-ONE H8/3048F-ONE deleted. Initial value of H'FFE9: H'7E deleted. Table 15.2 A/D Converter Registers Notes: *4 deleted. 15.2.3 A/D Control Register (ADCR) 540 Description of H8/3048F-ONE H8/3048F-ONE deleted. 15.6 Usage Notes 550 Description amended. 7. A/D Conversion Accuracy Definitions: A/D conversion accuracy in the H8/3048 H8/3048 Series is defined as follows: · Offset error Deviation from ideal A/D conversion characteristic of analog input voltage required to raise digital output from minimum voltage value B'0000000000 to B'0000000001 (figure 15.10) · Full-scale error Deviation from ideal A/D conversion characteristic of analog input voltage required to raise digital output from B'1111111110 to B'1111111111 (figure 15.10) 16.1.1 Features 555 Output voltage amended. 18.1 Overview 567 Note: Description of H8/3048F-ONE H8/3048F-ONE Hardware Manual (Rev. 1.0) added. 578 Newly added. · Output voltage: 0 V to 255/256 * VREF Table 18.1 Operating Mode and ROM 18.4 Notes on Ordering Mask ROM Version Chip Rev. 6.0, 09/02, page xi of xxxii Section Page Descriptions 19.8 Flash Memory Programming and Erasing Precautions (Dual-Power Supply) 641, 645, 647 Description of H8/3048F-ONE H8/3048F-ONE deleted. Section 20 Flash Memory (H8/3048F-ONE H8/3048F-ONE: Single Power Supply) - Deleted. 20.2.1 Connecting a Crystal Resonator 653 Description added. (1) Program with the specified voltages and timing. (7) If the watchdog timer generates a reset output signal when 12 V is not applied, the rise and fall of the reset output waveform will be delayed by any decoupling capacitors connected to the VPP pin. Figure 19.25 VPP Power Supply Circuit Design (Example) (8) Notes concerning mounting board development-handling of VPP and mode MD2 pins Figure 19.26 Example of Mounting Board Design for the H8/3048F-ZTAT H8/3048F-ZTAT with the Dual-Power Supply CL1 = CL2 = 10 pF to 20 pF Figure 20.2 Connection of Crystal Resonator (Example) 20.2.1 Connecting a Crystal Resonator 653 Description of 20MHz deleted. Table 20.1 Circuit Configuration · H8/3048F-ONE H8/3048F-ONE description and damping resistance value of 18 < f 25 deleted. Table 20.1 Damping Resistance Value · Damping resistance value amended. 4 12 MHz. 23.3 Electrical Characteristics of H8/3048F-ONE H8/3048F-ONE (SinglePower Supply) - Deleted. Appendix B Internal I/O Register 753 Description of H8/3048F-ONE H8/3048F-ONE deleted. B.2 Addresses (For H8/3048F-ONE H8/3048F-ONE) - Deleted. B.2 Function 779 Description of H8/3048F-ONE H8/3048F-ONE deleted. - Deleted. 780 Description of H8/3048F-ONE H8/3048F-ONE deleted. - Deleted. 781 Description of H8/3048F-ONE H8/3048F-ONE deleted. - Deleted. 782 Description of H8/3048F-ONE H8/3048F-ONE deleted. 811 Description of H8/3048F-ONE H8/3048F-ONE deleted. 835 Description of H8/3048F-ONE H8/3048F-ONE deleted. Table B.1 Comparison of H8/3048 H8/3048 Series Internal I/O Register Specifications FLMCR B.2 Function FLMCR 1 FLMCR (FLMCR2) B.2 Function EBR1 B.2 Function EBR B.2 Function EBR2 B.2 Function RAMCR (H'47) B.2 Function RAMCR (H'48) B.2 Function RSTCSR B.2 Function ADCR Rev. 6.0, 09/02, page xiv of xxxii Section Page Descriptions D.1 Port States in Each Mode 867, 869 Description amended. Pin Name Mode Reset - Clock output RESO *2 - T*2 P17 to P10 1 to 4 L 5, 6 T 7 T 1 to 4 L 5, 6 T 7 Table D.1 Port States T 3, 4, 6 L *4 T*4 P27 to P20 PA 7 1, 2, 5, 7 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode 873 t1 10tcyc Timing of Transition to Hardware Standby Mode Appendix F Product Code Lineup Description added. 874 t2 0 ns Description of H8/3048F-ONE H8/3048F-ONE deleted. Table F.1 H8/3048 H8/3048 Series Product Code Lineup Rev. 6.0, 09/02, page xv of xxxii Rev. 6.0, 09/02, page xvi of xxxii Comparison of H8/3048 H8/3048 Series Product Specifications 1 There are seven members of the H8/3048 H8/3048 Series; the H8/3048F-ZTAT H8/3048F-ZTAT (H8/3048F H8/3048F* , H8/3048F2 H8/3048F2 ONE* ), H8/3048ZTAT H8/3048ZTAT, H8/3048 H8/3048 mask ROM version, H8/3047 H8/3047 mask ROM version, H8/3045 H8/3045 mask ROM version, and H8/3044 H8/3044 mask ROM version. The specifications of each model is compared below. Notes: *1 H8/3048F H8/3048F has dual power supply with flash memory installed. *2 H8/3048F-ONE H8/3048F-ONE has single power supply with flash memory and E10T installed. Refer to the H8/3048F-ONE H8/3048F-ONE Hardware Manual (revision 1) for details. Hardware Manual ROM Type H8/3048 H8/3048 Series (Rev. 6.0) ZTAT H8/3048F-ONE H8/3048F-ONE (Rev. 1.0) Mask ROM F-ZTAT Model Type H8/3048 H8/3048 H8/3048 H8/3048 mask ROM version H8/3048F H8/3048F H8/3047 H8/3047 mask ROM version H8/3045 H8/3045 mask ROM version H8/3044 H8/3044 mask ROM version H8/3048F-ONE H8/3048F-ONE Model Spec PROM model Mask ROM model Dual power supply, flash memory is installed Single power supply, flash memory installed, internal step-down, high-speed operation model Refer to 1.4, Differences between H8/3048F H8/3048F and H8/3048F-ONE H8/3048F-ONE. Refer to 1.4.3, Differences between H8/3048F H8/3048F and H8/3048F-ONE H8/3048F-ONE. HD64F3048 HD64F3048 HD64F3048B HD64F3048B Model Type No. HD6473048 HD6473048 HD6433048 HD6433048 HD6433047 HD6433047 HD6433045 HD6433045 HD6433044 HD6433044 Pin Assignment Refer to figure 1.2, Pin Arrangement of H8/3048ZTAT H8/3048ZTAT, H8/3048 H8/3048 Mask ROM Version, H8/3047 H8/3047 Mask ROM Version, H8/3045 H8/3045 Mask ROM Version, H8/3044 H8/3044 Mask ROM Version, and H8/3048F H8/3048F (FP-100B FP-100B or TFP-100B TFP-100B, Top View), in section 1. 5-V operation models have a VCL pin and an external capacitor must be connected. Refer to figure 1.3, H8/3048F-ONE H8/3048F-ONE Pin Arrangement (FP-100B FP-100B or TFP-100B TFP-100B, Top View), in section 1. RAM Capacity 4 kbytes H8/3048 H8/3048: 4 kbytes H8/3047 H8/3047: 4 kbytes H8/3045 H8/3045: 2 kbytes H8/3044 H8/3044: 2 kbytes 4 kbytes 4 kbytes Rev. 6.0, 09/02, page xvii of xxxii Hardware Manual ROM Type ROM Capacity Flash Memory H8/3048 H8/3048 Series (Rev. 6.0) ZTAT Mask ROM 128 kbytes H8/3048 H8/3048: 128 kbytes H8/3047 H8/3047: 96 kbytes H8/3045 H8/3045: 64 kbytes H8/3044 H8/3044: 32 kbytes H8/3048F-ONE H8/3048F-ONE (Rev. 1.0) - - F-ZTAT 128 kbytes 128 kbytes Refer to section 19, ROM (H8/3048F H8/3048F). Refer to section 18, Flash Memory (H8/3048F-ONE H8/3048F-ONE Single Power Supply). Clock Pulse Generator Refer to section 20, Clock Pulse Generator. Refer to section 19, Clock Pulse Generator. Power-Down State Refer to section 21, Power-Down State. Refer to section 20, Power-Down State. Clock oscillator settling time: Waiting time of up to 131072 states Clock oscillator settling time: Waiting time of up to 262144 states Refer to table 22.1, Electrical Characteristics of H8/3048 H8/3048 Series Products, in section 22. Refer to table 21.1, Electrical Characteristics of H8/3048 H8/3048 Series Products, in section 21. 1 to 18 MHz 5 V operation models: 2 to 25 MHz, 3 V operation models: 2 to 25 MHz. Electrical Characteristics (Clock Rate) 1 to 16 MHz List of Registers Refer to table B.1, Comparison of H8/3048 H8/3048 Series Internal I/O Register Specifications, in appendix B. Refer to appendix B.1, Addresses. Notes on Usage - - - Refer to section 1.4, Notes on H8/3048FONE H8/3048FONE (Single Power Supply). On-chip Emulator (E10T) - - - On-chip emulator (E10T) Rev. 6.0, 09/02, page xviii of xxxii Contents Section 1 1.1 1.2 1.3 1.4 Overview. 1 Overview. 1 Block Diagram . 7 Pin Description. 8 1.3.1 Pin Arrangement . 8 1.3.2 Pin Assignments in Each Mode . 10 1.3.3 Pin Functions . 15 Differences between H8/3048F H8/3048F and H8/3048F-ONE H8/3048F-ONE . 20 Section 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 CPU . 25 Overview. 2.1.1 Features. 2.1.2 Differences from H8/300 H8/300 CPU . CPU Operating Modes . Address Space. Register Configuration. 2.4.1 Overview. 2.4.2 General Registers . 2.4.3 Control Registers . 2.4.4 Initial CPU Register Values. Data Formats. 2.5.1 General Register Data Formats . 2.5.2 Memory Data Formats . Instruction Set . 2.6.1 Instruction Set Overview . 2.6.2 Instructions and Addressing Modes. 2.6.3 Tables of Instructions Classified by Function. 2.6.4 Basic Instruction Formats . 2.6.5 Notes on Use of Bit Manipulation Instructions. Addressing Modes and Effective Address Calculation . 2.7.1 Addressing Modes . 2.7.2 Effective Address Calculation . Processing States. 2.8.1 Overview. 2.8.2 Program Execution State. 2.8.3 Exception-Handling State . 2.8.4 Exception-Handling Sequences . 2.8.5 Bus-Released State. 2.8.6 Reset State. 25 25 26 27 28 29 29 30 31 32 33 33 35 36 36 37 38 48 49 50 50 53 57 57 58 58 60 61 61 Rev. 6.0, 09/02, page xix of xxxii 2.9 2.8.7 Power-Down State . Basic Operational Timing . 2.9.1 Overview. 2.9.2 On-Chip Memory Access Timing. 2.9.3 On-Chip Supporting Module Access Timing . 2.9.4 Access to External Address Space . Section 3 3.1 3.2 3.3 3.4 3.5 3.6 MCU Operating Modes . Overview. 3.1.1 Operating Mode Selection . 3.1.2 Register Configuration. Mode Control Register (MDCR) . System Control Register (SYSCR) . Operating Mode Descriptions . 3.4.1 Mode 1 . 3.4.2 Mode 2 . 3.4.3 Mode 3 . 3.4.4 Mode 4 . 3.4.5 Mode 5 . 3.4.6 Mode 6 . 3.4.7 Mode 7 . Pin Functions in Each Operating Mode . Memory Map in Each Operating Mode . Section 4 4.1 4.2 4.3 4.4 4.5 4.6 Exception Handling . Overview. 4.1.1 Exception Handling Types and Priority. 4.1.2 Exception Handling Operation . 4.1.3 Exception Vector Table . Reset . 4.2.1 Overview. 4.2.2 Reset Sequence . 4.2.3 Interrupts after Reset. Interrupts. Trap Instruction. Stack Status after Exception Handling. Notes on Stack Usage . Section 5 5.1 Interrupt Controller . Overview. 5.1.1 Features. 5.1.2 Block Diagram. 5.1.3 Pin Configuration. Rev. 6.0, 09/02, page xx of xxxii 61 62 62 62 63 64 65 65 65 66 66 67 69 69 69 69 69 69 70 70 70 71 81 81 81 81 82 84 84 84 87 88 89 89 90 91 91 91 92 93 5.2 5.3 5.4 5.5 5.1.4 Register Configuration. Register Descriptions . 5.2.1 System Control Register (SYSCR) . 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB). 5.2.3 IRQ Status Register (ISR). 5.2.4 IRQ Enable Register (IER) . 5.2.5 IRQ Sense Control Register (ISCR) . Interrupt Sources. 5.3.1 External Interrupts . 5.3.2 Internal Interrupts . 5.3.3 Interrupt Vector Table . Interrupt Operation. 5.4.1 Interrupt Handling Process . 5.4.2 Interrupt Sequence . 5.4.3 Interrupt Response Time. Usage Notes . 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction . 5.5.2 Instructions that Inhibit Interrupts. 5.5.3 Interrupts during EEPMOV Instruction Execution. 5.5.4 Usage Notes on External Interrupts . 5.5.5 Notes on Non-Maskable Interrupts (NMI). Section 6 6.1 6.2 6.3 Bus Controller . Overview. 6.1.1 Features. 6.1.2 Block Diagram. 6.1.3 Input/Output Pins. 6.1.4 Register Configuration. Register Descriptions . 6.2.1 Bus Width Control Register (ABWCR). 6.2.2 Access State Control Register (ASTCR) . 6.2.3 Wait Control Register (WCR). 6.2.4 Wait State Controller Enable Register (WCER) . 6.2.5 Bus Release Control Register (BRCR) . 6.2.6 Chip Select Control Register (CSCR). Operation . 6.3.1 Area Division. 6.3.2 Chip Select Signals . 6.3.3 Data Bus. 6.3.4 Bus Control Signal Timing . 6.3.5 Wait Modes. 6.3.6 Interconnections with Memory (Example) . 6.3.7 Bus Arbiter Operation. 93 94 94 95 102 103 104 105 105 106 106 110 110 115 116 117 117 118 118 118 120 123 123 123 124 125 126 126 126 127 128 129 130 131 133 133 134 136 137 145 151 153 Rev. 6.0, 09/02, page xxi of xxxii 6.4 Usage Notes . 6.4.1 Connection to Dynamic RAM and Pseudo-Static RAM. 6.4.2 Register Write Timing . 6.4.3 BREQ Input Timing. 6.4.4 Transition To Software Standby Mode. Section 7 7.1 7.2 7.3 7.4 7.5 Refresh Controller . Overview. 7.1.1 Features. 7.1.2 Block Diagram. 7.1.3 Input/Output Pins. 7.1.4 Register Configuration. Register Descriptions . 7.2.1 Refresh Control Register (RFSHCR). 7.2.2 Refresh Timer Control/Status Register (RTMCSR) . 7.2.3 Refresh Timer Counter (RTCNT). 7.2.4 Refresh Time Constant Register (RTCOR) . Operation . 7.3.1 Overview. 7.3.2 DRAM Refresh Control. 7.3.3 Pseudo-Static RAM Refresh Control . 7.3.4 Interval Timer . Interrupt Source . Usage Notes . Section 8 8.1 8.2 8.3 8.4 156 156 156 158 158 159 159 159 160 161 161 162 162 165 166 167 168 168 170 185 189 195 195 DMA Controller . 197 Overview. 8.1.1 Features. 8.1.2 Block Diagram. 8.1.3 Functional Overview. 8.1.4 Input/Output Pins. 8.1.5 Register Configuration. Register Descriptions (Short Address Mode). 8.2.1 Memory Address Registers (MAR) . 8.2.2 I/O Address Registers (IOAR) . 8.2.3 Execute Transfer Count Registers (ETCR). 8.2.4 Data Transfer Control Registers (DTCR) . Register Descriptions (Full Address Mode). 8.3.1 Memory Address Registers (MAR) . 8.3.2 I/O Address Registers (IOAR) . 8.3.3 Execute Transfer Count Registers (ETCR). 8.3.4 Data Transfer Control Registers (DTCR) . Operation . Rev. 6.0, 09/02, page xxii of xxxii 197 197 198 199 201 201 203 203 204 205 206 209 209 209 210 212 218 8.5 8.6 8.4.1 Overview. 8.4.2 I/O Mode. 8.4.3 Idle Mode. 8.4.4 Repeat Mode . 8.4.5 Normal Mode. 8.4.6 Block Transfer Mode . 8.4.7 DMAC Activation. 8.4.8 DMAC Bus Cycle . 8.4.9 DMAC Multiple-Channel Operation . 8.4.10 External Bus Requests, Refresh Controller, and DMAC . 8.4.11 NMI Interrupts and DMAC . 8.4.12 Aborting a DMA Transfer . 8.4.13 Exiting Full Address Mode. 8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode . Interrupts. Usage Notes . 8.6.1 Note on Word Data Transfer. 8.6.2 DMAC Self-Access . 8.6.3 Longword Access to Memory Address Registers . 8.6.4 Note on Full Address Mode Setup. 8.6.5 Note on Activating DMAC by Internal Interrupts . 8.6.6 NMI Interrupts and Block Transfer Mode . 8.6.7 Memory and I/O Address Register Values . 8.6.8 Bus Cycle when Transfer is Aborted . Section 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 218 220 222 225 229 232 237 239 245 246 247 248 249 250 251 252 252 252 252 252 252 254 254 255 I/O Ports . 257 Overview. Port 1. 9.2.1 Overview. 9.2.2 Register Descriptions . Port 2. 9.3.1 Overview. 9.3.2 Register Descriptions . Port 3. 9.4.1 Overview. 9.4.2 Register Descriptions . Port 4. 9.5.1 Overview. 9.5.2 Register Descriptions . Port 5. 9.6.1 Overview. 9.6.2 Register Descriptions . Port 6. 257 261 261 262 264 264 265 268 268 268 270 270 271 274 274 275 278 Rev. 6.0, 09/02, page xxiii of xxxii 9.7.1 Overview. 9.7.2 Register Descriptions . 9.8 Port 7. 9.8.1 Overview. 9.8.2 Register Description. 9.9 Port 8. 9.9.1 Overview. 9.9.2 Register Descriptions . 9.10 Port 9. 9.10.1 Overview. 9.10.2 Register Descriptions . 9.11 Port A. 9.11.1 Overview. 9.11.2 Register Descriptions . 9.11.3 Pin Functions . 9.12 Port B . 9.12.1 Overview. 9.12.2 Register Descriptions . 9.12.3 Pin Functions . 278 279 282 282 283 284 284 285 289 289 290 294 294 296 298 304 304 306 308 Section 10 16-Bit Integrated Timer Unit (ITU) . 313 10.1 Overview. 10.1.1 Features. 10.1.2 Block Diagrams . 10.1.3 Input/Output Pins. 10.1.4 Register Configuration. 10.2 Register Descriptions . 10.2.1 Timer Start Register (TSTR). 10.2.2 Timer Synchro Register (TSNC) . 10.2.3 Timer Mode Register (TMDR) . 10.2.4 Timer Function Control Register (TFCR). 10.2.5 Timer Output Master Enable Register (TOER) . 10.2.6 Timer Output Control Register (TOCR) . 10.2.7 Timer Counters (TCNT) . 10.2.8 General Registers (GRA, GRB). 10.2.9 Buffer Registers (BRA, BRB) . 10.2.10 Timer Control Registers (TCR) . 10.2.11 Timer I/O Control Register (TIOR) . 10.2.12 Timer Status Register (TSR). 10.2.13 Timer Interrupt Enable Register (TIER) . 10.3 CPU Interface. 10.3.1 16-Bit Accessible Registers . 10.3.2 8-Bit Accessible Registers . Rev. 6.0, 09/02, page xxiv of xxxii 313 313 316 321 322 325 325 326 328 331 333 335 336 337 338 339 341 343 345 347 347 349 10.4 Operation . 10.4.1 Overview. 10.4.2 Basic Functions. 10.4.3 Synchronization . 10.4.4 PWM Mode. 10.4.5 Reset-Synchronized PWM Mode. 10.4.6 Complementary PWM Mode. 10.4.7 Phase Counting Mode. 10.4.8 Buffering. 10.4.9 ITU Output Timing . 10.5 Interrupts. 10.5.1 Setting of Status Flags . 10.5.2 Clearing of Status Flags . 10.5.3 Interrupt Sources and DMA Controller Activation. 10.6 Usage Notes . 351 351 352 361 363 367 370 379 381 388 390 390 392 393 394 Section 11 Programmable Timing Pattern Controller. 409 11.1 Overview. 11.1.1 Features. 11.1.2 Block Diagram. 11.1.3 TPC Pins . 11.1.4 Registers. 11.2 Register Descriptions . 11.2.1 Port A Data Direction Register (PADDR) . 11.2.2 Port A Data Register (PADR). 11.2.3 Port B Data Direction Register (PBDDR) . 11.2.4 Port B Data Register (PBDR) . 11.2.5 Next Data Register A (NDRA) . 11.2.6 Next Data Register B (NDRB). 11.2.7 Next Data Enable Register A (NDERA). 11.2.8 Next Data Enable Register B (NDERB) . 11.2.9 TPC Output Control Register (TPCR) . 11.2.10 TPC Output Mode Register (TPMR) . 11.3 Operation . 11.3.1 Overview. 11.3.2 Output Timing . 11.3.3 Normal TPC Output. 11.3.4 Non-Overlapping TPC Output. 11.3.5 TPC Output Triggering by Input Capture . 11.4 Usage Notes . 11.4.1 Operation of TPC Output Pins . 11.4.2 Note on Non-Overlapping Output. 409 409 410 411 412 413 413 413 414 414 415 417 419 420 421 423 425 425 426 427 429 431 432 432 432 Rev. 6.0, 09/02, page xxv of xxxii Section 12 Watchdog Timer . 435 12.1 Overview. 12.1.1 Features. 12.1.2 Block Diagram. 12.1.3 Pin Configuration. 12.1.4 Register Configuration. 12.2 Register Descriptions . 12.2.1 Timer Counter (TCNT). 12.2.2 Timer Control/Status Register (TCSR). 12.2.3 Reset Control/Status Register (RSTCSR) . 12.2.4 Notes on Register Access. 12.3 Operation . 12.3.1 Watchdog Timer Operation . 12.3.2 Interval Timer Operation . 12.3.3 Timing of Setting of Overflow Flag (OVF). 12.3.4 Timing of Setting of Watchdog Timer Reset Bit (WRST) . 12.4 Interrupts. 12.5 Usage Notes . 12.6 Notes . 435 435 436 436 437 437 437 438 440 441 443 443 444 444 445 446 446 447 Section 13 Serial Communication Interface . 449 13.1 Overview. 13.1.1 Features. 13.1.2 Block Diagram. 13.1.3 Input/Output Pins. 13.1.4 Register Configuration. 13.2 Register Descriptions . 13.2.1 Receive Shift Register (RSR) . 13.2.2 Receive Data Register (RDR) . 13.2.3 Transmit Shift Register (TSR) . 13.2.4 Transmit Data Register (TDR). 13.2.5 Serial Mode Register (SMR). 13.2.6 Serial Control Register (SCR). 13.2.7 Serial Status Register (SSR) . 13.2.8 Bit Rate Register (BRR) . 13.3 Operation . 13.3.1 Overview. 13.3.2 Operation in Asynchronous Mode . 13.3.3 Multiprocessor Communication. 13.3.4 Synchronous Operation. 13.4 SCI Interrupts. 13.5 Usage Notes . Rev. 6.0, 09/02, page xxvi of xxxii 449 449 451 452 452 453 453 453 454 454 455 458 462 466 474 474 476 485 492 500 501 Section 14 Smart Card Interface . 507 14.1 Overview. 14.1.1 Features. 14.1.2 Block Diagram. 14.1.3 Input/Output Pins. 14.1.4 Register Configuration. 14.2 Register Descriptions . 14.2.1 Smart Card Mode Register (SCMR) . 14.2.2 Serial Status Register (SSR) . 14.2.3 Serial Mode Register (SMR). 14.2.4 Serial Control Register (SCR). 14.3 Operation . 14.3.1 Overview. 14.3.2 Pin Connections . 14.3.3 Data Format . 14.3.4 Register Settings . 14.3.5 Clock. 14.3.6 Transmitting and Receiving Data . 14.4 Usage Notes . 507 507 508 509 509 510 510 511 513 514 515 515 515 517 518 520 522 528 Section 15 A/D Converter . 533 15.1 Overview. 15.1.1 Features. 15.1.2 Block Diagram. 15.1.3 Input Pins . 15.1.4 Register Configuration. 15.2 Register Descriptions . 15.2.1 A/D Data Registers A to D (ADDRA to ADDRD) . 15.2.2 A/D Control/Status Register (ADCSR) . 15.2.3 A/D Control Register (ADCR) . 15.3 CPU Interface. 15.4 Operation . 15.4.1 Single Mode (SCAN = 0) . 15.4.2 Scan Mode (SCAN = 1). 15.4.3 Input Sampling and A/D Conversion Time . 15.4.4 External Trigger Input Timing. 15.5 Interrupts. 15.6 Usage Notes . 533 533 534 535 536 537 537 538 540 541 542 542 544 546 547 548 548 Section 16 D/A Converter . 16.1 Overview. 16.1.1 Features. 16.1.2 Block Diagram. 555 555 555 556 Rev. 6.0, 09/02, page xxvii of xxxii 16.1.3 Input/Output Pins. 16.1.4 Register Configuration. Register Descriptions . 16.2.1 D/A Data Registers 0 and 1 (DADR0/1). 16.2.2 D/A Control Register (DACR) . 16.2.3 D/A Standby Control Register (DASTCR). Operation . D/A Output Control . Usage Notes . 557 557 558 558 558 560 561 562 562 Section 17 RAM . 17.1 Overview. 17.1.1 Block Diagram. 17.1.2 Register Configuration. 17.2 System Control Register (SYSCR) . 17.3 Operation . 563 563 564 564 565 566 16.2 16.3 16.4 16.5 Section 18 ROM (H8/3048ZTAT H8/3048ZTAT and Mask-ROM Versions) . 567 18.1 Overview. 18.1.1 Block Diagram. 18.2 PROM Mode. 18.2.1 PROM Mode Setting. 18.2.2 Socket Adapter and Memory Map . 18.3 PROM Programming . 18.3.1 Programming and Verification . 18.3.2 Programming Precautions. 18.3.3 Reliability of Programmed Data . 18.4 Notes on Ordering Mask ROM Version Chip. 567 568 569 569 569 571 572 576 577 578 Section 19 Flash Memory (H8/3048F H8/3048F: Dual Power Supply (VPP = 12 V) . 581 19.1 Overview. 581 19.2 Flash Memory Overview . 582 19.2.1 Flash Memory Operation . 582 19.2.2 Mode Programming and Flash Memory Address Space. 583 19.2.3 Features. 584 19.2.4 Block Diagram. 585 19.2.5 Input/Output Pins. 586 19.2.6 Register Configuration. 586 19.3 Flash Memory Register Descriptions. 587 19.3.1 Flash Memory Control Register. 587 19.3.2 Erase Block Register 1. 590 19.3.3 Erase Block Register 2. 591 19.3.4 RAM Control Register (RAMCR) . 593 Rev. 6.0, 09/02, page xxviii of xxxii 19.4 On-Board Programming Modes. 19.4.1 Boot Mode . 19.4.2 User Program Mode. 19.5 Programming and Erasing Flash Memory . 19.5.1 Program Mode . 19.5.2 Program-Verify Mode. 19.5.3 Programming Flowchart and Sample Program . 19.5.4 Erase Mode . 19.5.5 Erase-Verify Mode . 19.5.6 Erasing Flowchart and Sample Program. 19.5.7 Prewrite-Verify Mode. 19.5.8 Protect Modes . 19.5.9 NMI Input Masking . 19.6 Flash Memory Emulation by RAM. 19.7 Flash Memory PROM Mode. 19.7.1 PROM Mode Setting. 19.7.2 Socket Adapter and Memory Map . 19.7.3 Operation in PROM Mode. 19.8 Flash Memory Programming and Erasing Precautions (Dual-Power Supply). 19.9 Notes when Converting the F-ZTAT (Dual-Power Supply) Application Software to the Mask-ROM Versions . 594 595 600 602 603 603 604 607 607 608 622 623 626 627 629 629 630 632 641 649 Section 20 Clock Pulse Generator . 651 20.1 Overview. 20.1.1 Block Diagram. 20.2 Oscillator Circuit. 20.2.1 Connecting a Crystal Resonator. 20.2.2 External Clock Input. 20.3 Duty Adjustment Circuit. 20.4 Prescalers . 20.5 Frequency Divider . 20.5.1 Register Configuration. 20.5.2 Division Control Register (DIVCR) . 20.5.3 Usage Notes . 651 652 653 653 655 657 657 658 658 658 659 Section 21 Power-Down State . 661 21.1 Overview. 661 21.2 Register Configuration. 663 21.2.1 System Control Register (SYSCR) . 663 21.2.2 Module Standby Control Register (MSTCR) . 665 21.3 Sleep Mode . 667 21.3.1 Transition to Sleep Mode. 667 21.3.2 Exit from Sleep Mode. 667 Rev. 6.0, 09/02, page xxix of xxxii 21.4 Software Standby Mode. 21.4.1 Transition to Software Standby Mode . 21.4.2 Exit from Software Standby Mode . 21.4.3 Selection of Waiting Time for Exit from Software Standby Mode . 21.4.4 Sample Application of Software Standby Mode. 21.4.5 Note. 21.5 Hardware Standby Mode . 21.5.1 Transition to Hardware Standby Mode. 21.5.2 Exit from Hardware Standby Mode . 21.5.3 Timing for Hardware Standby Mode . 21.6 Module Standby Function. 21.6.1 Module Standby Timing . 21.6.2 Read/Write in Module Standby . 21.6.3 Usage Notes . 21.7 System Clock Output Disabling Function. 667 667 668 668 670 670 671 671 671 671 672 672 672 673 674 Section 22 Electrical Characteristics. 22.1 Electrical Characteristics for H8/3048 H8/3048 ZTAT (PROM) and On-Chip Mask ROM Versions . 22.1.1 Absolute Maximum Ratings . 22.1.2 DC Characteristics . 22.1.3 AC Characteristics . 22.1.4 A/D Conversion Characteristics. 22.1.5 D/A Conversion Characteristics. 22.2 Electrical Characteristics of H8/3048F H8/3048F (Dual-Power Supply) . 22.2.1 Absolute Maximum Ratings . 22.2.2 DC Characteristics . 22.2.3 AC Characteristics . 22.2.4 A/D Conversion Characteristics. 22.2.5 D/A Conversion Characteristics. 22.2.6 Flash Memory Characteristics . 22.3 Operational Timing. 22.3.1 Bus Timing . 22.3.2 Refresh Controller Bus Timing. 22.3.3 Control Signal Timing . 22.3.4 Clock Timing . 22.3.5 TPC and I/O Port Timing. 22.3.6 ITU Timing . 22.3.7 SCI Input/Output Timing. 22.3.8 DMAC Timing. 675 Appendix A A.1 677 677 678 684 691 692 693 693 694 701 707 708 709 710 710 714 719 721 721 722 723 724 Instruction Set. 725 Instruction List . 725 Rev. 6.0, 09/02, page xxx of xxxii A.2 A.3 Operation Code Map. 740 Number of States Required for Execution . 743 Appendix B B.1 B.2 Internal I/O Register . 753 Addresses . 754 Function . 762 Appendix C C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 I/O Port Block Diagrams . Port 1 Block Diagram . Port 2 Block Diagram . Port 3 Block Diagram . Port 4 Block Diagram . Port 5 Block Diagram . Port 6 Block Diagrams. Port 7 Block Diagrams. Port 8 Block Diagrams. Port 9 Block Diagrams. Port A Block Diagrams . Port B Block Diagrams . Appendix D D.1 D.2 842 842 843 844 845 846 847 851 852 855 859 863 Pin States. 867 Port States in Each Mode . 867 Pin States at Reset . 870 Appendix E Timing of Transition to and Recovery from Hardware Standby Mode . 873 Appendix F Product Code Lineup . 874 Appendix G Package Dimensions . 875 Rev. 6.0, 09/02, page xxxi of xxxii Rev. 6.0, 09/02, page xxxii of xxxii Section 1 Overview 1.1 Overview The H8/3048 H8/3048 Series is a series of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H H8/300H CPU core having an original Hitachi architecture. The H8/300H H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. Its instruction set is upward-compatible at the object-code level with the H8/300 H8/300 CPU, enabling easy porting of software from the H8/300 H8/300 Series. The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller (DMAC), a refresh controller, and other facilities. The four members of the H8/3048 H8/3048 Series are the H8/3048 H8/3048, the H8/3047 H8/3047, H8/3045 H8/3045, and the H8/3044 H8/3044. The H8/3048 H8/3048 has 128 kbytes of ROM and 4 kbytes of RAM. The H8/3047 H8/3047 has 96 kbytes of ROM and 4 kbytes of RAM. The H8/3045 H8/3045 has 64 kbytes of ROM and 2 kbytes of RAM. The H8/3044 H8/3044 has 32 kbytes of ROM and 2 kbytes of RAM. Seven MCU operating modes offer a choice of data bus width and address space size. The modes (modes 1 to 7) include one single-chip mode and six expanded modes. 1 In addition to the mask ROM versions of the H8/3048 H8/3048 Series, the H8/3048 H8/3048 has a ZTATTM* 2 version with user-programmable on-chip PROM and an F-ZTATTM* version with on-chip flash memory that can be programmed on-board. These versions enable users to respond quickly and flexibly to changing application specifications, growing production volumes, and other conditions. The F-ZTATTM version H8/3048F-ONE H8/3048F-ONE includes the on-chip emulator E10T. Table 1.1 summarizes the features of the H8/3048 H8/3048 Series. Notes: *1 ZTAT (Zero Turn-Around Time) is a trademark of Hitachi, Ltd. *2 F-ZTAT (Flexible ZTAT) is a trademark of Hitachi, Ltd. Rev. 6.0, 09/02, page 1 of 876 Table 1.1 Features Feature Description CPU Upward-compatible with the H8/300 H8/300 CPU at the object-code level · General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers + eight 16-bit registers or eight 32bit registers) · High-speed operation (flash memory version) H8/3048F H8/3048F Maximum clock rate: 16 MHz Add/subtract: 125 ns Multiply/divide: 875 ns · High-speed operation (mask ROM and PROM versions) Maximum clock rate: 18 MHz Add/subtract: 111 ns Multiply/divide: 778 ns · 16-Mbyte address space · Instruction features 8/16/32-bit data transfer, arithmetic, and logic instructions Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16 bits) Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits) Bit accumulator function Bit manipulation instructions with register-indirect specification of bit positions Rev. 6.0, 09/02, page 2 of 876 Feature Description Memory · H8/3048 H8/3048, H8/3048F H8/3048F ROM: 128 kbytes RAM: 4 kbytes · H8/3047 H8/3047 ROM: 96 kbytes RAM: 4 kbytes · H8/3045 H8/3045 ROM: 64 kbytes RAM: 2 kbytes · H8/3044 H8/3044 ROM: 32 kbytes RAM: 2 kbytes · 30 internal interrupts Three selectable interrupt priority levels · Address space can be partitioned into eight areas, with independent bus specifications in each area Chip select output available for areas 0 to 7 · 8-bit access or 16-bit access selectable for each area · Two-state or three-state access selectable for each area · Selection of four wait modes · Refresh controller Seven external interrupt pins: NMI, IRQ0 to IRQ5 · Bus controller · · Interrupt controller Bus arbitration function · DRAM refresh Directly connectable to 16-bit-wide DRAM CAS-before-RAS refresh Self-refresh mode selectable · Pseudo-static RAM refresh Self-refresh mode selectable · Usable as an interval timer Rev. 6.0, 09/02, page 3 of 876 Feature Description DMA controller (DMAC) · Short address mode Maximum four channels available Selection of I/O mode, idle mode, or repeat mode Can be activated by compare match/input capture A interrupts from ITU channels 0 to 3, transmit-data-empty and receive-data-full interrupts from SCI channel 0, or external requests · Full address mode Maximum two channels available Selection of normal mode or block transfer mode Can be activated by compare match/input capture A interrupts from ITU channels 0 to 3, external requests, or auto-request 16-bit timer counter (channels 0 to 4) Two multiplexed output compare/input capture pins (channels 0 to 4) · Operation can be synchronized (channels 0 to 4) · PWM mode available (channels 0 to 4) · Phase counting mode available (channel 2) · Buffering available (channels 3 and 4) · Reset-synchronized PWM mode available (channels 3 and 4) · Complementary PWM mode available (channels 3 and 4) · DMAC can be activated by compare match/input capture A interrupts (channels 0 to 3) · Maximum 16-bit pulse output, using ITU as time base · Up to four 4-bit pulse output groups (or one 1