HD404669 ADE-202-083B HD407A4669 HD4046612H HD404669H HCD404669 HD40A4668 - Datasheet Archive

 

Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit ADE-202-083B Rev. 3.0 Sept. 1999 Description The HD404669

 

HD404669 HD404669 Series Low-Voltage AS Microcomputers with On-Chip DTMF Generation Circuit ADE-202-083B ADE-202-083B Rev. 3.0 Sept. 1999 Description The HD404669 HD404669 Series microcomputers incorporate a DTMF generation circuit, two comparators, and a serial interface on chip. They also provide input and output pins with large current handling capacities. Thus they are 4-bit single-chip microcomputers that are optimal for use in multifunction telephones, cordless telephones, and other communications equipment. HD404669 HD404669 Series microcomputers have a 32.768 kHz sub-oscillator for realtime clock use, providing a time counting facility, and a variety of power supply modes to reduce current drain. The HD407A4669 HD407A4669 is a ZTATTM microcomputer with on-chip PROM that drastically shortens development time and ensures a smooth transition from debugging to mass production. (The PROM programming specifications are the same as for the 27256 type.) ZTATTM: Zero Turn-Around Time ZTAT is a trademark of Hitachi, Ltd. Features · 1,152-digit × 4-bit RAM · I/O pins: 47 High-current I/O pins (source: 10 mA max.): 4 High-current I/O pins (sink: 15 mA max.): 5 · Timer counters: 3 · Input capture: one 8-bit channel · Timer outputs: 2 (with PWM output capability) · Event input: 1 (edge-programmable) · Clock synchronous 8-bit serial interface: 1 · DTMF generation circuit · Comparator: 2 channels · System clock oscillator Ceramic oscillator, crystal oscillator, or external clock operation possible HD404669 HD404669 Series · Subsystem clock oscillator 32.768 kHz crystal oscillator for realtime clock use · Interrupts External: 5 (including 3 edge-programmable) Internal: 4 · Subroutine stack: max. 16 levels including interrupts · Low-power modes: 4 · System clock division software switching (1/4, 1/8, 1/16, 1/32) · Instruction execution time Min. 1 µs (fOSC = 4 MHz, 1/4 clock division) Min. 0.5 µs (fOSC = 8 MHz, 1/4 clock division) · Operating voltage 1.8 V to 5.5 V 2.2 V to 5.5 V (ZTATTM) Ordering Information Type Product Name Mask ROM (standard version) Model Name ROM (Words) HD4046612H HD4046612H HD404669H HD404669H 16,384 HCD404669 HCD404669 16,384 HD40A4668 HD40A4668 HD40A4668H HD40A4668H 8,192 HD40A46612 HD40A46612 HD40A46612H HD40A46612H 12,288 HD40A4669 HD40A4669 HD40A4669H HD40A4669H 16,384 HD407A4669 HD407A4669 HD407A4669H HD407A4669H 1,152 Package 12,288 HCD404669 HCD404669 Note: 8,192 HD404669 HD404669 ZTATTM (high-speed version) HD404668H HD404668H HD4046612 HD4046612 Mask ROM (high-speed version) HD404668 HD404668 RAM (Digits) 64-pin plastic QFP (FP-64A FP-64A) 16,384 Chip *1 *2 64-pin plastic QFP (FP-64A FP-64A) 1. ZTATTM chip shipment is not supported. 2. The specifications of shipped chips differ from those of the package product. Please contact our sales staff for details. Cautions about Operation The mask ROM and ZTATTM versions have been confirmed as fully meeting the reference values for electrical characteristics shown in this data sheet. However, actual performance figures, operating margins, noise margins, and other properties may vary due to differences in the manufacturing process, internal 2 HD404669 HD404669 Series wiring patterns, etc. Users are therefore requested to confirm the operation of individual products by conducting evaluation tests under conditions equivalent to those in the actual application system. List of Functions Standard version HD404668 HD404668 HD4046612 HD4046612 HD404669 HD404669 HD40A4668 HD40A4668 HD40A46612 HD40A46612 HD40A4669 HD40A4669 ROM (Words) 8,192 12,288 16,384 RAM (Digits) 1,152 I/O 52 (max) Highspeed version Product name Large-current I/O pins Timer / Counter HCD404669 HCD404669 - 16,384 HD407A4669 HD407A4669 16,384PROM 384PROM 4 ( Source 10mA max), 5 (Sink 15 mA max) 3 Input capture 8 bit × 1 Timer output 2 (PWM output possible) Event input 1 (edge selection possible) Serial interface 1 (8-bit clock syncronous) DTMF generation circuit Available Comparator 2 Interrupt External 5 (edge selection possible for 3) Internal 4 Low-Power Dissipation Mode 4 Stop mode Available Watch /mode Available Standby mode Available Subactive mode Available Main Oscillator Ceramic oscillation 400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4 MHz, 7.16 MHz*, 8 MHz* Crystal oscillation 400 kHz, 800 kHz, 2 MHz, 3.58 MHz, 4 Mhz, 7.16 MHz*, 8 MHz* Sub oscillator Crystal oscillation 32.768 kHz Minimum instruction execution time Standard version 1 µs (f OSC = 4 MHz, 1/4 frequency division) High-speed version 0.5 µs (fOSC = 8 MHz, 1/4 frequency division) Operating voltage (V) 1.8 to 5.5 1.8 to 5.5 2.2 to 5.5 Package 64-pin plastic QFP (FP-64A FP-64A) Chip 64-pin plastic QFP (FP-64A FP-64A) ­20 to +75 +75°C ­20 to +75 Guaranteed operation temperature (°C) Note: * Applies to high-speed versions (HD40A4668 HD40A4668, HD40A46612 HD40A46612, HD40A4669 HD40A4669, HD407A4669 HD407A4669). 3 HD404669 HD404669 Series RD0/COMP0 VTref TONER TONEC VCC SEL RA1 RA0 R93 R92 R91 R90 R83 R82 R81 63 62 61 60 58 57 56 55 54 53 52 51 50 49 59 RD1/COMP1 64 Pin Arrangement RE0/VCref 1 48 R80 TEST 2 47 R73 OSC1 3 46 R72 OSC2 4 45 R71 RESET 5 44 R70 X1 6 43 R63 X2 7 42 R62 GND 8 41 R61 D0 9 40 R60 D1 D2 D3 10 39 R43 /SO1 11 38 R42 /SI1 12 37 R41 /SCK1 D4 13 36 D5 14 35 R40 /EVND R31 /TOC D9 15 34 R32 /TOD D10 16 33 R33 23 24 25 26 27 28 29 30 31 32 R03 /INT4 R10 R11 R12 R13 R20 R21 R22 R23 R30 22 R02 /INT3 21 R01 /INT2 20 18 D12 /STOPC D13 /INT0 R00 /INT1 19 17 D11 FP-64A FP-64A Top view 4 HD404669 HD404669 Series Pad Arrangement HCD404669 HCD404669 64 62 63 60 61 58 59 56 57 54 55 52 53 50 51 49 TYPE CODE 1 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 19 18 21 20 23 22 25 24 27 26 29 28 31 30 32 TYPE CODE: HD404669 HD404669 5 HD404669 HD404669 Series Bonding Pad Coordinates HCD404669 HCD404669 Y Chip Size (X × Y): 4.34 × 4.01 (mm) Coordinates: Pad Center Home Point position: Chip Center Pad size (X × Y): 90 × 90 (µm) Chip thickness: 400 (µm) TYPE CODE X Chip center (X=0, Y=0) Pad Pad No. Name Coordinates X Y 1444 X 17 ­1607 ­1819 D11 Y Pad Pad No. Name 33 R33 Coordinates X 1983 Y Pad Pad No. Name ­1444 49 R81 Coordinates X Y 1 RE0 2 TESTN ­1983 1252 18 D12 ­1394 ­1819 34 R32 1983 ­1252 50 R82 1374 1819 3 OSC1 ­1983 1062 19 D13 ­1181 ­1819 35 R31 1983 ­1060 51 R83 1161 1819 4 OSC2 ­1983 871 20 R00 ­968 ­1819 36 R40 1983 ­867 52 R90 948 1819 5 RESET ­1983 657 21 R01 ­755 ­1819 37 R41 1983 ­675 53 R91 735 1819 6 X1 ­1983 466 22 R02 ­541 ­1819 38 R42 1983 ­483 54 R92 522 1819 7 X2 ­1983 275 23 R03 ­329 ­1819 39 R43 1983 ­291 55 R93 309 1819 8 GND ­1983 84 24 R10 ­117 ­1819 40 R60 1983 ­99 56 RA0 93 1819 9 D0 ­1983 ­108 25 R11 96 ­1819 41 R61 1983 93 57 RA1 ­177 1819 10 D1 ­1983 ­299 26 R12 309 ­1819 42 R62 1983 285 58 SEL ­329 1819 11 D2 ­1983 ­490 27 R13 522 ­1819 43 R63 1983 478 59 V CC ­542 1819 12 D3 ­1983 ­680 28 R20 735 ­1819 44 R70 1983 670 60 TONEC ­755 1819 13 D4 ­1983 ­871 29 R21 948 ­1819 45 R71 1983 862 61 TONER ­968 1819 14 D5 ­1983 ­1062 30 R22 1161 ­1819 46 R72 1983 1054 62 VTREF ­1181 1819 15 D9 ­1983 ­1253 31 R23 1374 ­1819 47 R73 1983 1246 63 RD0 ­1394 1819 16 D10 ­1983 ­1444 32 R30 1587 ­1819 48 R80 1983 1444 64 RD1 ­1607 1819 6 ­1983 Coordinates Pad Pad No. Name 1587 1819 HD404669 HD404669 Series Pin Description Pin Number Item Symbol FP-64A FP-64A, chip I/O Function Power supply VCC 59 ­ Applies power voltage GND 8 ­ Connected to ground Test TEST 2 I Used for factory testing only: Connect this pin to VCC Reset RESET 5 I Resets the MCU Oscillator OSC1 3 I Input/output pins for the internal oscillator circuit: Connect them to a ceramic oscillator ,crystal oscillator or connect OSC 1 to an external oscillator circuit OSC2 4 O X1 6 I X2 7 O D0­D5, D9­D11 9-17 I/O Port Used for a 32.768-kHz crystal for clock purposes. If not to be used, fix the X1 pin to V CC and leave the X2 pin open. Input/output pins addressed by individual bits; D0 to D3 are source high-current input/output pins. A maximum 10 mA current can be supplied to each pin. D4, D5, and D9 to D11 are sink high-current input/output pins. A maximum 15 mA current can be supplied to each pin. D12 , D13 18, 19 I Input pins addressable by individual bits R00­R4 3, R60­RA 1 20­57 I/O Input/output pins addressable in 4-bit units RD 0, RD1, RE0 63, 64, 1 I Input pins addressable in 4-bit units Interrupt INT0, INT1, INT2­INT4 19-23 I Input pins for external interrupts Stop clear STOPC 18 I Input pin for transition from stop mode to active mode Serial SCK1 37 I/O Serial interface clock input/output pin interface SI 1 38 I Serial interface receive data input pin SO 1 39 O Serial interface transmit data output pin TOC, TOD 35, 34 O Timer output pins EVND 36 I Event input pin TONER 61 O Output pin for DTMF row signals TONEC 60 O Output pin for DTMF column signals VTref 62 ­ Reference voltage pin for DTMF signals. Voltage conditions are: VCC VTref GND Timer DTMF 7 HD404669 HD404669 Series Pin Number Item Symbol FP-64A FP-64A, chip I/O Function Voltage comparator COMP0, COMP1 63, 64 I Comparator analog input pins. VCref 1 ­ Analog input pin threshold voltage reference level power supply pin. SEL 58 I Pin that selects the system clock division ratio immediately after a reset and when returning from stop mode to active mode. Connect to Vcc voltage to select division-by-4, or to GND potential to select division-by-32. Frequency division ratio selection 8 HD404669 HD404669 Series RESET TEST STOPC OSC1 OSC2 X1 X2 VCC GND SEL Block Diagram ROM INT0 INT1 INT2 INT3 INT4 RAM D port HMCS400 HMCS400 CPU 8-bit timer A (free-running timer) TOC 8-bit timer C EVND TOD 8-bit timer D SCK1 SI1 SO1 Synchronous 8-bit serial interface VTref TONER TONEC DTMF generation circuit VCref COMP0 COMP1 Comparator : Data bus RE RD RA port port port R9 port R8 port R7 port R6 port R4 port R3 port R2 port R1 port R0 port External interrupt control circuit D0 D1 D2 D3 D4 D5 D9 D10 D11 D12 D13 R00 R01 R02 R03 R10 R11 R12 R13 R20 R21 R22 R23 R30 R31 R32 R33 R40 R41 R42 R43 R60 R61 R62 R63 R70 R71 R72 R73 R80 R81 R82 R83 R90 R91 R92 R93 RA0 RA1 RD0 RD1 RE0 : Signal line 9 HD404669 HD404669 Series Memory Map ROM Memory Map The ROM memory map is shown in figure 1 and described below. ROM address ROM address $0000 $0000 $000F Vector addresses (16 words) $0010 $0001 $0002 $0003 Zero page subroutine area (64 words) JMPL instruction (Jump to reset, stop mode clearance routine) JMPL instruction (Jump to INT0 interrupt handling routine) JMPL instruction (Jump to INT1 interrupt handling routine) $0004 $003F $0005 $0040 $0006 Pattern area (4,096 words) JMPL instruction (Jump to timer A interrupt handling routine) $0007 JMPL instruction (Jump to INT2 interrupt handling routine) $0008 $0FFF $0009 $1000 $000A HD404668/HD40A4668 HD404668/HD40A4668 program area (8,192 word) $000B $000C $1FFF $000D $2000 HD4046612/HD40A46612 HD4046612/HD40A46612 program area (12,288 words) $000E $000F JMPL instruction (Jump to timer C, INT3 interrupt handling routine) JMPL instruction (Jump to timer D, INT4 interrupt handling routine) JMPL instruction (Jump to serial 1 routine) $2FFF $3000 HD404669/HD40A4669/ HD404669/HD40A4669/ HCD404669/HD407A4669 HCD404669/HD407A4669 program area (16,384 words) $3FFF Figure 1 ROM Memory Map Vector Address Area ($0000­$000F): Reserved for JMPL instructions that branch to the start addresses of the reset and interrupt routines. After MCU reset or an interrupt, program execution continues from the vector address. Zero-Page Subroutine Area ($0000­$003F): Reserved for subroutines. The program branches to a subroutine in this area in response to the CAL instruction. Pattern Area ($0000­$0FFF): Contains ROM data that can be referenced with the P instruction. Program Area ($0000­$1FFF: HD404668 HD404668, HD40A4668 HD40A4668; $0000­$2FFF: HD4046612 HD4046612, HD40A46612 HD40A46612; $0000­$3FFF: HD404669 HD404669, HD40A4669 HD40A4669, HD407A4669 HD407A4669, HCD404669 HCD404669): Used for program coding. 10 HD404669 HD404669 Series RAM Memory Map The MCU contains a RAM area consisting of a memory register area, a data area, and a stack area. In addition, an interrupt control bits area, special function register area, and register flag area are mapped onto the same RAM memory space. The RAM memory map is shown in figure 2 and described below. RAM-Mapped Register Area ($000­$03F): · Interrupt Control Bits Area ($000­$003) This area is used for interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. · Special Function Register Area ($004­$01F, $024­$03F) This area is used as mode registers and data registers for external interrupts, serial interface, timers, DTMF, comparator, and as data control registers for I/O ports. The structure is shown in figures 2 and 5. These registers can be classified into three types: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used for these registers. · Register Flag Area ($020­$023) This area is used for the DTON, WDON, and other register flags and interrupt control bits (figure 3). These bits can be accessed only by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, and TM/TMD). However, note that not all the instructions can be used for each bit. Limitations on using the instructions are shown in figure 4. 11 HD404669 HD404669 Series RAM address RAM address $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 $019 $01A $01B $01C $01D $01E $01F $020 $021 $022 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $02D $02E $02F $030 $031 $032 $033 $034 $035 $036 $037 $038 $039 $03A $03B $03C $03D $03E $03F $000 RAM-mapped register area $040 Memory registers (16 digits) $050 Not used $090 Data (464 digits x 2) V = 0 (bank = 0) V = 1 (bank = 1) *1 $260 Data (144 digits) $2F0 Not used $3C0 Stack area (64 digits) $3FF R : Read only W : Write only R/W : Read/Write Note : *1. There are two data areas, V = 0 (bank 0) and V = 1 (bank 1) $090 Data (464 digits) V=0 (bank = 0) Data (464 digits) V=1 (bank = 1) $25F Interrupt control bit area Port mode register A Serial mode register 1A Serial data register 1L Serial data register 1U Timer mode register A W W R/W R/W W (MIS) (TMC1) (TRCL/TWCL) (TRCU/TWCU) (TMD1) (TRDL/TWDL) (TRDU/TWDU) W W R/W R/W W R/W R/W (TMC2) (TMD2) R/W R/W (CDR) (CER) (TGM) (TGC) R W W W (PMRB) (PMRC) (ESR1) (ESR2) (SM1B) (SSR1) (SSR2) W W W W W W W (DCD0) (DCD1) (DCD2) W W W (DCR0) (DCR1) (DCR2) (DCR3) (DCR4) W W W W W (DCR6) (DCR7) (DCR8) (DCR9) (DCRA) W W W W W Not used Miscellaneous register Timer mode register C1 Timer C Timer mode register D1 Timer D Not used Timer mode register C2 Timer mode register D2 Not used Compare data register Compare enable register Tone generator mode register Tone generator control register Not used Register flag area Port mode register B Port mode register C Detection edge select register 1 Detection edge select register 2 Serial mode register 1B System clock select register 1 System clock select register 2 Not used Data control register D0 to D3 Data control register D4 to D5 Data control register D9 to D11 Not used Data control register R0 Data control register R1 Data control register R2 Data control register R3 Data control register R4 Not used Data control register R6 Data control register R7 Data control register R8 Data control register R9 Data control register RA Not used (V) V register *2. Two registers are mapped onto the same address ($00E, $00F, $011, $012) $00E $00F Timer read register CL Timer read register CU (TRCL) (TRCU) R R Timer write register CL Timer write register CU (TWCL) (TWCU) W W $011 $012 Timer read register DL Timer read register DU (TRDL) (TRDU) R R Timer write register DL Timer write register DU (TWDL) (TWDU) W W Figure 2 RAM Memory Map 12 (PMRA) (SM1A) (SR1L) (SR1U) (TMA) R/W *2 *2 HD404669 HD404669 Series RAM address Bit 3 Bit 2 Bit 1 IM0 (INT0 interrupt mask) IF0 (INT0 interrupt request flag) RSP (Reset stack pointer) IE (Interrupt enable flag) IMTA $001 (Timer A interrupt mask) IFTA (Timer A interrupt request flag) IM1 (INT1 interrupt mask) IF1 (INT1 interrupt request flag) IMTC $002 (Timer C interrupt mask) IFTC (Timer C interrupt request flag) Not used Not used IFS1 (Serial 1 interrupt request flag) IMTD (Timer D interrupt mask) IFTD (Timer D interrupt request flag) $000 $003 IMS1 (Serial 1 interrupt mask) Bit 0 Interrupt control bits area RAM address Bit 3 Bit 2 Bit 1 Bit 0 $020 DTON (DTON flag) Not used WDON (Watchdog on flag) LSON (Low speed on flag) $021 RAME (RAM enable flag) Not used ICEF (Input capture error flag) ICSF (Input capture status flag) $022 IM3 (INT3 interrupt mask) IF3 (INT3 interrupt request flag) IM2 (INT2 interrupt mask) IF2 (INT2 interrupt request flag) $023 Not used Not used IM4 (INT4 interrupt mask) IF4 (INT4 interrupt request flag) Register flag area IF IM IE SP : Interrupt Request Flag : Interrupt Mask : Interrupt Enable Flag : Stack Pointer Figure 3 Configuration of Interrupt Control Bits and Register Flag Areas 13 HD404669 HD404669 Series Bits in the interrupt control bits area and register flag area can be set and reset by the SEM or SEMD instruction and the REM or REMD instruction, and tested by the TM or TMD instruction. They are not affected by any other instructions. The following restrictions apply to individual bits. SEM/SEMD Not used Allowed Allowed Not executed DTON TM/TMD Allowed IE IM LSON IF ICSF ICEF RAME RSP WDON REM/REMD Allowed Allowed Not executed Allowed Not executed in active mode Used in subactive mode Not executed Allowed Not executed Inhibited Inhibited Allowed Allowed Not executed Inhibited Note: WDON is reset by MCU reset or by STOPC enable for stop mode cancellation. DTON is always reset in active mode. If the TM or TMD instruction is executed for the inhibited bits or non-existing bits, the value in ST becomes invalid. Figure 4 Usage Limitations of RAM Bit Manipulation Instructions 14 HD404669 HD404669 Series Bit 3 PMRA SM1A SR1L SR1U TMA MIS TMC1 TRCL/TWCL TRCU/TWCU TMD1 TRDL/TWDL TRDU/TWDU TMC2 TMD2 CDR CER TGM TGC PMRB PMRC ESR1 ESR2 SM1B SSR1 SSR2 DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 DCR3 DCR4 DCR6 DCR7 DCR8 DCR9 DCRA V Bit 2 Bit 1 Bit 0 $000 $001 Interrupt control bits area $002 $003 R42/SI1 R42/SI1 R43/SO1 R43/SO1 $004 $005 R41/SCK1 R41/SCK1 Serial transfer clock speed selection 1 $006 Serial data register 1 (lower) $007 Serial data register 1 (upper) Clock source setting (timer A) Timer A/time base $008 $009 $00A $00B $00C MOS pull-up/pull-down control R43/SO1 R43/SO1 PMOS control Interrupt frame period selection Clock source setting (timer C) $00D Reload on/off $00E Timer C register (lower) $00F Timer C register (upper) $010 Reload on/off Clock source setting (timer D) $011 Timer D register (lower) $012 Timer D register (upper) $013 $014 Timer C output mode setting $015 Input capture selection Timer D output mode setting $016 $017 COMP1 comparison result COMP0 comparison result $018 Comparator operation selection Comparator selection $019 TONEC output frequency TONER output frequency $01A TONEC output TONER output DTMF enable $01B $01C $01D $01E $01F $020 $021 Register flag area $022 $023 R02/INT3 R02/INT3 $024 R01/INT2 R01/INT2 R00/INT1 R00/INT1 R03/INT4 R03/INT4 D13/INT0 D13/INT0 $025 D12/STOPC D12/STOPC R40/EVND R40/EVND INT3 detection edge selection INT2 detection edge selection $026 EVND detection edge selection INT4 detection edge selection $027 SO1 idle High/Low setting Serial clock selection $028 DTMF speed setting $029 *1 *2 $02A DTMF speed setting OSC frequency division ratio switching $02B Port D0DCR Port D3DCR Port D2DCR Port D1DCR $02C Port D5DCR Port D4DCR $02D Port D11DCR D11DCR Port D10DCR D10DCR Port D9DCR $02E $02F Port R03DCR R03DCR Port R02DCR R02DCR Port R01DCR R01DCR Port R00DCR R00DCR $030 Port R13DCR R13DCR Port R12DCR R12DCR Port R11DCR R11DCR Port R10DCR R10DCR $031 Port R23DCR R23DCR Port R22DCR R22DCR Port R21DCR R21DCR Port R20DCR R20DCR $032 Port R33DCR R33DCR Port R32DCR R32DCR Port R31DCR R31DCR Port R30DCR R30DCR $033 Port R43DCR R43DCR Port R42DCR R42DCR Port R41DCR R41DCR Port R40DCR R40DCR $034 $035 Port R63DCR R63DCR Port R62DCR R62DCR Port R61DCR R61DCR Port R60DCR R60DCR $036 Port R73DCR R73DCR Port R72DCR R72DCR Port R71DCR R71DCR Port R70DCR R70DCR $037 Port R83DCR R83DCR Port R82DCR R82DCR Port R81DCR R81DCR Port R80DCR R80DCR $038 Port R93DCR R93DCR Port R92DCR R92DCR Port R91DCR R91DCR Port R90DCR R90DCR $039 Port RA1DCR Port RA0DCR $03A $03B $03C $03D $03E Bank setting $03F : Not used *1: 32kHz oscillation stop setting *2: 32kHz frequency division ratio switching Figure 5 Special Function Register Area 15 HD404669 HD404669 Series Memory Register (MR) Area ($040­$04F): Consisting of 16 addresses, this area (MR0­MR15) can be accessed by register-register instructions (LAMR and XMRA). The structure is shown in figure 6. RAM address $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04A $04B $04C $04D $04E $04F MR MR MR MR MR MR MR MR MR MR MR MR MR MR MR MR (0) (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (a) Memory registers $3C0 $3FF Level 16 Level 15 Level 14 Level 13 Level 12 Level 11 Level 10 Level 9 Level 8 Level 7 Level 6 Level 5 Level 4 Level 3 Level 2 Level 1 Bit 3 Bit 2 Bit 1 Bit 0 $3FC ST PC13 PC12 PC11 $3FD PC10 PC9 PC8 PC7 $3FE CA PC6 PC5 PC4 $3FF PC3 PC2 PC1 PC0 (b) Stack area PC13 to PC0 : Program counter ST : Status flag CA : Carry flag Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position 16 HD404669 HD404669 Series Data Area ($090­$2EF): 464 digits from $090 to $25F have two banks, which can be selected by setting the bank register (V: $03F). Before accessing this area, set the bank register to the required value (figure 7). The area from $026 to $2EF is accessed without setting the bank register. Bank register (V: $03F) Bit 3 2 1 0 Initial value - - - 0 - - - R/W Read/Write Bit name Not used Not used Not used V0 V0 Bank area selection 0 Bank 0 is selected 1 Bank 1 is selected Note: After reset, the value in the bank register is 0, and therefore bank 0 is selected. Figure 7 Bank Register (V) Stack Area ($3C0­$3FF): Used for saving the contents of the program counter (PC), status flag (ST), and carry flag (CA) at subroutine call (CAL or CALL instruction) and for interrupts. This area can be used as a 16-level nesting subroutine stack in which one level requires four digits. The data to be saved and the save conditions are shown in figure 6. The program counter is restored by either the RTN or RTNI instruction, but the status and carry flags can only be restored by the RTNI instruction. Any unused space in this area is used for data storage. 17 HD404669 HD404669 Series Functional Description Registers and Flags The MCU has nine registers and two flags for CPU operations. They are shown in figure 8 and described below. 3 Accumulator 0 (A) Initial value: Undefined, R/W 3 B register Initial value: Undefined, R/W W register 0 Initial value: Undefined, R/W (B) 1 0 (W) 3 X register Initial value: Undefined, R/W 0 (X) 3 Y register 0 (Y) Initial value: Undefined, R/W 3 SPX register Initial value: Undefined, R/W SPY register Initial value: Undefined, R/W Carry Initial value: Undefined, R/W Status 0 Initial value: 1, R/W not possible (SPX) 3 0 (SPY) 0 (CA) 0 Program counter Initial value: $0000, R/W not possible (ST) 13 0 (PC) 9 Stack pointer Initial value: $3FF, R/W not possible 1 5 1 1 1 0 (SP) Figure 8 Registers and Flags Accumulator (A) and B Register (B): A and B are 4-bit registers, and are used to hold the results of ALU (arithmetic and logical unit) operations and to transfer data between memory, I/O ports, and other registers. 18 HD404669 HD404669 Series W Register (W), X Register (X), and Y Register (Y): W is a 2-bit register and X and Y are 4-bit registers. These registers are used in RAM register indirect addressing. The Y register is also used in D port addressing. SPX Register (SPX) and SPY Register (SPY): The SPX and SPY registers are 4-bit registers used to supplement the X and Y registers. Carry Flag (CA): CA is a 1-bit flag that stores ALU overflow generated by an arithmetic operation. CA is set to 1 when an overflow is generated, and is cleared to 0 after operations in which no overflow occurred. CA is also affected by the carry set/carry clear instructions (SEC and REC), and by the rotate with carry instructions (ROTL and ROTR). During interrupt handling, CA is saved on the stack, and is restored from the stack by the RTNI instruction. (but is not affected by the RTN instruction) Status Flag (ST): ST is a 1-bit flag that stores the results of arithmetic instructions, compare instructions, and bit test instructions, and is used as the branch condition for the BR, BRL, CAL, and CALL conditional branch instructions. The contents of the ST flag are held until the next arithmetic, compare, bit test, or conditional branch instruction is executed. After the execution of a conditional branch instruction, the value of ST is set to 1 without regard to the condition. During interrupt handling, ST is saved on the stack, and is restored from the stack by the RTNI instruction. (but is not affected by the RTN instruction) Program Counter (PC): The PC is a 14-bit counter that indicates the ROM address of the next instruction the CPU will execute. Stack Pointer (SP): The SP is a 10-bit register that indicates the RAM address of the next stack frame in the stack area. The SP is initialized to $3FF by a reset. The SP is decremented by 4 by a subroutine call or by interrupt handling, and is incremented by 4 when the saved data has been restored by a return instruction. The upper 4 bits of the SP are fixed at 1111; the maximum number of stack levels is thus 16. In addition to the reset method described above, the SP can also be initialized to $3FF by clearing the reset stack pointer (RSP) in the interrupt control bits area with a RAM bit manipulation instruction, i.e., REM or REMD. 19 HD404669 HD404669 Series Reset The MCU can be reset by setting the RESET pin high or by setting the STOPC pin low*. When power is first applied, or when clearing subactive mode, watch mode, or stop mode, the RESET input must be held for at least tRC to assure that the oscillation stabilization time (tRC) condition is fulfilled. Similarly, the STOPC pin input must held for at least tRC when clearing stop mode with a STOPC pin input to assure that the oscillator stabilizes. In all other cases, the MCU is reset by a RESET input that is held for at least two instruction execution cycles. Table 1 lists the section of the MCU that are initialized by a reset and the initial values. Note: * The STOPC pin reset is only effective in stop mode. 20 HD404669 HD404669 Series Table 1 Initial Values After MCU Reset Item Abbr. Initial Value Contents Program counter (PC) $0000 Indicates program execution point from start Status flag (ST) 1 Enables conditional branching address of ROM area Stack pointer I/O (SP) $3FF Stack level 0 Interrupt enable flag (IE) 0 Inhibits all interrupts Interrupt request flag (IF) 0 Indicates there is no interrupt request Interrupt mask Interrupt flags/mask (IM) 1 Prevents (masks) interrupt requests (PDR) All bits 1 Enables output at level 1 (DCD0) 0000 Turns output buffer off (to high impedance) Data control register (DCD1) -00 Data control register (DCD2) 000- Data control register (DCR0­DCR4, DCR6­DCR9) 0000 Data control register (DCRA) -00 Port mode register A (PMRA) -00 Refer to description of port mode register A Port mode register B (PMRB) 0000 Refer to description of R port Port mode register C bits 3, 1, 0 (PMRC3, PMRC1, PMRC0) 00- Refer to description of port mode register C Detection Edge select registers 1 and 2 Timer/ counters, serial interface Port data register Data control register (ESR1, 2) 0000 Refer to description of interrupts Timer mode register A (TMA) 0000 Refer to description of timer mode register A section Timer mode register C1 (TMC1) 0000 Refer to description of timer mode register C1 Timer mode register C2 (TMC2) -000 Refer to description of timer mode register C2 Timer mode register D1 (TMD1) 0000 Refer to description of timer mode register D1 Timer mode register D2 (TMD2) 0000 Refer to description of timer mode register D2 Serial mode register 1A (SM1A) 0000 Refer to description of serial mode register 1A Serial mode register 1B (SM1B) -X0 Refer to description of serial mode register 1B Prescaler S (PSS) $000 Refer to description of prescalers Prescaler W (PSW) $00 Refer to description of prescalers Timer counter A (TCA) $00 Refer to description of timer A Timer counter C (TCC) $00 Refer to description of timer C Timer counter D (TCD) $00 Refer to description of timer D 21 HD404669 HD404669 Series Abbr. Initial Value Contents Timer write register C (TWCU, L) $X0 Refer to description of timer write register C Timer write register D (TWDU, L) $X0 Refer to description of timer write register D Serial data register 1 (SR1U, L) $XX Refer to description of serial data register 1 Octal counter (OC1) 000 Refer to description of serial interface Tone generator mode register (TGM) 0000 Refer to description of tone generator mode register Tone generator control register (TGC) 000 - Refer to description of tone generator control register Compare data register (CDR) -XX Refer to description of compare data register Compare enable register (CER) 0-00 Refer to description of compare enable register Item Timer/ counters, serial interface DTMF Comparator Bit registers Low speed on flag (LSON) 0 Refer to description of operating modes Watchdog timer on flag (WDON) 0 Refer to description of timer C Direct transfer on flag (DTON) 0 Refer to description of operating modes Input capture status flag (ICSF) 0 Refer to description of timer D Input capture error flag (ICEF) 0 Refer to description of timer D Miscellaneous register (MIS) 0000 Refer to description of operating modes and pull-up and pull-down MOS transistor control. System clock select register 1 bits 2 to 0 (SSR12 SSR12 ­SSR10 SSR10) 000 Refer to description of internal oscillator circuit and system clock select register 1 and 2 System clock select register 2 (SSR2) 0000 Refer to description of internal oscillator circuit and system clock select register 1 and 2 Bank register Others (V) - - -0 Refer to description of RAM memory map Notes: 1. The statuses of other registers and flags after MCU reset are shown in the following table. 2. X indicates invalid value. ­ indicates that the bit does not exist. Item Abbr. Carry flag (CA) Accumulator Status After all Other Types of Reset Pre-stop-mode values are not guaranteed; values must be initialized by program Pre-MCU-reset values are not guaranteed; values must be initialized by program (A) B register Status After Cancel-lation of Stop Mode by STOPC Input (B) W register (W) X/SPX register (X/SPX) Y/SPY register (Y/SPY) RAM Pre-stop-mode values are retained RAM enable flag (RAME) 1 0 Port mode register C bit 2 (PMRC2) Pre-stop-mode values are retained 0 System clock select register 1 bit 3 (SSR13 SSR13) 22 HD404669 HD404669 Series Interrupts The MCU has 9 interrupt sources: five external signals (INT0 , INT1, INT 2­INT 4), three timer/ counters (timers A, C, and D), serial interface (Serial 1). An interrupt request flag (IF), interrupt mask (IM), and vector address are provided for each interrupt source, and an interrupt enable flag (IE) controls the entire interrupt process. As vector addresses are shared by interrupt sources timer C and INT3, and timer D and INT4, so the type of request that has occurred must be checked at the beginning of interrupt processing. Interrupt Control Bits and Interrupt Processing: Locations $000 to $003 and $022 to $023 in RAM are reserved for the interrupt control bits which can be accessed by RAM bit manipulation instructions. The interrupt request flag (IF) cannot be set by software. MCU reset initializes the interrupt enable flag (IE) and the IF to 0 and the interrupt mask (IM) to 1. A block diagram of the interrupt control circuit is shown in figure 9, interrupt priorities and vector addresses are listed in table 2, and interrupt processing conditions for the 9 interrupt sources are listed in table 3. An interrupt request occurs when the IF is set to 1 and the IM is set to 0. If the IE is 1 at that point, the interrupt is processed. A priority programmable logic array (PLA) generates the vector address assigned to that interrupt source. The interrupt processing sequence is shown in figure 10 and an interrupt processing flowchart is shown in figure 11. After an interrupt is acknowledged, the previous instruction is completed in the first cycle. The IE is reset in the second cycle, the carry, status, and program counter values are pushed onto the stack during the second and third cycles, and the program jumps to the vector address to execute the instruction in the third cycle. Program the JMPL instruction at each vector address, to branch the program to the start address of the interrupt program, and reset the IF by a software instruction within the interrupt program. Table 2 Vector Addresses and Interrupt Priorities Reset/Interrupt Priority Vector Address RESET, STOPC* - $0000 INT0 1 $0002 INT1 2 $0004 Timer A 3 $0006 INT2 4 $0008 Timer C, INT3 5 $000A Timer D, INT4 6 $000C Serial 1 7 $000E Note: * The STOPC interrupt request is valid only in stop mode. 23 HD404669 HD404669 Series $000, 0 Interrupt request IE $000, 2 INT0 interrupt IF0 $000, 3 Vector address IM0 $001, 0 INT1 interrupt Priority controller IF1 $001, 1 IM1 $022, 0 $001, 2 Timer A interrupt IF2 IFTA IM2 IMTA $022, 2 $002, 2 Timer C interrupt IFTC IF3 IMTC IM3 $023, 0 $003, 0 IFTD IF4 $023, 1 $003, 1 IMTD IM4 $003, 2 Serial 1 interrupt IFS1 $003, 3 IMS1 Figure 9 Interrupt Control Circuit 24 INT3 interrupt $022, 3 $002, 3 Timer D interrupt INT2 interrupt $022, 1 $001, 3 INT4 interrupt HD404669 HD404669 Series Table 3 Interrupt Processing and Activation Conditions Interrupt Source Interrupt Cuntrol Bit INT0 INT1 Timer A INT2 Timer C or INT3 Timer D or INT4 Serial 1 IE 1 1 1 1 1 1 1 IF0 . IM0 IF1 . IM1 1 0 0 0 0 0 0 * 1 0 0 0 0 0 IFTA . IMTA IF2 . IM2 * * 1 0 0 0 0 * * * 1 0 0 0 IFTC . IMTC + IF3 . IM3 IFTD . IMTD + IF4 . IM4 * * * * 1 0 0 * * * * * 1 0 IFS1 . IMS1 * * * * * * 1 Note: Bits marked * can be either 0 or 1. Their values have no effect on operation. Instruction cycles 1 2 3 4 5 6 Instruction execution* Interrupt acceptance Stacking IE reset Vector address generation Execution of JMPL instruction at vector address Note: * The stack is accessed and the IE reset after the instruction is executed, even if it is a 2-cycle instruction. Execution of instruction at start address of interrupt routine Figure 10 Interrupt Sequence 25 HD404669 HD404669 Series Power on RESET = "1"? No Yes Yes Interrupt request? No No IE = 1? Yes MCU reset Execute instruction PC IE Stack Stack Stack (PC)+1 PC Accept interrupt $0002 Yes 0 (PC) (CA) (ST) INT0 interrupt? No Yes PC $0004 INT1 interrupt? No Yes PC Timer A interrupt? $0006 No Yes PC $0008 INT2 interrupt? No Yes PC $000A Timer C or INT3 interrupt? No Yes PC $000C Timer D or INT4 interrupt? No PC $000E (Serial 1 interrupt) Figure 11 Interrupt Processing Flowchart 26 HD404669 HD404669 Series Interrupt Enable Flag (IE: $000, Bit 0): Controls the entire interrupt process. It is reset by the interrupt processing and set by the RTNI instruction, as listed in table 4. Table 4 Interrupt Enable Flag (IE: $000, Bit 0) IE Interrupt Enabled/Disabled 0 Disabled 1 Enabled External Interrupt Request Flags (IF0­IF4: $000, $001, $022, $023): IF0 and IF1 are set at the falling edge of signals input to INT0 and INT1, and IF2­IF4 are set at the rising or falling edge of signals input to INT 2­INT 4, as listed in table 5. The INT2­INT4 interrupt edges are selected by the detection edge select registers (ESR1, ESR2: $026, $027) as shown in figures 12 and 13. Detection edge selection register 1 (ESR1: $026) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W ESR13 ESR13 ESR12 ESR12 ESR11 ESR11 ESR10 ESR10 Bit name INT3 detection edge ESR13 ESR13 ESR12 ESR12 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Falling/Rising-edge detection 1 INT2 detection edge ESR11 ESR11 ESR10 ESR10 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Falling/Rising-edge detection 1 Figure 12 Detection Edge Selection Register 1 (ESR1) 27 HD404669 HD404669 Series Detection edge selection register 2 (ESR2: $027) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W ESR23 ESR23 ESR22 ESR22 ESR21 ESR21 ESR20 ESR20 Bit name EVND detection edge ESR23 ESR23 ESR22 ESR22 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Falling/Rising-edge detection 1 INT4 detection edge ESR21 ESR21 ESR20 ESR20 0 0 No detection 1 Falling-edge detection 0 Rising-edge detection 1 Falling/Rising-edge detection 1 Figure 13 Detection Edge Selection Register 2 (ESR2) Table 5 External Interrupt Request Flags (IF0­IF4: $000, $001, $022, $023) IF0­IF4 Interrupt Request 0 No 1 Yes External Interrupt Masks (IM0­IM4: $000, $001, $022, $023): Prevent (mask) interrupt requests caused by the corresponding external interrupt request flags, as listed in table 6. Table 6 External Interrupt Masks (IM0­IM4: $000, $001, $022, $023) IM0­IM4 Interrupt Request 0 Enabled 1 Disabled (masked) 28 HD404669 HD404669 Series Timer A Interrupt Request Flag (IFTA: $001, Bit 2): Set by overflow output from timer A, as listed in table 7. Table 7 Timer A, C, D Interrupt Request Flags (IFTA: $001, Bit 2, IFTC: $002, Bit 2, IFTD: $003, Bit 0) Timer A, C, D Interrupt Request Flags (IFTA, IFTC, IFTD) Interrupt Request 0 No 1 Yes Timer A Interrupt Mask (IMTA: $001, Bit 3): Prevents (masks) an interrupt request caused by the timer A interrupt request flag, as listed in table 8. Table 8 Timer A, C, D Interrupt Masks (IMTA: $001, Bit 3, IMTC: $002, Bit 3, IMTD: $003, Bit 1) Timer A, C, D Interrupt Masks (IMTA, IMTC, IMTD) InterruptRequest 0 Enabled 1 Disabled (masked) Timer C Interrupt Request Flag (IFTC: $002, Bit 2): Set by overflow output from timer C, as listed in table 7. Timer C Interrupt Mask (IMTC: $002, Bit 3): Prevents (masks) an interrupt request caused by the timer C interrupt request flag, as listed in table 8. Timer D Interrupt Request Flag (IFTD: $003, Bit 0): Set by overflow output from timer D, or by the rising or falling of signals input to EVND when the input capture function is used, as listed in table7. Timer D Interrupt Mask (IMTD: $003, Bit 1): Prevents (masks) an interrupt request caused by the timer D interrupt request flag, as listed in table 8. Serial 1 Interrupt Request Flag (IFS1: $003, Bit 2): Set when data transfer is completed or when data transfer is suspended, as listed in table 9. Table 9 Serial 1 Interrupt Request Flag (IFS1: $003, Bit 2) IFS1 Interrupt Request 0 No 1 Yes 29 HD404669 HD404669 Series Serial 1 Interrupt Mask (IMS1: $003, Bit 3): Prevents (masks) an interrupt request caused by the serial 1 interrupt request flag, as listed in table 10. Table 10 Serial 1 Interrupt Mask (IMS1: $003, Bit 3) IMS1 Interrupt Request 0 Enabled 1 Disabled (masked) 30 HD404669 HD404669 Series Operating Modes The MCU has five operating modes as shown in table 11. The operations in each mode are listed in table 12. Transitions between operating modes are shown in figure 14. Table 11 Operating Modes and Clock Status Mode Name Active Standby Stop Watch Subactive*2 RESET cancellation, interrupt request, STOPC cancellation in stop mode, STOP/SBY instruction in subactive mode (when direct transfer is selected) SBY instruction STOP instruction when TMA3 = 0 STOP instruction when TMA3 = 1 INT0 or timer A interrupt request from watch mode when LSON = 1 System oscillator Operation Operation Stopped Stopped Stopped Subsystem oscillator Operation Operation *1 Operation Operation RESET input, STOP/SBY instruction RESET input, RESET input, interrupt STOPC input request RESET input, INT0 or timer A interrupt request RESET input, STOP/SBY instruction Activation method Status Cancellation method STOP/SBY instruction in subactive mode (except when direct transition is specified) Notes: 1. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (SSR: $029). 2. Subactive mode is an optional function; specify it on the function option list. 31 HD404669 HD404669 Series Table 12 Operations in Low-Power Dissipation Modes Function Stop Mode Watch Mode Standby Mode Subactive Mode*2 CPU Reset Retained Retained Operation RAM Retained Retained Retained Operation Timer A Reset Operation Operation Operation Timer C Reset Stopped Operation Operation Timer D Reset Stopped Operation Operation Serial interface 1 Reset Stopped *1 Operation Operation DTMF Reset Reset Operation Reset Comparator Reset Stopped Stopped Operation I/O Reset Retained Retained Operation (highimpedance) Notes: 1. When a clock is input in external clock mode, transmit/receive operations are performed, but interrupt operations are halted. 2. Subactive mode is a function option, and should be specified in the function option list. 32 HD404669 HD404669 Series Reset by RESET input or by watchdog timer Stop mode (TMA3 = 0, SSR13 SSR13 = 0) RAME = 0 RESET1 RAME = 1 RESET2 STOPC STOPC STOP Oscillate Oscillate Stop fcyc fcyc Stop Oscillate Stop Stop Stop Active mode Standby mode fOSC: fX: ø CPU : ø CLK : ø PER : fOSC: fX: ø CPU : ø CLK : ø PER : SBY Interrupt fOSC: fX: ø CPU : ø CLK : ø PER : Oscillate Oscillate fcyc fcyc fcyc (TMA3 = 0, SSR13 SSR13 = 1) STOP fOSC: fX: ø CPU : ø CLK : ø PER : Stop Stop Stop Stop Stop (TMA3 = 0) Watch mode (TMA3 = 1) fOSC: fX: ø CPU : ø CLK : ø PER : Oscillate Oscillate Stop fW fcyc SBY Interrupt fOSC: fX: ø CPU : ø CLK : ø PER : Oscillate Oscillate fcyc fW fcyc (TMA3 = 1, LSON = 0) STOP INT0, timer A fOSC: fX: ø CPU : ø CLK : ø PER : Stop Oscillate Stop fW Stop *2 *1 Main oscillation frequency Subactive Suboscillation frequency STOP mode (TMA3 = 1, LSON = 1) for time-base fOSC: Stop fOSC: Stop *3 fcyc: fOSC/4, fOSC/8, fOSC/16 or Oscillate Oscillate fX: fX: fOSC/32 (selected by software) INT0, ø CPU : fSUB ø CPU : Stop fSUB: fX/8 or fX/4 timer A ø CLK : fW ø CLK : fW (software selectable) ø PER : fSUB ø PER : Stop fW: fX/8 ø CPU : System clock ø CLK : Clock for time-base Notes: 1. STOP/SBY (DTON = 1, LSON = 0) ø PER : Peripheral functions clock 2. STOP/SBY (DTON = 0, LSON = 0) LSON: Low speed on flag 3. STOP/SBY (DTON = Don't care, LSON = 1) DTON: Direct transfer on flag fOSC: fX: Figure 14 MCU Status Transitions 33 HD404669 HD404669 Series Active Mode: All MCU functions operate according to the clock generated by the system oscillator OSC1 and OSC2. Standby Mode: In standby mode, the oscillators continue to operate, but the clocks related to instruction execution stop. Therefore, the CPU operation stops, but all RAM and register contents are retained, and the D or R port status, when set to output, is maintained. Peripheral functions such as interrupts, timers, and serial interface continue to operate. The power dissipation in this mode is lower than in active mode because the CPU stops. (Interrupts, timers, the serial interface, and other peripheral functions continue to operate. The exception is the comparator, which is halted.) The MCU enters standby mode when the SBY instruction is executed in active mode. Standby mode is terminated by a RESET input or an interrupt request. If it is terminated by RESET input, the MCU is reset as well. After an interrupt request, the MCU enters active mode and executes the next instruction after the SBY instruction. If the interrupt enable flag is 1, the interrupt is then processed; if it is 0, the interrupt request is left pending and normal instruction execution continues. Figure 15 shows a flowchart of MCU operation. Stop mode Standby mode No RESET=1? No Watch mode RESET=1? Yes No IF0 · IM0=1? No Yes STOPC=0? Yes IF1 · IM1=1? Yes * Yes No No IFTA · IMTA=1? No RAME=1 RAME=0 Yes IF2·IM2 = 1? Yes * IFTC·IMTC + IF3·IM3=1? Yes * No IFTD·IMTD + IF4·IM4=1? No No Yes * IFS1·IMS1=1 Yes * System clock oscillator started Next instruction execution MCU reset No IF =1, IM=0, IE =1? Yes Next instruction execution Interrupts enabled Note: * Only when clearing from standby mode. Figure 15 MCU Operation Flowchart 34 System clock oscillator started HD404669 HD404669 Series Stop Mode: In stop mode, all MCU operations stop and RAM data is retained. Therefore, the power dissipation in this mode is the least of all modes. The OSC 1 and OSC2 oscillator stops. For the X1 and X2 oscillator to operate or stop can be selected by setting bit 3 of the system clock select register 1 (SSR1: $029; operating: SSR13 SSR13 = 0, stop: SSR3 = 1) (figure 24). The MCU enters stop mode if the STOP instruction is executed in active mode when bit 3 of timer mode register A (TMA: $008) is set to 0 (TMA3 = 0) (figure 40). Stop mode is cleared by a RESET or STOPC* input. The RESET or STOPC input must be held for at least the oscillation stabilization time (t RC) as shown in figure 16. (refer to the "AC Characteristics" section.) In either of these cases, the MCU will start program execution from the program start address (location 0). However, the value of the RAM enable flag (RAME: $021,3) will be different in these cases. In particular, RAME will be set to 0 for a RESET input and will be set to 1 for a STOPC input. Also note that while a RESET input is effective in all MCU modes, STOPC is only effective in stop mode, and is ignored in all other modes. If a program needs to determine if stop mode was cleared by a STOPC input (for example, if the program intends to use the contents of RAM that were stored before stop mode was entered after returning to active mode) the program should test the RAM enable flag with a TEST instruction at the start of the program. Note: * If stop mode is to be cleared by a S TOP C input, applications should set bit 2 of port mode register C (PMRC) to 1 (PMRC2 = 1) before switching to stop mode. Stop mode Oscillator Internal clock RESET STOPC tres STOP instruction execution (at least equal to oscillation stabilization time tRC) Figure 16 Timing of Stop Mode Cancellation Watch Mode: In watch mode, the clock function (timer A) using the X1 and X2 oscillator, but other function operations stop. Therefore, the power dissipation in this mode is the second least to stop mode, and this mode is convenient when only clock display is used. In this mode, the OSC 1 and OSC2 oscillator stops, but the X1 and X2 oscillator operates. The MCU is switched to watch mode by executing a STOP instruction while TMA3 = 1 in active mode, or by executing a STOP/SBY instruction while LSON is set to 1 or DTON is cleared to 0 in subactive mode. Watch mode is terminated by a RESET input or a timer-A/INT0 interrupt request. For details of RESET input, refer to the Stop Mode section. When terminated by a timer-A/INT0 interrupt request, the MCU enters active mode if LSON = 0, or subactive mode if LSON = 1. After an interrupt request is generated, the time required to enter active mode is tRC for a timer A interrupt, and TX(where T + tRC < TX < 2T + tRC ) for an INT 0 interrupt, as shown in figures 17 and 18. 35 HD404669 HD404669 Series Operation during mode transition is the same as that at standby mode cancellation (figure 15). Oscillation stabilization time Active mode Watch mode Active mode Interrupt strobe INT0 Interrupt request generation (During the transition from watch mode to active mode only) T T tRC TX T: Interrupt frame period t RC : Oscillation stabilization time Note: If the time from the fall of the INT0 signal until the interrrupt is accepted and active mode is entered is designated Tx, then Tx will be in the following range: T + tRC < Tx < 2T + tRC Figure 17 Interrupt Frame 36 HD404669 HD404669 Series Subactive Mode: The OSC1 and OSC2 oscillator stops and the MCU operates with a clock generated by the X1 and X2 oscillator. In this mode, functions other than the DTMF generation circuit operate, but since the operating clocks are slow, power consumption is the lowest after watch mode. The CPU instruction execution speed can be selected as 244 µs or 122 µs by setting bit 2 (SSR12 SSR12) of the system clock select register (SSR1: $029). Note that the SSR12 SSR12 value must be changed in active mode. If the value is changed in subactive mode, the MCU may malfunction. When the STOP or SBY instruction is executed in subactive mode, the MCU enters either watch or active mode, depending on the statuses of the low speed on flag (LSON: $020, bit 0) and the direct transfer on flag (DTON: $020, bit 3). Subactive mode is an optional function that the user must specify on the function option list. Interrupt Frame: In watch and subactive modes, CLK is applied to timer A and the INT0Icircuit. Prescaler W and timer A operate as the time-base and generate the timing clock for the interrupt frame. Three interrupt frame periods (T) can be selected by setting the miscellaneous register (MIS: $00C) (figure 18). In watch and subactive modes, the timer-A/ INT0 interrupt is generated synchronously with the interrupt frame. The interrupt request is generated synchronously with the interrupt strobe timing except during transition to active mode. An overflow and interrupt request in timer A is generated synchronously with the interrupt strobe timing. Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 MIS1 MIS0 0 0 Bit name MIS3 MIS2 Buffer control. See figure 37 in the pull-up and pull-down MOS transistor control section T*1 tRC * 1 0.24414 ms 0.12207 ms 0.24414 Oscillation circuit conditions External clock input ms* 2 Ceramic oscillator 0 1 15.625 ms 7.8125 ms 1 0 62.5 ms 31.25 ms Crystal oscillator 1 1 Not used Not used - Notes: 1. Values of T and tRC when a 32.768-kHz crystal oscillator is used to pins x1 and x2. 2. The value is applied only when direct transfer operation is used. Figure 18 Miscellaneous Register (MIS) 37 HD404669 HD404669 Series Direct Transition from Subactive Mode to Active Mode: Available by controlling the direct transfer on flag (DTON: $020, bit 3) and the low speed on flag (LSON: $020, bit 0). The procedures are described below: · Set LSON to 0 and DTON to 1 in subactive mode. · Execute the STOP or SBY instruction. · The MCU automatically enters active mode from subactive mode after waiting for the MCU internal processing time and oscillation stabilization time (figure 19). Notes: 1. The DTON flag can be set only in subactive mode. It is always reset in active mode. 2. The transition time (TD) from subactive mode to active mode: tRC < TD < T + tRC STOP/SBY instruction execution Subactive mode MCU internal processing time Oscillation stabilization time Active mode (Set LSON = 0, DTON = 1) Interrupt strobe Direct transfer completion timing t RC T TD Interrupt frame period T: t RC : Oscillation stabilization time TD : Direct transition time Figure 19 Direct Transition Timing MCU Operation Sequence: The MCU operates in the sequence shown in figure 20. It is reset by an asynchronous RESET input, regardless of its status. With the IE flag cleared and an interrupt request flag set together with its interrupt mask cleared, if a STOP/SBY instruction is executed, the instruction is cancelled (regarded as an NOP) and the following instruction is executed. Before executing a STOP/SBY instruction, make sure all interrupt request flags are cleared or all interrupts are masked. 38 HD404669 HD404669 Series STOP/SBY instruction IF = 1 and IM = 0? No Yes Standby/watch mode No Interrupt service routine IE = 0 * No Yes Stop mode IF = 1 and IM = 0? No STOPC = 0? Yes Yes Hardware NOP execution Hardware NOP execution RAME = 1 PC (PC)+1 PC (PC)+1 Reset MCU Instruction execution MCU operation cycle Note: * Refer to figure 15, Flowchart for Exiting Low Power Modes, for IF and IM operation. Figure 20 MCU Operating (Low-Power Mode Operation) Notes: When the MCU is in watch mode or subactive mode, if the high level period before the falling edge of INT0 is shorter than the interrupt frame, INT0 is not detected. Also, if the low level period after the falling edge of INT0 is shorter than the interrupt frame, INT0 is not detected. Edge detection is shown in figure 21. The level of the INT0 signal is sampled by a sampling clock. When this sampled value changes to low from high, a falling edge is detected. 39 HD404669 HD404669 Series In figure 22(a), the level of the INT0 signal is sampled by an interrupt frame. In (a) the sampled value is low at point A, and also low at point B. Therefore, a falling edge is not detected. In (b), the sampled value is high at point A, and also high at point B. A falling edge is not detected in this case either. When the MCU is in watch mode or subactive mode, keep the high level and low level period of INT 0 longer than interrupt frame. INT0 Sampling High Low Low Figure 21 Edge Detection INT0 INT0 Interrupt frame Interrupt frame A: Low B: Low (a) High level period Figure 22 Sampling Example 40 A: High B: High (b) Low level period HD404669 HD404669 Series Internal Oscillator Circuit A block diagram of the clock generation circuit is shown in figure 23. As shown in table 13, a ceramic oscillator or crystal oscillator can be connected to OSC1 and OSC2, and a 32.768-kHz oscillator can be connected to X1 and X2. The system oscillator can also be operated by an external clock. Set bits 0 and 1 (SSR10 SSR10, SSR11 SSR11) of system clock select register 1 (SSR1: $029) and bits 2 and 3 (SSR22 SSR22, SSR23 SSR23) of system clock select register 2 (SSR2: $02A) according to the frequency of the oscillator connected to OSC1 and OSC2 (figures 24 and 25). The system clock division ratio can be set with bits 0 and 1 (SSR20 SSR20, SSR21 SSR21) of system clock select register 2 (SSR2: $02A). The value set in these bits does not become valid until watch mode is entered. Therefore, the system clock must be halted temporarily when changing the division ratio. The system clock division ratio immediately after a reset or when stop mode is cleared can be selected by means of the SEL pin level, division-by-4 being selected when the SEL pin is at Vcc potential, and division-by-32 when at GND potential. Note: If the system clock select register 1 and 2 (SSR1, SSR2: $029, $02A) setting does not match the oscillator frequency, DTMF generation circuit and subsystems using the 32.768-kHz oscillation will malfunction. LSON OSC2 OSC1 System fOSC 1/4, 1/8, 1/16 or clock 1/32 oscillator division circuit fX X1 X2 Subsystem clock oscillator fcyc tcyc Timing generation circuit CPU with ROM, RAM, registers, flags, and I/O øCPU System clock selection circuit øPER Internal Peripheral module interrupts fSUB 1/8 or 1/4 Timing division tsubcyc generation circuit circuit TMA3 bit 1/8 division circuit fW tWcyc Timing generation circuit Time-base clock øCLK selection circuit Time base interrupt Figure 23 Clock Generation Circuit 41 HD404669 HD404669 Series System clock select register 1 (SSR1: $029) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W SSR13 SSR13 W W W SSR13 SSR13 Bit name SSR12 SSR12 SSR11 SSR11 SSR10 SSR10 System clock SSR23 SSR23 SSR22 SSR22 SSR11 SSR11 SSR10 SSR10 selection 32-kHz oscillation stop 0 1 0 0 Oscillation stops in stop mode 1 SSR12 SSR12 32-kHz oscillation division ratio selection 400 kHz 800 kHz 0 2 MHz 1 0 0 1 Oscillation operates in stop mode 4 MHz fSUB = fX/4 1 × × 3.58 MHz 0 fSUB = fX/8 1 1 1 1 8 MHz 1 0 × × 7.16 MHz Note: SSR13 SSR13 is cleared only by a RESET input. SSR13 SSR13 will not be cleared by a STOPC input during stop mode, and will retain its value. SSR13 SSR13 will also not be cleared upon entering stop mode. Figure 24 System Clock Select Register 1 (SSR1) System clock select register 2 (SSR2: $02A) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W SSR23 SSR23 SSR22 SSR22 SSR21 SSR21 SSR20 SSR20 Bit name System clock selection*2 System clock division ratio selection*1 SSR20 SSR20 Selected from 400 kHz, 800 kHz, 2 MHz, 4 MHz 0 0 Division by 4 1 Division by 8 3.58MHz 1 0 Division by 16 0 8MHz 1 Division by 32 1 1 SSR21 SSR21 1 SSR23 SSR23 0 7.16MHz SSR22 SSR22 0 Notes : *1 The DTMF generation circuit frequencies are not affected by the system clock division ratio setting. *2 See system clock select register 1 (SSR1). Figure 25 System Clock Select Register 2 (SSR2) 42 HD404669 HD404669 Series Table 13 Oscillator Circuit Examples Circuit Configuration External clock - External oscillator OSC 1 Open operation Circuit Constants OSC 2 Ceramic oscillator Ceramic oscillator: CSB400P22 CSB400P22 (Murata) CSB400P CSB400P (Murata) Rf = 1 M ± 20% C1 = C2 = 220 pF ± 5% (OSC1, OSC 2) C1 OSC1 Ceramic oscillator Ceramic oscillator: CSB800J122 CSB800J122 (Murata), CSB800J CSB800J (Murata) Rf = 1 M ± 20% C1 = C2 = 220 pF ± 5% Rf OSC2 C2 Ceramic oscillator: CSA2.00MG (Murata) Rf = 1 M ± 20% C1 = C2 = 30 pF ± 20% GND Ceramic oscillator: CSA4.00MG (Murata) Rf = 1 M ± 20% C1 = C2 = 30 pF ± 20% Ceramic oscillator: CSA3.58MG (Murata) Rf = 1 M ± 20% C1 = C2 = 30 pF ± 20% Ceramic oscillator: CSA8.00MT (Murata) Rf = 1 M ± 20% C1 = C2 = 30 pF ± 20% Crystal oscillator Rf = 1 M ± 20% C1 = C2 = 10 to 22pF ± 20% C1 (OSC1, OSC 2) Crystal oscillator OSC1 Rf Crystal oscillator: Equivalent circuit at left C0 =7pF max Rs = 100 max f = 400kHz, 800kHz, 2MHz, 3.58MHz, 4MHz, 7.16MHz, 8MHz OSC2 C2 GND OSC1 L CS RS OSC2 C0 43 HD404669 HD404669 Series Circuit Configuration Circuit Constants C1 Crystal oscillator Crystal oscillator: 32.768 kHz: MX38T MX38T (Nippon Denpa) C1 = C2 = 20 pF ± 20% RS=14 k C0=1.5 pF X1 (X1, X2) Crystal oscillator X2 C2 GND L CS RS X1 X2 C0 Notes: 1. Circuit constants differ by the different types of crystal oscillators, ceramic oscillators, and with the stray capacitance of the board, so consult the manufacturer of the oscillator to determine the circuit parameters. 2. The wiring between the OSC1, OSC 2 (X1 and X2 pins), and the other elements should be as short as possible, and must not cross other wiring. Refer to figure 26. 3. If not using a 32.768-kHz crystal oscillator, fix the X1 pin to VCC and leave the X2 pin open. GND X2 X1 RESET OSC2 OSC1 TEST GND Figure 26 Typical Layouts of Crystal and Ceramic Oscillator 44 HD404669 HD404669 Series Input/Output The MCU has 47 input/output pins (D0 to D5, D 9 to D11, R00 to R43 and R60 to RA 1) and 5 input pins (D12, D13, RD0, RD1 and RE0). The features are described below. · Four pins D0 to D3 are high source current (10 mA maximum) input/output pins. · Five pins D 4, D5, and D9 to D11 are high sink current (15 mA maximum) input/output pins. · Certain of these input and output pins have shared functions with timers, the serial interface, and other peripheral functions. The D 12, D13, R0, R30, R32, R4, RD 0, RD1 and RE0 pins are shared function pins. The use of these pins as peripheral function pins takes precedence over their use as the D and R port pins. Pins that are set to function as peripheral function pins are switched automatically between their various functions and between the input and output directions according to their specifications under the peripheral function setting. · Input or output selection for input/output pins and port or peripheral function selection for multiplexed pins are set by software. · Peripheral function output pins are all CMOS outputs. However, the SO1 pin and the R43 port pin can be set to function as NMOS open drain outputs by software. · Since the MCU goes to the reset state internally after a reset and in stop mode, the peripheral function settings for these pins are cleared. Furthermore, since the data control registers (DCD and DCR) are also reset, the input/output pins go to the high-impedance state. · The D0 to D3 pin circuits include pull-down MOS transistors, and all the other pin circuits include pullup MOS transistors. Note that the on/off states of the pull-up and pull-down MOS transistors can be set independently of the setting for use as peripheral function pins. I/O buffer configurations are shown in figures 27 and 28, and I/O pin circuit structures are listed in tables 14 and 15. HLT Pull-up control signal VCC VCC MIS3 Buffer control signal Pull-up MOS DCD,DCR Output data PDR Input data Input control signal Figure 27 I/O Buffer Configuration (with Pull-Up MOS) 45 HD404669 HD404669 Series Input data Input control signal VCC Buffer control signal DCD Output data Pull-down MOS PDR Pull-down MOS control signal MIS3 HLT Figure 28 I/O Buffer Configuration (with Pull-Down MOS) Table 14 I/O Pin Control by Register Settings (with Pull-Up MOS) MIS3 (bit 3 of MIS) 0 DCD, DCR 1 0 PDR 1 0 1 0 0 1 0 1 0 1 PMOS - - - On - - - On NMOS CMOS buffer 1 - - On - - - On - - - - - - On - On Pull-up MOS Note: 1. - indicates off status. 2. PDR is not assigned to a RAM address. It is accessed with special input/output instructions. Table 15 I/O Pin Control by Register Settings (with Pull-Down MOS) MIS3 (bit 3 of MIS) 0 DCD 1 0 PDR 1 0 1 0 Pull-down MOS Note: 46 0 1 0 1 0 1 PMOS - - - On - - - On NMOS CMOS buffer 1 - - On - - - On - - - - - On - On - 1. - indicates off status. 2. PDR is not assigned to a RAM address. It is accessed with special input/output instructions. HD404669 HD404669 Series Table 16 Input/Output Pin Circuit Configurations I/O Pin Type Circuit Configuration Relevant Pins Input/output pins HLT VCC VCC Pull-up control signal Buffer control signal MIS3 DCD,DCR Output data PDR Input data Input control signal Input data Input control signal D4 , D5 , D9 ­ D11 R0 0­R0 3 R1 0­R1 3 R2 0­R2 3 R3 0­R3 3 R4 0­R4 2 R6 0­R6 3 R7 0­R7 3 R8 0­R8 3 R9 0­R9 3 RA 0, RA 1 D0­D 3 VCC Buffer control signal DCD Output data Pull-down control signal PDR MIS3 HLT VCC HLT VCC Pull-up control signal Buffer control signal Output data R4 3 MIS3 DCR MIS2 PDR Input data Input control signal Input pins Input data D12, D13 RD0, RD1, RE 0 Input control signal 47 HD404669 HD404669 Series Table 16 Input/Output Pin Circuit Configurations (cont) I/O Pin Type Peripheral function Relevant Pins Circuit Configuration Input/output pins VCC VCC Pull-up control signal Output data Input data VCC SCK 1 MIS3 SCK1 SCK1 Output pins VCC HLT Pull-up control signal HLT SO1 MIS3 PMOS control signal MIS2 Output data VCC VCC Pull-up control signal Output data Input pins SO1 HLT MIS3 TOC,TOD HLT VCC MIS3 PDR Input data Input data TOC, TOD SI 1, INT1, INT2, INT3, INT4, EVND SI1,INT1,etc. INT0, STOPC, RESET INT0, STOPC RESET Note: In a reset and in stop mode, since the I/O control registers are reset, input/output pins go to the highimpedance state and peripheral function selections are cleared. 48 HD404669 HD404669 Series D Port The D port consists of 9 input/output pins and 2 input-only pins that can be addressed individually on a perbit basis. The D0 to D3 pins are high source current input/output pins and the D4, D 5, and D9 to D11 pins are high sink current input/output pins. The D 12 and D 13 pins are input-only pins. The D0 to D 5 and D9 to D11 pins can be set or reset by the SED/RED and SEDD/REDD instructions. The output data is stored in the port data register for the pin. All the D port pins can be tested using the TD and TDD instructions. The D port data control registers (DCD0 to DCD2: $02C to $02E) are used to turn the D0 to D5 and D9 to D11 pin output buffers on and off. The DCD registers are mapped to addresses in the RAM area. (figure 29.) The D12 and D 13 pins have shared functions as internal peripheral function pins and the STOPC and INT0 pins. Port mode register C (PMRC: $025) bits 2 and 3 (PMRC2 and PMRC3) are used to switch the functions of these pins. (figure 32.) 49 HD404669 HD404669 Series Data control register DCD0 to DCD2 Bit 3 (DCD0 to 2: $02C to $02E) (DCR0 to 4, DCR6 to A: $030 to $034, $036 to $03A) 2 1 0 Initial value 0 0 0 0 Read/Write W W W W Bit name DCD03 DCD03, DCD02 DCD02, DCD01 DCD01­ DCD00 DCD00­ DCD23 DCD23 DCD22 DCD22 DCD21 DCD21 DCD10 DCD10 DCR0 to DCR4 DCR6 to DCRA Bit 3 2 1 0 Initial value 0 0 0 0 W W W W Read/Write Bit name DCR03 DCR03­ DCR02 DCR02­ DCR01 DCR01­ DCR00 DCR00­ DCR43 DCR43 DCR42 DCR42 DCR41 DCR41 DCR40 DCR40 DCR63 DCR63­ DCR62 DCR62­ DCR61 DCR61­ DCR60 DCR60­ DCR93 DCR93 DCR92 DCR92 DCRA1 DCRA0 Note: Other bits are not used. All Bits CMOS Buffer Control 0 CMOS buffer Off (high-impedance) 1 CMOS buffer active Correspondence between ports and DCD/DCR bits Register Name Bit 3 Bit 2 Bit 1 Bit 0 DCD0 D3 D2 D1 D0 DCD1 - - D5 D4 DCD2 D11 D10 D9 - DCR0 R03 R02 R01 R00 DCR1 R13 R12 R11 R10 DCR2 R23 R22 R21 R20 DCR3 R33 R32 R31 R30 DCR4 R43 R42 R41 R40 DCR6 R63 R62 R61 R60 DCR7 R73 R72 R71 R70 DCR8 R83 R82 R81 R80 DCR9 R93 R92 R91 R90 DCRA - - RA1 RA0 Figure 29 Data Control Registers (DCD, DCR) 50 HD404669 HD404669 Series R Port The R port consist of 38 input/output pins and 3 input pins that can be addressed in groups of 4 bits. Data can be input using the LAR and LBR instructions, and data can be output using the LRA and LRB instructions. Output data is stored in the port data register for the corresponding pin. The R port data control registers (DCR0 to DCR4 and DCR6 to DCRA: $030 to $034, and $036 to $03A) are used to turn the R port output buffers on and off. The DCR registers are mapped to addresses in the RAM area. (figure 29.) The R00 to R04 port pins have shared functions as the external interrupt input pins INT1 to INT4. Port mode register B (PMRB $024) is used to set these pins to their peripheral function usage. (figure 31.) The R40 port pin has a shared function as the EVND peripheral function pin. Port mode register C (PMRC: $025) bit 1 (PMRC1) is used to switch the function of this pin. (figure 32.) The R31 and R32 port pins have shared functions as the TOC and TOD peripheral function pins. Timer mode register C2 (TMC2: $014) bits 0 to 2 (TMC20 TMC20 to TMC22 TMC22) and timer mode register D2 (TMD2: $015) are used to set these pins to their peripheral function usage. (figures 33 and 34.) The R4 1 to R43 port pins have shared functions as the SCK 1, SI 1, and SO1 peripheral function pins. Serial mode register 1A (SM1A: $005) bit 3 (SM1A3) and port mode register A (PMRA: $004) bits 0 and 1 (PMRA0 and PMRA1) are used to set these pins to their peripheral function usage. (figures 30 and 35.) The R4 3/SO 1 pin can be set to function as an NMOS open drain output with the output buffer off. Miscellaneous register (MIS: $00C) bit 2 (MIS2) is used for this setting. (figure 37.) The RD0 and RD1 port pins have shared functions as the COMP0 and COMP1 peripheral function pins. The compare enable register (CER: $018) is used to set these pins to their comparator pin functions. (figure 36.) Port mode register A (PMRA: $004) Bit 3 2 1 0 Initial value - - 0 0 Read/Write - - W W Bit name PMRA1 Not used Not used PMRA1 PMRA0 R42/SI1 R42/SI1 mode selection PMRA0 R43/SO1 R43/SO1 mode selection 0 R42 0 R43 1 SI1 1 SO1 Figure 30 Port Mode Register A (PMRA) 51 HD404669 HD404669 Series Port mode register B (PMRB: $024) Bit 3 2 1 0 Initial value 0 0 0 0 W W W Read/Write Bit name PMRB3 W PMRB3 PMRB2 PMRB1 PMRB0 PMRB0 R03/INT4 R03/INT4 mode selection R00/INT1 R00/INT1 mode selection 0 R03 0 R00 1 INT4 1 INT1 PMRB2 R02/INT3 R02/INT3 mode selection PMRB1 R01/INT2 R01/INT2 mode selection 0 R02 0 R01 1 INT3 1 INT2 Figure 31 Port Mode Register B (PMRB) Port mode register C (PMRC: $025) Bit 3 2 1 0 Initial value 0 0 0 - W W W - Read/Write Bit name PMRC3 PMRC3 PMRC2 PMRC1 Not Used D13/INT0 D13/INT0 mode selection 0 D13 1 INT0 PMRC2 D12/STOPC D12/STOPC mode selection PMRC1 R40/EVND R40/EVND mode selection 0 D12 0 R40 1 STOPC 1 EVND Figure 32 Port Mode Register C (PMRC) 52 HD404669 HD404669 Series Timer mode register C2 (TMC2: $014) Bit 3 2 1 0 Initial value - 0 0 0 Read/Write - R/W R/W R/W TMC21 TMC21 TMC20 TMC20 Bit name Not used TMC22 TMC22 TMC22 TMC22 TMC21 TMC21 TMC20 TMC20 0 0 0 R31 R31 port 1 TOC Toggle output 0 TOC 0 output 1 TOC 1 output 0 - Not Used TOC PWM output 1 0 1 R31/TOC R31/TOC mode selection 1 1 0 1 Figure 33 Timer Mode Register C2 (TMC2) Timer mode register D2 (TMD2: $015) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write R/W R/W R/W R/W TMD23 TMD23 Bit name TMD22 TMD22 TMD21 TMD21 TMD20 TMD20 R32/TOD R32/TOD mode selection TMD23 TMD23 TMD22 TMD22 TMD21 TMD21 TMD20 TMD20 0 0 0 0 R32 R32 port 1 TOD Toggle output 0 TOD 0 output 1 TOD 1 output 0 - Not used 1 TOD PWM output × R32 Input capture (R32 port) 1 1 0 1 1 1 × × 0 × : Don't care Figure 34 Timer Mode Register D2 (TMD2) 53 HD404669 HD404669 Series Serial mode register 1A (SM1A: $005) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W Bit name SM1A3 SM1A2 SM1A1 SM1A0 SM1A3 R41/SCK1 R41/SCK1 mode selection SCK1 Clock source 0 0 Output Prescaler ÷2048 Output Prescaler ÷512 0 Output Prescaler ÷128 1 Output Prescaler ÷32 0 Output Prescaler ÷8 1 Output Prescaler ÷2 0 Output System clock - 1 1 SM1A0 1 R41 SM1A1 0 0 SM1A2 Prescaler division ratio Input External clock - SCK1 1 1 0 1 Figure 35 Serial Mode Register 1A (SM1A) Compare enable register (CER: $018) Bit 3 2 1 0 Initial value 0 - 0 0 Read/Write W - W W Bit name CER1 0 CER3 CER0 Not Used CER1 Analog input pin selection 0 COMP0 1 1 CER0 COMP1 × Not Used × : Don't care CER3 Comparator operation selection 0 Normal operation (digital input mode): RD0/COMP0 and RD1/COMP1 pins function as R port pins 1 Comparator operation (analog input mode): RD0/COMP0 and RD1/COMP1 pins function as comparator pins Figure 36 Compare Enable Register (CER) 54 HD404669 HD404669 Series Pull-up and Pull-down MOS Transistor Control The D4, D5, D9 to D11, and the R port pins have built-in pull-up MOS transistors that can be controlled by software, and the D0 to D3 pins have built-in pull-down MOS transistors that can be controlled by software. The on/off status of all these transistors is controlled by bit 3 (MIS3) of the miscellaneous register (MIS: $00C), and the on/off status of an individual transistor can also be controlled by the port data register (PDR) of the corresponding pin-enabling on/off control of that pin alone (tables 14, 15 and figure 37). The on/off status of each transistor and the peripheral function mode of each pin can be set independently. Miscellaneous register (MIS: $00C) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W MIS3 MIS2 MIS1 MIS0 MIS2 CMOS buffer on/off selection for pin R43/SO1 R43/SO1 Bit name MIS3 Pull-up/Pull-down MOS transistor control 0 Off 0 Active 1 Active 1 Off MIS1 MIS0 tRC selection. Refer to figure 18 in the operation modes section. Figure 37 Miscellaneous Register (MIS) How to Deal with Unused I/O Pins: I/O pins that are not needed by the user system (floating) must be connected to V CC to prevent LSI malfunctions due to noise. These pins must either be pulled up to VCC by their pull-up MOS transistors or by resistors of about 100 k. Pins provided with pull-down MOS should be pulled down to GND potential with the built-in pull-down MOS or connected to GND. 55 HD404669 HD404669 Series Prescalers The MCU has the following two prescalers, S and W. The prescalers operating conditions are listed in table 17, and the prescalers output supply is shown in figure 38. The timers A, C, D input clocks except external events, the serial transmit clock except the external clock, are selected from the prescaler outputs, depending on corresponding mode registers. Table 17 Prescaler Operating Conditions Prescaler Input Clock Reset Conditions Stop Conditions Prescaler S System clock (in active and standby mode), Subsystem clock (in subactive mode) MCU reset MCU reset, stop mode, watch mode Prescaler W Clock derived by dividing subsystem clock 32.768 kHz oscillation by 8 MCU reset, software* MCU reset, stop mode Note: * If bits TMA3 to TMA1 in timer mode register A (TMA) are all set to 1, PSW is cleared to $00. Subsystem clock Prescaler W Timer A Timer C Timer D System clock Clock selector Prescaler S Serial interface 1 Figure 38 Prescaler Output Supply Prescaler Operation Prescaler S: 11-bit counter that inputs the system clock signal. After being reset to $000 by MCU reset, prescaler S divides the system clock. Prescaler S keeps counting, except in watch and stop modes and at MCU reset. Prescaler W: Five-bit counter that inputs the X1 input clock signal (32-kHz crystal oscillation) divided by eight. After being reset to $00 by MCU reset, prescaler W divides the input clock. Prescaler W can be reset by software. 56 HD404669 HD404669 Series Timers The MCU has three timer/counters (A, C, D). · Timer A: Free-running timer · Timer C: Multifunction timer · Timer D: Multifunction timer Timer A is an 8-bit free-running timer. Timers C, D are 8-bit multifunction timers, whose functions are listed in table 18. The operating modes are selected by software. Table 18 Timer Functions Functions Timer A Timer C Timer D Clock Prescaler S Available Available Available source Prescaler W Available - - External event - - Available Timer Free-running Available Available Available functions Time-base Available - - Event counter - - Available Reload - Available Available Watchdog - Available - Input capture - - Available Timer Toggle - Available Available outputs 0 output - Available Available 1 output - Available Available PWM - Available Available Note: - implies not available. Timer A Timer A Functions: Timer A has the following functions. · Free-running timer · Clock time-base The block diagram of timer A is shown in figure 39. 57 HD404669 HD404669 Series 1/4 1/2 2 fW fW twcyc Timer A interrupt request flag (IFTA) Prescaler W (PSW) ÷2 ÷8 ÷ 16 ÷ 32 32.768-kHz oscillator 1/2 twcyc Clock Timer counter A (TCA) Overflow ÷2 ÷4 ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 1024 ÷ 2048 Selector ø PER System clock Internal data bus Selector Selector Prescaler S (PSS) 3 Timer mode register A (TMA) Data bus Clock line Signal line Figure 39 Block Diagram of Timer A Timer A Operations Free-running timer operation: The timer A input clock is selected by timer mode register A (TMA: $008). Timer A is reset to $00 by an MCU reset, and counts up each time the input clock is input. When the input clock is input after the timer A value reaches $FF, overflow output is generated, and the timer A value becomes $00. The generated overflow output sets the timer A interrupt request flag (IFTA: $001, 2). Timer A continues counting up after the count value returns to $00, so that an interrupt is generated regularly every 256 input clock cycles. Realtime clock time base operation: Timer A can be used as the realtime clock time base by setting bit 3 (TMA3) of timer mode register A to 1. As the prescaler W output is input to timer counter A (TCA), interrupts are generated with accurate timing using the 32.768 kHz crystal oscillator as the basic clock.When timer A is used as the realtime clock time base, prescaler W and timer counter A (TCA) can be reset to $00 by the program. Registers for Timer A Operation Timer A operating modes are set by the following registers. Timer mode register A (TMA: $008): Four-bit write-only register that selects timer A's operating mode and input clock source as shown in figure 40. 58 HD404669 HD404669 Series Timer mode register A (TMA: $008) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TMA3 Bit name TMA2 TMA1 TMA0 Source Input clock TMA3 TMA2 TMA1 TMA0 prescaler frequency 0 0 0 1 1 0 1 PSS 128tcyc 0 PSS 32tcyc PSS 8tcyc 0 PSS 4tcyc PSS 2tcyc 0 PSW 32tWcyc PSW 16tWcyc 0 PSW 8tWcyc PSW 2tWcyc 0 - 1/2tWcyc 1 0 512tcyc 1 0 PSS 1 1 0 - Not used × - Timer A mode 1024tcyc 1 1 PSS 1 0 2048tcyc 1 1 PSS 1 1 0 Operating mode Reset PSW and TCA Time-base mode × : Don't care Note: 1. tWcyc = 244.14 µs (when a 32.768-kHz crystal oscillator is used) 2. Timer counter overflow output period (seconds) = input clock period (seconds) × 256. 3. The division ratio must not be modified during time-base mode operation, otherwise an overflow cycle error will occur. Figure 40 Timer Mode Register A (TMA) 59 HD404669 HD404669 Series Timer C Timer C Functions: Timer C has the following functions. · Free-running/reload timer · Watchdog timer · Timer output operation (toggle, 0, 1, and PWM outputs) The block diagram of timer C is shown in figure 41. 60 HD404669 HD404669 Series System reset signal Watchdog on flag (WDON) Timer C interrupt request flag (IFTC) Watchdog timer control logic TOC Timer output control logic ø PER Timer read register CL (TRCL) Timer read register CU (TRCU) ÷2 ÷8 ÷ 128 ÷ 512 clock Timer counter C (TCCL) ÷ 1024 ÷ 2048 3 Timer mode register C1 (TMC1) Free-running/reload control ÷ 32 (TCCU) 4 4 Overflow Internal data bus 4 ÷4 Selector Prescaler S (PSS) System clock Timer write register C (TWCL) (TWCU) 3 Timer output control Data bus Timer mode register C2 (TMC2) Clock line Signal line Figure 41 Block Diagram of Timer C 61 HD404669 HD404669 Series Timer C Operations Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register C1 (TMC1: $00D). Timer C is initialized to the value set in timer write register C (TWCL: $00E, TWCU: $00F) by software and incremented by one at each clock input. If an input clock is applied to timer C after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer C is initialized to its initial value set in timer write register C (TWCL: $00E, TWCU: $00F); if the free-running timer function is enabled, the timer is initialized to $00 and then incremented again. The overflow sets the timer C interrupt request flag (IFTC: $002, bit 2 ). The timer C interrupt request flag is reset by the program, an MCU reset or a transition to stop mode. For details, see figure 3, Configuration of Interrupt Control Bits and Register Flag Area, and table 1, Initial Values after MCU Reset. Watchdog timer operation: Timer C is used as a watchdog timer for detecting out-of-control program routines by setting the watchdog on flag (WDON: $020, bit 1) to 1. If a program routine runs out of control and an overflow is generated, the MCU is reset. Program run can be controlled by initializing timer C by software before it reaches $FF. Timer output operation: The following four output modes can be selected for timer C by setting timer mode register C2 (TMC2: $014). With timer C, the R3 1/TOC pin is designated as the TOC pin, and toggle waveform output, low-level output, high-level output, or PWM waveform output can be selected, by timer mode register C2 (TMC2: $014). TOC pin output is initialized to the low level by an MCU reset. · Toggle output With toggle output, the output level is changed upon input of the next clock pulse after the timer C value reaches $FF. Use of this function in combination with the reload timer allows a clock signal with any period to be output, enabling it to be used as buzzer output. The output waveform is shown in figure 42. · Low-level output With low-level output, the output is changed to the low level when timer C overflows. This function should be used when the output is high. · High-level output With high-level output, the output is changed to the high level when timer C overflows. This function should be used when the output is low. · PWM output With PWM output, variable-duty pulses are output. The output waveform is as shown in figure 42, according to the contents of timer mode register C1 (TMC1: $00D) and timer write register C (TWCL: $00E, TWCU: $00F). 62 HD404669 HD404669 Series Toggle output waveform (timers C and D) Free-running timer 256 clock cycles 256 clock cycles Reload timer (256 ­ N) clock cycles (256 ­ N) clock cycles PWM output waveform (timers C and D) T × (N + 1) TMC13 TMC13 = 0 TMD13 TMD13 = 0 (free-running timer) T T × 256 TMC13 TMC13 = 1 TMD13 TMD13 = 1 (reload timer) T × (256 ­ N) Notes: T: Counter input clock period The clock input source and division ratio are controlled by timer mode register C1 and timer mode register D1. N: Value in timer write register C or timer write register D (When N = 255 (= $FF), PWM output is always fixed low.) Figure 42 Timer Output Waveforms 63 HD404669 HD404669 Series Registers for Timer C Operation By using the following registers, timer C operation modes are selected and the timer C count is read and written. · · · · Timer mode register C1 (TMC1: $00D) Timer mode register C2 (TMC2: $014) Timer write register C (TWCL: $00E, TWCU: $00F) Timer read register C (TRCL: $00E, TRCU: $00F) Timer mode register C1 (TMC1: $00D): Four-bit write-only register that selects the free-running/reload timer function, and the prescaler division ratio as shown in figure 43. It is reset to $0 by MCU reset or in stop mode. Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register C1 write instruction. Setting timer C's initialization by writing to timer write register C (TWCL: $00E, TWCU: $00F) must be done after a mode change becomes valid. Timer mode register C1 (TMC1: $00D) Bit 3 2 0 1 Initial value 0 0 0 0 Read/Write W W W W TMC13 TMC13 TMC12 TMC12 TMC11 TMC11 TMC10 TMC10 Bit name TMC13 TMC13 Free-running/reload timer selection Input clock period 0 0 0 2048tcyc 1024tcyc 0 512tcyc 128tcyc 0 32tcyc 1 8tcyc 0 4tcyc 1 1 TMC10 TMC10 1 Free-running timer TMC11 TMC11 1 0 TMC12 TMC12 2tcyc Reload timer 1 1 0 1 Figure 43 Timer Mode Register C1 (TMC1) 64 HD404669 HD404669 Series Timer mode register C2 (TMC2: $014): Timer mode register C2 (TMC2: $014) is a 3-bit read/write register, used to switch the function of the R31/TOC R31/TOC pin and select the timer C output mode as shown in figure 44. Timer mode register C2 (TMC2: $014) is reset to $0 by an MCU reset or in stop mode. Timer mode register C2 (TMC2: $014) Bit 3 2 1 0 Initial value - 0 0 0 Read/Write - R/W R/W R/W TMC21 TMC21 TMC20 TMC20 Bit name Not used TMC22 TMC22 TMC22 TMC22 TMC21 TMC21 TMC20 TMC20 0 0 0 R31 R31 port 1 TOC Toggle output 0 TOC 0 output 1 TOC 1 output 0 - Not used TOC PWM output 1 1 0 R31/TOC R31/TOC mode selection 1 1 0 1 Figure 44 Timer Mode Register C2 (TMC2) Timer write register C (TWCL: $00E, TWCU: $00F): Timer write register C (TWCL: $00E, TWCU: $00F) is a write-only register composed of a lower digit (TWCL: $00E) and an upper digit (TWCU: $00F). The lower digit (TWCL) of timer write register C is reset to $0 by an MCU reset or in stop mode, while the upper digit (TWCU) is undetermined. Timer C can be initialized by writing to timer write register C (TWCL, TWCU). To write the data, first write the lower digit (TWCL). The lower digit write does not change the timer C value. Next, write the upper digit (TWCU). Timer C is then initialized to the timer write register C (TWCL, TWCU) value. When writing to timer write register C (TWCL, TWCU) from the second time onward, if it is not necessary to change the lower digit (TWCL) reload value, timer C initialization is completed by the upper digit write alone. 65 HD404669 HD404669 Series Timer write register C (lower digit) (TWCL: $00E) Bit 3 2 1 0 Initial value 0 0 0 0 Read/Write W W W W TWCL3 TWCL2 TWCL1 TWCL0 Bit name Figure 45 Timer Write Register C Lower Digit (TWCL) Timer write register C (upper digit) (TWCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined W W W W TWCU3 TWCU2 TWCU1 TWCU0 Figure 46 Timer Write Register C Upper Digit (TWCU) Timer read register C (TRCL: $00E, TRCU: $00F): Timer read register C (TRCL: $00E, TRCU: $00F) is a read-only register composed of a lower digit (TRCL: $00E), and an upper digit (TRCU: $00F) from which the value of the upper digit of timer C is read directly. First, read the upper digit (TRCU) of timer read register C. The current value of the timer C upper digit is read and, at the same time, the value of the timer C lower digit is latched in the lower digit (TRCL) of timer read register C. The timer C value is obtained when the upper digit (TRCU) of timer read register C is read by reading the lower digit (TRCL) of timer read register C. Timer read register C (lower digit) (TRCL: $00E) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCL3 TRCL2 TRCL1 TRCL0 Figure 47 Timer Read Register C Lower Digit (TRCL) 66 HD404669 HD404669 Series Timer read register C (upper digit) (TRCU: $00F) Bit Initial value Read/Write Bit name 3 2 1 0 Undefined Undefined Undefined Undefined R R R R TRCU3 TRCU2 TRCU1 TRCU0 Figure 48 Timer Read Register C Upper Digit (TRCU) Timer D Timer D Functions: Timer D has the following functions. · · · · Free-running/reload timer External event counter Timer output operation (toggle, low-level, high-level, and PWM outputs) Input capture timer The block diagram for each operation mode of timer D is shown in figures 49(1) and 49(2). 67 HD404669 HD404669 Series Timer D interrupt request flag (IFTD) EVND Edge detection logic Timer read register DU (TRDU) øPER System clock ÷ 32 ÷ 128 clock Timer counter D (TCDL) ÷ 512 ÷ 2048 3 Free-running/reload control ÷8 (TCDU) 4 4 Internal data bus 4 ÷4 Selector Prescaler S (PSS) ÷2 Overflow Timer read register DL (TRDL) Timer write register D (TWDL) (TWDU) Timer mode register D1 (TMD1) 2 Edge detection select register 2 Edge detection control (ESR2) Timer mode register D2 (TMD2) Timer output control logic TOD Data bus Clock line Signal line Figure 49(1) Block Diagram of Timer D (Free-Running/Reload Timer/Event Counter Modes) 68 HD404669 HD404669 Series Timer D interrupt request flag (IFTD) Input capture error flag (ICEF) Input capture status flag (ICSF) Error control logic EVND Edge detection logic ø PER Timer read register D 4 4 ÷4 ÷ 32 ÷ 128 clock Selector ÷8 Timer counter D (TCDL) ÷ 512 ÷ 2048 (TCDU) Input capture timer control 3 Timer mode register D1 (TMD1) Internal data bus ÷2 (TRDU) Overflow (TRDL) Prescaler S (PSS) System clock Read signal Timer mode register D2 (TMD2) 2 Edge detection select register 2 Edge detection control (ESR2) Data bus Clock line Signal line Figure 49(2) Block Diagram of Timer D (Input Capture Timer) 69 HD404669 HD404669 Series Timer D Operations: · Free-running/reload timer operation: The free-running/reload operation, input clock source, and prescaler division ratio are selected by timer mode register D1 (TMD1: $010). Timer D is initialized to the value set in timer write register D (TWDL: $011, TWDU: $012) by software and incremented by one at each clock input. If an input clock is applied to timer D after it has reached $FF, an overflow is generated. In this case, if the reload timer function is enabled, timer D is initialized to its initial value set in timer write register D (TWDL: $011, TWDU: $012); if the freerunning timer function is enabled, the timer is initialized to $00 and then incremented again. The timer D interrupt request flag (IFTD: $003, 0) is reset by the program, and by an MCU reset or a transition to stop mode. For details, see figure 3, Configuration of Interrupt Control Bits and Register Flag Areas, and table 1, Initial Values after MCU Reset. · External event counter operation: When external event input is designated for the input clock by timer mode register D1 (TMD1), timer D operates as an external event counter.In this case, pin R40/EVND R40/EVND must be set to EVND by port mode register C (PMRC: $025). Either falling or rising edge, or both falling and rising edges of input signals can be selected as the external event detection edge by detection edge select register 2 (ESR2: $027). When both rising and falling edges detection is selected, the time between the falling edge and rising edge of input signals must be 2t cyc or longer. Timer D is incremented by one at each detection edge selected by detection edge select register 2 (ESR2: $027). The other operation is basically the same as the free-running/reload timer operation. · Timer output operation: The following four output modes can be selected for timer D by setting timer mode register D2 (TMD2: $015). Toggle Low-level output Hige-level output PWM output Pin R3 2/TOD is set to TOD. Toggle output: The operation is basically the same as that of timer-C's toggle output. 0 output: The operation is basically the same as that of timer-C's 0 output. 1 output: The operation is basically the same as that of timer-C's 1 output. PWM output: The operation is basically the same as that of timer-C's PWM output. 70 HD404669 HD404669 Series · Input capture timer operation: The input capture timer counts the clock cycles between trigger edges input to pin EVND. Either falling or rising edge, or both falling and rising edges of input signals can be selected as the trigger input edge by detection edge select register 2 (ESR2: $027). When a trigger edge is input to EVND, the count of timer D is written to timer read register D (TRDL: $011, TRDU: $012), and the timer D interrupt request flag (IFTD: $003, bit 0) and the input capture status flag (ICSF: $021, bit 0) are set. Timer D is reset to $00, and then incremented again. While ICSF is set, if a trigger input edge is applied to timer D, or if timer D generates an overflow, the input capture error flag (ICEF: $021, bit 0) is set. ICSF and ICEF are reset to 0 by MCU reset or by writing 0. By selecting the input capture operation, pin R3 2/TOD is set to R3 2 and timer D is reset to $00. Registers for Timer D Operation: By using the following registers, timer D operation modes are selected and the timer D count is read and written. Timer mode register D1 (TMD1: $010) Timer mode register D2 (TMD2: $015) Timer write register D (TWDL: $011, TWDU: $012) Timer read register D (TRDL: $011, TRDU: $012) Port mode register C (PMRC: $025) Detection edge select register 2 (ESR2: $027) Timer mode register D1 (TMD1: $010): Four-bit write-only register that selects the free-running/reload timer function, input clock source, and the prescaler division ratio as shown in figure 50. Timer mode register D1 (TMD1: $010) is reset to $0 by an MCU reset or in stop mode. · Writing to this register is valid from the second instruction execution cycle after the execution of the previous timer mode register D1 (TMD1: $010) write instruction. Setting timer D's initialization by writing to timer write register D (TWDL: $011, TWDU: $012) must be done after a mode change becomes valid. · When selecting the input capture timer operation, select the internal clock as the input clock source. When designating external event input for the input clock, set bit 1 (PMRC1) of port mode register C (