HD404374/HD404384/ HD404389/HD404082/HD404084 ADE-202-086C HD404374 HD404384 - Datasheet Archive

 

HD404389/HD404082/HD404084 Series Low-Voltage AS Microcomputers with On-Chip A/D Converter ADE-202-086C (O) Rev. 4.0 Feb. 2000

 

HD404374/HD404384/ HD404374/HD404384/ HD404389/HD404082/HD404084 HD404389/HD404082/HD404084 Series Low-Voltage AS Microcomputers with On-Chip A/D Converter ADE-202-086C ADE-202-086C (O) Rev. 4.0 Feb. 2000 Description The HD404374 HD404374, HD404384 HD404384, and HD404389 HD404389 Series comprise low-voltage, 4-bit single-chip microcomputers equipped with four 10-bit A/D converter channels, a serial interface, and large-current I/O pins. These devices are suitable for use in applications requiring high resolution A/D converter control, such as battery chargers. The HD404082 HD404082 and HD404084 HD404084 series offer less advanced features than the HD404384 HD404384 series. They are 4bit microcomputers that support low-voltage operation for backward software compatibility. HD404374 HD404374 Series microcomputers have a 32.768 kHz sub-resonator for realtime clock use, providing a time counting facility, and a variety of low-power modes to reduce current drain. The HD407A4374 HD407A4374, HD407A4384 HD407A4384, HD407A4389 HD407A4389, HD407C4374 HD407C4374, HD407C4384 HD407C4384, and HD407C4389 HD407C4389 are ZTAT TM microcomputers with on-chip PROM that drastically shortens development time and ensures a smooth transition from debugging to mass production. (The PROM programming specifications are the same as for the 27256 type.) ZTAT TM: Zero Turn-Around Time. ZTAT TM is a trademark of Hitachi, Ltd. Features · 20 I/O pins Large-current I/O pins (source: 10 mA max.):4 Large-current I/O pins (sink: 15 mA max.):4 Analog input multiplexed pins: 4 (HD404374 HD404374, HD404384 HD404384, and HD404389 HD404389 Series) · 8-bit timer: 1 channel 16-bit timer: 1 channel (Can also be used as two 8-bit timer channels) · Two timer outputs (including PWM output) · Event counter inputs (edge-programmable) · Clock-synchronous 8-bit serial interface · A/D converter 4 channels × 10-bits (HD404374 HD404374 and HD404384 HD404384 Series) HD404374/HD404384/HD404389/HD404082/HD404084 Series 4 channels × 10-bits (HD404374 HD404374 and HD404384 HD404384 Series) 6 channels × 10-bits (HD404389 HD404389 Series) None (HD404082 HD404082 and HD404084 HD404084 Series) · On-chip oscillators HD404374 HD404374 Series · Main clock (ceramic resonator, crystal resonator, CR oscillation* or external clock operation possible) · Sub-clock (32.768 kHz crystal resonator) HD404384 HD404384, HD404389 HD404389, HD404082 HD404082, and HD404084 HD404084 Series · Main clock (ceramic resonator, crystal resonator, CR oscillation* or external clock operation possible) Note: CR oscillation in an optional function. · Interrupts External: 2 (including one edge-programmable) Internal : 5 (HD404374/HD404384/HD404389 HD404374/HD404384/HD404389 Series) : 4 (HD404082/HD404084 HD404082/HD404084 Series) · Subroutine stack up to 16 levels, including interrupts · Low-power dissipation modes HD404374 HD404374 Series: 4 HD404384 HD404384, HD404389 HD404389, HD404082 HD404082, and HD404084 HD404084 Series: · Module standby (timers, serial interface, A/D converter) · System clock division software switching (1/4 or 1/32) · Inputs for return from stop mode (wakeup): 1 · Instruction execution time Min. 0.89 µs (fOSC = 4.5 MHz, division by 1/4) Min. 0.47 µs (fOSC = 8.5 MHz, division by 1/4) · Operation voltage 1.8 V to 5.5 V 2.0 V to 5.5 V (ZTAT TM) 2 Cautions about operation! · Electrical properties presented on the data sheet for the mask ROM and ZTATTM versions will surely and sufficiently satisfy the standard values. However, real capabilities, operation margin, noise margin, and other properties may vary depending on differences of manufacturing processes, internal wiring patterns, etc. Therefore, it is requested for users to carry out an evaluation test for each product on an actual system under the same conditions to see its operation. · After power supply has been connected, the values for the memory register, data and stack areas will be undefined. Initialize prior to use. 2 HD404374/HD404384/HD404389/HD404082/HD404084 Series Ordering Information HD404374 HD404374 Series Type Product Name Model Name Mask ROM HD404372 HD404372 HD404372FT HD404372FT ROM (Words) RAM (Digits) Package 2,048 512 30-pin plastic SSOP(FP-30D FP-30D) HD404372H HD404372H HD404374 HD404374 30-pin plastic SSOP(FP-30D FP-30D) 48-pin plastic LQFP(FP-48B FP-48B) *1 HD40C4372FT HD40C4372FT 30-pin plastic SSOP(FP-30D FP-30D) HD40C4372H HD40C4372H HD40C4372 HD40C4372 HD40A4372FT HD40A4372FT HD40A4372H HD40A4372H HD40A4372 HD40A4372 48-pin plastic LQFP(FP-48B FP-48B) *1 48-pin plastic LQFP(FP-48B FP-48B) *1 HD404374FT HD404374FT 4,096 30-pin plastic SSOP(FP-30D FP-30D) HD404374H HD404374H 48-pin plastic LQFP(FP-48B FP-48B) *1 HD40A4374FT HD40A4374FT 30-pin plastic SSOP(FP-30D FP-30D) HD40A4374H HD40A4374H 48-pin plastic LQFP(FP-48B FP-48B) *1 HD40C4374FT HD40C4374FT 30-pin plastic SSOP(FP-30D FP-30D) HD40C4374H HD40C4374H 48-pin plastic LQFP(FP-48B FP-48B) *1 HD407A4374 HD407A4374 HD407A4374FT HD407A4374FT 4,096 30-pin plastic SSOP (FP-30D FP-30D) HD407C4374 HD407C4374 HD407C4374FT HD407C4374FT 30-pin plastic SSOP(FP-30D FP-30D) HD40A4374 HD40A4374 HD40C4374 HD40C4374 TM ZTAT 3 HD404374/HD404384/HD404389/HD404082/HD404084 Series HD404384 HD404384 Series Type Product Name Model Name Mask ROM HD404382 HD404382 HD404382FT HD404382FT ROM (Words) RAM (Digits) Package 2,048 512 30-pin plastic SSOP (FP-30D FP-30D) HD404382S HD404382S HD404382H HD404382H 30-pin plastic SSOP (FP-30D FP-30D) 28-pin plastic DILP (DP-28S DP-28S) 48-pin plastic LQFP (FP-48B FP-48B)*1 HD40C4382FT HD40C4382FT 30-pin plastic SSOP (FP-30D FP-30D) HD40C4382S HD40C4382S 28-pin plastic DILP (DP-28S DP-28S) HD40C4382H HD40C4382H HD404384 HD404384 HD40A4382FT HD40A4382FT HD40A4382H HD40A4382H HD40C4382 HD40C4382 48-pin plastic LQFP (FP-48B FP-48B)*1 HD40A4382S HD40A4382S HD40A4382 HD40A4382 28-pin plastic DILP (DP-28S DP-28S) 48-pin plastic LQFP (FP-48B FP-48B)*1 HD404384FT HD404384FT 4,096 30-pin plastic SSOP (FP-30D FP-30D) HD404384S HD404384S HD404384H HD404384H 4 HD40C4384FT HD40C4384FT 30-pin plastic SSOP (FP-30D FP-30D) 28-pin plastic DILP (DP-28S DP-28S) 48-pin plastic LQFP (FP-48B FP-48B)*1 HD407A4384FT HD407A4384FT 4,096 30-pin plastic SSOP (FP-30D FP-30D) 28-pin plastic DILP (DP-28S DP-28S) HD407C4384FT HD407C4384FT 30-pin plastic SSOP (FP-30D FP-30D) HD407C4384S HD407C4384S HD407C4384 HD407C4384 48-pin plastic LQFP (FP-48B FP-48B)*1 HD407A4384S HD407A4384S HD407A4384 HD407A4384 28-pin plastic DILP (DP-28S DP-28S) HD40C4384H HD40C4384H TM 30-pin plastic SSOP (FP-30D FP-30D) HD40C4384S HD40C4384S ZTAT HD40A4384FT HD40A4384FT HD40A4384H HD40A4384H HD40C4384 HD40C4384 48-pin plastic LQFP (FP-48B FP-48B)*1 HD40A4384S HD40A4384S HD40A4384 HD40A4384 28-pin plastic DILP (DP-28S DP-28S) 28-pin plastic DILP (DP-28S DP-28S) HD404374/HD404384/HD404389/HD404082/HD404084 Series HD404389 HD404389 Series Type Product Name Model Name Mask ROM HD404388 HD404388 HD404388FT HD404388FT ROM (Words) RAM (Digits) Package 8,192 512 30-pin plastic SSOP (FP-30D FP-30D) HD40A4388 HD40A4388 HD40C4388 HD40C4388 HD404389FT HD404389FT HD40A4389 HD40A4389 HD40A4389FT HD40A4389FT HD40C4389 HD40C4389 ZTAT HD40C4388FT HD40C4388FT HD404389 HD404389 TM HD40A4388FT HD40A4388FT HD40C4389FT HD40C4389FT HD407A4389 HD407A4389 HD407A4389FT HD407A4389FT 16,384 HD407C4389 HD407C4389 HD407C4389FT HD407C4389FT 16,384 5 HD404374/HD404384/HD404389/HD404082/HD404084 Series HD404082 HD404082 Series Type Product Name Model Name Mask ROM HD404081 HD404081 HD404081FT HD404081FT ROM (Words) RAM (Digits) Package 1,024 128 30-pin plastic SSOP (FP-30D FP-30D) HD404081S HD404081S HD404081H HD404081H 30-pin plastic SSOP (FP-30D FP-30D) 28-pin plastic DILP (DP-28S DP-28S) 48-pin plastic LQFP (FP-48B FP-48B)*2 HD40C4081FT HD40C4081FT 30-pin plastic SSOP (FP-30D FP-30D) HD40C4081S HD40C4081S 28-pin plastic DILP (DP-28S DP-28S) HD40C4081H HD40C4081H HD404082 HD404082 HD40A4081FT HD40A4081FT HD40A4081H HD40A4081H HD40C4081 HD40C4081 48-pin plastic LQFP (FP-48B FP-48B)*2 HD40A4081S HD40A4081S HD40A4081 HD40A4081 28-pin plastic DILP (DP-28S DP-28S) 48-pin plastic LQFP (FP-48B FP-48B)*2 HD404082FT HD404082FT 2,048 30-pin plastic SSOP (FP-30D FP-30D) HD404082S HD404082S 28-pin plastic DILP (DP-28S DP-28S) HD404082H HD404082H 48-pin plastic LQFP (FP-48B FP-48B)*2 HCD404082 HCD404082 HCD404082 HCD404082 chip HD40A4082 HD40A4082 HD40A4082FT HD40A4082FT 30-pin plastic SSOP (FP-30D FP-30D) HD40A4082S HD40A4082S 28-pin plastic DILP (DP-28S DP-28S) HD40A4082H HD40A4082H 48-pin plastic LQFP (FP-48B FP-48B)*2 HD40C4082FT HD40C4082FT 30-pin plastic SSOP (FP-30D FP-30D) HD40C4082S HD40C4082S 28-pin plastic DILP (DP-28S DP-28S) HD40C4082H HD40C4082H 48-pin plastic LQFP (FP-48B FP-48B)*2 HCD40C4082 HCD40C4082 chip HD40C4082 HD40C4082 HCD40C4082 HCD40C4082 TM ZTAT TM Uses HD404384 HD404384 series ZTAT . Notes: 1. The FP-48B FP-48B is subject to the following limitations: (1) It is available in a mask ROM version only. For debugging, etc., the ZTATTM version of a different package will need to be used. (2) The WS version will become available at the beginning of mass production. 2. Currently in planning stage. 6 HD404374/HD404384/HD404389/HD404082/HD404084 Series HD404084 HD404084 Series Type Product Name Model Name Mask ROM HD404084 HD404084 HD404084FT HD404084FT ROM (Words) RAM (Digits) Package 4,096 256 30-pin plastic SSOP (FP-30D FP-30D) HD404084S HD404084S 28-pin plastic DILP (DP-28S DP-28S) HCD404084 HCD404084 HCD404084 HCD404084 chip HD40A4084 HD40A4084 HD40A4084FT HD40A4084FT 30-pin plastic SSOP (FP-30D FP-30D) HD40A4084S HD40A4084S 28-pin plastic DILP (DP-28S DP-28S) HD40C4084FT HD40C4084FT 30-pin plastic SSOP (FP-30D FP-30D) HD40C4084S HD40C4084S 28-pin plastic DILP (DP-28S DP-28S) HCD40C4084 HCD40C4084 chip HD40C4084 HD40C4084 HCD40C4084 HCD40C4084 TM ZTAT Uses HD404384 HD404384 series ZTAT TM 7 HD404374/HD404384/HD404389/HD404082/HD404084 Series List of Functions Product Name HD404372 HD404372, HD40A4372 HD40A4372, HD40C4372 HD40C4372 ROM(words) 2,048 RAM (digit) 20 (max) Large-current I/O pins 4,096 ZTAT PROM HD404382 HD404382, HD40A4382 HD40A4382, HD40C4382 HD40C4382 HD404384 HD404384, HD40A4384 HD40A4384, HD40C4384 HD40C4384, HD407A4384 HD407A4384, HD407C4384 HD407C4384 512 I/O HD404374 HD404374, HD40A4374 HD40A4374, HD40C4374 HD40C4374, HD407A4374 HD407A4374, HD407C4374 HD407C4374 2,048 4,096 ZTAT PROM HD404388 HD404388, HD40A4388 HD40A4388, HD40C4388 HD40C4388 8,192 4 (source, 10 mA max), 4 (sink, 15 mA max) Analog input 4 multiplexed pins Timer/ counter 3 Timer output 2 (PWM output possible) Event input 1 (edge selection possible) Serial interface 1 (8-bit synchronous) A/D converter 10 bits × 4 channels Interrupt External 2 sources Internal 10 bits × 6 channels 5 Low-power modes 4 Stop mode Available Watch mode Available Standby mode 2 Available Subactive mode Available - - Module standby Available System clock division software switching Available Main oscillator Ceramic oscillation Available Crystal oscillation Available CR oscillation Available (HD40C4372 HD40C4372, HD40C4374 HD40C4374, HD407C4374 HD407C4374, HD40C4382 HD40C4382, HD40C4384 HD40C4384, HD407C4384 HD407C4384, HD40C4388 HD40C4388, HD40C4389 HD40C4389, HD407C4389 HD407C4389, HD40C4081 HD40C4081, HD40C4082 HD40C4082, HCD40C4082 HCD40C4082, HD40C4084 HD40C4084, HCD40C4084 HCD40C4084) Crystal oscillation Available (32.768kHz) Sub-oscillator 8 - HD404374/HD404384/HD404389/HD404082/HD404084 Series HD404372 HD404372, HD40A4372 HD40A4372, HD40C4372 HD40C4372 Product Name Minimum instruction execution time HD404374 HD404374, HD40A4374 HD40A4374, HD40C4374 HD40C4374, HD407A4374 HD407A4374, HD407C4374 HD407C4374 HD404382 HD404382, HD40A4382 HD40A4382, HD40C4382 HD40C4382 HD404384 HD404384, HD40A4384 HD40A4384, HD40C4384 HD40C4384, HD404388 HD404388, HD407A4384 HD407A4384, HD40A4388 HD40A4388, HD407C4384 HD407C4384 HD40C4388 HD40C4388 0.47 ms (f OSC = 8.5 MHz) : HD40A4372 HD40A4372, HD40A4374 HD40A4374, HD407A4374 HD407A4374, HD40A4382 HD40A4382, HD40A4384 HD40A4384, HD407A4384 HD407A4384, HD40A4388 HD40A4388, HD40A4389 HD40A4389, HD407A4389 HD407A4389, HD40A4081 HD40A4081, HD40A4082 HD40A4082, HD40A4084 HD40A4084 0.89 ms (f OSC = 4.5 MHz) : HD404372 HD404372, HD404374 HD404374, HD404382 HD404382, HD404384 HD404384, HD404388 HD404388, HD404389 HD404389, HD404081 HD404081, HD404082 HD404082, HCD404082 HCD404082, HD404084 HD404084, HCD404084 HCD404084 1.14 ms (f OSC = 3.5 MHz) : HD40C4372 HD40C4372, HD40C4374 HD40C4374, HD407C4374 HD407C4374, HD40C4382 HD40C4382, HD40C4384 HD40C4384, HD407C4384 HD407C4384, HD40C4388 HD40C4388, HD40C4389 HD40C4389, HD407C4389 HD407C4389, HD40C4081 HD40C4081, HD40C4082 HD40C4082, HCD40C4082 HCD40C4082, HD40C4084 HD40C4084, HCD40C4084 HCD40C4084 Operating voltage (V) Package 1.8 to 5.5 V : Mask ROM, 2.0 to 5.5 V : ZTATTM FP-30D FP-30D Available DP-28S DP-28S - FP-48B FP-48B Available Chip - - - Guaranteed operation temperature(°C) Available ­20 to +75: Mask ROM ­40 to +85: ZTAT TM 9 HD404374/HD404384/HD404389/HD404082/HD404084 Series HD404389 HD404389, HD40A4389 HD40A4389, HD40C4389 HD40C4389, HD404081 HD404081, HD404084 HD404084, HD404082 HD404082, HD407A4389 HD407A4389, HD40A4081 HD40A4081, HD40A4082 HD40A4082, HCD404082 HCD404082, HD40A4084 HD40A4084, HCD404084 HCD404084, HD40C4081 HD40C4081 HD40C4082 HD40C4082 HCD40C4082 HCD40C4082 HD40C4084 HD40C4084 HCD40C4084 HCD40C4084 Product Nme HD407C4389 HD407C4389 ROM(words) 16,384 1,024 ZTAT PROM RAM (digit) 512 I/O 20 (max) Large-current I/O pins counter 4,096 128 4 (source, 10 mA max), 4 (sink, 15 mA max) Analog input 4 multiplexed pins Timer/ 2,048 - 3 Timer output 2 (PWM output possible) Event input 1 (edge selection possible) Serial interface 1 (8-bit synchronous) A/D converter 10 bits × 6 channels Interrupt External 2 sources Internal 5 - Low-power modes 4 4 Stop mode Available Watch mode Available Standby mode Available Subactive mode Available Module standby Available System clock division software switching Available Main oscillator Ceramic oscillation Available Crystal oscillation Available CR oscillation Available (HD40C4372 HD40C4372, HD40C4374 HD40C4374, HD407C4374 HD407C4374, HD40C4382 HD40C4382, HD40C4384 HD40C4384, HD407C4384 HD407C4384, HD40C4388 HD40C4388, HD40C4389 HD40C4389, HD407C4389 HD407C4389, HD40C4081 HD40C4081, HD40C4082 HD40C4082, HCD40C4082 HCD40C4082, HD40C4084 HD40C4084, HCD40C4084 HCD40C4084) Crystal oscillation - Sub-oscillator 10 HD404374/HD404384/HD404389/HD404082/HD404084 Series HD404389 HD404389, HD40A4389 HD40A4389, HD40C4389 HD40C4389, HD404081 HD404081, HD404084 HD404084, HD404082 HD404082, HD407A4389 HD407A4389, HD40A4081 HD40A4081, HD40A4082 HD40A4082, HCD40482 HCD40482, HD40A4084 HD40A4084, HCD404084 HCD404084, HD40C4081 HD40C4081 HD40C4082 HD40C4082 HCD40C4082 HCD40C4082 HD40C4084 HD40C4084 HCD40C4084 HCD40C4084 Product Nme HD407C4389 HD407C4389 Minimum instruction execution time 0.47 µs (fOSC = 8.5 MHz) : HD40A4372 HD40A4372, HD40A4374 HD40A4374, HD407A4374 HD407A4374, HD40A4382 HD40A4382, HD40A4384 HD40A4384, HD407A4384 HD407A4384, HD40A4388 HD40A4388, HD40A4389 HD40A4389, HD407A4389 HD407A4389, HD40A4081 HD40A4081, HD40A4082 HD40A4082, HD40A4084 HD40A4084 0.89 µs (fOSC = 4.5 MHz) : HD404372 HD404372, HD404374 HD404374, HD404382 HD404382, HD404384 HD404384, HD404388 HD404388, HD404389 HD404389, HD404081 HD404081, HD404082 HD404082, HCD404082 HCD404082, HD404084 HD404084, HCD404084 HCD404084 1.14 µs (fOSC = 3.5 MHz) : HD40C4372 HD40C4372, HD40C4374 HD40C4374, HD407C4374 HD407C4374, HD40C4382 HD40C4382, HD40C4384 HD40C4384, HD407C4384 HD407C4384, HD40C4388 HD40C4388, HD40C4389 HD40C4389, HD407C4389 HD407C4389, HD40C4081 HD40C4081, HD40C4082 HD40C4082, HCD40C4082 HCD40C4082, HD40C4084 HD40C4084, HCD40C4084 HCD40C4084 1.8 to 5.5 V : Mask ROM, 2.0 to 5.5 V : ZTAT TM Operating voltage (V) Package FP-30D FP-30D Available DP-28S DP-28S - Available - FP-48B FP-48B - In planning stage - Available - Chip - Available - Available Guaranteed operation temperature(°C) ­20 to +75: Mask ROM ­40 to +85: ZTATTM +75 ­20 to +75: Mask ROM ­40 to +85: ZTATTM +75 11 HD404374/HD404384/HD404389/HD404082/HD404084 Series Pin Arrangement HD404374 HD404374 Series GND Vcc AVcc R70/AN0 R70/AN0 R71/AN1 R71/AN1 R72/AN2 R72/AN2 R73/AN3 R73/AN3 AVss OSC1 OCS2 TEST X2 X1 RESET R00/WU0 R00/WU0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 R70/AN0 R70/AN0 R71/AN1 R71/AN1 R72/AN2 R72/AN2 R73/AN3 R73/AN3 NC AVSS OSC1 NC OSC2 NC TEST X2 48 47 46 45 44 43 42 41 40 39 38 37 36 1 35 2 34 3 33 4 32 5 FP-48B FP-48B 31 6 (Top View) 30 7 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 FP-30D FP-30D D9 D8 D7 D6 N-MOS large current pins D5 D4 D3 D2 P-MOS large current pins D1 D0/INT0 R22/SI/SO R22/SI/SO R21/SCK R21/SCK R20/TOC R20/TOC R13/TOB R13/TOB R10/EVNB R10/EVNB AVCC VCC NC GND NC D9 NC NC D8 D7 NC D6 (Top View) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 X1 NC RESET NC R00/WU0 R00/WU0 NC R10/EVNB R10/EVNB NC R13/TOB R13/TOB NC R20/TOC R20/TOC R21/SCK R21/SCK N-MOS large current pins 12 D5 D4 NC D3 NC D2 NC P-MOS large current pins D1 NC D0/INT0 NC R22/SI/SO R22/SI/SO HD404374/HD404384/HD404389/HD404082/HD404084 Series HD404384 HD404384 Series 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND Vcc AVcc R70/AN0 R70/AN0 R71/AN1 R71/AN1 R72/AN2 R72/AN2 R73/AN3 R73/AN3 AVss OSC1 OCS2 TEST RESET R00/WU0 R00/WU0 R10/EVNB R10/EVNB 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FP-30D FP-30D (Top View) DP-28S DP-28S (Top View) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 D9 D8 D7 D6 N-MOS large current pins D5 D4 D3 D2 P-MOS large current pins D1 D0/INT0 R22/SI/SO R22/SI/SO R21/SCK R21/SCK R20/TOC R20/TOC R13/TOB R13/TOB R10/EVNB R10/EVNB 28 27 26 25 24 23 22 21 20 19 18 17 16 15 D9 D8 D7 D6 N-MOS large current pins D5 D4 D3 D2 P-MOS large current pins D1 D0/INT0 R22/SI/SO R22/SI/SO R21/SCK R21/SCK R20/TOC R20/TOC R13/TOB R13/TOB AVCC VCC NC GND NC D9 NC NC D8 D7 NC D6 GND Vcc AVcc R70/AN0 R70/AN0 R71/AN1 R71/AN1 R72/AN2 R72/AN2 R73/AN3 R73/AN3 AVss OSC1 OCS2 TEST NC NC RESET R00/WU0 R00/WU0 N-MOS large current pins D5 D4 NC D3 NC D2 NC N-MOS large current pins D1 NC D0/INT0 NC R22/SI/SO R22/SI/SO NC NC RESET NC R00/WU0 R00/WU0 NC R10/EVNB R10/EVNB NC R13/TOB R13/TOB NC R20/TOC R20/TOC R21/SCK R21/SCK R70/AN0 R70/AN0 R71/AN1 R71/AN1 R72/AN2 R72/AN2 R73/AN3 R73/AN3 NC AVSS OSC1 NC OSC2 NC TEST NC 48 47 46 45 44 43 42 41 40 39 38 37 36 1 35 2 34 3 33 4 32 5 31 6 FP-48B FP-48B 30 7 (Top View) 29 8 28 9 27 10 26 11 25 12 13 14 15 16 17 18 19 20 21 22 23 24 13 HD404374/HD404384/HD404389/HD404082/HD404084 Series HD404389 HD404389 Series GND Vcc AVcc R70/AN0 R70/AN0 R71/AN1 R71/AN1 R72/AN2 R72/AN2 R73/AN3 R73/AN3 AN4 AN5 AVSS TEST OSC1 OSC2 RESET R00/WU0 R00/WU0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FP-30D FP-30D (Top View) D9 D8 D7 D6 N-MOS large current pins D5 D4 D3 D2 P-MOS large current pins D1 D0/INT0 R22/SI/SO R22/SI/SO R21/SCK R21/SCK R20/TOC R20/TOC R13/TOB R13/TOB R10/EVNB R10/EVNB 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 HD404082 HD404082 and HD404084 HD404084 Series GND VCC NC R70 R71 R72 R73 NC OSC1 OSC2 TEST NC NC RESET R00/WU0 R00/WU0 GND VCC NC R70 R71 R72 R73 NC OSC1 OSC2 TEST RESET R00/WU0 R00/WU0 R10/EVNB R10/EVNB 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FP-30D FP-30D (Top View) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0/INT0 R22/SI/SO R22/SI/SO R21/SCK R21/SCK R20/TOC R20/TOC R13/TOB R13/TOB R10/EVNB R10/EVNB DP-28S DP-28S (Top View) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0/INT0 R22/SI/SO R22/SI/SO R21/SCK R21/SCK R20/TOC R20/TOC R13/TOB R13/TOB N-MOS large current pins P-MOS large current pins N-MOS large current pins P-MOS large current pins HD404374/HD404384/HD404389/HD404082/HD404084 Series Pad Arrangement 23 24 25 26 1 2 3 HCD404082 HCD404082 and HCD404084 HCD404084 22 5 6 21 Model Name 4 20 19 7 18 8 17 9 15 14 13 12 11 10 16 Model Name: HD404082 HD404082 (HCD404082 HCD404082) HD404084 HD404084 (HCD404084 HCD404084) 15 HD404374/HD404384/HD404389/HD404082/HD404084 Series Pad Coordinates HCD404082 HCD404082 and HCD404084 HCD404084 Y Chip size (X × Y): Coordinates: 4.63 × 4.77 (mm) Pad center Mold Home point position: Chip center Pad size (X × Y): 90 × 90 (µm) Chip thickness: X 280 (µm) Chip center (X=0,Y=0) Pad Coodinates Pad Coodinates No. Pad name X (µm) Y (µm) No. Pad name X (µm) Y (µm) 1 GND -458 1403 14 R2 0 572 -1403 2 VCC -826 1403 15 R2 1 982 -1403 3 R7 0 -1338 1403 16 R2 2 1338 -1403 4 R7 1 -1338 1006 17 D0 1338 -1020 5 R7 2 -1338 525 18 D1 1338 -637 6 R7 3 -1338 285 19 D2 1338 -254 7 OSC1 -1338 -550 20 D3 1338 129 8 OSC2 -1338 -954 21 D4 1338 768 9 TEST -1338 -1251 22 D5 1338 1170 10 RESETN -1197 -1403 23 D6 1153 1403 11 R0 0 -577 -1403 24 D7 751 1403 12 R1 0 -194 -1403 25 D8 349 1403 13 R1 3 189 -1403 26 D9 -53 1403 16 HD404374/HD404384/HD404389/HD404082/HD404084 Series Pin Description HD404374 HD404374 and HD404384 HD404384 Series Pin Number Item Symbol FP-30D FP-30D DP-28S DP-28S*2 DP-48B DP-48B I/O Function Power supply VCC 2 2 47 - Apply the power supply voltage to this pin. GND 1 1 45 - Connect to ground. Test TEST 11 11 11 Input Not for use by the user application. Connect to GND potential. Reset RESET 14 12 15 Input Used to reset the MCU. 9 9 7 Input Internal oscillator input/output pins. Connect a ceramic resonator, crystal resonator, or external oscillator circuit. OSC2 10 10 9 Output When using CR oscillation, connect a resistor. X1 13*1 - 13*1 Input X2 12*1 - 12*1 Output Realtime clock oscillator input/output pins. Connect a 32.768 kHz crystal. If 32.768 kHz crystal oscillation is not used, fix the X1 pin to VCC and leave the X2 pin open. D0­D9 21­30 19­28 27, 29, 31, 33, 35­ I/O 37, 39, 40, 43 I/O pins addressed bit by bit. D 0 to D3 are large-current source pins (max. 10 mA), and D4 to D9 are large-current sink pins (max. 15 mA). R00, R1 0, R1 3, 15­20, R20, R2 1, R2 2, 4­7 R70­R7 3 13­18, 4­7 17, 19, 21, 23­25, I/O 1­4 I/O pins, addressed in 4-bit units. Interrupt INT0 21 19 27 Input External interrupt input pin Wakeup WU0 15 13 17 Input Input pin used for transition from stop mode to active mode. Serial SCK 19 17 24 I/O Serial interface clock I/O pin interface SI 20 18 25 Input Serial interface receive data input pin SO 20 18 25 Output Serial interface transmit data output pin TOB,TOC 17, 18 15, 16 21, 23 Output Timer output pins EVNB 16 14 19 Input Event count input pin AV CC 3 3 48 - A/D converter power supply pin. Connect as close as possible to the VCC pin so as to be at the same potential as V CC. AV SS 8 8 6 - Ground pin for AVCC. Connect as close as possible to the GND pin so as to be at the same potential as GND. AN0­AN 3 4­7 4­7 1­4 Input A/D converter analog input pins NC 12*2, 13*2 - 5, 8, 10, 12*2, - 13*2, 14, 16, 18, 20, 22, 26, 28, 30, 32, 34, 38, 41, 42, 44, 46 Oscillation OSC1 Port Timer A/D converter Other Connect to GND potential. Notes: *1 Applies to HD404374 HD404374 Series. *2 Applies to HD404384 HD404384 Series. 17 HD404374/HD404384/HD404389/HD404082/HD404084 Series HD404389 HD404389 Series Pin Number Item Symbol FP-30D FP-30D I/O Function Power supply VCC 2 - Apply the power supply voltage to this pin. GND 1 - Connect to ground. Test TEST 11 Input Not for use by the user application. Connect to GND potential. Reset RESET 14 Input Used to reset the MCU. Oscillation OSC1 12 Input Internal oscillator input/output pins. Connect a ceramic resonator, crystal resonator, or external oscillator circuit. OSC2 13 Output When using CR oscillation, connect a resistor. D0­D9 21­30 I/O I/O pins addressed bit by bit. D 0 to D3 are large-current source pins (max. 10 mA), and D 4 to D9 are large-current sink pins (max. 15 mA). R00, R1 0, R1 3, 15­20, R20, R2 1, R2 2, 4­7 R70­R7 3 I/O I/O pins, addressed in 4-bit units. Interrupt INT0 21 Input External interrupt input pin Wakeup WU0 15 Input Input pin used for transition from stop mode to active mode. Serial SCK 19 I/O Serial interface clock I/O pin interface SI 20 Input Serial interface receive data input pin SO 20 Output Serial interface transmit data output pin TOB,TOC 17, 18 Output Timer output pins EVNB 16 Input Event count input pin AV CC 3 - A/D converter power supply pin. Connect as close as possible to the V CC pin so as to be at the same potential as VCC. AV SS 10 - Ground pin for AVCC. Connect as close as possible to the GND pin so as to be at the same potential as GND. AN0­AN 5 4­9 Input A/D converter analog input pins Port Timer A/D converter 18 HD404374/HD404384/HD404389/HD404082/HD404084 Series HD404082 HD404082 and HD404084 HD404084 Series Pin Number Item Symbol FP-30D FP-30D DP-28S DP-28S Chip I/O Function Power supply VCC 2 2 2 - Apply the power supply voltage to this pin. GND 1 1 1 - Connect to ground. Test TEST 11 11 9 Input Not for use by the user application. Connect to GND potential. Reset RESET 14 12 10 Input Used to reset the MCU. 9 9 7 Input Internal oscillator input/output pins. Connect a ceramic resonator, crystal resonator, or external oscillator circuit. OSC2 10 10 8 Output When using CR oscillation, connect a resistor. D0­D9 21­30 19­28 17­26 I/O I/O pins addressed bit by bit. D 0 to D3 are large-current source pins (max. 10 mA), and D4 to D9 are large-current sink pins (max. 15 mA). R00, R1 0, R1 3, 15­20, R20, R2 1, R2 2, 4­7 R70­R7 3 13­18, 4­7 11­16, 3­6 I/O I/O pins, addressed in 4-bit units. Interrupt INT0 21 19 17 Input External interrupt input pin Wakeup WU0 15 13 11 Input Input pin used for transition from stop mode to active mode. Serial SCK 19 17 15 I/O Serial interface clock I/O pin interface SI 20 18 16 Input Serial interface receive data input pin SO 20 18 16 Output Serial interface transmit data output pin TOB,TOC 17, 18 15, 16 13, 14 Output Timer output pins EVNB 16 14 12 Input Event count input pin NC 3, 8, 12, 3, 8 13 - - Connect to GND potential. Oscillation OSC1 Port Timer Other 19 HD404374/HD404384/HD404389/HD404082/HD404084 Series Block Diagram D Port D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 R0 Port R00 R1 Port R10 R13 R2 Port R20 R21 R22 R7 Port RESET TEST OSC1 OSC2 X1 * X2 * Vcc GND HD404374 HD404374 and HD404384 HD404384 Series R70 R71 R72 R73 HMCS400 HMCS400 CPU ROM INT0 WU0 RAM External interrupt control circuit 8-bit timer A TOB P-MOS large current buffer N-MOS large current buffer 8-bit timer B EVNB TOC 8-bit timer C SCK SI/SO 8-bit synchronous serial interface AVcc AN0 AN1 AN2 AN3 AVss A/D converter 10 bit × 4 channels : Data bus Note : * Applies to HD404374 HD404374 Series. 20 : Signal line HD404374/HD404384/HD404389/HD404082/HD404084 Series D Port D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 R0 Port R00 R1 Port R10 R13 R2 Port R20 R21 R22 R7 Port Vcc GND RESET TEST OSC1 OSC2 HD404389 HD404389 Series R70 R71 R72 R73 HMCS400 HMCS400 CPU ROM INT0 WU0 RAM External interrupt control circuit 8-bit timer A TOB P-MOS large current buffer N-MOS large current buffer 8-bit timer B EVNB TOC 8-bit timer C SCK SI/SO 8-bit synchronous serial interface AVcc AN0 AN1 AN2 AN3 AN4 AN5 AVss A/D converter 10 bit × 6 channels : Data bus : Signal line 21 HD404374/HD404384/HD404389/HD404082/HD404084 Series D Port D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 R0 Port R00 R1 Port R10 R13 R2 Port R20 R21 R22 R7 Port Vcc GND RESET TEST OSC1 OSC2 HD404082 HD404082 and HD404084 HD404084 Series R70 R71 R72 R73 HMCS400 HMCS400 CPU ROM INT0 WU0 RAM External interrupt control circuit 8-bit timer A TOB P-MOS large current buffer N-MOS large current buffer 8-bit timer B EVNB TOC 8-bit timer C SCK SI/SO 8-bit synchronous serial interface : Data bus 22 : Signal line HD404374/HD404384/HD404389/HD404082/HD404084 Series Memory Map ROM Memory Map The ROM memory map is shown in figure 1 and is described below. Vector address area ($0000 to $000F): When an MCU reset or interrupt handling is performed, the program is executed from the vector address. A JMPL instruction should be used to branch to the start address of the reset routine or the interrupt routine. Zero page subroutine area ($0000 to $003F):A branch can be made to a subroutine in the area $0000 to $003F with the CAL instruction. Pattern area ($0000 to $0FFF): ROM data in the area $0000 to $0FFF can be referenced as pattern data with the P instruction. Program area ($0000 to $03FF (HD404081 HD404081, HD40A4081 HD40A4081, HD40C4081 HD40C4081), ($0000 to $07FF (HD404372 HD404372, HD40A4372 HD40A4372, HD40C4372 HD40C4372, HD404382 HD404382, HD40A4382 HD40A4382, HD40C4382 HD40C4382, HD404082 HD404082, HCD404082 HCD404082, HD40A4082 HD40A4082, HD40C4082 HD40C4082, HCD40C4082 HCD40C4082), ($0000 to $0FFF (HD404374 HD404374, HD40A4374 HD40A4374, HD40C4374 HD40C4374, HD404384 HD404384, HD40A4384 HD40A4384, HD40C4384 HD40C4384, HD407A4374 HD407A4374, HD407C4374 HD407C4374, HD407A4384 HD407A4384, HD407C4384 HD407C4384, HD404084 HD404084, HCD404084 HCD404084, HD40A4084 HD40A4084, HD40C4084 HD40C4084, HCD40C4084 HCD40C4084), ($0000 to $1FFF (HD404388 HD404388, HD40A4388 HD40A4388, HD40C4388 HD40C4388), ($0000 to $3FFF (HD404389 HD404389, HD40A4389 HD40A4389, HD40C4389 HD40C4389, HD407A4389 HD407A4389, HD407C4389 HD407C4389). 23 HD404374/HD404384/HD404389/HD404082/HD404084 Series ROM address $0000 $000F $0010 ROM address $0000 Vector addresses (16 words) $0001 $0002 Zero page subroutine area (64 words) $003F $0040 $03FF $0400 $0003 Pattern and program area (1,024 words) *1 $0005 Pattern and program area (2,048 words) *2 $0004 $0008 $0009 $07FF $0800 $000A $000B $000C Pattern and program area (4,096 words) *3 $000D $000E $000F JMPL instruction (Jump to reset routine) JMPL instruction (Jump to WU0 routine) JMPL instruction (Jump to INT0 routine) JMPL instruction (Jump to timer A routine) JMPL instruction (Jump to timer B routine) JMPL instruction (Jump to timer C routine) JMPL instruction (Jump to A/D or serial interface routine) $0FFF $1000 Pattern and program area (8,192 words) *4 $1FFF $2000 Notes: *1 HD404081 HD404081, HD40A4081 HD40A4081, HD40C4081 HD40C4081 *2 HD40372 HD40372, HD40A4372 HD40A4372, HD40C4372 HD40C4372, HD404382 HD404382, HD40A4382 HD40A4382, HD40C4382 HD40C4382, HD404082 HD404082, HCD404082 HCD404082, HD40A4082 HD40A4082, HD40C4082 HD40C4082, HCD40C4082 HCD40C4082 *3 HD404374 HD404374, HD40A4374 HD40A4374, HD40C4374 HD40C4374, HD404384 HD404384, HD40A4384 HD40A4384, HD40C4384 HD40C4384, HD407A4374 HD407A4374, HD407C4374 HD407C4374, HD407A4384 HD407A4384, HD407C4384 HD407C4384, HD404084 HD404084, HCD404084 HCD404084, HD40A4084 HD40A4084, HD40C4084 HD40C4084, HCD40C4084 HCD40C4084 *4 HD404388 HD404388, HD40A4388 HD40A4388, HD40C4388 HD40C4388 *5 HD404389 HD404389, HD40A4389 HD40A4389, HD40C4389 HD40C4389, HD407A4389 HD407A4389, HD407C4389 HD407C4389 Pattern and program area (16,384 words) *5 $3FFF Figure 1 ROM Memory Map RAM Memory Map The MCU has on-chip RAM comprising a memory register area, data area, and stack area. In addition to these areas, an interrupt control bit area, special register area, and register flag area are mapped onto RAM memory space as a RAM-mapped register area.The RAM memory map is shown in figure 2 and described below. After power supply has been connected, regardless of a reset, the values for the memory register, data and stack areas will be undefined. Make sure to initialize prior to use. 24 HD404374/HD404384/HD404389/HD404082/HD404084 Series HD404374 HD404374 Series HD404384 HD404384 Series HD404389 HD404389 Series $000 HD404082 HD404082 Series RAM­mapped register area $03F $040 $04F $050 HD404084 HD404084 Series $000 Memory register (MR) area (16 digits) $000 RAM­mapped register area $03F $040 $04F $050 Memory register (MR) area (16 digits) $03F $040 $04F $050 Memory register (MR) area (16 digits) Not used Not used Not used $08F $090 RAM­mapped register area $08F $090 $08F $090 Data (48 digits) $0BF $0C0 Data (176 digits) $000 $001 $002 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 Interrupt control bit area Speed Select Reg. Miscellaneous Reg. (SSR) (MIS) W W (PMR0) (PMR1) (PMR2) (PMR3) W W W W Not used Port Mode Reg.0 Port Mode Reg.1 Port Mode Reg.2 Port Mode Reg.3 Not used Module Standby Reg.1 (MSR1) Module Standby Reg.2 (MSR2) Timer Mode Reg.A (TMA) Timer Mode Reg.B1 (TMB1) Timer Mode Reg.B2 (TMB2) (TRBL/TWBL) Timer-B (TRBU/TWBU) Timer Mode Reg.C1 (TMC1) Timer Mode Reg.C2 (TMC2) (TRCL/TWCL) Timer-C (TRCU/TWCU) W W W W W R/W R/W W W R/W R/W *1 *1 Not used $01F $020 Register flag area Data (432 digits) $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C $13F $140 Not used $23F $240 Serial Mode Reg.1 Serial Mode Reg.2 Serial Data Reg.Lower Serial Data Reg.Upper A/D Mode reg. A/D Data Reg.Lower A/D Data Reg.Middle A/D Data Reg.Upper Not used $3BF $3C0 $3BF $3C0 $3BF $3C0 *2 *2 *2 *2 Not used $02F $030 $031 $032 $033 $034 $035 $036 $037 Not used (SMR1) W (SMR2) W (SRL) R/W (SRU) R/W (AMR) W (ADRL) R (ADRM) R (ADRU) R Port D0~D3 DCR Port D4~D7 DCR Port D8~D9 DCR (DCD0) (DCD1) (DCD2) W W W (DCR0) (DCR1) (DCR2) W W W (DCR7) W Not used Port R0 DCR Port R1 DCR Port R2 DCR Not used Stack area Stack area Stack area (64 digits) (64 digits) $03A $03B $03C (64 digits) Port R7 DCR Not used $03F $3FF $3FF Notes: R W : Read : Write R/W : Read/Write *1 Two registers are mapped onto $3FF $012 $013 Timer Read Reg.B Lower Timer Read Reg.B Upper (TRBL) (TRBU) R R Timer Write Reg.B Lower Timer Write Reg.B Upper (TWBL) W (TWBU) W $016 $017 Timer Read Reg.C Lower Timer Read Reg.C Upper (TRCL) (TRCU) R R Timer Write Reg.C Lower Timer Write Reg.C Upper (TWCL) W (TWCU) W the same address ($012, $013, $016, $017). *2 Applies to HD404374 HD404374, HD404384 HD404384, and HD404389 HD404389 Series. Figure 2 RAM Memory Map 25 HD404374/HD404384/HD404389/HD404082/HD404084 Series RAM-mapped register area ($000 to $03F): · Interrupt control bit area ($000 to $003) This area consists of bits used for interrupt control. Its configuration is shown in figure 3. Individual bits can only be accessed by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, TM/TMD). There are restrictions on access to certain bits. The individual bits and instruction restrictions are shown in figure 4. · Special register area ($004 to $01F, $024 to $03F) This area comprises mode registers and data registers for external interrupts, the serial interface, timers, A/D converter, etc., and I/O pin data control registers. Its configuration is shown in figures 2 and 5. These registers are of three kinds: write-only (W), read-only (R), and read/write (R/W). RAM bit manipulation instructions cannot be used on the other registers. · Register flag area ($020 to $023) This area consists of the DTON and WDON flags and interrupt control bits. Its configuration is shown in figure 3. Individual bits can only be accessed by RAM bit manipulation instructions (SEM/SEMD, REM/REMD, TM/TMD). There are restrictions on access to certain bits. The individual bits and instruction restrictions are shown in figure 4. Memory register (MR) area ($040 to $04F): In this data area, the 16 memory register digits (MR(0) to MR(15) can also be accessed by the registerregister instructions LAMR and XMRA. The configuration of this area is shown in figure 6. Data area ($090 to $23F (HD404374 HD404374, HD404384 HD404384, HD404389 HD404389 Series) ($090 to $0BF (HD404082 HD404082 Series) ($090 to $13F (HD404084 HD404084 Series) Stack area ($3C0 to $3FF): This is the stack area used to save the contents of the program counter (PC), status flag (ST), and carry flag (CA) when a subroutine call (CAL or CALL instruction) or interrupt handling is performed. As four digits are used for one level, the area can be used as a subroutine stack with a maximum of 16 levels. The saved data and saved status information are shown in figure 6. The program counter is restored by the RTN and RTNI instructions. The status and carry flags are restored by the RTNI instruction, but are not affected by the RTN instruction. Any part of the area not used for saving can be used as a data area. 26 HD404374/HD404384/HD404389/HD404082/HD404084 Series $000 Bit 3 IMWU (WU0 interrupt mask) Bit 2 IFWU (WU0 interrupt request flag) $001 Not used Not used IMTB (Timer B interrupt mask) IMAD *2 (A/D converter interrupt mask) Bit 1 RSP (Stack pointer reset) Bit 0 IE (Interrupt enable flag) IFTB (Timer B interrupt request flag) IFAD *2 (A/D converter interrupt request flag) IM0 (INT0 interrupt mask) IMTA (Timer A interrupt mask) IMTC (Timer C interrupt mask) IF0 (INT0 interrupt request flag) IFTA (Timer A interrupt request flag) IFTC (Timer C interrupt request flag) DTON *1 (DTON flag) ADSF *2 (A/D start flag) WDON (Watchdog on flag) LSON *1 (Low speed on flag) $021 GEF (Gear enable flag) Not used Not used Not used $022 Not used Not used Not used Not used $023 IMS (Serial interrupt mask) IFS (Serial interrupt request flag) Not used Not used RAM address $002 $003 $020 IF IM IE SP : Interrupt Request Flag : Interrupt Mask : Interrupt Enable Flag : Stack Pointer Notes: *1 Applies to HD404374 HD404374 Series. *2 Applies to HD404374 HD404374, HD404384 HD404384, and HD404389 HD404389 Series. Figure 3 Interrupt Control Bit and Register Flag Area Configuration 27 HD404374/HD404384/HD404389/HD404082/HD404084 Series Bits in the interrupt control bit area and register flag area can be set and reset by the SEM or SEMD instruction and the REM or REMD instruction, and tested by the TM or TMD instruction. They are not affected by any other instructions. The following restrictions apply to individual bits. SEM/SEMD REM/REMD TM/TMD Allowed Allowed Allowed Not executed Allowed Allowed GEF Allowed Allowed RSP Not executed Allowed Inhibited Inhibited Allowed Not executed Inhibited Allowed Inhibited Allowed Allowed Allowed Not executed Inhibited IE IM LSON *1 IF ICSF ICEF WDON ADSF *2 DTON *1 Not Used Not executed in active mode Used in subactive mode Not executed Notes : The WDON bit is reset only by stop mode clearance by means of an MCU reset. Do not use the REM or REMD instruction on the ADSF bit during A/D conversion. The DTON bit is always in the reset state in active mode. If the TM or TMD instruction is used on a bit for which its use is prohibited, or on a nonexistent bit, the status flag value will be undetermined * 1 Applies to HD404374 HD404374 Series. * 2 Applies to HD404374 HD404374, HD404384 HD404384, and HD404389 HD404389 Series. Figure 4 Instruction Restrictions 28 HD404374/HD404384/HD404389/HD404082/HD404084 Series RAM address SSR MIS PMR0 PMR1 PMR2 PMR3 MSR1 MSR2 TMA TMB1 TMB2 TRBL/TWBL TRBU/TWBU TMC1 TMC2 TRCL/TWCL TRCU/TWCU $000 $003 $004 $005 $006 $007 $008 $009 $00A $00B $00C $00D $00E $00F $010 $011 $012 $013 $014 $015 $016 $017 $018 Bit 3 Bit 2 Bit 1 Bit 0 Interrupt control bit area *1 32 kHz oscillation stop setting 32 kHz frequency division*1 ratio selection Pull-up MOS control Not used System clock selection *1 System clock frequency division ratio switching Interrupt frame period selection *1 Not used Not used D0/INT0 Not used R00/WU0 R00/WU0 Not used R13/TOB R13/TOB R10/EVNB R10/EVNB R20/TOC R20/TOC R22/SI/SO R22/SI/SO R21/SCK R21/SCK Not used Timer B lock on/off Timer C clock on/off Not used Serial clock on/off A/D clock on/off *2 Not used Timer A / time base Timer A clock source selection Reload on/off Timer B clock source selection Timer B output mode setting EVNB edge detection selection Not used Timer B register (lower) Timer B register (upper) Timer C clock source selection Reload on/off Time C output mode selection Not used Not used Timer C register (lower) Timer C register (upper) Not used SMR1 SMR2 SRL SRU AMR ADRL ADRM ADRU $01F $020 $023 $024 $025 $026 $027 $028 $029 $02A $02B $02C Register flag area Serial transfer clock speed selection Not used Not used SO idle H/L setting Serial data register (lower) Serial data register (upper) Analog channel selection *2 A/D conversion time *2 A/D data register (bit 1, 0) *2 Not used A/D data register (bit 5 to 2) *2 A/D data register (bit 9 to 6) *2 R22/SI/SO R22/SI/SO PMOS control Not used DCD0 DCD1 DCD2 DCR0 DCR1 DCR2 $02F $030 $031 $032 $033 $034 $035 $036 $037 PortD3DCR PortD2DCR PortD1DCR PortD6DCR PorD5DCR PortD7DCR Not used PortD9DCR Not used Not used Not used PortR13DCR Not used PortR22DCR PortR21DCR PortD0DCR PortD4DCR PortD8DCR PortR00DCR PortR10DCR PortR20DCR Not used $03A DCR7 $03B $03C PortR73DCR PortR72DCR PortR71DCR PortR70DCR Not used $03F Notes: *1 Applies to HD404374 HD404374 Series. *2 Applies to HD404374 HD404374, HD404384 HD404384, and HD404389 HD404389 Series. Figure 5 Special Function Register Area 29 HD404374/HD404384/HD404389/HD404082/HD404084 Series $040 $041 $042 $043 $044 $045 $046 $047 $048 $049 $04A $04B $04C $04D $04E $04F MR (0) MR (1) MR (2) MR (3) MR (4) MR (5) MR (6) MR (7) MR (8) MR (9) MR (10) MR (11) MR (12) MR (13) MR (14) MR (15) (a) Memory registers 960 Level Level Level Level Level Level Level Level Level Level Level Level Level Level Level 1,023 Level 16 $3C0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 $3FF Bit 3 Bit 2 Bit 1 Bit 0 1020 ST PC13 PC12 PC11 $3FC 1021 PC10 PC9 PC8 PC7 $3FD 1022 CA PC6 PC5 PC4 $3FE 1023 PC3 PC2 PC1 PC0 $3FF (b) Stack area PC13 to PC0 ST CA : Program counter : Status flag : Carry flag Figure 6 Configuration of Memory Registers and Stack Area, and Stack Position 30 HD404374/HD404384/HD404389/HD404082/HD404084 Series Functional Description Registers and Flags The MCU has nine registers and two flags for CPU operations. they are shown in figure 7 and described below. 3 Accumulator 0 (A) Initial value: Undefined, R/W 3 B register 0 (B) Initial value: Undefined, R/W 1 W register (W) Initial value: Undefined, R/W 3 X register 0 (X) Initial value: Undefined, R/W 3 Y register 0 (Y) Initial value: Undefined, R/W 3 SPX register 0 (SPX) Initial value: Undefined, R/W 3 SPY register Carry flag Status flag Program counter Initial value: $0000, no R/W 0 (SPY) Initial value: Undefined, R/W Initial value: Undefined, R/W 0 (CA) Initial value: 1, no R/W 0 (ST) 13 0 (PC) 9 Stack pointer Initial value: $3FF, no R/W 0 5 1 1 1 1 0 (SP) Figure 7 Registers and Flags Accumulator (A) and B register (B): The accumulator and B register are 4-bit registers used to hold the result of an ALU operation, and for data transfer to or from memory, an I/O area, or another register. 31 HD404374/HD404384/HD404389/HD404082/HD404084 Series W register (W), X register (X) and Y register (Y): The W register is a 2-bit register, and the X and Y registers are 4-bit registers, used for RAM register indirect addressing. The Y register is also used for D port addressing. SPX register (SPX) and SPY register (SPY): The SPX and SPY registers are 4-bit registers used as X register and Y register auxiliary registers, respectively. Carry flag (CA): This flag holds ALU overflow when an arithmetic/logic instruction is executed. It is also affected by the SEC, REC, ROTL, and ROTR instructions. The contents of the carry flag are saved to the stack when interrupt handling is performed, and are restored from the stack by the RTNI instruction (but are not affected by the RTN instruction). Status flag (ST): This flag holds ALU overflow when an arithmetic/logic or compare instruction is executed, and the result of an ALU non-zero or bit test instruction. It is used as the branch condition for the BR, BRL, CAL, and CALL instructions. The status flag is a latch-type flag, and does not change until the next arithmetic/logic, compare, or bit test instruction is executed. After a BR, BRL, CAL, or CALL instruction, the status flag is set to 1 regardless of whether the instruction is executed or skipped. The contents of the status flag are saved to the stack when interrupt handling is performed, and are restored from the stack by the RTNI instruction (but are not affected by the RTN instruction). Program counter (PC): This is a 14-bit binary counter that holds ROM address information. Stack pointer (SP): The stack pointer is a 10-bit register that holds the address of the next save space in the stack area. The stack pointer is initialized to $3FF by an MCU reset. The stack pointer is decremented by 4 each time data is saved, and incremented by 4 each time data is restored. The upper 4 bits of the stack pointer are fixed at 1111, so that a maximum of 16 stack levels can be used. There are two ways in which the stack pointer is initialized to $3FF: by an MCU reset as mentioned above, or by resetting the RSP bit with the REM or REMD instruction. Reset An MCU reset is performed by driving the RESET pin low. At power-on, and when subactive mode, watch mode, or stop mode is cleared, RESET should be input for at least tRC to provide the oscillation settling time for the oscillator.In other cases, the MCU is reset by inputting RESET for at least two instruction cycles. Table 1 shows the areas initialized by an MCU reset, and their initial values. 32 HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 1 (1) Initial Values after MCU Reset Abbr. Initial value Contents Program counter (PC) $0000 Program executed from ROM start address Status flag (ST) 1 Branching by conditional branch instruction enabled Stack pointer (SP) $3FF Stack level is 0 Interrupt (IE) 0 All interrupts disabled Item Interrupt enable flag flags/ mask Interrupt request flag No interrupt requests 1 Interrupt requests masked Port data register (PDR) All bits 1 "1" level output possible (DCD0 ~ 2) All bits 0 Output buffer off (high impedance) Data control registers (DCR00 DCR00 , DCR10 DCR10, DCR13 DCR13, DCR20 DCR20 ­ DCR22 DCR22, DCR70 DCR70 ­ DCR73 DCR73) All bits 0 Port mode register 0 (PMR0) -0 See port mode register 0 section Port mode register 1 (PMR1) -0 See port mode register 1 section Port mode register 2 (PMR2) 0-0 See port mode register 2 section Port mode register 3 Timers 0 (IM) Data control registers I/O (IF) Interrupt mask (PMR3) 0000 See port mode register 3 section Timer mode register A (TMA) 0000 See timer mode register A section Timer mode register B1 (TMB1) 0000 See timer mode register B1 section Timer mode register B2 (TMB2) -000 See timer mode register B2 section Timer mode register C1 (TMC1) 0000 See timer mode register C1 section Timer mode register C2 (TMC2) -0- See timer mode register C2 section Prescaler S (PSS) $000 Prescaler W (PSW) $00 Timer/counter A (TCA) $00 Timer/counter B (TCB) $00 Timer/counter C (TCC) $00 Timer write register B (TWBU,L) $X0 Timer write register C (TWCU,L) $X0 33 HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 1 (2) Initial Values after MCU Reset Abbr. Initial value Contents Serial mode register 1 (SMR1) 0000 See serial mode register 1 section Serial mode register 2 (SMR2) -0X- See serial mode register 2 section Serial data register (SRU,L) Item Serial interface Octal counter A/D converter $XX 000 0000 See A/D mode register section (ADRU) 0111 See A/D data register section A/D data register M (ADRM) 1111 A/D data register L (ADRL) 11- - Low speed on flag (LSON) 0 See low-power mode section Watchdog timer on flag (WDON) 0 See timer C section A/D start flag (ADSF) 0 See A/D converter section Direct transfer on flag (DTON) 0 See low-power mode section Gear enable flag (GEF) 0 See system clock gear function Miscellaneous register (MIS) 0-00 See low-power mode and input/output sections System clock select register (SSR) 0000 See low-power mode and oscillator circuit sections Module standby register 1 (MSR1) -00 See timer section Module standby register 2 (MSR2) Others (AMR) A/D data register U Bit registers A/D mode register -00 See serial interface and A/D converter sections Notes: 1. The state of registers and flags other than those listed above after an MCU reset is shown in table 1 (3). 2. X: Indicates invalid value, - indicates that the bit does not exist. Table 1 (3) Initial Values after MCU Reset Item Abbr. After Stop Mode Clearance by WU0 After Other MCU Reset Carry flag (CA) Accumulator (A) Retain value immediately prior to entering stop mode Value immediately prior to MCU reset is not guaranteed. Must be initialized by program. B register (B) W register (W) X/SPX register (X/SPX) Y/SPY register (Y/SPY) RAM 34 HD404374/HD404384/HD404389/HD404082/HD404084 Series Interrupts There are a total of seven interrupt sources, comprising wakeup input (WU0), external interrupts (INT0), timer/counter (timer A, timer B, timer C) interrupts, a serial interface interrupt, and an A/D converter interrupt. Each interrupt source is provided with an interrupt request flag, interrupt mask, and vector address, used for storing and controlling interrupt requests. In addition, an interrupt enable flag is provided to control interrupts as a whole. Of the interrupt sources, the A/D converter and serial interface share the same vector address. Software must therefore determine which of the interrupt sources is requesting an interrupt at the start of interrupt handling. Interrupt control bits and interrupt handling: The interrupt control bits are mapped onto RAM addresses $000 to $003 and $023, and can be accessed by RAM bit manipulation instructions. However, the interrupt request flags (IF) cannot be set by software. When the MCU is reset, the interrupt enable flag (IE) and interrupt request flags (IF) are initialized to 0, and the interrupt masks (IM) are initialized to 1. Figure 8 shows a block diagram of the interrupt control circuit, table 2 shows interrupt priorities and vector addresses, and table 3 lists the conditions for executing interrupt handling for each of the nine kinds of interrupt source. When the interrupt request flag is set to 1 and the interrupt mask is cleared to 0, an interrupt is requested. If the interrupt enable flag is set to 1 at this time, interrupt handling is started. The vector address corresponding to the interrupt source is generated by the priority control circuit. The interrupt handling sequence is shown in figure 9, and the interrupt handling flowchart in figure 10. When an interrupt is accepted, execution of the previous instruction is completed in the first cycle. In the second cycle, the interrupt enable flag (IE) is reset. In the second and third cycles, the contents of the carry flag, status flag, and program counter are saved on the stack. In the third cycle, a jump is made to the vector address and instruction execution is resumed from that address. In each vector address area, a JMPL instruction should be written that branches to the start address of the interrupt routine. In the interrupt routine, the interrupt request flag that caused interrupt handling must be reset by software. 35 HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 2 Vector Addresses and Interrupt Priorities Interrupt Source Priority Vector Address RESET - $0000 WU0 1 $0002 INT0 2 $0004 Timer A 3 $0008 Timer B 4 $000A Timer C 5 $000C Serial interface, A/D converter 6 $000E 36 HD404374/HD404384/HD404389/HD404082/HD404084 Series $000,0 I/E Interrupt request $000,2 (WU0 interrupt) IFWU $000,3 IMWU $001,0 (INT0 interrupt) Priority control circuit Vector address IF0 $001,1 IM0 $002,0 (Timer A interrupt) IFTA $002,1 IMTA $002,2 (Timer B interrupt) IFTB $002,3 IMTB $003,0 (Timer C interrupt) IFTC $003,1 IMTC $003,2 (A/D interrupt) $023,2 IFAD IFS $003,3 $023,3 IMAD IMS (Serial interrupt) Figure 8 Block Diagram of Interrupt Control Circuit 37 HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 3 Interrupt Processing and Activation Conditions Interrupt Source Interrupt Control Bit WU0 INT0 Timer A Timer B Timer C A/D or Serial IE 1 1 1 1 1 1 IFWU·IMWU 1 0 0 0 0 0 IF0·IM0 * 1 0 0 0 0 IFTA·IMTA * * 1 0 0 0 IFTB·IMTB * * * 1 0 0 IFTC·IMTC * * * * 1 0 IFAD·IMAD+IFS·IMS * * * * * 1 Note: Operation is not affected whether the value is 0 or 1. Instruction cycle 1 2 3 4 5 6 Instruction execution* Interrupt acceptance Save to stack IE reset Save to stack Vector address generated Execution of JMPL instruction at vector address Execution of instruction at start address of interrupt routine Note: The stack is accessed and the IE reset after the instruction is executed, even if it is a 2cycle instruction. Figure 9 Interrupt Sequence 38 HD404374/HD404384/HD404389/HD404082/HD404084 Series Power ON RESET="0"? No Yes Interrupt request? Yes No IE="1"? Yes Execute instruction Accept interrupt Reset MCU IE"0" Stack(PC) Stack(CA) Stack(ST) PC(PC)+1 PC$0002 Yes WU0 interrupt? No PC$0004 Yes INT0 interrupt? No PC$0008 Yes Timer A interrupt? No PC$000A Yes Timer B interrupt? No PC$000C Yes Timer C interrupt? No PC$000E (A/D, serial interrupt) Figure 10 Interrupt Handling Flowchart 39 HD404374/HD404384/HD404389/HD404082/HD404084 Series Interrupt enable flag (IE: $000,0): The interrupt enable flag controls interrupt enabling/disabling of all interrupt requests as shown in table 4. The interrupt enable flag is reset by interrupt handling and set by the RTNI instruction. Table 4 Interrupt Enable Flag (IE: $000,0) Interrupt Enable Flag (IE) Interrupt Enabling/Disabling 0 Interrupts disabled 1 Interrupts enabled Wakeup interrupt request flag (IFWU: $000,2): The wakeup interrupt request flag (IFWU) is set by the detection of a falling edge in WU0 input in active mode, subactive mode,watch mode, or standby mode. In stop mode, when a falling edge is detected at the wakeup pin, the MCU waits for the oscillation settling time, then switches to active mode. When a transition is made from stop mode to active mode with IE set to 1 and IMWU cleared to 0, wakeup interrupt handling is executed after the switch to active mode. The wakeup interrupt request flag (IFWU) is not set in this case (table 5). Table 5 Wakeup Interrupt Request Flag (IFWU: $000,2) Wakeup Interrupt Request Flag (IFWU) Interrupt Request 0 No wakeup interrupt request 1 Wakeup interrupt request generated Wakeup Interrupt Mask (IMWU: $000,3): This bit masks an interrupt request by the wakeup interrupt request flag (table 6). Table 6 Wakeup Interrupt Request Mask (IMWU: $000,3) Wakeup Interrupt Mask (IMWU) Interrupt Request 0 Wakeup interrupt request enabled 1 Wakeup interrupt request masked (held pending) 40 HD404374/HD404384/HD404389/HD404082/HD404084 Series External interrupt request flag (IF0: $001, 0): The external interrupt request flag is set by an INT0 input falling edge (table 7). Table 7 External Interrupt Request Flag (IF0: $001, 0) External Interrupt Request Flag (IF0) Interrupt Request 0 No external interrupt request 1 External interrupt request generated External interrupt mask (IM0: $001, 1): This bit masks an interrupt request by the external interrupt request flag (table 8). Table 8 External Interrupt Mask (IM0: $001, 1) External Interrupt Mask (IM0) Interrupt Request 0 External interrupt request enabled 1 External interrupt request masked (held pending) Timer A interrupt request flag (IFTA: $002,0): The timer A interrupt request flag is set by timer A overflow output (table 9). Table 9 Timer A Interrupt Request Flag (IFTA: $002,0) Timer A Interrupt Request Flag (IFTA) Interrupt Request 0 No timer A interrupt request 1 Timer A interrupt request generated Timer A interrupt mask (IMTA: $002,1): This bit masks an interrupt request by the timer A interrupt request flag (table 10). Table 10 Timer A Interrupt Mask (IMTA: $002,1) Timer A Interrupt Mask (IMTA) Interrupt Request 0 Timer A interrupt request enabled 1 Timer A interrupt request masked (held pending) 41 HD404374/HD404384/HD404389/HD404082/HD404084 Series Timer B interrupt request flag (IFTB: $002,2): The timer B interrupt request flag is set by timer B overflow output (table 11). Table 11 Timer B Interrupt Request Flag (IFTB: $002,2) Timer B Interrupt Request Flag (IFTB) Interrupt Request 0 No timer B interrupt request 1 Timer B interrupt request generated Timer B interrupt mask (IMTB: $002,3): This bit masks an interrupt request by the timer B interrupt request flag (table 12). Table 12 Timer B Interrupt Mask (IMTB: $002,3) Timer B Interrupt Mask (IMTB) Interrupt Request 0 Timer B interrupt request enabled 1 Timer B interrupt request masked (held pending) Timer C interrupt request flag (IFTC: $003,0): The timer C interrupt request flag is set by timer C overflow output (table 13). Table 13 Timer C Interrupt Request Flag (IFTC: $003,0) Timer C Interrupt Request Flag (IFTC) Interrupt Request 0 No timer C interrupt request 1 Timer C interrupt request generated (held pending) Timer C interrupt mask (IMTC: $003,1): This bit masks an interrupt request by the timer C interrupt request flag (table 14). Table 14 Timer C Interrupt Mask (IMTC: $003,1) Timer C Interrupt Mask (IMTC) Interrupt Request 0 Timer C interrupt request enabled 1 Timer C interrupt request masked (held pending) 42 HD404374/HD404384/HD404389/HD404082/HD404084 Series Serial interrupt request flag (IFS: $023,2): The serial interrupt request flag is set on completion of serial data transfer, or if data transfer is halted midway (table 15). Table 15 Serial Interrupt Request Flag (IFS: $023,2) Serial Interrupt Request Flag (IFS) Interrupt Request 0 No serial interrupt request 1 Serial interrupt request generated Serial interrupt mask (IMS: $023,3): This bit masks an interrupt request by the serial interrupt request flag (table 16). Table 16 Serial Interrupt Mask (IMS: $023,3) Serial Interrupt Mask (IMS) Interrupt Request 0 Serial interrupt request enabled 1 Serial interrupt request masked (held pending) A/D interrupt request flag (IFAD: $003,2) (Applies to HD404374 HD404374, HD404384 HD404384, and HD404389 HD404389 Series): The A/D interrupt request flag is set on completion of A/D conversion (table 17). Table 17 A/D Interrupt Request Flag (IFAD: $003,2) A/D Interrupt Request Flag (IFAD) Interrupt Request 0 No A/D interrupt request 1 A/D interrupt request generated A/D interrupt mask (IMAD: $003,3) (Applies to HD404374 HD404374, HD404384 HD404384, and HD404389 HD404389 Series): This bit masks an interrupt request by the A/D interrupt request flag (table 18). Table 18 A/D Interrupt Mask (IMAD: $003,3) Serial Interrupt Mask (IMAD) Interrupt Request 0 A/D interrupt request enabled 1 A/D interrupt request masked (held pending) 43 HD404374/HD404384/HD404389/HD404082/HD404084 Series Operating Modes The five operating modes shown in table 19 can be used for the MCU. The function of each mode is shown in table 20, and the state transition diagram among each mode in figure 11. Table 19 Operating Modes and Clock Status Mode Name Stop Watch*1 Subactive*1, 3 SBY RESET cancellation, instruction interrupt request, WU0 input in stop mode STOP/SBY instruction in subactive mode (when direct transfer is selected) STOP instruction when TMA3 = 0 STOP instruction when TMA3 = 1 INT0/timer A or WU0 interrupt request in watch mode OP Stopped Stopped Stopped OP OP Active Activation method Status System oscillator 1 Subsystem oscillator* OP Cancellation method RESET input, STOP/SBY instruction Standby OP 2 OP OP* RESET input, interrupt request RESET input, WU0 input RESET input, RESET STOP/SBY input, INT0/timer A instruction or WU0 interrupt request Notes: OP: implies in operation. 1. Applies to HD404374 HD404374 Series. 2. Operating or stopping the oscillator can be selected by setting bit 3 of the system clock select register (SSR: $004) 3. Subactive mode is an optional function; specify it on the fnction option list. 44 HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 20 Operation in Low-Power Dissipation Modes Function Stop Mode Watch mode*1 Standby Mode Subactive Mode*1, 3 CPU Retained Retained Retained OP RAM Retained Retained Retained OP Timer A Stopped OP OP OP Timer B Stopped Stopped OP OP Timer C Stopped OP OP OP OP Serial interface 4 Stopped * Stopped 2 Stopped * 2 A/D * Stopped Stopped OP Stopped I/O Retained Retained Retained OP Notes: OP: implies in operation. 1. Applies to HD404374 HD404374 Series. 2. Transmission/Reception is activated if a clock is input in external clock mode. However, interrupts stop. 3. Subactive mode is an optional function specified on the function option list. 4. Applies to HD404374 HD404374, HD404384 HD404384, and HD404389 HD404389 Series. 45 HD404374/HD404384/HD404389/HD404082/HD404084 Series Reset by RESET pin input or watchdog timer Stop mode (TMA3=0,SSR3=0,LSON=0) fosc fx øCPU øCLK øPER Reset Standby mode fosc fx øCPU øCLK øPER : Active : Active : Stop : fcyc : fcyc : Stop : Active : Stop : Stop : Stop WU0 Active mode SBY instruction fosc fx øCPU øCLK øPER interrupt : Active : Active : fcyc : fcyc : fcyc (TMA3=0,SSR3=1,LSON=0) STOP instruction fosc : Stop fx : Stop WU0 øCPU : Stop øCLK : Stop STOP øPER : Stop instruction (TMA3=0) *4 fosc fx øCPU øCLK øPER : Active : Active : Stop : fw : fcyc Subactive mode (TMA3=1) SBY instruction fosc fx øCPU øCLK øPER interrupt : Active : Active : fcyc : fw : fcyc fosc fx øCPU øCLK øPER *1 : Stop : Active : fSUB : fw : fSUB STOP instruction *2 Timer A, WU0 or INT0 interrupt STOP instruction Timer A, WU0 or INT0 interrupt *3 Watch mode fosc : Main oscillator frequency fx : Sub-oscillator frequency (for realtime clock) fcyc : fOSC/32 or fOSC/4 (selected by software) fw : fx/8 fSUB : fx/8 or fx/4 (selected by software) øCPU : System clock øCLK : Clock for realtime clock øPER : Peripheral function clock LSON : Low speed on flag DTON : Direct transfer on flag TMA3 : Timer mode register A bit3 fosc fx øCPU øCLK øPER : Stop : Active : Stop : fw : Stop (TMA3=1,LSON=0) : Stop : Active : Stop : fw : Stop (TMA3=1,LSON=1) Transition Condition DTON LSON TMA3 *1 STOP/SBY instruction 1 0 1 *2 STOP/SBY instruction 0 0 1 *3 STOP/SBY instruction Don't care 1 1 *4 STOP/SBY instruction 0 0 0 Note: Watch mode and subactive mode apply to HD404374 HD404374 Series. Figure 11 MCU Status Transitions 46 fosc fx øCPU øCLK øPER HD404374/HD404384/HD404389/HD404082/HD404084 Series Active mode: In active mode all functions operate. In this mode, the MCU operates on clocks generated by the OSC1 and OSC2 oscillator circuits. Standby mode: In standby mode the oscillators continue to operate but clocks relating to instruction execution halt. As a result, CPU operation stops, and registers, RAM, and the D port/R port set for output retain their state immediately prior to entering standby mode. Interrupts, timers, the serial interface, and other peripheral functions continue to operate. Power consumption is lower than in active mode due to the halting of the CPU. The MCU is switched to standby mode by executing the SBY instruction in active mode. Standby mode is cleared by RESET input or an interrupt request. When standby mode is cleared by RESET input, an MCU reset is performed. When standby mode is cleared by an interrupt request, the MCU enters active mode and executes a instruction following the SBY instruction. After executing the instruction, if the interrupt enable flag is set to 1, interrupt handling is executed; if the interrupt enable flag is cleared to 0, the interrupt request is held pending and normal instruction execution is continued. MCU operation flowchart is shown in figure 12. 47 HD404374/HD404384/HD404389/HD404082/HD404084 Series Stop mode No RESET=0? No RESET=0? Yes Yes No WU0 = Watch mode*1 Standby mode IFWU·IMWU =1? No Yes ? IF0·IM0 = 1? Yes No Yes IFTA · IMTA = 1? No Yes No IFTB · IMTB = 1? Yes*2 IFTC· IMTC = 1? System clock oscillator started No Yes*2 System reset IFAD·IMAD+ IFS·IMS = 1? Yes*2 System clock oscillator started Next Instruction execution NOP Notes: 1. Applies to HD404374 HD404374 Series No 2. Only when clearing from standby mode IF = 1, IM = 0, IE = 1? Yes Next Instruction execution Interrupts enabled Figure 12 MCU Operation Flowchart 48 System clock oscillator started No HD404374/HD404384/HD404389/HD404082/HD404084 Series Stop mode: In stop mode, all MCU function stop except that states prior to entry into stop mode are retained. This mode thus has the lowest power consumption of all operating mode. In stop mode, the OSC1 and OSC2 oscillators stop. Bit 3 (SSR3) of the system clock select register (SSR: $004) (figure 22) can be used to select the active (= 0) or stopped (= 1) state for the X1 and X2 oscillators. The MCU is switched to stop mode by executing a STOP instruction while bit 3 (TMA3) of timer mode register A (TMA: $00F) (figure 33) is cleared to 0 in active mode. Stop mode is cleared by RESET or WU0 input. When stop mode is cleared by RESET, the RESET signal should be input for at least the oscillation settling time (tRC) (see "AC Characteristics") shown in figure 13. Then, the MCU is initialized and starts instruction execution from the start (address 0) of the program (IE = 0, IMWU = 0). If IE is set before entering stop mode (IE = 1, IMWU = 0), wakeup interrupt handling is executed after the transition to active mode. When the MCU detects a falling edge at WU0 in stop mode, it automatically waits for the oscillation settling time, then switches to active mode. After the transition to active mode, the MCU resumes program execution from the instruction following the STOP instruction. If stop mode is cleared by wakeup input, RAM data and registers retain their values prior to entering stop mode. Stop mode Oscillator Internal clock RESET tres STOP instruction executed (At least oscillation settling time (tRC) Figure 13 Timing Chart for Clearing Stop Mode by RESET Input Note: If stop mode is cleared by wakeup input when an external clock is used as the system clock (OSC1), the subclock should not be stopped in stop mode. Watch mode ( Applies to HD404374 HD404374 Series) : In watch mode, the realtime clock function (timer A) and LCD function using the X1 and X2 oscillators operate, but other functions stop. This mode thus has the second lowest power consumption after stop mode, and is useful for performing realtime clock display only. In watch mode, the OSC 1 and OSC2 oscillators stop but the X1 and X2 oscillators continue to operate. 49 HD404374/HD404384/HD404389/HD404082/HD404084 Series The MCU is switched to watch mode by executing a STOP instruction while TMA3 = 1 in active mode, or by executing a STOP/SBY instruction in subactive mode. Watch mode is cleared by RESET input or an INT0,timer A or WU 0 interrupt request. For RESET input, refer to the section on stop mode. When watch mode is cleared by an INT0, timer A or W U0 interrupt request, the mode transition depends on the value of the LSON bit: the MCU enters active mode if LSON = 0, and enters subactive mode if LSON = 1. In the case of a transition to active mode, interrupt request generation is delayed to secure the oscillation settling time: the delay is the tRC set time for the timer A interrupt, and, for the INT0 interrupt or WU0 interrupt, Tx (T + tRC < Tx < 2T + tRC) if bit 1 and 0 (MIS1, MIS0) of the miscellaneous register are set to 00, or Tx (tRC < Tx < T + tRC) if MIS1 and MIS0 are set to 01 or 10 (figures 14 and 15). Other operations when the transition is made are the same as when watch mode is cleared (figure 12). Subactive mode ( Applies to HD404374 HD404374 Series): In subactive mode, the OSC1 and OSC2 oscillator circuits stop and the MCU operates on clocks generated by the X1 and X2 oscillator circuits. In this mode, functions other than the A/D converter operate, but since the operating clocks are slow, power consumption is the lowest after watch mode. A CPU instruction processing speed of 244 µs or 122 µs can be selected according to whether bit 2 (SSR2) of the system clock select register (SSR: $004) is set to 1 or cleared to 0. The value of the SSR2 bit should be changed (01 or 10) only in active mode. If the value is changed in subactive mode, the MCU may operate incorrectly. Subactive mode is cleared by executing a STOP/SBY instruction. A transition is then made to either watch mode or active mode according to the value of the low speed on flag (LSON: $020,0) and the direct transfer on flag (DTON: $020,3). Subactive mode is a function option, and should be specified in the function option list. Interrupt frame ( Applies to HD404374 HD404374 Series): In watch mode and subactive mode, øCLK is supplied to the timer A, WU0, and INT0 acceptance circuits. Prescaler W and timer A operate as time bases, and generate interrupt frame timing. Either of two values can be selected for the interrupt frame period, T, by means of the miscellaneous register (MIS: $005) (figure 15). In watch mode and subactive mode, the timing for generation of timer A, INT0 and WU0 interrupts is synchronized with the interrupt frame. Except for the case of an active mode transition, the interrupt strobe timing is used for interrupt request generation. Timer A generates overflow and interrupt requests at the interrupt strobe timing. 50 HD404374/HD404384/HD404389/HD404082/HD404084 Series Oscillation stabilization period Active mode Watch mode Active mode Interrupt strobe INT0, WU0 Interrupt request generation T T Only in case of transition to active mode tRC TX T: Interrupt frame period tRC : Oscillation stabilization period Note: If the time from the fall of the INT0 or WU0 signal until the interrupt is accepted and active mode is entered and is designated TX, then TX will be in the following range : T+tRCTX2T+tRC (MIS1, MIS0=00) tRCTXT+tRC (MIS1, MIS0=01 or 10) Figure 14 Interrupt Frame Miscellaneous Register (MIS: $005) Bit 3 2 1 0 Read/Write W W W W Reset 0 0 0 0 Bit name MIS3 Not used*4 MIS1*1 See pull-up MOS control, figure 30 MIS1 0 1 MIS0*1 MIS0 0 1 0 1 Interrupt Frame Oscillation Settling period T(ms)*2 Time tRC(ms)*2 0.24414 3.90625 3.90625 Oscillator Circuit Condition 0.12207(0.24414)*3 External clock input, CR oscillation frequency 7.8125 Ceramic resonator 31.25 Crystal resonator Not used Notes: *1. Applies to HD404374 HD404374 series. *2. T and tRC values are for use of a 32.768 kHz crystal oscillator at the X1-X2 pins. *3. This value applies only in case of direct transition operation. *4. Must always be cleared to 0. Setting to 1 will cause incorrect operation. Figure 15 Miscellaneous Register (MIS) 51 HD404374/HD404384/HD404389/HD404082/HD404084 Series Direct transition from subactive to active mode (Applies to HD404374 HD404374 Series): A direct transition can be made from subactive mode to active mode by controlling the direct transfer on flag (DTON: $020,3) and low speed on flag (LSON: $020,0). The procedure is shown below. (a) Set LSON = 0 and DTON = 1 in subactive mode. (b) Execute a STOP or SBY instruction. (c) After the lapse of the MCU internal processing time and the oscillation settling time, the MCU automatically switches from subactive mode to active mode (figure 16). Notes: 1. The DTON flag ($020,3) can be set in only subactive mode. It is always in the reset state in active mode. 2. The condition for transition time TD from the subactive mode to active mode is as follows: tRC < TD < T + tRC. STOP/SBY instruction execution MCU internal processing time Subactive mode Oscillation stabilization time Active mode (Set LSON =0, DTON =1) Interrupt strobe Direct transition completion timing T tRC TD T: Interrupt frame period tRC: Oscillation settling time TD: Direct transition time Figure 16 Direct Transition Timing MCU operation sequence: The MCU operates in accordance with the flowchart shown in figure 17. RESET input is asynchronous input, and the MCU immediately enters the reset state upon RESET input, regardless of its current state. In the low-power mode operation sequence, if a STOP/SBY instruction is executed while the IE flag is cleared and the interrupt flag is set, releasing the relevant interrupt mask, the STOP/SBY instruction is canceled (regarded as NOP) and the next instruction is executed. Therefore, when executing a STOP/SBY instruction, all interrupt flags must be cleared, or interrupts masked, beforehand. 52 HD404374/HD404384/HD404389/HD404082/HD404084 Series STOP/SBY instruction IF=1 IM=0 No Yes Standby/watch mode (HD404374 HD404374 Series) No Interrupt handling routine Stop Mode IE=0 Yes No IF=1 IM=0 WU0 = No Yes Yes Clearing Standby watch mode Clearing Stop mode Hardware NOP Execution NOP PC(PC)+1 PC(PC)+2 Hardware NOP Execution PC(PC)+1 Instruction Execution Instruction Execution MCU Operation Cycle Note: See figure 12, MCU Operation Flowchart, for IF and IM operation. Figure 17 MCU Operating Sequence (Low-Power Mode Operation) 53 HD404374/HD404384/HD404389/HD404082/HD404084 Series Usage notes (Applies to HD404374 HD404374 Series): In watch mode and subactive mode, an interrupt will not be detected correctly if the INT0 or WU0 high or low-level period is shorter than the interrupt frame period. The MCU's edge sensing method is shown in figure 18. The MCU samples the INT0 and WU0 signals at regular intervals, and if consecutive sampled values change from high to low, it determines that a falling edge has been generated. Interrupt detection errors occur since this sampling is performed at the interrupt frame period. If the highlevel period of the INT0 or WU0 signal is within an interrupt frame, as shown in figure 19 (a), the signal will be low at point A and point B, with the result that the falling edge will not be recognized. Similarly, If the low-level period of the INT0 or WU0 signal is within an interrupt frame, as shown in figure 19 (b), the signal will be high at point A and point B, with the result that the falling edge will not be recognized. In watch mode and subactive mode, therefore, ensure that the high-level and low-level periods of the INT 0 and WU 0 signals is at least as long as the interrupt frame period. INT0 or WU0 Sampling High Low Low Figure 18 Edge Sensing Method (a) High-level mode (b) Low-level mode INT0 or WU0 INT0 or WU0 Interrupt frame Point A: Low Point B: Low Interrupt frame Figure 19 Sampling Examples 54 Point A: High Point B: High HD404374/HD404384/HD404389/HD404082/HD404084 Series Internal Oscillator Circuit Figure 20 shows the clock pulse generator circuit. As shown in table 21, a ceramic oscillator or crystal oscillator can be connected to OSC1 and OSC2, and a 32.768 kHz crystal oscillator can be connected to X1 and X2. External clock operation is possible for the system oscillator. CR oscillation for system oscillator is possible. CR oscillation function is optional. Set bit 1 (SSR1) of the system clock select register (SSR: $004) according to the frequency of the oscillator connected to OSC1 and OSC2 (figure 22). Note: If the setting of bit 1 in the system clock select register does not match the frequency of the system oscillator, the subsystem using 32.768 kHz oscillation will not operate correctly in the HD404374 HD404374 Series. Also, the CR oscillation frequency differs depending on the operating voltage and resistance value. Set bit 1 of the system clock select register to match the operating frequency. Note that if the frequency being used does not match the setting of bit 1 of the system clock select register, subsystems using the 32.768 kHz oscillation frequency will not operate correctly. LSON OSC2 CPU ·ROM System oscillator fOSC 1/4 or 1/32 fcyc Timing tcyc generation division circuit* circuit øCPU ·RAM · Registers, flags ·I/O System clock selection circuit OSC1 Peripheral functions Interrupts øPER X2 Sub system clock oscillator fx 1/8 or 1/4 fSUB Timing division tsubcyc generator circuit* circuit TMA3 bit X1 1/8 division circuit Timing fW twcyc generation circuit Time base clock selection circuit øCLK Timer A interrupts HD404374 HD404374 series Notes: The division ratio can be selected by setting bit 0 or bit 2 in the system clock select register (SSR:$004). Figure 20 Clock Pulse Generator Circuit 55 HD404374/HD404384/HD404389/HD404082/HD404084 Series System Clock Gear Function The MCU has a built-in system clock gear function that allows the system clock divided by 4 or by 32 to be selected by software for the instruction execution time. Efficient power consumption can be achieved by operating at the divided-by-4 rate when high-speed processing is needed, and at the divided-by-32 rate at the other times. Figure 21 shows the system clock conversion method. System clock conversion from division-by-4 to division-by-32 is performed as follows. First, make the division-by-32 setting (SSR0 write), then set the gear enable flag (GEF: $021,3). This flag is used to distinguish between gear conversion and a transition to standby mode. Next, execute an SBY instruction. When the gear enable flag is not set, standby mode is entered; when this flag is set, gear conversion mode is entered. In this case a transition is made to standby mode for the duration of the gear conversion, but after the synchronization time has elapsed, a transition is made automatically to active mode. As soon as the transition is made to active mode, the gear enable flag is reset. The same procedure is used for conversion from division-by-32 to division-by-4. Clear all interrupts, then disable interrupts, before carrying out gear conversion. Incorrect operation may result if an interrupt is generated during gear conversion. Division-by-32 setting (SSR0 = 1) Set gear enable flag Execute SBY instruction Synchronization time Execute next instruction Division-by-4 setting (SSR0 = 0) Set gear enable flag Execute SBY instruction Synchronization time Execute next instruction Figure 21 System Clock Division Ratio Conversion Flowchart 56 HD404374/HD404384/HD404389/HD404082/HD404084 Series Make sure to set bit 3 of the system clock select register to 1 if the HD404374 HD404374 series is being used without the subsystem clock, and on the HD404384 HD404384, HD404389 HD404389, HD404082 HD404082, and HD404084 HD404084 series. The microcomputer will malfunction if the setting is not 1. System clock select register (SSR: $004) Bit 3 2 1 0 Read/Write W W W W Initial value on reset 0 0 0 0 SSR3 SSR2* SSR1* SSR0 Bit name System clock division ratio switch 0 Division-by-4 (fcyc - fOSC/4) 1 Division-by-32 (fcyc - fOSC/32) System clock division ratio switch 0 fosc=0.4­1.0MHz 1 fosc=1.6­8.5MHz Subsystem clock division ratio switch 0 fSUB=fx/8 1 fSUB=fx/4 Subsystem clock stop setting (HD404374 HD404374 Series) 0 Subsystem clock operates in stop mode 1 Subsystem clock stops in stop mode This bit must be set to 1 following power-on and reset if the HD404374 HD404374 series is being used without the subsystem clock, and on the HD404384 HD404384, HD404389 HD404389, HD404082 HD404082, and HD404084 HD404084 series. If it is set to 0 (the initial value), malfunctioning may occur in the stop mode. Note: * Applies to HD404374 HD404374 Series. The CR oscillation frequency differs depending on the operating voltage and resistance value. Set SSR1 to match the operating frequency. Note that if the frequency being used does not match the SSR1 setting, subsystems using the 32.768 kHz oscillation frequency will not operate correctly. Figure 22 System Clock Select Register 57 HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 21 Oscillator Circuit Examples Circuit Structure External clock operation External oscillator Circuit Constants OSC1 Open OSC2 C1 Ceramic oscillator (OSC1, OSC 2) Ceramic oscillator: CSA4.00MG (Murata) OSC1 Ceramic oscillator Rf GND OSC2 C2 C1 Crystal oscillator (OSC1, OSC 2) Rf=1M±20% C1=C2=24pF±20% OSC1 Rf=1M±20% C1=C2=10­20pF±20% Crystal oscillator Rf GND OSC2 C2 4 CR oscillator* (OSC1, OSC 2) Rf=20k±1% OSC1 Rf OSC2 Crystal oscillator (X1, X2) HD404374 HD404374 Series C1 X1 Crystal oscillator Crystal: 32.768 kHz: MX38T MX38T (Nihon Denpa Kogyo) C1=C2=20pF±20% X2 GND C2 Notes: 1. With a crystal or ceramic oscillator, circuit constants will differ depending on the resonator, stray capacitance in the interconnecting circuit, and other factors. Suitable constants should be determined in consultation with the resonator manufacturer. 2. Make the connections between the OSC1 and OSC 2 pins (X1 and X2 pins) and external components as short as possible, and ensure that no other lines cross these lines (see layout example in figure 23). 3. When 32.768 kHz crystal oscillation is not used, fix the X1 pin at V CC and leave the X2 pin open. 4. Applies to HD40C4372 HD40C4372, HD40C4374 HD40C4374, HD40C4382 HD40C4382, HD40C4384 HD40C4384, HD40C4388 HD40C4388, HD40C4389 HD40C4389, HD40C4081 HD40C4081, HD40C4082 HD40C4082, HCD40C4082 HCD40C4082, HD40C4084 HD40C4084, HCD40C4084 HCD40C4084, HD407C4374 HD407C4374 and HD407C4384 HD407C4384. 58 HD404374/HD404384/HD404389/HD404082/HD404084 Series AVSS AVSS OSC1 OSC1 OSC2 OSC2 TEST TEST X2 NC X1 NC (GND) RESET RESET (GND) HD404374 HD404374 Series HD404384/HD404389/HD404082/HD404084 HD404384/HD404389/HD404082/HD404084 Series Figure 23 Typical Layouts of Crystal and Ceramic Oscillator 59 HD404374/HD404384/HD404389/HD404082/HD404084 Series Input/Output The MCU has 20 input/output pins (D 0 to D9, R0, R10, R13, R20 to R2 2, R70 to R73). The features of these pins are described below. · The four pins D 0 to D3 are source large-current (10 mA max.) I/O pins. · The four pins D 4 to D7 are sink large-current (15 mA max.) I/O pins. · I/O pins comprise pins (D0, R0 0, R1 0, R1 3, R2 0 to R22, R70 to R73) that also have a peripheral function (timer, serial interface, etc.). With these pins, the peripheral function setting has priority over the D port or R port pin setting. When a peripheral function setting has been made for a pin, the pin function and input/output mode will be switched automatically in accordance with that setting. · Selection of input or output for I/O pins, or selection of the port or peripheral function for pins multiplexed as peripheral function pins, is performed by the program. · All output of the peripheral function pins are CMOS outputs. The SO pin and R2 2 port pin can be designated as NMOS open-drain output by the program. · A reset clears peripheral function selection. And since the data control registers (DCD, DCR) are also reset, input/output pins go to the high-impedance state. · Each I/O pin has a built-in pull-up MOS that can be turned on and off individually by the program. Figure 24 shows the I/O buffer configuration, and table 22 shows I/O pin circuit configuration control by the program. Table 23 shows the circuit configuration of each I/O pin. VCC Pull-up control signal Pull-up MOS MIS3 VCC PMOS Buffer control signal Output data NMOS Input data Input control signal Figure 24 I/O Pin Circuit Configuration 60 DCD, DCR PDR HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 22 Programmable I/O Circuits MIS3 (bit 3 of MIS) 0 DCD,DCR 1 0 PDR 1 0 1 0 0 1 0 1 0 1 PMOS - - - ON - - - ON NMOS CMOS buffer 1 - - ON - - - ON - - - - - - ON - ON Pull-up MOS Note: - : OFF Table 23 Circuit Configurations of I/O Pins Type I/O pins Circuit Configuration VCC VCC Pins Pull-up control signal MIS3 Buffer control signal DCD, DCR Output data D0-D9 R0 0 R1 0, R1 3 R2 0, R2 1 PDR Input data Input control signal VCC VCC Pull-up control signal Buffer control signal Output data R2 2 R7 0­R7 3 MIS3 DCR SMR22 SMR22 PDR *2 R7 0-R73 0-R73 AN 0-AN3 *1 Input data Input control signal VCC Pull-up control signal VCC Buffer control signal Output data MIS3 DCR PDR A/D input A/D channel control signal Input data Input control signal Notes: In a reset, since the I/O control registers are reset, input/output pins go to the high-impedance state and peripheral function selections are cleared. 1. Applies to HD404374 HD404374, HD404384 HD404384, and HD404389 HD404389 Series. 2. Applies to HD404082 HD404082 and HD404084 HD404084 Series. 61 HD404374/HD404384/HD404389/HD404082/HD404084 Series Table 23 Circuit Configurations of I/O Pins (cont) Type Peripheral function pins Circuit Configuration I/O pins VCC VCC Pins Pull-up control signal Output data Input data Output pins VCC VCC Pull-up control signal Output data VCC SCK MIS3 PDR SMR22 SMR22 SO Pull-up control signal Output data Input pins Input data SCK SCK PMOS control signal VCC MIS3 PDR I/O control signal MIS3 PDR SO TOB, TOC TOB, TOC RESET RESET VCC MIS3 WU0, INT0, EVNB, SI PDR WU0 etc. A/D Input AN 4, AN 5 *1 A/D channel control signal Note: In a reset, since the I/O control registers are reset, input/output pins go to the high-impedance state and peripheral function selections are cleared. 1. Applies to HD404389 HD404389 Series. 62 HD404374/HD404384/HD404389/HD404082/HD404084 Series D Port The D port consists of 10 I/O pins that are addressed bit-by-bit. Ports D0 to D3 are source large-current I/O pins, and ports D4 to D7 are sink large-current I/O pins. The D port can be set and reset by the SED and RED instructions or the SEDD and REDD instructions. Output data is stored in the port data register (PDR) for each pin. The entire D port can be tested by the TD or TDD instruction. The D port output buffer is turned on and off by the D port data control registers (DCD0 to DCD2: $030 to $032). The DCD registers are mapped onto memory addresses (figure 25). Port D0 is multiplexed as interrupt input pin INT0. Setting as interrupt pin is performed by bit 0 (PMR00 PMR00) of port mode register 0 (PMR0: $008) (figure 26). Data control registers (DCD0­2 : $030­$032) (DCR0­2, 7 : $034­$036, $03B) Register Name 2 1 0 W W W W Reset 0 0 0 0 Bit name DCDn3 DCDn2 DCDn1 DCDn0 Read/Write DCRm (m=0 to 2, 7) 3 Read/Write DCDn (n=0 to 2) Bit W W W W Reset 0 0 0 0 Bit name DCRm3 DCRm2 DCRm1 DCRm0 All bits CMOS buffer control 0 CMOS buffer off (high impedance) 1 CMOS buffer active Correspondence between each bit of DCD and DCR and ports Register Name Bit 3 Bit 2 Bit 1 Bit 0 DCD0 D3 D2 D1 D0 DCD1 D7 D6 D5 D4 D9 D8 DCD2 R00 DCR0 DCR1 R13 R22 DCR2 DCR7 R10 R73 R21 R20 R72 R71 R70 Figure 25 Data Control Registers (DCD, DCR) 63 HD404374/HD404384/HD404389/HD404082/HD404084 Series R Port The R port consists of 10 I/O pins that are addressed in 4-bit units. Input can be performed by means of the LAR and LBR instructions, and output by means of the LRA and LRB instructions. Output data is stored in the port data register (PDR) for each pin. The R port output buffer is turned on and off by the R port data control registers (DCR0 to DCR2, DCR7: $034 to $036, $03B). The DCR registers are mapped onto memory addresses (figure 25). Port R00 is multiplexed as wakeup input pin WU0 . Setting of this pin as peripheral function pins is performed by port mode register 1 (PMR1: $009) (figure 27). Port R1 0 is multiplexed as peripheral function pin EVNB. Setting of this pin as peripheral function pins is performed by bit 0 (PMR20 PMR20) of port mode register 2 (PMR2: $00A) (figure 28). Ports R1 3 and R20 are multiplexed as peripheral function pins TOB, and TOC, respectively. Setting of these pins as peripheral function pins is performed by bits 3 (PMR23 PMR23) of port mode register 2 (PMR2: $00A) and bit 0 (PMR30 PMR30) of port mode register 3 (PMR3: $00B)(figures 28 and 29). Ports R21 and R22 are multiplexed as peripheral function pins SCK and SI/SO, respectively. Setting of these pins as peripheral function pins is performed by bits 1 to 3 (PMR31 PMR31 to PMR33 PMR33) of port mode register 3 (PMR3: $00B) (figure 29). Ports R7 0 to R73 are multiplexed as peripheral function pins AN0 to AN3 (HD404374 HD404374, HD404384 HD404384, and HD404389 HD404389 Series only). Setting of these pins as peripheral function pins is performed by bits 1 to 3 (AMR1 to AMR3) of the A/D mode register (AMR: $028) (see figure 64 in section 8, A/D Converter). Port mode register 0 (PMR0: $008) Bit 3 2 1 0 Read/Write W Initial value on reset 0 Bit name Not used Not used Not used PMR00 PMR00 PMR00 PMR00 D0/INT0 pin mode selection 0 D0 1 INT0 Figure 26 Port Mode Register 0 (PMR0: $008) 64 HD404374/HD404384/HD404389/HD404082/HD404084 Series Port mode register 1 (PMR1: $009) Bit 3 2 1 0 Read/Write W Initial value on reset 0 Bit name Not used Not used Not used PMR10 PMR10 PMR10 PMR10 R00/WU0 R00/WU0 pin mode selection 0 R00 1 WU0 Figure 27 Port Mode Register 1 (PMR1: $009) Port mode register 2 (PMR2: $00A) 2 1 Bit 3 Read/Write W W Initial value on reset 0 0 Bit name PMR23 PMR23 Not used Not used 0 PMR20 PMR20 PMR20 PMR20 0 R13 1 EVNB R13/TOB R13/TOB pin mode selection 0 R10 1 PMR23 PMR23 R10/EVNB R10/EVNB pin mode selection TOB Figure 28 Port Mode Register 2 (PMR2: $00A) 65 HD404374/HD404384/HD404389/HD404082/HD404084 Series Port mode register 3 (PMR3: $00B) Bit 3 2 1 0 Read/Write W W W W Initial value on reset 0 0 0 0 PMR33 PMR33 PMR32 PMR32 PMR31 PMR31 PMR30 PMR30 Bit name PMR30 PMR30 R20/TOC R20/TOC pin mode selection 0 R20 1 TOC PMR31 PMR31 R21/SCK R21/SCK pin mode selection 0 R21 1 SCK PMR33 PMR33 PMR32 PMR32 R22/SI/SO R22/SI/SO pin mode selection 0 R22 1 0 SI 1 SO : Don't care Figure 29 Port Mode Register 3 (PMR3: $00B) Pull-Up MOS Control Program-controllable pull-ups MOS are incorporated in all I/O pins. On/off control of all pull-ups MOS is performed by bit 3 (MIS3) of the miscellaneous register (MIS: $005) and the port data register (PDR) for each pin, enabling the pull-up MOS to be turned on or off independently for each pin (table 22, figure 30). Except for analog input multiplexed pins, the pull-up MOS on/off setting can be made independent of the setting as an on-chip supporting module pin. 66 HD404374/HD404384/HD404389/HD404082/HD404084 Series Bit 2 of the miscellaneous register must always be set to 0. The microcomputer will malfunction if it is set to 1. Miscellaneous register (MIS: $005) Bit 3 2 1 0 Read/Write W W W W Initial value on reset 0 0 0 0 MIS3 Not used*1 MIS1 MIS0 Bit name tRC selection (See figure 15 in the Operating Modes section) MIS2 Setting bit2 0 1 MIS3 Set to 0 Use prohibited pull-up MOS control 0 All pull-ups MOS off 1 pull-up MOS active Note: 1. This bit must always be set to 0. The microcomputer will malfunction if it is set to 1. Figure 30 Miscellaneous Register (MIS:$005) Handling of I/O Pins Not Used by User System If I/O pins that are not used by the user system are left floating, they may generate noise that can result in chip malfunctions. Therefore, the pin potential must be fixed. In this case, pull the pins up to VCC with the built-in pull-up MOS or with an external resistor of approximately 100 k. 67 HD404374/HD404384/HD404389/HD404082/HD404084 Series Prescalers The MCU has the following prescalers, S and W (HD404374 HD404374 Series). The operating conditions for each prescaler are shown in table 24, and the output supply destinations in figure 31. Timer A to C input clocks other than external events, and serial transfer clocks other than external clocks are selected from the prescaler outputs in accordance with the respective mode register. Prescaler Operation Prescaler S (PSS): Prescaler S is an 11-bit counter that has the system clock as input. When the MCU is reset, prescaler S is reset to $000, then divides the system clock. Prescaler S operation is stopped by a reset by the MCU, and in stop mode and watch mode*1. It does not stop in any other modes. Prescaler W (PSW) (HD404374 HD404374 Series): Prescaler W is a counter that has a clock divided from the X1 input (32 kHz crystal oscillation) as input. When the MCU is reset, prescaler W is reset to $00, then divides the input clock. Prescaler W can also be reset by software. Table 24 Prescaler Operating Conditions Prescaler Input Clock Prescaler S System clock in active and MCU reset, stop mode standby modes, subsystem clearance clock in subactive mode*1 MCU reset, stop mode, watch mode*1 Prescaler W Clock obtained by division- MCU reset, software*2 by-8 of 32.768 kHz oscillation by subsystem clock oscillator MCU reset, stop mode Notes: 1 2 68 Reset Conditions Stop Conditions Applies to HD404374 HD404374 Series If bits TMA3 to TMA1 in timer mode register A (TMA) are all set to 1, PSW is cleared to $00. HD404374/HD404384/HD404389/HD404082/HD404084 Series Subsystem clock Prescaler W Timer A HD404374 HD404374 series Timer B Timer C System clock Clock selector Prescaler S Serial interface Figure 31 Prescaler Output Destinations 69 HD404374/HD404384/HD404389/HD404082/HD404084 Series Timers The MCU incorporates three timers, A to C. · Timer A: Free-running timer · Timer B: Multifunctional timer · Timer C: Multifunctional timer Timer A is an 8-bit free-running timer. Timers B and C are 8-bit multifunctional timers; Each one of their have the functions shown in table 25 and their operating mode can be set by the program. Table 25 Timer Functions Functios Prescaler S Available Available Available Available - - - Available - Free-running Available Available Available Time-base* Available - - Event counter - Available - Reload - Available Available Watchdog - - Available Toggle - Available Available PWM Timer outputs Timer C External event Timer functions Timer B Prescaler W* Clock source Timer A - Available Available Note: - implies not available * Applies to HD404374 HD404374 Series Timer A Timer A Functions Timer A has the following functions. · Free-running timer · Realtime clock time base The block diagram of timer A is shown in figure 32. 70 HD404374/HD404384/HD404389/HD404082/HD404084 Series 1/4 1/2 2 fW fW t Wcyc Timer A interrupt request flag (IFTA) Prescaler W (PSW) ÷2 ÷8 ÷ 16 ÷ 32 32.768-kHz oscillator 1/2 t Wcyc Clock Timer counter A (TCA) Overflow ø PER System clock ÷2 ÷4 ÷8 ÷ 32 ÷ 128 ÷ 512 ÷ 1024 ÷ 2048 Selector Internal data bus Selector Selector HD404374 HD404374 Series Prescaler S (PSS) 3 Timer mode register A (TMA) Data bus Clock line Signal line Figure 32 Timer A Block Diagram Timer A Operation Free-running timer operation: The timer A input clock is selected by timer mode register A (TMA: $00F). Timer A is reset to $00 by an MCU reset, and counts up each time the input clock is input. When the input clock is input after the timer A value reaches $FF, overflow output is generated, and the timer A value becomes $00. The generated overflow output sets the timer A interrupt request flag (IFTA: $002,0). Timer A continues counting up after the count value returns to $00, so that an interrupt is generated regularly every 256 input clock cycles. Realtime clock time base operation (HD404374 HD404374 Series): Timer A can be used as the realtime clock time base by setting bit 3 (TMA3) of timer mode register A to 1. As the prescaler W output is input to timer/counter A, interrupts are generated with accurate timing using the 32.768 kHz crystal oscillator as the basic clock. When timer A is used as the realtime clock time base, prescaler W and timer/counter A can be reset to $00 by the program. 71 HD404374/HD404384/HD404389/HD404082/HD404084 Series Timer A Register Timer A operation is set by means of the following register. Timer mode register A (TMA: $00F): Timer mode register A (TMA: $00F) is a 4-bit write-only register. Timer A operation and input clock selection are set as shown in figure 33. 72 HD404374/HD404384/HD404389/HD404082/HD404084 Series Timer mode register A (TMA: $00F) Bit 3 2 1 0 Read/Write W W W W Initial value on reset 0 0 0 0 TMA3*4 TMA2 TMA1 TMA0 TMA3*4 TMA2 TMA1 TMA0 Source prescaler 0 PSS 2,048 tcyc 1 PSS 1,024 tcyc 0 PSS 512 tcyc 1 PSS 128 tcyc 0 PSS 32 tcyc 1 PSS 8 tcyc 0 PSS 4 tcyc 1 PSS 2 tcyc 0 PSW 32 twcyc 1 PSW 16 twcyc 0 PSW 8 twcyc 1 PSW 2 twcyc 0 PSW Bit name Input clock period Operating mode 0 0 1 0 0 Timer A mode 1 1 0 0 1 1 0 1 1 Time base mode 1/2 twcyc 1 Not Used x PSW, TCA reset x : Don't care Notes : 1. twcyc = 244.14 µs (using 32.768 kHz crystal oscillator) 2. Timer/counter overflow output period (s) = input clock period (s) × 256. 3. The division ratio must not be changed while time base mode is being used, as this will result in an error in the overflow period. 4. Applies to HD404374 HD404374 Series. In HD404384 HD404384, HD404389 HD404389, HD404082 HD404082 and HD404084 HD404084 Series, write as 0. Figure 33 Timer Mode Register A (TMA) 73 HD404374/HD404384/HD404389/HD404082/HD404084 Series Timer B Timer B Functions: Timer B has the following functions. · Free-running/reload timer · External event counter · Timer output operation (toggle output, PWM output) The block diagram of timer B is shown in figure 34. Timer B ineterrupt request flag (IFTB) Timer C clock source Timer output control logic Edge detection logic EVNB Timer read register BL (TRBL) 2 ÷2 Timer read register BU (TRBU) 4 ÷8 ÷32 ÷1