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Part : NIN-HD100KTRF Supplier : NIC Components Manufacturer : Avnet Stock : - Best Price : $0.0569 Price Each : $0.0629
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HD100K

Catalog Datasheet MFG & Type PDF Document Tags

HD10K

Abstract: the future. Hitachi developed HD10K series (compatible with Motorola's M E C L 10K series) and HD100K series (compatible with Fairchild's F100K series) and they are both in mass production stage. HD100K has , new technologies have been put in to the HD100K series such as 3/u lithography process
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HD100K

Abstract: GENERAL INFORMATION OF HD100K SERIES FEATURES · On-chip complementary output Built-in complementary output requires no appli cation of inverters, and it avoids the problems of number of external , G E >24 Pin Ceramic Flat Package (HDIOOKF Series) >24 Pin Ceramic Dual-in-line Package (HD100K Series) 0 H IT A C H I 21 GENERAL INFORMATION OF HD100K SE R IE S D E F IN IT IO N O F S Y , -2 .0 V ; 22 0 H IT A C H I GENERAL INFORMATION OF HD100K S E R IE S · A C
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HD10131

Abstract: HD10125 CONTENTS G E N E R A L I N F O R M A T I O N . · l · Definition of Letter Symbols and Abbreviations. General Information o f WD10K S e rie s . General Information o f HD100K Series , . 117 · HD100K Series
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HD10131 HD10125 HD10231 HD100112 HM10474 HD10116 HD10101 HD10102 HD10104 HD10105 HM100422CG 100415CG
Abstract: COMMON DC CHARACTERISTICS OF HD100K SERIES B V e e = - 4.5V , V cc = V cca = G N D , 7 a = 0 t o Item Symbol Voi, V i s = V ih Vol. VoHC + 85°C min * ¿ = 500 Vt t = T e st Condition « i or Vis' = V u . mi* typ 955 - m ax 880 Unit mV mV mV mV mV mV M O utput V oltage -1 0 2 5 -1 8 1 0 -1 0 3 5 -1165 -1810 -2.0V -1 7 0 5 - -1 6 2 0 - A .= 5 o n V is ~ - V ih O utput T hreshold V oltage VoiA' VlH »i« or V i s = V u . m ,x Vt t = -2. ÖV -
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HD100123F

Abstract: hd100123 HD100123 Hex Bus Drivers The HD100123 contains six bus drivers capable of driving terminated lines with terminations as low as 25iì. To reduce crosstalk, each output has its respective ground connection and transition times were designed to be longer than on other HD100K devices, The driver itself performs the positive logie AND of a data input (A, B inputs) and the OR of two select inputs (Cr D inputs). The output voltage low level is designed to be more negative than normal ECL outputs. This allows
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HD100123F

HM100415

Abstract: HMl00415fHM100415CG 1024-word x 1-bit Fully Decoded Random Access Memory The HM100415 is a 1024-word x 1-bit, read/write random access memory developed for application to scratch pads, control and buffer storages which require very high speeds. The HM100415 is compatible with the HD100K families and includes on-chip voltage and temperature compensation for improved noise margin. This memory is encapsulated in cerdip-16pin package. â  FEATURES â'¢ Level . 100K ECL Compatible â
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HM100415CG F100415 1HM100415CG

HD100125

Abstract: HD100125F HD10012S Hex ECL-to-TTL Translators The HD100125 is a Hex Translator for converting HD100K logic levels to TTL logic levels. Differential inputs allow each circuits to be used as an inverting, non-inverting or as a differential receiver. An internal reference voltage generator provides VBB on pin 17 for single-ended operation or for use in Schmitt trigger applications. The outputs, which will go low when the inputs are left unconnected, have a fan-out of 10 Schottky TTL loads. When used in the differential mode
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HD100125F
Abstract: HM100474.HM100474F 1024-w o rd x 4 -b it Fully Decoded Random Access Memory The HM100474 is a 1024-words x 4-bit, read/write, random access memory developed for high speed systems such as scratch pads and control/buffer storages. The fabrication process is the Hitachi's low capacitance, oxide isolation method with double metalization. The HM100474 is compatible with the HD100K ECL families and includes on-chip voltage and temperature compensation for im proved noise margin. This device is -
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100474F

HD100K

Abstract: HM100415.HM100415CG 1 0 2 4 - w o r d x 1-bit Fully Decoded Random A c c e s s Memory The HM 100415 is a 1024-word x 1-bit, read/write random access memory developed for application to scratch pads, control and buffer storages which require very high speeds. The HM100415 is compatible with the HD100K families and includes on-chip voltage and temperature compensation for im proved noise margin. This memory is encapsulated in cerdip-16pin package. HM 100415 FEATURES · · · · · · · Level
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F100470

Abstract: HD100K HM100470 4 0 9 6 -w o rd x 1-bit Fully Decoded Random Access Memory The HM 100470 is a 4096-words x 1-bit, read/write, random access memory developed for high speed systems such as scratch pads and control buffer storages. The fabrication process is the Hitachi's low capacitance, oxide isolation method with double metalization. The HM 100470 is compatible with the HD100K ECL families and includes on-chip voltage and temperature compensation for im proved noise margin. This device is encapsulated in cerdip
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F100470
Abstract: H D 100125 Hex ECL-to-TTL Translators The HD100125 is a Hex Translator for converting outputs, which will go low when the inputs are left HD100K logic levels to T T L logic levels. Differen­ tial inputs allow each circuits to be used as an inverting, non-inverting or as a differential re­ ceiver. An internal reference voltage generator provides V Bg on pin 17 for single-ended operation or for use in Schmitt trigger applications. The unconnected, have a fan-out of 10 Schottky T T L -
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L1340

Abstract: H D 10012S Hex E C L -to -T T L T ranslators The H D 100125 is a Hex Translator for converting HD100K logic levels to T T L logic levels. Differen tial inputs allow each circuits to be used as an inverting, non-inverting or as a differential re ceiver. An internal reference voltage generator provides Vgg on pin 17 for single-ended operation or for use in Schmitt trigger applications. The outputs, which will go low when the inputs are left unconnected, have a fan-out of 10 Schottky T T L loads. When
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L1340

HA 12058

Abstract: HA12047 Dual High Speed D Master-Slave F.F. DG-16 Bipolar ECL DB 39 DG-24 DG-16 HD100K Series A A , HD100K 0.1 1.0 10 50 Power C onsum ption per Gate P j (mW) -_ _ _ _ O
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HA 12058 HA12047 HA12038 ha12058 17812P HA 12046 HD25/HD HMCS40 HD61J/K/L/MM 27K/L/P/Q ECLHD10K/100K 2SK296

WPCE775LA0DG

Abstract: RT8206B HM100474.HM100474F 1024-w o rd x 4 -b it Fully Decoded Random Access Memory The HM100474 is a 1024-words x 4-bit, read/write, random access memory developed for high speed systems such as scratch pads and control/buffer storages. The fabrication process is the Hitachi's low capacitance, oxide isolation method with double metalization. The HM100474 is compatible with the HD100K ECL families and includes on-chip voltage and temperature compensation for im proved noise margin. This device is
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RT8206B RT8207A RT8202A ALC269X WPCE775LA0DG winbond wpce775 wpce775la winbond wpce775la0dg 318MHZ CK505 QFN-64 ISL6261A

CERDIP24

Abstract: 100474f HM100470 4 0 9 6 -w o rd x 1-bit Fully Decoded Random Access Memory The HM 100470 is a 4096-words x 1-bit, read/write, random access memory developed for high speed systems such as scratch pads and control buffer storages. The fabrication process is the Hitachi's low capacitance, oxide isolation method with double metalization. The HM 100470 is compatible with the HD100K ECL families and includes on-chip voltage and temperature compensation for im proved noise margin. This device is encapsulated in cerdip
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CERDIP24 100474F------W