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HCTL-2020 Datasheet

Part Manufacturer Description PDF Type
HCTL-2020 Agilent Technologies Quadrature Decoder/Counter Interface Ics Original
HCTL-2020 Agilent Technologies Quadrature Decoder/Counter Interface ICs Original
HCTL-2020 Agilent Technologies Motion Motor Control, Without Current Limiter, 4.5V to 5.5V Operating Voltage, -40C to 85C Operating Temperature, PDIP Original
HCTL-2020 Agilent Technologies Quadrature Decoder/Counter Interface ICs Original
HCTL-2020 Agilent Technologies Surface Mount Quadrature Decoder/Counter Interface Ics Original
HCTL-2020 Agilent Technologies Quadrature Decoder/Counter Interface ICs Original
HCTL-2020 Avago Technologies Quadrature Decoder/Counter Interface ICs Original
HCTL2020 Hewlett-Packard (HCTL20xx) Quadrature Decoder/Counter Interface ICs Original
HCTL-2020 Hewlett-Packard QUADRATURE DECODER / COUNTER INTERFACE IC Scan
HCTL-2020 #PLC Agilent Technologies Surface Mount Quadrature Decoder/Counter Interface Ics Original
HCTL-2020#PLC Agilent Technologies Motion Motor Control, Without Current Limiter, 4.5V to 5.5V Operating Voltage, -40C to 85C Operating Temperature, PLCC Original
HCTL-2020#PLC Avago Technologies Quadrature Decoder/Counter Interface ICs Original
HCTL-2020PLC Hewlett-Packard Surface Mount Quadrature Decoder/Counter Interface ICs Original

HCTL-2020

Catalog Datasheet MFG & Type PDF Document Tags

motorola 6802

Abstract: -2000 HCTL-2016 HCTL-2020 QUADRATURE DECODER/ COUNTER INTERFACE 1C Features â'¢ INTERFACES ENCODER , 12-bit counter. The HCTL-2016 and 2020 contain a 16-bit counter. The HCTL-2020 also contains , -2000. 16-bit counter. A HCTL-2020 All features of the HCTL-2016. Quadrature decoder output signals , presented on this LS TTL-com patible o utput when the HCTL-2020 internal counter overflows or underflows , . In the case of the HCTL-2020, the signals also go to external pins 5 and 16 respectively. Figure 9
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OCR Scan
motorola 6802 HCTL-2000 16-BIT HCTL-20XX 5091-0683E

Quadrature Decoder Interface ICs

Abstract: HCTL-2020 circuit H Surface Mount Quadrature Decoder/Counter Interface ICs Technical Data HCTL-2016 #PLC HCTL-2020 #PLC Features Applications The HCTL-2016 #PLC and HCTL2020 #PLC have all of the same features, functions, and operating characteristics as the HCTL-2016 and HCTL-2020 PDIP (plastic dual-in-line package). · 20 Pin PLCC Surface Mount Package · All Features of the HCTL2016 and HCTL-2020 PDIP , digital potentiometers to digital data input buses. Description The HCTL-2016 #PLC and HCTL2020 #PLC
Hewlett-Packard
Original
Quadrature Decoder Interface ICs HCTL-2020 circuit hctl 3 quadrature decoder HCTL2000/HCTL-2016/HCTL-2020 5965-5895E

2020

Abstract: HCTL-2020 HCTL-2020 Quadrature Decoder/Counter with Launch Pad Application Note 5236 Introduction HCTL-2020 Quadrature Decoder/Counter is obsolete and will be replaced with the HCTL-2032 and HCTL2022. Since HCTL-2020 is a 16-bit counter and 20-pin package, direct replacement is impossible using the , HCTL-2020. Solutions In order to continue to use the HCTL-2020 ICs in the current design, the HCTL-2032 is used to configure as HCTL-2020 with Launch Pad. The HCTL-2032 is mounted on the Launch Pad with
Avago Technologies
Original
HCTL-2022 PDIP-20 2020 hctl 2032 counter HCTL-20 PDIP-32 SOIC-32 5989-3240EN

C68HC11

Abstract: maI H E W L E T T 1 mitim P A C K A R D Interfacing the MC68HC11 to the HCTL-2020 Application , interfaces for the HCTL-2020 to the MC68HC11. One is a port interface and the other is a bus interface. T H , E. T H E SU B R O U T IN E R E T U R N S TH E 16 B IT DATA FRO M T H E HCTL2020 IN R E G IS T E R IX , used for the control signals to the HCTL-2020. The E clock from the 68HC11E9 is used to clock the HCTL-2020 , read from the HCTL-2020 and to reset the HCTL-2020 follow. RD 2020: P SH A P SH B LDAA#00 STAA $1007
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C68HC11 M-023 CTL-2020 ST2020

68hc11e9

Abstract: MC68HC11 Interfacing the MC68HC11 to the HCTL-2020 Application Brief M-023 Introduction Port Interface This application brief describes two interfaces for the HCTL-2020 to the MC68HC11. One is a , the control signals to the HCTL-2020. The E clock from the 68HC11E9 is used to clock the HCTL-2020 , read from the HCTL-2020 and to reset the HCTL-2020 follow. ;* ;THIS SUBROUTINE IS USED TO READ DATA FROM THE HCTL-2020 ;FOR THE PORT INTERFACE. ;THE SUBROUTINE
Avago Technologies
Original
74HC138 74HC373 74HC00 74hc00 on 74hc00 datasheet 68HC11*E9 RD2020 REST2020 RST2020 74HC20 74HC32

74LS193

Abstract: AD 2020 interface the HCTL2020 to a DAC (Digital Analog Converter) without having to use a processor or micro , control the loading of the high and low bytes from the HCTL-2020 called HBE (High Byte: Enable) and LBE , can be arbitrarily selected. For example, they can be used to reset the in hibit in the HCTL-2020 by , HI HI HI HI HI Remarks enable the HI byte from HCTL-2020, load the byte into the DAC with the HBE signal. ;complete the loading process. enable the LO byte from the HCTL2020, load the byte into the DAC
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74LS193 AD 2020 M-020

74LS193

Abstract: 74LS32 A Simple Interface for the HCTL-2020 with a 16-bit DAC without using a processor Application Brief M-020 Introduction In certain applications it becomes necessary to interface the HCTL-2020 to , of the high and low bytes from the HCTL-2020 called HBE (High Byte Enable) and LBE (Low Byte Enable , selected. For example, they can be used to reset the inhibit in the HCTL-2020 by dummy read. In order to , corresponds to enabling the HCTL-2020 and the AD 569. After this last state the circuit is made to start from
Avago Technologies
Original
74LS14 74LS32 74LS04 74LS04 truth table 74LS193 truth table 74LS32 truth table 5964-3767E

datasheet 6802 processor motorola

Abstract: intel 8748 microprocessor 4X decode logic of the HCTL2020. When the decoder has detected a count, a pulse, onehalf clock cycle , . Decode and Cascade Output Diagram. Cascade Considerations (HCTL-2020 Only) The HCTL-2020's cascading , generated. A read starting on this clock cycle will show FFFFH from the HCTL2020. The external latch , . Address AO is connected directly to the SEL pin on the HCTL2020. This line selects the low or high byte of data from the HCTL2020. Cascading is accomplished by connecting the CNTCAS output on the HCTL-2020
Avago Technologies
Original
datasheet 6802 processor motorola intel 8748 microprocessor shaft encoder HCTL-20XX M027 Interfacing the HCTL-20XX INSTRUCTION SET motorola 6802 m027 MC68HCII 5965-5894E 5988-5895EN

HCTL-2016

Abstract: Quadrature Decoder Interface ICs HCTL-2016 #PLC HCTL-2020 #PLC Surface Mount Quadrature Decoder/Counter Interface ICs Data Sheet Description Applications The HCTL-2016 #PLC and HCTL-2020 #PLC are quadrature decoder , if more clarification is needed. The HCTL-2016 #PLC and HCTL-2020 #PLC have all of the same features, functions, and operating characteristics as the HCTL-2016 and HCTL-2020 PDIP (plastic , HCTL-2020 PDIP For further information on the operation and function of the HCTL-2016 #PLC and 2020
Avago Technologies
Original
esd 20.20 HCTL-2000/HCTL-2016/ 5988-5894EN

Quadrature Decoder Interface ICs

Abstract: HCTL-2020 circuit Surface Mount Quadrature Decoder/Counter Interface ICs Technical Data HCTL-2016 #PLC HCTL-2020 #PLC Features Applications The HCTL-2016 #PLC and HCTL2020 #PLC have all of the same features, functions, and operating characteristics as the HCTL-2016 and HCTL-2020 PDIP (plastic dual-in-line package). · 20 Pin PLCC Surface Mount Package · All Features of the HCTL2016 and HCTL-2020 PDIP Description The HCTL-2016 #PLC and HCTL2020 #PLC are quadrature decoder/counter interface ICs in a 20 pin
Agilent Technologies
Original
PLC datasheets b-814 5091-1096E

74LS32 truth table

Abstract: 74LS193 truth table A Simple Interface for the HCTL-2020 with a 16-bit DAC without Using a Processor Application Brief M-020 Introduction In certain applications it becomes necessary to interface the HCTL2020 to , of the high and low bytes from the HCTL-2020 called HBE (High Byte Enable) and LBE (Low Byte , can be arbitrarily selected. For example, they can be used to reset the inhibit in the HCTL-2020 by , HEB LBE LO LO LO HI ;enable the HI byte from HCTL-2020, ;load the byte into the DAC
Hewlett-Packard
Original
74LS326 OF 74LS32 74LS32 and gate 74ls32 datasheet truth 74ls04 74LS04 gate and

TL-2020

Abstract: HCTL-2016 Technical Data HCTL-2016 #PLC HCTL-2020 #PLC Features · 20 Pin PLCC Surface Mount Package · All Features o f the HCTL2016 and HCTL-2020 PDIP The HCTL-2016 #PLC and HCTL2020 #PLC have all of the same features, functions, and operating characteristics as the HCTL-2016 and HCTL-2020 PDIP (plastic , digital potentiom eters to digital data input buses. Description The HCTL-2016 #PLC and HCTL2020 #PLC , 14 D°4 HCTL-2016 #PLC HCTL-2020 #PLC E SI) WARNING: NORMAL HANDLING PRECAUTIONS SHOULD B
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TL-2020 TL2020 HCTL2000/H

68HC11E9

Abstract: M023 H Interfacing the MC68HC11 to the HCTL-2020 Application Brief M-023 Introduction This application brief describes two interfaces for the HCTL-2020 to the MC68HC11. One is a port interface and , the control signals to the HCTL-2020. The E clock from the 68HC11E9 is used to clock the HCTL-2020 , read from the HCTL-2020 and to reset the HCTL-2020 follow. ;* ;THIS SUBROUTINE IS USED TO READ DATA FROM THE HCTL-2020 ;FOR THE PORT INTERFACE. ;THE SUBROUTINE
Hewlett-Packard
Original
M023 74hc004 schematic 74HC32 PC752 H2020 0C000 74HC30

datasheet 6802 processor motorola

Abstract: 3 to 8 line decoder using 8051 of the HCTL2020. When the decoder has detected a count, a pulse, onehalf clock cycle long, will be , Figure 12. Decode and Cascade Output Diagram. Cascade Considerations (HCTL-2020 Only) The HCTL-2020's , starting on this clock cycle will show FFFFH from the HCTL2020. The external latch should read F0H, but , connected directly to the SEL pin on the HCTL2020. This line selects the low or high byte of data from the HCTL2020. Cascading is accomplished by connecting the CNT CAS output on the HCTL-2020 with the counter
Agilent Technologies
Original
3 to 8 line decoder using 8051 intel 8748 motorola intel 6802 74LS697 6802 processor motorola 74LS138 decoder 5091-9974E

Quadrature Decoder Interface ICs

Abstract: hctl 3 Data HCTL-2016 #PLC HCTL-2020 #PLC Features â'¢ 20 Pin PLCC Surface Mount Package â'¢ All Features of the HCTL-2016 and HCTL-2020 PD1P Description The HCTL-2016 #PLC and HCTL-2020 #PLC are , , counter, and bus transfer functions. The HCTL-2016 #PLC and HCTL-2020 #PLC have all of the same features, functions, and operating characteristics as the HCTL-2016 and HCTL-2020 PDIP (plastic dual-in-line package). , refer to the HÇTL-2000/HCTL-2016/HCTL-2020 data sheet. Applications Typical applications include
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OCR Scan
incremental decoder TL-2000/HCTL-2016/HCTL-2020

motorola 6802

Abstract: intel 8748 microprocessor (HCTL-2020 Only) The HCTL-2020's cascading system allows for position reads of more than two bytes , the HCTL- 2020. This line selects the low or high byte of data from the HCTL2020. Cascading is , HCTL-2000, HCTL-2016, HCTL-2020 Quadrature Decoder/Counter Interface ICs Data Sheet , PINOUT B Devices Part Number HCTL-2000 HCTL-2016 HCTL-2020 Description 12-bit counter. 14 MHz , - 2000 contains a 12-bit counter. The HCTL-2016 and 2020 contain a 16-bit counter. The HCTL-2020 also
Avago Technologies
Original
M019 Encoder interface with HCTL-2016 HCTL-1101 Application 8051 AV02-3800EN

motorola 6802

Abstract: intel 8748 CONSIDERATIONS (HCTL-2020 ONLY) The HCTL-2020's cascading system allows for position reads of more than two ,  QUADRATURE DECODER/ COUNTER INTERFACE IC HCTL-2000 HCTL-2016 HCTL-2020 Features â , -2000 contains a 12-bit counter. The HCTL-2016 and 2020 contain a 16-bit counter. The HCTL-2020 also contains , -bit counter. A HCTL-2020 All features of the HCTL-2016. Quadrature decoder output signals. Cascade output , presented on this LSTTL-compatible output when the HCTL-2020 internal counter overflows or underflows. The
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block diagram of 74LS138 3 to 8 decoder DS 2020 HCTL2000 applications note 74ls02 8748 block diagram of 74LS138 1 line to 16 line

HCTL-2000

Abstract: HCTL-20XX / down outputs derived from the 4X decode logic of the HCTL2020. When the decoder has detected a count , Figure 12. Decode and Cascade Output Diagram. Cascade Considerations (HCTL-2020 Only) The HCTL-2020's , FFFFH from the HCTL2020. The external latch should read F0H, but if the host latches the count after , . Address AO is connected directly to the SEL pin on the HCTL2020. This line selects the low or high byte of data from the HCTL2020. Cascading is accomplished by connecting the CNT CAS output on the HCTL-2020
Agilent Technologies
Original
processor 8748 8748 instruction set Motorola 8748

intel 8748 microprocessor

Abstract: TL-20XX / down outputs derived from the 4X decode logic of the HCTL2020. When the decoder has detected a count, a , (HCTL-2020 Only) The HCTL-2020's cascading system allows for position reads of more than two bytes , will be generated. A read starting on this clock cycle will show FFFFH from the HCTL2020. The external , AO is connected directly to the SEL pin on the HCTL2020. This line selects the low or high byte of , and gives an example of reading the HCTL2020. Figure 16 shows the interface timing for the circuit
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OCR Scan
TL-20XX

M023

Abstract: intel 8748 4X decode logic of the HCTL2020. When the decoder has detected a count, a pulse, onehalf clock cycle , this clock cycle will show FFFFH from the HCTL2020. The external latch should read FOH. but if the host , the HCTL2020. This line selects the low or high byte of data from the HCTL2020 . Cascading is , the HCTL2020. Figure 16 shows the interface timing for the circuit. A ddress CXXX 4XXX 2XX0 2XX1 , HCTL-2000 HCTL-2016 HCTL-2020 Features · Interfaces Encoder to Microprocessor · 14 MHz Clock
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ic ds 2020
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