HCPL-316J SO-16 HCPL316J VLED18 UL1577 -000E -500E HCPL-316J-500E E55361 - Datasheet Archive

 

2.5 Amp Gate Drive Optocoupler with Integrated (VCE) Desaturation Detection and Fault Status Feedback Data Sheet Lead (Pb) Free

 

HCPL-316J HCPL-316J 2.5 Amp Gate Drive Optocoupler with Integrated (VCE) Desaturation Detection and Fault Status Feedback Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features (continued) Avago's 2.5 Amp Gate Drive Optocoupler with Integrated Desaturation (VCE) Detection and Fault Status Feedback makes IGBT VCE fault protection compact, affordable, and easy-to-implement while satisfying worldwide safety and regulatory requirements. · "Soft" IGBT turn-off · Integrated fail-safe IGBT protection ­ Desat (VCE) detection ­ Under Voltage Lock-Out protection (UVLO) with hysteresis · User configurable: inverting, noninverting, auto-reset, auto-shutdown · Wide operating VCC range: 15 to 30 Volts · -40°C to +100°C operating temperature range · 15 kV/µs min. Common Mode Rejection (CMR) at VCM=1500V · Regulatory approvals: UL, CSA, IEC/EN/DIN EN 607475-2 (891Vpeak Working Voltage) Features · 2.5 A maximum peak output current · Drive IGBTs up to IC = 150A, VCE = 1200V · Optically isolated, FAULT status feedback · SO-16 SO-16 package · CMOS/TTL compatible · 500 ns max. switching speeds Fault Protected IGBT Gate Drive +HV ISOLATION BOUNDARY ISOLATION BOUNDARY ISOLATION BOUNDARY HCPL - 316J HCPL - 316J HCPL - 316J 3-PHASE INPUT M HCPL - 316J HCPL - 316J ISOLATION BOUNDARY HCPL - 316J ISOLATION BOUNDARY ISOLATION BOUNDARY HCPL - 316J ISOLATION BOUNDARY ­HV FAULT MICRO-CONTROLLER CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. HCPL-316J HCPL-316J Gate Drive Typical Fault Protected IGBT Gate Drive Circuit The HCPL316J HCPL316J is an easy-to-use, intelligent gate driver which makes IGBT VCE fault protection compact, affordable, and easy-to-implement. Features such as user configurable inputs, integrated VCE detection, under volt- age lockout (UVLO), "soft" IGBT turn-off and isolated fault feedback provide maximum design flexibility and circuit protection. HCPL-316J HCPL-316J 1 + ­ VE 16 2 µC VIN+ VIN- VLED2+ 15 3 VCC1 DESAT 14 4 GND1 5 VCC2 RESET VC 12 FAULT VOUT VLED1+ VEE VLED1- VEE DDESAT + 10 8 100 11 7 CBLANK 13 6 RF * 9 + ­ * VF ­ + RG VCE ­ + * ­ + RPULL-DOWN VCE ­ * THESE COMPONENTS ARE ONLY REQUIRED WHEN NEGATIVE GATE DRIVE IS IMPLEMENTED. Figure 1. Typical desaturation protected gate drive circuit, noninverting. Description of Operation during Fault Condition 1. DESAT terminal monitors the IGBT VCE voltage through DDESAT. 2. When the voltage on the DESAT terminal exceeds 7volts, the IGBT gate voltage (VOUT ) is slowly lowered. 3. FAULT output goes low, notifying the microcontroller of the fault condition. 4. Microcontroller takes appropriate action. UVLO VIN+ VIN- (VCC2 - VE) X X Active X Low X High X X High Low X X X Not Active Output Control The outputs (VOUT and FAULT) of the HCPL316J HCPL316J are controlled by the combination of VIN, UVLO and a detected IGBT Desat condition. As indicated in the below table, the HCPL316J HCPL316J can be configured as inverting or noninverting using the VIN+ or VIN- inputs respectively. When an inverting configuration is desired, VIN+ must be held high and VIN- toggled. When a noninverting configuration is desired, VIN- must be held low and VIN+ toggled. Once UVLO is not active (VCC2 VE > VUVLO), VOUT is allowed to go high, and the DESAT (pin 14) detection feature of the HCPL316J HCPL316J will be the primary source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once VUVLO+ > 11.6 V, DESAT will remain functional until VUVLO- < 12.4 V. Thus, the DESAT detection and UVLO features of the HCPL316J HCPL316J work in conjunction to ensure constant IGBT protection. Desat Condition Detected on Pin 14 Pin 6 (FAULT) Output X Yes X X No X Low X X High VOUT Low Low Low Low High Product Overview Description The HCPL316J HCPL316J is a highly integrated power control device that incorporates all the necessary components for a complete, isolated IGBT gate drive circuit with fault protection and feedback into one SO16 package. TTL input logic levels allow direct interface with a microcontroller, and an optically isolated power output stage drives IGBTs with power ratings of up to 150 A and 1200 V. A high speed internal optical link minimizes the propagation delays between the microcontroller and the IGBT while allowing the two systems to operate at very large common mode voltage differences that are common in industrial motor drives and other power switching applications. An output IC provides local protection for the IGBT to prevent damage during overcurrents, and a second optical link provides a fully isolated fault status feedback signal for the microcontroller. A built in "watchdog" circuit monitors the power stage supply voltage to prevent IGBT caused by insufficient gate drive voltages. This integrated IGBT gate driver is designed to increase the performance and reliability of a motor drive without the cost, size, and complexity of a discrete design. Two light emitting diodes and two integrated circuits housed in the same SO16 package provide the input control circuitry, the output power stage, and two optical channels. The input Buffer IC is designed on a bipolar process, while the output Detector IC is designed manufactured on a high voltage BiCMOS/Power DMOS VLED1+ 7 VCC1 Under normal operation, the input gate control signal directly controls the IGBT gate through the isolated output detector IC. LED2 remains off and a fault latch in the input buffer IC is disabled. When an IGBT fault is detected, the output detector IC immediately begins a "soft" shutdown sequence, reducing the IGBT current to zero in a controlled manner to avoid potential IGBT damage from inductive overvoltages. Simultaneously, this fault status is transmitted back to the input buffer IC via LED2, where the fault latch disables the gate control input and the active low fault output alerts the microcontroller. During powerup, the Under Voltage Lockout (UVLO) feature prevents the application of insufficient gate voltage to the IGBT, by forcing the HCPL316J HCPL316J's output low. Once the output is in the high state, the DESAT (VCE) detection feature of the HCPL316J HCPL316J provides IGBT protection. Thus, UVLO and DESAT work in conjunction to provide constant IGBT protection. VLED18 VLED18 13 INPUT IC VIN+ VIN- process. The forward optical signal path, as indicated by LED1, transmits the gate control signal. The return optical signal path, as indicated by LED2, transmits the fault status feedback signal. Both optical channels are completely controlled by the input and output ICs respective-ly, making the internal isolation boundary transparent to the microcontroller. 12 1 LED1 2 D R I V E R 3 UVLO 11 14 9,10 LED2 16 5 FAULT 6 SHIELD 4 GND1 VOUT DESAT DESAT SHIELD RESET FAULT VCC2 VC OUTPUT IC 15 VLED2+ HCPL-316J HCPL-316J functional diagram VEE VE Package Pin Out 1 VIN+ VE 16 2 VIN- VLED2+ 15 3 VCC1 DESAT 14 4 GND1 VCC2 13 5 RESET VC 12 6 FAULT VOUT 11 7 VLED1+ VEE 10 8 VLED1- VEE 9 Pin Descriptions Symbol Description Symbol VIN+ Noninverting gate drive voltage output (VOUT ) VE control input. Description Common (IGBT emitter) output supply voltage. VIN- Inverting gate drive voltage output VLED2+ (VOUT ) control input. LED 2 anode. This pin must be left unconnected for guaranteed data sheet performance. (For optical coupling testing only.) VCC1 Positive input supply voltage. (4.5 V to 5.5 V) DESAT HCPL-316J HCPL-316J Pkg Pinout Desaturation voltage input. When the voltage on DESAT exceeds an internal reference voltage of 7V while the IGBT is on, FAULT output is changed from a high impedance state to a logic low state within 5 µs. See Note 25. GND1 Input Ground. Positive output supply voltage. RESET FAULT reset input. A logic low input for at least VC 0.1 µs, asynchronously resets FAULT output high and enables VIN. Synchronous control of RESET relative to VIN is required. RESET is not affected by UVLO. Asserting RESET while VOUT is high does not affect VOUT. Collector of output pull-up triple-darlington transistor. It is connected to VCC2 directly or through a resistor to limit output turn-on current. FAULT Fault output. FAULT changes from a high impedance state to a logic low output within 5 µs of the voltage on the DESAT pin exceeding an internal reference voltage of 7V. FAULT output remains low until RESET is brought low. FAULT output is an open collector which allows the FAULT outputs from all HCPL-316Js in a circuit to be connected together in a "wired OR" forming a single fault bus for interfacing directly to the micro-controller. Gate drive voltage output. VLED1+ LED 1 anode. This pin must be left unconnected VEE Output supply voltage. for guaranteed data sheet performance. (For optical coupling testing only.) VLED1- LED 1 cathode. This pin must be connected to ground. VCC2 VOUT Ordering Information HCPL-316J HCPL-316J is UL Recognized with 3750 Vrms for 1 minute per UL1577 UL1577. Option RoHS Compliant Non RoHS Compliant -000E -000E No option -500E -500E Part number #500 HCPL-316J HCPL-316J Surface Mount Package Tape & Reel IEC/EN/DIN EN 60747-5-2 Quantity X SO-16 SO-16 X X 45 per tube X X 850 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-316J-500E HCPL-316J-500E to order product of SO-16 SO-16 Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant. Example 2: HCPL-316J HCPL-316J to order product of SO-16 SO-16 Surface Mount package in tube packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation `#XXX' is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use `-XXXE`. Package Outline Drawings 16-Lead Surface Mount 0.018 (0.457) 0.050 (1.270) LAND PATTERN RECOMMENDATION 16 15 14 13 12 11 10 9 TYPE NUMBER DATE CODE A 316J YYWW 1 2 3 4 5 0.458 (11.63) 0.295 ± 0.010 (7.493 ± 0.254) 6 7 0.085 (2.16) 8 0.406 ± 0.10 (10.312 ± 0.254) 0.025 (0.64) 0.345 ± 0.010 (8.763 ± 0.254) 9° 0.018 (0.457) 0.138 ± 0.005 (3.505 ± 0.127) 0­8° 0.025 MIN. 0.408 ± 0.010 (10.363 ± 0.254) ALL LEADS TO BE COPLANAR ± 0.002 0.008 ± 0.003 (0.203 ± 0.076) STANDOFF Dimensions in inches (millimeters) Notes: Initial and continued variation in the color of the HCPL-316J HCPL-316J's white mold compound is normal and does note affect device performance or reliability. Floating Lead Protrusion is 0.25 mm (10 mils) max. Package Characteristics All specifications and figures are at the nominal (typical) operating conditions of VCC1 = 5 V, VCC2 - VEE = 30 V, VE - VEE = 0 V, and TA = +25°C. Parameter Symbol Min. Typ. Max. Units Test Conditions Note Input-Output Momentary VISO 3750 Vrms Withstand Voltage RH < 50%, t = 1 min., TA = 25°C 1, 2, 3 3 Resistance (Input-Output) RI-O >109 VI-O = 500 Vdc Capacitance (Input-Output) CI-O 1.3 pF f = 1 MHz Output IC-to-Pins 9 &10 Thermal Resistance qO9-10 30 °C/W TA = 100°C Input IC-to-Pin 4 Thermal Resistance qI4 60 Solder Reflow Thermal Profile TEMPERATURE ( °C) 300 PREHEATING RATE 3 °C + 1 C/­0.5 °C/SEC. REFLOW HEATING RATE 2.5 °C ± 0.5 °C/SEC. 200 PEAK TEMP. 245 °C PEAK TEMP. 240 °C 2.5 °C ± 0.5 °C/SEC. SOLDERING TIME 200 °C 30 SEC. 160 °C 150 °C 140 °C 30 SEC. 3 °C + 1 °C/­0.5 °C 100 PREHEATING TIME 150 °C, 90 + 30 SEC. 50 SEC. TIGHT TYPICAL LOOSE ROOM TEMPERATURE 0 0 50 100 150 TIME (SECONDS) Note: Non-halide flux should be used. Recommended Pb-Free IR Profile tp Tp TEMPERATURE TL Tsmax 260 +0/-5 °C TIME WITHIN 5°C of ACTUAL PEAK TEMPERATURE 20-40 SEC. 217 °C RAMP-UP 3°C/SEC. MAX. 150 - 200°C RAMP-DOWN 6°C/SEC. MAX. Tsmin ts PREHEAT 60 to 180 SEC. 25 tL 60 to 150 SEC. t 25°C to PEAK TIME NOTES: THE TIME FROM 25 C to PEAK TEMPERATURE = 8 MINUTES MAX. Tsmax = 200°C, Tsmin = 150°C Note: Non-halide flux should be used. PEAK TEMP. 230 °C 200 250 Regulatory Information The HCPL-316J HCPL-316J has been approved by the following organizations: IEC/EN/DIN EN 60747-5-2 Approved under: IEC 60747-5-2:1997 + A1:2002 EN 60747-5-2:2001 + A1:2002 DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01. UL Recognized under UL 1577, component recognition program, File E55361 E55361. CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics* Description Symbol Characteristic Unit Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage 150 Vrms for rated mains voltage 300 Vrms for rated mains voltage 600 Vrms I - IV I - IV I - III Climatic Classification 55/100/21 Pollution Degree (DIN VDE 0110/1.89) 2 Maximum Working Insulation Voltage VIORM 891 VPEAK Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1sec, Partial Discharge < 5 pC VPR 1670 VPEAK Input to Output Test Voltage, Method a* VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, Partial Discharge < 5 pC VPR 1336 VPEAK Highest Allowable Overvoltage* (Transient Overvoltage tini = 10 sec) VIOTM 6000 VPEAK Safety-limiting values ­ maximum values allowed in the event of a failure, also see Figure 2. Case Temperature Input Power Output Power TS PS, INPUT PS, OUTPUT 175 400 1200 °C mW mW Insulation Resistance at TS, VIO = 500 V RS >109 *Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. Surface mount classification is class A in accordance with CECCOO802 CECCOO802. *Refer to the optocoupler section of the Isolation and Control Components Designer's Catalog, under Product Safety Regulations section IEC/ EN/DIN EN 60747-5-2, for a detailed description of Method a and Method b partial discharge test profiles. 1400 PS, OUTPUT PS, INPUT PS ­ POWER ­ mW 1200 1000 800 600 400 200 0 0 25 50 75 100 125 150 175 200 TS ­ CASE TEMPERATURE ­ °C Figure 2. Dependence of safety limiting values on temperature. HCPL-316J HCPL-316J fig 2 Insulation and Safety Related Specifications Parameter Symbol Value Units Conditions Minimum External Air Gap L(101) 8.3 mm (Clearance) Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking L(102) 8.3 mm (Creepage) Measured from input terminals to output terminals, shortest distance path along body. Minimum Internal Plastic Gap 0.5 mm (Internal Clearance) Through insulation distance conductor to conductor, usually the straight line distance thickness between the emitter and detector. Tracking Resistance (Comparative Tracking Index) DIN IEC 112/VDE 112/VDE 0303 Part 1 CTI >175 Isolation Group Volts IIIa Material Group (DIN VDE 0110, 1/89, Table 1) Absolute Maximum Ratings Parameter Symbol Min. Max. Units Note °C Storage Temperature Ts -55 125 Operating Temperature TA -40 100 Output IC Junction Temperature TJ 125 4 Peak Output Current |Io(peak)| 2.5 A 5 Fault Output Current IFAULT 8.0 mA Positive Input Supply Voltage VCC1 -0.5 5.5 Volts Input Pin Voltages VIN+, VIN- and VRESET -0.5 VCC1 Total Output Supply Voltage (VCC2 - VEE) -0.5 35 Negative Output Supply Voltage (VE - VEE) -0.5 15 Positive Output Supply Voltage (VCC2 - VE) -0.5 35 - (VE - VEE) Gate Drive Output Voltage Vo(peak) -0.5 VCC2 Collector Voltage VC VEE + 5 V VCC2 DESAT Voltage VDESAT VE VE + 10 Output IC Power Dissipation PO 600 Input IC Power Dissipation PI 150 mW 6 4 Solder Reflow Temperature Profile See Package Outline Drawings section Recommended Operating Conditions Parameter Symbol Min. Max. Units Note Operating Temperature TA -40 +100 °C Input Supply Voltage VCC1 4.5 5.5 Volts Total Output Supply Voltage (VCC2 - VEE) 15 30 9 Negative Output Supply Voltage (VE - VEE) 0 15 6 Positive Output Supply Voltage (VCC2 - VE) 15 30 - (VE - VEE) Collector Voltage VC VEE + 6 VCC2 28 Electrical Specifications (DC) Unless otherwise noted, all typical values at TA = 25°C, VCC1 = 5 V, and VCC2 - VEE = 30 V, VE - VEE = 0 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. Typ. Max. Units Logic Low Input Voltages VIN+L, VIN-L, VRESETL V Logic High Input Voltages VIN+H, VIN-H, 2.0 VRESETH Logic Low Input Currents IIN+L, IIN-L, IRESETL -0.5 -0.4 FAULT Logic Low Output Current IFAULTL 5.0 12 FAULT Logic High Output Current IFAULTH -40 µA High Level Output Current IOH -0.5 A 0.8 -1.5 mA Test Conditions Fig. Note VIN = 0.4 V VFAULT = 0.4 V 30 VFAULT = VCC1 31 VOUT = VCC2 - 4 V 3, 8, 32 -2.0 VOUT = VCC2 - 15 V Low Level Output Current 0.5 2.3 VOUT = VEE + 2.5 V 2.0 Low Level Output Current During Fault Condition IOLF 90 160 230 High Level Output Voltage VOH VC - 3.5 VC - 2.5 VC - 1.5 VC -2.9 VC - 2.0 VC - 1.2 IOUT = -650 µA VC 7 IOUT = 0 IOL 5 7 VOUT = VEE + 15 V 4, 9, 33 mA VOUT - VEE = 14 V 5, 34 8 V IOUT = -100 mA 6, 8, 35 9, 10, 11 Low Level Output Voltage VOL 0.17 0.5 IOUT = 100 mA 7, 9, 36 26 High Level Input Supply ICC1H 17 22 mA Current VIN+ = VCC1 = 5.5 V, VIN- = 0 V 10, 37 38 Low Level Input Supply ICCIL 6 11 Current VIN+ = VIN- = 0 V, VCC1 = 5.5 V 5 Output Supply Current ICC2 2.5 5 VOUT open 11, 12, 11 39, 40 Low Level Collector Current ICL 0.3 1.0 IOUT = 0 15, 59 27 High Level Collector Current ICH 0.3 1.3 IOUT = 0 15,58 1.8 3.0 IOUT = -650 µA 15,57 VE Low Level Supply Current IEL -0.7 -0.4 0 14, 61 VE High Level Supply Current IEH -0.5 -0.14 0 14, 40 25 Blanking Capacitor ICHG -0.13 -0.25 -0.33 Charging Current -0.18 -0.25 -0.33 VDESAT = 0 - 6 V Blanking Capacitor IDSCHG 10 50 Discharge Current VDESAT = 7 V 42 UVLO Threshold VUVLO+ VOUT > 5 V 43 27 12.3 13.5 VUVLO- 11.1 12.4 VOUT < 5 V UVLO Hysteresis (VUVLO+ - VUVLO-) 0.4 1.2 DESAT Threshold VDESAT 6.5 7.0 7.5 VCC2 - VE > VUVLO- 11.6 V 13, 41 11, 12 VDESAT = 0 - 6 V, TA = 25°C - 100°C 9, 11, 13 9, 11, 14 16, 44 11 Switching Specifications (AC) Unless otherwise noted, all typical values at TA = 25°C, VCC1 = 5 V, and VCC2 - VEE = 30 V, VE - VEE = 0 V; all Minimum/Maximum specifications are at Recommended Operating Conditions. Parameter Symbol Min. Typ. Max. Units Test Conditions Fig. Note VIN to High Level Output tPLH 0.10 0.30 0.50 µs Propagation Delay Time Rg = 10 Cg = 10 nF, 17,18,19, 15 20,21,22, VIN to Low Level Output tPHL 0.10 0.32 0.50 Propagation Delay Time f = 10 kHz, Duty Cycle = 50% 45,54,55 Pulse Width Distortion PWD -0.30 0.02 0.30 16,17 Propagation Delay Difference Between Any Two Parts (tPHL - tPLH) PDD -0.35 0.35 17,18 10% to 90% Rise Time tr 0.1 90% to 10% Fall Time tf 0.1 DESAT Sense to 90% VOUT Delay tDESAT(90%) 0.3 0.5 Rg = 10 , Cg = 10 nF 45 23,56 19 DESAT Sense to 10% VOUT Delay tDESAT(10%) 2.0 3.0 VCC2 - VEE = 30 V 24,28, 46,56 DESAT Sense to Low Level FAULT tDESAT(FAULT) 1.8 5 Signal Delay 25,47, 56 20 DESAT Sense to DESAT Low Propagation Delay 56 21 26,27, 56 22 49 13 tDESAT(LOW) 0.25 RESET to High Level FAULT Signal tRESET(FAULT) 3 7 20 Delay RESET Signal Pulse Width PWRESET UVLO to VOUT High Delay tUVLO ON 4.0 VCC2 = 1.0 ms UVLO to VOUT Low Delay tUVLO OFF 6.0 ramp 14 Output High Level Common Mode |CMH| 15 30 kV/µs Transient Immunity TA = 25°C, VCM = 1500 V, VCC2 = 30 V 23 Output Low Level Common Mode |CML| 15 30 Transient Immunity TA = 25°C, VCM = 1500 V, VCC2 = 30 V 10 0.1 50,51, 52,53 24 Notes: 1. In accordance with UL1577 UL1577, each optocoupler is proof tested by applying an insulation test voltage 4500 Vrms for 1 second (leakage detection current limit, II-O 5 µA). This test is performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-2 Insulation Characteristic Table, if applicable. 2. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table. 3. Device considered a two terminal device: pins 1 - 8 shorted together and pins 9 - 16 shorted together. 4. In order to achieve the absolute maximum power dissipation specified, pins 4, 9, and 10 require ground plane connections and may require airflow. See the Thermal Model section in the application notes at the end of this data sheet for details on how to estimate junction temperature and power dissipation. In most cases the absolute maximum output IC junction temperature is the limiting factor. The actual power dissipation achievable will depend on the application environment (PCB Layout, air flow, part placement, etc.). See the Recommended PCB Layout section in the application notes for layout considerations. Output IC power dissipation is derated linearly at 10 mW/°C above 90°C. Input IC power dissipation does not require derating. 5. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum = 2.0 A. See Applications section for additional details on IOH peak. Derate linearly from 3.0 A at +25°C to 2.5 A at +100°C. This compensates for increased IOPEAK due to changes in VOL over temperature. 6. This supply is optional. Required only when negative gate drive is implemented. 7. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%. 8. See the Slow IGBT Gate Discharge During Fault Condition section in the applications notes at the end of this data sheet for further details. 9. 15 V is the recommended minimum operating positive supply voltage (VCC2 - VE) to ensure adequate margin in excess of the maximum VUVLO+ threshold of 13.5 V. For High Level Output Voltage testing, VOH is measured with a dc load current. When driving capacitive loads, VOH will approach VCC as IOH approaches zero units. 10. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%. 11. Once VOUT of the HCPL-316J HCPL-316J is allowed to go high (VCC2 - VE > VUVLO), the DESAT detection feature of the HCPL-316J HCPL-316J will be the primary source of IGBT protection. UVLO is needed to ensure DESAT is functional. Once VUVLO+ > 11.6 V, DESAT will remain functional until VUVLO- < 12.4 V. Thus, the DESAT detection and UVLO features of the HCPL-316J HCPL-316J work in conjunction to ensure constant IGBT protection. 12. See the Blanking Time Control section in the applications notes at the end of this data sheet for further details. 13. This is the "increasing" (i.e. turn-on or "positive going" direction) of VCC2-VE. 14. This is the "decreasing" (i.e. turn-off or "negative going" direction) of VCC2-VE. 15. This load condition approximates the gate load of a 1200 V/75A IGBT. 16. Pulse Width Distortion (PWD) is defined as |tPHL - tPLH| for any given unit. 17. As measured from VIN+, VIN- to VOUT. 18. The difference between tPHL and tPLH between any two HCPL-316J HCPL-316J parts under the same test conditions. 19. Supply Voltage Dependent. 20. This is the amount of time from when the DESAT threshold is exceeded, until the FAULT output goes low. 21. This is the amount of time the DESAT threshold must be exceeded before VOUT begins to go low, and the FAULT output to go low. 22. This is the amount of time from when RESET is asserted low, until FAULT output goes high. The minimum specification of 3 µs is the guaranteed minimum FAULT signal pulse width when the HCPL-316J HCPL-316J is configured for Auto-Reset. See the Auto-Reset section in the applications notes at the end of this data sheet for further details. 23. Common mode transient immunity in the high state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15 V or FAULT > 2 V). A 100 pF and a 3K pull-up resistor is needed in fault detection mode. 24. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VO < 1.0 V or FAULT < 0.8 V). 25. Does not include LED2 current during fault or blanking capacitor discharge current. 26. To clamp the output voltage at VCC - 3 VBE, a pull-down resistor between the output and VEE is recommended to sink a static current of 650 µA while the output is high. See the Output Pull-Down Resistor section in the application notes at the end of this data sheet if an output pulldown resistor is not used. 27. The recommended output pull-down resistor between VOUT and VEE does not contribute any output current when VOUT = VEE. 28. In most applications VCC1 will be powered up first (before VCC2) and powered down last (after VCC2). This is desirable for maintaining control of the IGBT gate. In applications where VCC2 is powered up first, it is important to ensure that Vin+ remains low until VCC1 reaches the proper operating voltage (minimum 4.5 V) to avoid any momentary instability at the output during VCC1 ramp-up or ramp-down. 11 Performance Plots IOL ­ OUTPUT LOW CURRENT 1.6 1.4 1.2 1.0 -40 -20 0 20 40 60 80 5 VOUT = VEE + 15 V VOUT = VEE + 2.5 V 4 3 2 1 0 -40 -20 100 0 Figure 3. IOH vs. temperature. 80 100 -1 -2 -3 0 20 40 60 80 IOUT = 100 mA 0.15 0.10 0.05 0 -40 -20 100 0 20 40 60 80 100 ICC1 ­ SUPPLY CURRENT ­ mA 3 2 1 2.0 IOL ­ OUTPUT LOW CURRENT ­ A HCPL-316J HCPL-316J fig 9 5 10 2.5 15 20 25 30 +100°C +25°C -40°C 28.8 28.6 28.4 28.2 28.0 27.8 27.6 27.4 0 0.2 HCPL-316J HCPL-316J fig 7 4 Figure 9: VOL vs. IOL. 0 ICC1H ICC1L 10 5 0 20 0.6 0.8 1.0 HCPL-316J HCPL-316J fig 08 15 0 -40 -20 0.4 Figure 8. VOH vs. IOH. 20 1.5 25 IOH ­ OUTPUT HIGH CURRENT ­ A Figure 7. VOL vs. temperature. +100°C +25°C -40°C 1.0 50 TA ­ TEMPERATURE ­ °C 6 0.5 -40°C 25°C 100°C 75 HCPL-316J HCPL-316J fig 5 0.20 HCPL-316J HCPL-316J fig 6 0 0.1 100 29.0 TA ­ TEMPERATURE ­ °C 5 125 Figure 5. IOLF vs. VOUT. VOH ­ OUTPUT HIGH VOLTAGE ­ V IOUT = -650 µA IOUT = -100 mA -4 -40 -20 150 VOUT ­ OUTPUT VOLTAGE ­ V 0.25 0 VOL ­ OUTPUT LOW VOLTAGE ­ V (VOH -VCC) ­ HIGH OUTPUT VOLTAGE DROP ­ V 60 175 HCPL-316J HCPL-316J fig 4 Figure 6. VOH vs. temperature. VOL ­ OUTPUT LOW VOLTAGE ­ V 40 Figure 4. IOL vs. temperature. HCPL-316J HCPL-316J fig 3 12 20 200 TA ­ TEMPERATURE ­ °C TA ­ TEMPERATURE ­ °C 40 60 80 TA ­ TEMPERATURE ­ °C Figure 10. ICC1 vs. temperature. HCPL-316J HCPL-316J fig 10 100 ICC2 ­ OUTPUT SUPPLY CURRENT ­ mA IOH ­ OUTPUT HIGH CURRENT ­ A 1.8 6 IOLF ­ LOW LEVEL OUTPUT CURRENT DURING FAULT CONDITION ­ mA 7 2.0 2.6 2.5 2.4 ICC2H ICC2L 2.3 2.2 -40 -20 0 20 40 60 80 TA ­ TEMPERATURE ­ °C Figure 11: ICC2 vs. t emperature. HCPL-316J HCPL-316J fig 11 100 2.55 2.50 2.45 ICC2H ICC2L 2.40 2.35 15 20 25 0.50 IE -VE SUPPLY CURRENT ­ mA ICHG ­ BLANKING CAPACITOR CHARGING CURRENT ­ mA -0.20 -0.25 -0.30 -40 -20 30 Figure 12. ICC2 vs. VCC2. 0 2 -40°C +25°C +100°C 1 0 0.5 1.0 1.5 2.0 6.0 -40 -20 0.45 PROPAGATION DELAY ­ µs tPHL tPLH 0.35 0.30 0.25 25 30 VCC ­ SUPPLY VOLTAGE ­ V Figure 18. Propagation delay vs. supply voltage. 0.40 0 20 40 60 80 80 100 0.4 0.3 0.2 -40 -20 100 20 40 60 80 100 Figure 17. Propagation delay vs. temperature. HCPL-316J HCPL-316J fig 17 0.50 VCC1 = 5.5 V VCC1 = 5.0 V VCC1 = 4.5 V 0.30 0 0 TA ­ TEMPERATURE ­ °C 0.35 0.25 -50 60 tPHL tPLH HCPL-316J HCPL-316J fig 16 0.40 40 0.5 6.5 HCPL-316J HCPL-316J fig 15 20 HCPL-316J HCPL-316J fig 14 Figure 16. DESAT threshold vs. temperature. HCPL-316J HCPL-316J fig 18 0 Figure 14. IE vs. temperature. TA ­ TEMPERATURE ­ °C Figure 15. IC vs. IOUT. 20 0.35 TA ­ TEMPERATURE ­ °C 7.0 IOUT (mA) 0.20 15 0.40 0.30 -40 -20 100 TP ­ PROPAGATION DELAY ­ µs VDESAT ­ DESAT THRESHOLD ­ V IC (mA) 80 7.5 3 TP ­ PROPAGATION DELAY ­ µs 60 0.45 HCPL-316J HCPL-316J fig 13 4 13 40 Figure 13. ICHG vs. temperature. HCPL-316J HCPL-316J fig 12 0 20 IEH IEL TA ­ TEMPERATURE ­ °C VCC2 ­ OUTPUT SUPPLY VOLTAGE ­ V PROPAGATION DELAY ­ µs ICC2 ­ OUTPUT SUPPLY CURRENT ­ mA -0.15 2.60 50 TEMPERATURE ­ °C Figure 19. VIN to high propagation delay vs. temperature. HCPL-316J HCPL-316J fig 19 100 0.45 VCC1 = 5.5 V VCC1 = 5.0 V VCC1 = 4.5 V 0.40 0.35 0.30 0.25 -50 0 50 TEMPERATURE ­ °C Figure 20. VIN to low propagation delay vs. temperature. HCPL-316J HCPL-316J fig 20 100 0.40 0.45 0.40 tPLH tPHL tPLH tPHL 0.25 DELAY ­ µs 0.30 0.30 0 20 40 60 80 0.20 100 0 Figure 21. Propagation delay vs. load capacitance. HCPL-316J HCPL-316J fig 21 2.4 DELAY ­ µs 2.0 1.5 0.25 -50 50 50 VCC2 = 15 V VCC2 = 30 V 0.006 2.0 0 50 100 12 VCC1 = 5.5 V VCC1 = 5.0 V VCC1 = 4.5 V VCC2 = 15 V VCC2 = 30 V 10 DELAY ­ µs 0.0025 0.0020 8 6 0.0015 20 30 40 50 LOAD RESISTANCE ­ Figure 27. DESAT sense to 10% Vout delay vs. load resistance. HCPL-316J HCPL-316J fig 27 4 -50 0 50 100 150 TEMPERATURE ­ °C Figure 28. RESET to high level fault signal delay vs. temperature. HCPL-316J HCPL-316J fig 28 0 0 10 20 30 40 50 LOAD CAPACITANCE ­ nF Figure 25. DESAT sense to low level fault signal delay vs. temperature. HCPL-316J HCPL-316J fig 25 0.0030 0.004 0.002 TEMPERATURE ­ °C Figure 24. DESAT sense to 10% Vout delay vs. temperature. HCPL-316J HCPL-316J fig 24 100 0.008 1.6 -50 100 50 Figure 23. DESAT sense to 90% Vout delay vs. temperature. HCPL-316J HCPL-316J fig 23 VEE = 0 V VEE = -5 V VEE = -10 V VEE = -15 V 1.8 0 0 TEMPERATURE ­ °C 2.2 TEMPERATURE ­ °C DELAY ­ µs 40 2.6 2.5 14 30 HCPL-316J HCPL-316J fig 22 VCC2 = 15 V VCC2 = 30 V 0.0010 10 20 Figure 22. Propagation delay vs. load resistance. 3.0 DELAY ­ µs 10 LOAD RESISTANCE ­ LOAD CAPACITANCE ­ nF 1.0 -50 0.35 0.30 0.25 DELAY ­ ms 0.20 0.40 0.35 DELAY ­ µs DELAY ­ µs 0.35 Figure 26. DESAT sense to 10% Vout delay vs. load capacitance. HCPL-316J HCPL-316J fig 26 Test Circuit Diagrams VLED2+ VE VIN- VLED2+ DESAT VCC1 DESAT VCC2 GND1 VCC2 RESET FAULT + ­ VOUT VLED1- 5V VC VLED1+ RESET VC FAULT VOUT VEE VLED1+ VEE VEE VLED1- VEE 5V IFAULT Figure 30. IFAULTL test circuit. Figure 31. IFAULTH test circuit. HCPL-316J HCPL-316J fig 30 VLED2+ DESAT VCC2 RESET VC FAULT VOUT VLED1+ VIN- + ­ DESAT GND1 VCC2 RESET VLED1+ + ­ 30 V 0.1 µF Figure 32. IOH pulsed test circuit. VEE VEE VIN+ VE VIN- DESAT GND1 0.1 µF VLED2+ VCC1 VCC2 RESET VC FAULT VOUT VLED1+ VEE Figure 34. IOLF test circuit. 30 V VE VIN- VLED2+ DESAT GND1 + ­ 0.1 µF VIN+ VCC1 5V 0.1 µF VEE VLED1- 15 30 V + 15 V ­ PULSED HCPL-316J HCPL-316J fig 33 + ­ 5V 0.1 µF + ­ IOUT Figure 33. IOL pulsed test circuit. HCPL-316J HCPL-316J fig 32 + ­ 0.1 µF VOUT VLED1- IOUT 30 V 0.1 µF VC FAULT VEE 15 V PULSED 0.1 µF VLED2+ VCC1 30 V 0.1 µF VEE VLED1- 0.1 µF + ­ 0.1 µF VIN- GND1 + ­ HCPL-316J HCPL-316J fig 31 VE VIN+ VE VCC1 5V VIN+ VCC2 RESET + ­ IOUT + ­ 14 V 0.1 µF 30 V VOUT VLED1+ VEE VLED1- VEE Figure 35. VOH pulsed test circuit. HCPL-316J HCPL-316J fig 34 HCPL-316J HCPL-316J fig 35 30 V 0.1 µF VC FAULT 0.1 µF + ­ IFAULT 0.1 µF 10 mA + ­ ­ + VIN- VIN+ 0.1 µF + ­ 0.4 V VE GND1 + ­ VIN+ VCC1 4.5 V 0.1 µF + ­ VOUT 2A PULSED 0.1 µF 30 V VLED2+ DESAT VCC2 RESET VIN+ 0.1 µF VOUT VLED1+ VEE VLED1- + ­ VEE VOUT VOUT VEE VLED1- VEE Figure 37. ICC1H test circuit. HCPL-316J HCPL-316J fig 37 VLED2+ VCC1 DESAT GND1 VCC2 5V + ­ VIN+ VE VIN- VLED2+ VCC1 DESAT GND1 0.1 µF VCC2 RESET VC RESET VOUT FAULT VOUT VLED1+ VEE VLED1+ VEE VLED1- VEE Figure 38. ICC1L test circuit. VCC1 DESAT GND1 VCC2 RESET VOUT VLED1+ VLED1- 5V 30 V 0.1 µF + ­ VE VIN- VLED2+ VCC1 DESAT GND1 0.1 µF ICC2 VC FAULT VIN+ 0.1 µF + ­ VLED2+ VCC2 RESET FAULT VOUT VEE VLED1+ VEE VEE VLED1- VEE ICHG 0.1 µF + ­ 0.1 µF 30 V Figure 41. ICHG pulsed test circuit. HCPL-316J HCPL-316J fig 40 HCPL-316J HCPL-316J fig 41 30 V 0.1 µF VC Figure 40. ICC2L test circuit. 30 V HCPL-316J HCPL-316J fig 39 VE VIN- + ­ + ­ VIN+ 0.1 µF Figure 39. ICC2H test circuit. HCPL-316J HCPL-316J fig 38 16 0.1 µF VEE VLED1- 30 V ICC2 VC FAULT 0.1 µF + ­ VE VINICC1 VC VLED1+ 0.1 µF VIN+ + ­ VCC2 FAULT 30 V HCPL-316J HCPL-316J fig 36 5.5 V DESAT RESET + ­ Figure 36. VOL test circuit. 0.1 µF VCC1 ICC1 VLED2+ GND1 5.5 V 30 V VE VIN- 0.1 µF 0.1 µF 100 mA VC FAULT + ­ GND1 + ­ VE VINVCC1 5V VIN+ 0.1 µF 0.1 µF + ­ 30 V VLED2+ VCC1 DESAT GND1 + ­ 0.1 µF IDSCHG VCC2 RESET 0.1 µF VLED2+ DESAT GND1 + ­ 5V 30 V VE VIN- 0.1 µF VCC2 RESET VC + ­ FAULT VOUT VEE VLED1+ VEE VLED1- VEE VOUT VLED1- 0.1 µF 30 V Figure 42. IDSCHG test circuit. Figure 43. UVLO threshold test circuit. HCPL-316J HCPL-316J fig 42 VCC1 DESAT GND1 SWEEP 0.1 µF 15 V VCC2 RESET VC FAULT VOUT VLED1+ VLED1- 0.1 µF HCPL-316J HCPL-316J fig 43 VE VLED2+ VCC1 DESAT GND1 5V VIN+ VIN- 0.1 µF + ­ VLED2+ + ­ VIN- VIN VE + ­ VIN+ VCC2 RESET FAULT VLED1+ VEE VEE VLED1- VEE + ­ 0.1 µF 15 V 3k VE VIN- VLED2+ VCC1 VCC2 RESET VC FAULT VOUT VLED1+ VEE VLED1- VEE Figure 46. tDESAT(10%) test circuit. HCPL-316J HCPL-316J fig 46 17 VIN 0.1 µF DESAT GND1 3k VOUT 10 + ­ 30 V 10 nF HCPL-316J HCPL-316J fig 45 VOUT 10 10 nF + ­ 5V + ­ 0.1 µF Figure 45. tPLH, tPHL, tr, tf test circuit. HCPL-316J HCPL-316J fig 44 VIN+ 30 V 0.1 µF VOUT VEE 0.1 µF VC Figure 44. DESAT threshold test circuit. 0.1 µF 0.1 µF 0.1 µF 30 V 0.1 µF + ­ VIN- DESAT VCC2 RESET FAULT VOUT VEE VLED1- VEE VIN VC VLED1+ VFAULT 30 V VLED2+ VCC1 3k VE GND1 5V + ­ VIN+ 0.1 µF Figure 47. tDESAT(FAULT) test circuit. HCPL-316J HCPL-316J fig 47 0.1 µF 0.1 µF 10 10 nF + ­ VLED1+ 0.1 µF VOUT VEE FAULT 10 mA SWEEP + ­ VC + ­ VIN- 7V VIN+ VCC1 VE + ­ VIN+ 30 V 0.1 µF + ­ 30 V VIN- 3k DESAT GND1 VIN HIGH TO LOW VLED2+ VCC1 + ­ VE VCC2 RESET VFAULT 0.1 STROBE µF 8V GND1 30 V 3k 10 nF VOUT VEE VEE VIN+ VE VIN- VLED2+ 3 VCC1 DESAT 14 4 GND1 VCC2 RESET VC VLED1+ VEE 0.1 µF 10 8 VLED1 VEE VCC1 DESAT 14 GND1 VCC2 13 RESET VC 12 FAULT VOUT 11 7 25 V SCOPE 11 7 VLED1+ VEE 10 9 10 VLED1 VEE 9 10 nF 0.1 µF 10 10 nF 9V VCm Figure 50. CMR test circuit, LED2 off. Figure 51. CMR test circuit, LED2 on. HCPL-316J HCPL-316J fig 50 VE 16 2 VIN- VLED2+ 3 VCC1 DESAT VCC2 0.1 µF 0.1 µF 13 3 k 16 2 VIN- 15 3 VCC1 DESAT 14 4 GND1 VCC2 13 RESET VC 12 FAULT VOUT 11 7 VLED1+ VEE 10 8 25 V VE HCPL-316J HCPL-316J fig 51 VLED2+ 6 5V VIN+ 5 14 GND1 1 15 4 25 V 750 VCm 0.1 µF 15 + ­ VOUT VLED2+ VIN- 3 k 100 pF FAULT 16 6 12 6 VE HCPL-316J HCPL-316J fig 49 8 13 5 VIN+ 4 0.1 µF 3 k 5V 10 nF 5 15 VIN+ RAMP 10 3 16 2 1 0.1 µF VOUT 2 5V 1 100 pF VC Figure 49. UVLO delay test circuit. 1 SCOPE VCC2 FAULT VEE 10 HCPL-316J HCPL-316J fig 48 0.1 µF DESAT VLED1+ + ­ Figure 48. tRESET(FAULT) test circuit. 5V VLED2+ VLED1- VEE VLED1- VINVCC1 + ­ 5V VE RESET 0.1 µF VOUT VLED1+ 30 V VIN+ 0.1 µF 0.1 µF VC FAULT + ­ 5V VIN+ 0.1 µF VLED1 VEE 9 3 k 5 RESET VC 12 6 FAULT VOUT 11 7 VLED1+ VEE 10 8 VLED1 VEE 9 25 V 0.1 µF SCOPE 100 pF 10 10 nF 100 pF VCm VCm Figure 52. CMR test circuit, LED1 off. 18 Figure 53. CMR test circuit, LED1 on. SCOPE 10 10 nF VINVIN- VIN+ 2.5 V 0V 2.5 V VIN+ 2.5 V 5.0 V 2.5 V tr tf tr tf 90% 90% 50% 50% 10% VOUT tPLH 10% VOUT tPHL tPLH Figure 54. VOUT propagation delay waveforms, noninverting configuration. tPHL Figure 55. VOUT propagation delay waveforms, inverting configuration. tDESAT (FAULT) HCPL-316J HCPL-316J fig 54 tDESAT (10%) HCPL-316J HCPL-316J fig 55 tDESAT (LOW) 7V VDESAT 50% tDESAT (90%) VOUT 90% 10% FAULT 50% (2.5 V) tRESET (FAULT) RESET 50% Figure 56. Desat, VOUT, fault, reset delay waveforms. HCPL-316J HCPL-316J fig 56 19 VIN- VLED2+ VCC1 DESAT GND1 0.1 µF RESET VLED1- 0.1 µF VOUT VLED1+ 30 V IC VC FAULT VIN- 0.1 µF VE VLED2+ DESAT GND1 + ­ VIN+ VCC1 5V VCC2 + ­ VCC2 RESET VLED1+ VEE VEE VLED1- VEE + ­ 0.1 µF 650 µA 30 V Figure 57. ICH test circuit. VCC1 DESAT GND1 0.1 µF + ­ VLED2+ VC 0.1 µF IC VE VIN- VLED2+ DESAT GND1 + ­ VIN+ VCC1 5V 0.1 µF 30 V VCC2 RESET RESET + ­ FAULT VOUT VLED1+ VEE VLED1+ VEE VLED1- VEE VLED1- VEE 30 V Figure 59. ICL test circuit. Figure 60. IEH test circuit. HCPL-316J HCPL-316J fig 60 HCPL-316J HCPL-316J fig 59 VLED2+ DESAT VCC2 RESET VOUT VLED1+ VEE VLED1- VEE 0.1 µF Figure 61. IEL test circuit. HCPL-316J HCPL-316J fig 61 30 V 0.1 µF VC FAULT 20 IE + ­ VIN- GND1 0.1 µF VE VCC1 + ­ VIN+ 0.1 µF + ­ 30 V 0.1 µF 30 V 0.1 µF VC VOUT 0.1 µF IE VCC2 FAULT 5V 30 V HCPL-316J HCPL-316J fig 58 VE VIN- + ­ 0.1 µF Figure 58. ICH test circuit. HCPL-316J HCPL-316J fig 57 VIN+ 0.1 µF VOUT VEE 30 V IC VC FAULT 0.1 µF + ­ + ­ VE + ­ 5V VIN+ 0.1 µF 0.1 µF + ­ 30 V Typical Application/Operation Introduction to Fault Detection and Protection The power stage of a typical three phase inverter is susceptible to several types of failures, most of which are potentially destructive to the power IGBTs. These failure modes can be grouped into four basic categories: phase and/or rail supply short circuits due to user misconnect or bad wiring, control signal failures due to noise or computational errors, overload conditions induced by the load, and component failures in the gate drive circuitry. Under any of these fault conditions, the current through the IGBTs can increase rapidly, causing excessive power dissipation and heating. The IGBTs become damaged when the current load approaches the saturation current of the device, and the collector to emitter voltage rises above the saturation voltage level. The drastically increased power dissipation very quickly overheats the power device and destroys it. To prevent damage to the drive, fault protection must be implemented to reduce or turnoff the overcurrents during a fault condition. A circuit providing fast local fault detection and shutdown is an ideal solution, but the number of required components, board space consumed, cost, and complexity have until now limited its use to high performance drives. The features which this circuit must have are high speed, low cost, low resolution, low power dissipation, and small size. Applications InformationThe HCPL316J HCPL316J satisfies these criteria by combining a high speed, high output current driver, high voltage optical isolation between the input and output, local IGBT desaturation detection and shut down, and an optically isolated fault status feedback signal into a single 16pin surface mount package. The fault detection method, which is adopted in the HCPL316J HCPL316J, is to monitor the saturation (collector) voltage of the IGBT and to trigger a local fault shutdown sequence if the collector voltage exceeds a predetermined threshold. A small gate discharge device slowly reduces the high short circuit IGBT current to prevent damaging voltage spikes. Before the dissipated energy can reach destructive levels, the IGBT is shut off. During the off state of the IGBT, the fault detect circuitry is simply disabled to prevent false `fault' signals. 21 The alternative protection scheme of measuring IGBT current to prevent desaturation is effective if the short circuit capability of the power device is known, but this method will fail if the gate drive voltage decreases enough to only partially turn on the IGBT. By directly measuring the collector voltage, the HCPL316J HCPL316J limits the power dissipation in the IGBT even with insufficient gate drive voltage. Another more subtle advantage of the desaturation detection method is that power dissipation in the IGBT is monitored, while the current sense method relies on a preset current threshold to predict the safe limit of operation. Therefore, an overly- conservative overcurrent threshold is not needed to protect the IGBT. Recommended Application Circuit The HCPL316J HCPL316J has both inverting and noninverting gate control inputs, an active low reset input, and an open collector fault output suitable for wired `OR' applications. The recommended application circuit shown in Figure 62 illustrates a typical gate drive implementation using the HCPL316J HCPL316J. The four supply bypass capacitors (0.1 µF) provide the large transient currents necessary during a switching transition. Because of the transient nature of the charging currents, a low current (5 mA) power supply suffices. The desat diode and 100 pF capacitor are the necessary external components for the fault detection circuitry. The gate resistor (10 ) serves to limit gate charge current and indirectly control the IGBT collector voltage rise and fall times. The open collector fault output has a passive 3.3 k pullup resistor and a 330 pF filtering capacitor. A 47 k pulldown resistor on VOUT provides a more predictable high level output voltage (VOH). In this application, the IGBT gate driver will shut down when a fault is detected and will not resume switching until the microcontroller applies a reset signal. HCPL-316J HCPL-316J 1 5V + ­ 3.3 k 16 VIN- VLED2+ 15 3 0.1 µF VE 2 µC VIN+ VCC1 DESAT 14 4 GND1 VCC2 5 VC 6 VOUT DDESAT 100 + 11 7 VLED1+ VEE 10 8 330 pF 100 pF 12 FAULT 0.1 µF VF ­ 13 RESET 0.1 µF VLED1- VEE + ­ VCC2 = 18 V Q1 VCE Rg 47 k ­ 0.1 µF 9 + ­ + 3-PHASE OUTPUT VEE = -5 V Q2 + VCE ­ Figure 62. Recommended application circuit. Description of Operation/Timing Fault Condition Figure 63 below illustrates input and output waveforms under the conditions of normal operation, a desat fault condition, and normal reset behavior. When the voltage on the DESAT pin exceeds 7V while the IGBT is on, VOUT is slowly brought low in order to "softly" turn-off the IGBT and prevent large di/dt induced voltages. Also activated is an internal feedback channel which brings the FAULT output low for the purpose of notifying the micro-controller of the fault condition. See Figure 63. Normal Operation During normal operation, VOUT of the HCPL-316J HCPL-316J is controlled by either VIN+ or VIN-, with the IGBT collector-toemitter voltage being monitored through DDESAT. The FAULT output is high and the RESET input should be held high. See Figure63. NORMAL OPERATION VINNON-INVERTING CONFIGURED INPUTS 0V 5V VIN+ VIN- INVERTING CONFIGURED INPUTS FAULT CONDITION 5V VIN+ 5V VDESAT 7V VOUT FAULT RESET Figure 63. Timing diagram. HCPL-316J HCPL-316J fig 63 22 Reset The FAULT output remains low until RESET is brought low. See Figure 63. While asserting the RESET pin (LOW), the input pins must be asserted for an output low state (VIN+ is LOW or VIN- is HIGH). This may be accomplished either by software control (i.e. of the microcontroller) or hardware control (see Figures 73 and 74). RESET Slow IGBT Gate Discharge During Fault Condition Under Voltage Lockout When a desaturation fault is detected, a weak pull-down device in the HCPL-316J HCPL-316J output drive stage will turn on to `softly' turn off the IGBT. This device slowly discharges the IGBT gate to prevent fast changes in drain current that could cause damaging voltage spikes due to lead and wire inductance. During the slow turn off, the large output pull-down device remains off until the output voltage falls below VEE + 2 Volts, at which time the large pull down device clamps the IGBT gate to VEE. The HCPL-316J HCPL-316J Under Voltage Lockout (UVLO) feature is designed to prevent the application of insufficient gate voltage to the IGBT by forcing the HCPL-316J HCPL-316J output low during power-up. IGBTs typically require gate voltages of 15 V to achieve their rated VCE(ON) voltage. At gate voltages below 13 V typically, their on-voltage increases dramatically, especially at higher currents. At very low gate voltages (below 10 V), the IGBT may operate in the linear region and quickly overheat. The UVLO function causes the output to be clamped whenever insufficient operating supply (VCC2) is applied. Once VCC2 exceeds VUVLO+ (the positive-going UVLO threshold), the UVLO clamp is released to allow the device output to turn on in response to input signals. As VCC2 is increased from 0 V (at some level below VUVLO+), first the DESAT protection circuitry becomes active. As VCC2 is further increased (above VUVLO+), the UVLO clamp is released. Before the time the UVLO clamp is released, the DESAT protection is already active. Therefore, the UVLO and DESAT FAULT DETECTION features work together to provide seamless protection regardless of supply voltage (VCC2). DESAT Fault Detection Blanking Time The DESAT fault detection circuitry must remain disabled for a short time period following the turn-on of the IGBT to allow the collector voltage to fall below the DESAT theshold. This time period, called the DESAT blanking time, is controlled by the internal DESAT charge current, the DESAT voltage threshold, and the external DESAT capacitor. The nominal blanking time is calculated in terms of external capacitance (CBLANK), FAULT threshold voltage (VDESAT ), and DESAT charge current (ICHG) as tBLANK = CBLANK x VDESAT/ICHG. The nominal blanking time with the recommended 100 pF capacitor is 100pF*7V / 250µA = 2.8 µsec. The capacitance value can be scaled slightly to adjust the blanking time, though a value smaller than 100 pF is not recommended. This nominal blanking time also represents the longest time it will take for the HCPL316J HCPL316J to respond to a DESAT fault condition. If the IGBT is turned on while the collector and emitter are shorted to the supply rails (switching into a short), the soft shutdown sequence will begin after approximately 3 µsec. If the IGBT collector and emitter are shorted to the supply rails after the IGBT is already on, the response time will be much quicker due to the parasitic parallel capacitance of the DESAT diode. The recommended 100 pF capacitor should provide adequate blanking as well as fault response times for most applications. 23 Behavioral Circuit Schematic Output IC The functional behavior of the HCPL-316J HCPL-316J is represented by thelogicdiagram in Figure 64 which fully describes the interaction and sequence of internal and external signals in the HCPL-316J HCPL-316J. Three internal signals control the state of the driver output: the state of the signal LED, as well as the UVLO and Fault signals. If no fault on the IGBT collector is detected, and the supply voltage is above the UVLO threshold, the LED signal will control the driver output state. The driver stage logic includes an interlock to ensure that the pull-up and pull-down devices in the output stage are never on at the same time. If an undervoltage condition is detected, the output will be actively pulled low by the 50x DMOS device, regardless of the LED state. If an IGBT desaturation fault is detected while the signal LED is on, the Fault signal will latch in the high state. The triple darlington AND the 50x DMOS device are disabled, and a smaller 1x DMOS pulldown device is activated to slowly discharge the IGBT gate. When the output drops below two volts, the 50x DMOS device again turns on, clamping the IGBT gate firmly to Vee. The Fault signal remains latched in the high state until the signal LED turns off. Input IC In the normal switching mode, no output fault has been detected, and the low state of the fault latch allows the input signals to control the signal LED. The fault output is in the opencollector state, and the state of the Reset pin does not affect the control of the IGBT gate. When a fault is detected, the FAULT output and signal input are both latched. The fault output changes to an active low state, and the signal LED is forced off (output LOW). The latched condition will persist until the Reset pin is pulled low. 250 µA ­ LED VCC1 (3) UVLO DELAY 7V VCC2 (13) ­ + 12 V VC (12) FAULT FAULT (6) DESAT (14) + VIN+ (1) VIN­ (2) GND (4) VE (16) Q VOUT (11) R S RESET (5) 50 x FAULT VEE (9,10) 1x Figure 64. Behavioral circuit schematic. HCPL-316J HCPL-316J fig 64 24 HCPL-316J HCPL-316J 1 VIN+ 2 VIN- 3 VCC1 4 GND1 5 RESET 6 FAULT 7 VLED1+ 8 VLED1- HCPL-316J HCPL-316J VE HCPL-316J HCPL-316J 16 VE 16 VLED2+ 15 VLED2+ 15 DESAT 14 DESAT 14 VCC2 13 VCC2 13 VC 12 VC 12 VOUT 11 VOUT 11 VEE 10 VEE 10 VEE 9 VEE 9 Rg RPULL-DOWN Figure 65. Output pull-down resistor. 100 pF µC 100 DDESAT Rg Figure 66. DESAT pin protection. 3.3 k + ­ 330 pF Figure 67. FAULT pin CMR protection. HCPL-316J HCPL-316J fig 67 HCPL-316J HCPL-316J fig 66-new HCPL-316J HCPL-316J fig 65 Other Recommended Components Capacitor on FAULT Pin for High CMR The application circuit in Figure 62 includes an output pull-down resistor, a DESAT pin protection resistor, a FAULT pin capacitor (330 pF), and a FAULT pin pull-up resistor. Rapid common mode transients can affect the fault pin voltage while the fault output is in the high state. A 330pF capacitor (Fig. 66) should be connected between the fault pin and ground to achieve adequate CMOS noise margins at the specified CMR value of 15kV/µs. The added capacitance does not increase the fault output delay when a desaturation condition is detected. Output Pull-Down Resistor During the output high transition, the output voltage rapidly rises to within 3 diode drops of VCC2. If the output current then drops to zero due to a capacitive load, the output voltage will slowly rise from roughly VCC2-3(VBE) to VCC2 within a period of several microseconds. To limit the output voltage to VCC2-3(VBE), a pull-down resistor between the output and VEE is recommended to sink a static current of several 650 µA while the output is high. Pull-down resistor values are dependent on the amount of positive supply and can be adjusted according to the formula, Rpull-down = [VCC2-3*(VBE)]/650 µA. DESAT Pin Protection The freewheeling of flyback diodes connected across the IGBTs can have large instantaneous forward voltage transients which greatly exceed the nominal forward voltage of the diode. This may result in a large negative voltage spike on the DESAT pin which will draw substantial current out of the IC if protection is not used. To limit this current to levels that will not damage the IC, a 100 ohm resistor should be inserted in series with the DESAT diode. The added resistance will not alter the DESAT threshold or the DESAT blanking time. 25 Pull-up Resistor on FAULT Pin The FAULT pin is an open-collector output and therefore requires a pull-up resistor to provide a high-level signal. Driving with Standard CMOS/TTL for High CMR Capacitive coupling from the isolated high voltage circuitry to the input referred circuitry is the primary CMR limitation. This coupling must be accounted for to achieve high CMR performance. The input pins VIN+ and VIN- must have active drive signals to prevent unwanted switching of the output under extreme common mode transient conditions. Input drive circuits that use pull-up or pull-down resistors, such as open collector configurations, should be avoided. Standard CMOS or TTL drive circuits are recommended. User-Configuration of the HCPL-316J HCPL-316J Input Side The VIN+, VIN-, FAULT and RESET input pins make a wide variety of gate control and fault configurations possible, depending on the motor drive requirements. The HCPL316J HCPL316J has both inverting and noninverting gate control inputs, an open collector fault output suitable for wired `OR' applications and an active low reset input. HCPL-316J HCPL-316J 1 2 The Gate Drive Voltage Output of the HCPL316J HCPL316J can be configured as inverting or noninverting using the VIN­ and VIN+ inputs. As shown in Figure 68, when a noninverting configuration is desired, VIN­ is held low by connecting it to GND1 and VIN+ is toggled. As shown in Figure69, when an inverting configuration is desired, VIN+ is held high by connecting it to VCC1 and VIN­ is toggled. RESET 6 FAULT 7 VLED1+ 8 VLED1- Figure 68. Typical input configuration, noninverting. HCPL-316J HCPL-316J fig 68 HCPL-316J HCPL-316J 1 VIN- 3 VCC1 4 GND1 5 RESET 6 FAULT 7 VLED1+ 8 + ­ µC VIN+ 2 Global-Shutdown, Global Reset As shown in Figure 71, when configured for inverting operation, the HCPL-316J HCPL-316J can be configured to shutdown automatically in the event of a fault condition by tying the FAULT output to VIN+. For high reliability drives, the open collector FAULT outputs of each HCPL-316J HCPL-316J can be wire `OR'ed together on a common fault bus, forming a single fault bus for interfacing directly to the micro-controller. When any of the six gate drivers detects a fault, the fault output signal will disable all six HCPL-316J HCPL-316J gate drivers simultaneously and thereby provide protection against further catastrophic failures. GND1 5 Local Shutdown, Local Reset As shown in Figure 70, the fault output of each HCPL316J HCPL316J gate driver is polled separately, and the individual reset lines are asserted low independently to reset the motor controller after a fault condition. VCC1 4 Driving Input pf HCPL-316J HCPL-316J in NonInverting/Inverting Mode VIN- 3 + ­ µC VIN+ VLED1- Figure 69. Typical Input Configuration, Inverting. HCPL-316J HCPL-316J fig 69 HCPL-316J HCPL-316J 1 2 3 VCC1 4 GND1 RESET 6 FAULT 7 VLED1+ 8 + ­ VIN- 5 µC VIN+ VLED1- Figure 70. Local shutdown, local reset configuration. HCPL-316J HCPL-316J fig 70 26 Auto-Reset Resetting Following a Fault Condition As shown in Figure 72, when the inverting VIN- input is connected to ground (noninverting configuration), the HCPL316J HCPL316J can be configured to reset automatically by connecting RESET to VIN+. In this case, the gate control signal is applied to the noninverting input as well as the reset input to reset the fault latch every switching cycle. During normal operation of the IGBT, asserting the reset input low has no effect. Following a fault condition, the gate driver remains in the latched fault state until the gate control signal changes to the `gate low' state and resets the fault latch. If the gate control signal is a continuous PWM signal, the fault latch will always be reset by the next time the input signal goes high. This configuration protects the IGBT on a cyclebycycle basis and automatically resets before the next `on' cycle. The fault outputs can be wire `OR'ed together to alert the microcontroller, but this signal would not be used for control purposes in this (AutoReset) configuration. When the HCPL 316J is configured for AutoReset, the guaranteed minimum FAULT signal pulse width is 3 µs. To resume normal switching operation following a fault condition (FAULT output low), the RESET pin must first be asserted low in order to release the internal fault latch and reset the FAULT output (high). Prior to asserting the RESET pin low, the input (VIN) switching signals must be configured for an output (VOL) low state. This can be handled directly by the microcontroller or by hardwiring to synchronize the RESET signal with the appropriate input signal. Figure 73a shows how to connect the RESET to the VIN+ signal for safe automatic reset in the noninverting input configuration. Figure 73b shows how to configure the VIN+/RESET signals so that a RESET signal from the microcontroller causes the input to be in the "output-off" state. Similarly, Figures 73c and 73d show automatic RESET and microcontroller RESET safe configurations for the inverting input configuration. HCPL-316J HCPL-316J HCPL-316J HCPL-316J 1 3 6 7 8 CONNECT TO OTHER RESETS CONNECT TO OTHER FAULTS VLED1+ 8 VLED1- FAULT 7 VLED1+ RESET 6 FAULT GND1 5 RESET VCC1 4 + ­ µC VIN- 3 GND1 5 µC VCC1 4 + ­ VIN- VIN+ 2 VIN+ 2 1 VLED1- Figure 72. Auto-reset configuration. Figure 71. Global-shutdown, global reset configuration. HCPL-316J HCPL-316J fig 71 1 HCPL-316J HCPL-316J VIN+ VIN+ 2 HCPL-316J HCPL-316J fig 72 HCPL-316J HCPL-316J VIN- 1 2 VIN- 3 VCC1 4 VCC VIN+ GND1 5 RESET 6 FAULT VCC 3 VCC1 µC µC VIN+/ RESET 4 GND1 RESET 6 FAULT FAULT 7 VLED1+ 7 VLED1+ 8 FAULT 5 RESET VLED1- 8 VLED1- Figure 73a. Safe hardware reset for noninverting input configuration (automatically resets for every VIN+ input). 27 HCPL-316J HCPL-316J fig 73a Figure 73b. Safe hardware reset for noninverting input configuration. HCPL-316J HCPL-316J fig 73b User-Configuration of the HCPL-316J HCPL-316J Output Side RG and Optional Resistor RC: The value of the gate resistor RG (along with VCC2 and VEE) determines the maximum amount of gate-charging/discharging current (ION,PEAK and IOFF,PEAK) and thus should be carefully chosen to match the size of the IGBT being driven. Often it is desirable to have the peak gate charge current be somewhat less than the peak discharge current (ION,PEAK < IOFF,PEAK). For this condition, an optional resistor (RC) can be used along with RG to independently determine ION,PEAK and IOFF,PEAK without using a steering diode. As an example, refer to Figure 74. Assuming that RG is already determined and that the design IOH,PEAK = 0.5 A, the value of RC can be estimated in the following way: RC + RG = [VCC2 ­ VOH ­ (VEE)] IOH,PEAK = [4 V ­ (-5 V)] 0.5 A = 18 RC = 8 See "Power and Layout Considerations" section for more information on calculating value of RG. HCPL-316J HCPL-316J VCC 1 2 HCPL-316J HCPL-316J VCC VIN+ 1 VIN- 2 VCC1 4 GND1 5 RESET 6 VIN- VCC VIN- 3 VIN- VIN+ FAULT VCC 3 VCC1 µC µC 4 GND1 RESET RESET 5 6 FAULT 7 VLED1+ 7 VLED1+ 8 FAULT RESET VLED1- 8 VLED1- FAULT Figure 73c. Safe hardware reset for inverting input configuration. HCPL-316J HCPL-316J fig 73c HCPL-316J HCPL-316J fig 73d HCPL-316J HCPL-316J VE 16 VLED2+ 15 DESAT 14 VCC2 13 VC 12 VOUT 11 VEE 10 VEE 9 100 pF RC 8 10 10 nF 15 V Figure 74. Use of RC to further limit ION,PEAK. 28 Figure 73d. Safe hardware reset for inverting input configuration (automatically resets for every VIN- input). -5 V Higher Output Current Using an External Current Buffer: DESAT Diode and DESAT Threshold To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in Figure 75) may be used. Inverting types are not compatible with the desatura-tion fault protection circuitry and should be avoided. To preserve the slow IGBT turn-off feature during a fault condition, a 10 nF capacitor should be connected from the buffer input to VEE and a 10 W resistor inserted between the output and the common npn/ pnp base. The MJD44H11/MJD45H11 MJD44H11/MJD45H11 pair is appropriate for currents up to 8A maximum. The D44VH10/D45VH10 D44VH10/D45VH10 pair is appropriate for currents up to 15 A maximum. The DESAT diode's function is to conduct forward current, allowing sensing of the IGBT's saturated collectorto-emitter voltage, VCESAT, (when the IGBT is "on") and to block high voltages (when the IGBT is "off"). During the short period of time when the IGBT is switching, there is commonly a very high dVCE/dt voltage ramp rate across the IGBT's collector-to-emitter. This results in ICHARGE (= CD-DESAT x dVCE/dt) charging current which will charge the blanking capacitor, CBLANK. In order to minimize this charging current and avoid false DESAT triggering, it is best to use fast response diodes. Listed in the below table are fast-recovery diodes that are suitable for use as a DESAT diode (DDESAT ). In the recommended application circuit shown in Figure 62, the voltage on pin 14 (DESAT) is VDESAT = VF + VCE, (where VF is the forward ON voltage of DDESAT and VCE is the IGBT collector-to-emitter voltage). The value of VCE which triggers DESAT to signal a FAULT condition, is nominally 7V ­ VF. If desired, this DESAT threshold voltage can be decreased by using multiple DESAT diodes in series. If n is the number of DESAT diodes then the nominal threshold value becomes VCE,FAULT(TH) = 7 V ­ n x VF. In the case of using two diodes instead of one, diodes with half of the total required maximum reverse-voltage rating may be chosen. HCPL-316J HCPL-316J VE 16 VLED2+ 15 DESAT 14 VCC2 13 VC 12 VOUT 11 VEE 10 VEE 9 100 pF MJD44H11 MJD44H11 or D44VH10 D44VH10 4.5 10 2.5 10 nF MJD45H11 MJD45H11 or D45VH10 D45VH10 15 V -5 V Figure 75. Current buffer for increased drive current. Part Number Manufacturer trr (ns) Max. Reverse Voltage Rating, VRRM (Volts) Package Type MUR1100E MUR1100E Motorola 75 1000 59-04 (axial leaded) MURS160T3 MURS160T3 Motorola 75 600 Case 403A (surface mount) UF4007 UF4007 General Semi. 75 1000 DO-204AL DO-204AL (axial leaded) BYM26E BYM26E Philips 75 1000 SOD64 (axial leaded) BYV26E BYV26E Philips 75 1000 SOD57 (axial leaded) BYV99 BYV99 Philips 75 600 SOD87 (surface mount) Power/Layout Considerations Operating Within the Maximum Allowable Power Ratings (Adjusting Value of RG): When choosing the value of RG, it is important to confirm that the power dissipation of the HCPL316J HCPL316J is within the maximum allowable power rating. The steps for doing this are: 1. Calculate the minimum desired RG; 29 2. Calculate total power dissipation in the part referring to Figure 77. (Average switching energy supplied to HCPL316J HCPL316J per cycle vs. RG plot); 3. Compare the input and output power dissipation calculated in step #2 to the maximum recommended dissipation for the HCPL316J HCPL316J. (If the maximum recommended level has been exceeded, it may be necessary to raise the value of RG to lower the switching power and repeat step #2.) As an example, the total input and output power dissipation can be calculated given the following conditions: · ION, MAX ~ 2.0 A · VCC2 = 18 V · VEE = -5 V · fCARRIER = 15 kHz Step 1: Calculate RG minimum from IOL peak specification: To find the peak charging lOL assume that the gate is initially charged the steadystate value of VEE. Therefore apply the following relationship: [VOH@650 µA ­ (VOL+VEE)] RG= - IOL,PEAK [VCC2 ­ 1 ­ (VOL + VEE )] = - IOL,PEAK PO(BIAS) = steadystate power dissipation in the HCPL316J HCPL316J due to biasing the device. PO(SWITCH) = transient power dissipation in the HCPL316J HCPL316J due to charging and discharging power device gate. ESWITCH = Average Energy dissipated in HCPL316J HCPL316J due to switching of the power device over one switching cycle (µJ/cycle). fSWITCH = average carrier signal frequency. For RG = 10.5, the value read from Figure 77 is ESWITCH = 6.05 µJ. Assume a worstcase average ICC1 = 16.5 mA (which is given by the average of ICC1H and ICC1L ). Similarly the average ICC2 = 5.5 mA. PI = 16.5 mA * 5.5 V = 90.8 mW PO = PO(BIAS) + PO,SWITCH 18 V ­ 1 V ­ (1.5 V + (5 V) = - 2.0 A = 5.5 mA * (18 V ­ (­5 V) + 6.051 µJ * 15 kHz = 10.25 W = 217.3 mW 10.5 W (for a 1% resistor) (Note from Figure 76 that the real value of IOL may vary from the value calculated from the simple model shown.) Step 2: Calculate total power dissipation in the HCPL-316J HCPL-316J: The HCPL316J HCPL316J total power dissipation (PT ) is equal to the sum of the inputside power (PI) and outputside power (PO): PT = PI + PO PI = ICC1 * VCC1 PO = PO(BIAS) + PO,SWTICH = ICC2 * (VCC2­VEE ) + ESWITCH * fSWITCH where, 4 = 126.5 mW + 90.8 mW Step 3: Compare the calculated power dissipation with the absolute maximum values for the HCPL-316J HCPL-316J: For the example, PI = 90.8 mW < 150 mW (abs. max.) ) OK PO = 217.3 mW < 600 mW (abs. max.) ) OK Therefore, the power dissipation absolute maximum rating has not been exceeded for the example. Please refer to the following Thermal Model section for an explanation on how to calculate the maximum junction temperature of the HCPL316J HCPL316J for a given PC board layout configuration. MAX. ION, IOFF vs. GATE RESISTANCE (VCC2 / VEE2 = 25 V / 5 V SWITCHING ENERGY vs. GATE RESISTANCE (VCC2 / VEE2 = 25 V / 5 V 9 8 3 7 1 6 IOFF (MAX.) 0 -1 ION (MAX.) Ess (Qg = 650 nC) 4 3 1 0 20 40 60 80 100 120 140 160 180 200 Rg () Figure 76. Typical peak ION and IOFF currents vs. Rg (for HCPL-316J HCPL-316J output driving an IGBT rated at 600 V/100 A. HCPL-316J HCPL-316J fig 76 30 5 2 -2 -3 Ess (µJ) ION, IOFF (A) 2 0 0 50 100 150 200 Rg () Figure 77. Switching energy plot for calculating average Pswitch (for HCPL-316J HCPL-316J output driving an IGBT rated at 600 V/100 A). HCPL-316J HCPL-316J fig 77 Thermal Model The HCPL-316J HCPL-316J is designed to dissipate the majority of the heat through pins 4 for the input IC and pins 9 and 10 for the output IC. (There are two VEE pins on the output side, pins 9 and 10, for this purpose.) Heat flow through other pins or through the package directly into ambient are considered negligible and not modeled here. From the earlier power dissipation calculation example: In order to achieve the power dissipation specified in the absolute maximum specification, it is imperative that pins 4, 9, and 10 have ground planes connected to them. As long as the maximum power specification is not exceeded, the only other limitation to the amount of power one can dissipate is the absolute maximum junction temperature specification of 125°C. The junction temperatures can be calculated with the following equations: Tjo= (240mW)(30°C/W + 50°C/W) + 100°C Tji = Pi (qi4 + q4A) + TA where Pi = power into input IC and Po = power into output IC. Since q4A and q9,10A are dependent on PCB layout and airflow, their exact number may not be available. Therefore, a more accurate method of calculating the junction temperature is with the following equations: Tji = Piqi4 + TP4 Tjo = Poqo9,10 + TP9,10 These equations, however, require that the pin 4 and pins 9, 10 temperatures be measured with a thermal couple on the pin at the HCPL-316J HCPL-316J package edge. Tjo i4 = 60°C/W O9,10 = 30°C/W TP4 TP9,10 4A = 50°C/W* 9,10A = 50°C/W* TA Figure 78. HCPL-316J HCPL-316J thermal model. HCPL-316J HCPL-316J fig 78 31 Tji = (90.8mW)(60°C/W + 50°C/W) + 100°C = 110°C = 119°C both of which are within the absolute maximum specification of 125°C. If we, however, assume a worst case PCB layout and no air flow where the estimated q4A and q9,10A are 100°C/W. Then the junction temperatures become Tji = (90.8mW)(60°C/W + 100°C/W) + 100°C Tjo = Po (qo9,10 + q9,10A) + TA Tji Pi = 90.8mW, Po = 314mW, TA = 100°C, and assuming the thermal model shown in Figure 77 below. = 115°C Tjo= (240mW)(30°C/W + 100°C/W) + 100°C = 131°C The output IC junction temperature exceeds the absolute maximum specification of 125°C. In this case, PCB layout and airflow will need to be designed so that the junction temperature of the output IC does not exceed 125°C. If the calculated junction temperatures for the thermal model in Figure 78 is higher than 125°C, the pin temperature for pins 9 and 10 should be measured (at the package edge) under worst case operating environment for a more accurate estimate of the junction temperatures. Tji = junction temperature of input side IC Tjo = junction temperature of output side IC TP4 = pin 4 temperature at package edge TP9,10 = pin 9 and 10 temperature at package edge qI4 = input side IC to pin 4 thermal resistance qI9,10 = output side IC to pin 9 and 10 thermal resistance q4A = pin 4 to ambient thermal resistance q9,10A = pin 9 and 10 to ambient thermal resistance *The q4A and q9,10A values shown here are for PCB layouts shown in Figure 78 with reasonable air flow. This value may increase or decrease by a factor of 2 depending on PCB layout and/or airflow. Printed Circuit Board Layout Considerations Adequate spacing should always be maintained between the high voltage isolated circuitry and any input referenced circuitry. Care must be taken to provide the same minimum spacing between two adjacent high-side isolated regions of the printed circuit board. Insufficient spacing will reduce the effective isolation and increase parasitic coupling that will degrade CMR performance. The placement and routing of supply bypass capacitors requires special attention. During switching transients, the majority of the gate charge is supplied by the bypass capacitors. Maintaining short bypass capacitor trace lengths will ensure low supply ripple and clean switching waveforms. Figure 79. Recommended layout(s). 32 Ground Plane connections are necessary for pin 4 (GND1) and pins 9 and 10 (VEE) in order to achieve maximum power dissipation as the HCPL-316J HCPL-316J is designed to dissipate the majority of heat generated through these pins. Actual power dissipation will depend on the application environment (PCB layout, air flow, part placement, etc.) See the Thermal Model section for details on how to estimate junction temperature. The layout examples below have good supply bypassing and thermal properties, exhibit small PCB footprints, and have easily connected signal and supply lines. The four examples cover single sided and double sided component placement, as well as minimal and improved performance circuits. System Considerations Propagation Delay Difference (PDD) The HCPL-316J HCPL-316J includes a Propagation Delay Difference (PDD) specification intended to help designers minimize "dead time" in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q1 and Q2 in Figure 62) are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices between the high and low voltage motor rails, a potentially catastrophic condition that must be prevented. Delaying the HCPL-316J HCPL-316J turn-on signals by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specifications as shown in Figure 81. The maximum dead time for the HCPL-316J HCPL-316J is 800ns (= 400ns - (-400ns) over an operating temperature range of -40°C to 100°C. To minimize dead time in a given design, the turn-on of the HCPL-316J HCPL-316J driving Q2 should be delayed (relative to the turn-off of the HCPL-316J HCPL-316J driving Q1) so that under worst-case conditions, transistor Q1 has just turned off when transistor Q2 turns on, as shown in Figure 80. The amount of delay necessary to achieve this condition is equal to the maximum value of the propagation delay difference specification, PDDMAX, which is specified to be 400ns over the operating temperature range of 40°C to 100°C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs. VIN- VLED2+ DESAT GND1 IE VCC2 RESET VOUT VLED1+ VLED1- VE VIN- VLED2+ DESAT GND1 + ­ 30 V VIN+ VCC1 5V 0.1 µF 0.1 µF VC FAULT 0.1 µF + ­ VE IE VCC2 RESET VOUT VEE VLED1+ VEE VEE VLED1- VEE 0.1 µF + ­ 30 V Figure 80. Minimum LED Skew for Zero Dead Time. Figure 81. Waveforms for Dead Time Calculation. HCPL-316J HCPL-316J fig 61 HCPL-316J HCPL-316J fig 60 For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. Obsoletes AV01-0579EN AV01-0579EN AV02-0717EN AV02-0717EN - April 9, 2009 30 V 0.1 µF VC FAULT 0.1 µF + ­ VIN+ VCC1 5V + ­ 0.1 µF 0.1 µF + ­ 30 V