NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: HardCopy II devices. Table 1Â1. HardCopy II Device Family Features Feature HC210W (1) HC210 HC210 , ) Notes to Table 1Â1: (1) (2) (3) (4) (5) HC210W devices are in a wire bond package. All other , ) 484-pin FineLine BGA v v EP2S130 EP2S130 EP2S180 EP2S180 v (2) HC210W HC210 HC210 HC220 HC220 672-pin FineLine , Table 1Â2: (1) (2) The HC210W device uses a wire bond package while the Stratix II FPGA prototype , 1,089 1,600 23 Ã- 23 23 Ã- 23 27 Ã- 27 29 Ã- 29 33 Ã- 33 40 Ã- 40 Device HC210W ... | Original |
6 pages, |
instant-on-after-50-ms HC240 HC230 HC210 EP2S90 EP2S60 EP2S30 EP2S180 HC220 H51015-2 H51015-2 abstract |
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| Abstract: in the HardCopy II devices. Table 1Â1. HardCopy II Device Family Features Feature HC210W (1 , ), (5) Notes to Table 1Â1: (1) (2) (3) (4) (5) HC210W devices are in a wire bond package. , (2) HC210W HC210 HC210 HC220 HC220 672-pin FineLine BGA HC220 HC220 780-pin FineLine BGA v v (2 , FineLine BGA v v v (2) Notes to Table 1Â2: (1) (2) The HC210W device uses a wire bond , 23 Ã- 23 27 Ã- 27 29 Ã- 29 33 Ã- 33 40 Ã- 40 Device HC210W Maximum User I/O Pins 308 ... | Original |
6 pages, |
HC240 DDR2 pin out EP2S180 EP2S30 EP2S60 EP2S90 HC210 HC220 HC230 bga 529 H51015-2 H51015-2 abstract |
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| Abstract: HC210W-EP2S90 H484 Pin List Page 8 of 14 Pin Information for HardCopy® II HC210W / Stratix® II EP2S90 EP2S90 , HC210W-EP2S90 H484 Pin List Page 10 of 14 Pin Information for HardCopy® II HC210W / Stratix® II EP2S90 EP2S90 , HC210W-EP2S90 H484 Pin List H484 DQ Group for DQS x8/x9 Mode D20 F18 C22 C21 E20 E19 D22 D21 F20 , HC210W-EP2S90 H484 Pin List H484 DQ Group for DQS x8/x9 Mode N22 N21 N20 N19 P21 P20 N16 N15 R22 , PLL6_FBn/OUT2n HC210W-EP2S90 H484 Pin List H484 DQ Group for DQS x8/x9 Mode Y19 Y14 W14 W16 ... | Original |
14 pages, |
pin information EP2S90 AA19 EP2S90 HC210W HC210W abstract |
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| Abstract: HC210W-EP2S60 F484 Pin List F484 DQ Group for DQS x8/x9 Mode D20 F18 C22 C21 E20 E19 D22 D21 F20 , HC210W-EP2S60 F484 Pin List F484 DQ Group for DQS x8/x9 Mode N22 N21 N20 N19 P21 P20 N16 N15 R22 , /OUT2n HC210W-EP2S60 F484 Pin List F484 DQ Group for DQS x8/x9 Mode T15 Y14 R14 T14 U15 , Function for Stratix II Only (Note 1) PORSEL nIO_PULLUP PLL_ENA nCEO HC210W-EP2S60 F484 Pin List , ) INPUT INPUT CLK8n CLK8p INPUT INPUT CLK10p CLK10n HC210W-EP2S60 F484 Pin List F484 DQ ... | Original |
13 pages, |
EP2S60 AA19 HC210W HC210W abstract |
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| Abstract: CLK0p/DIFFIO_RX_C0p INPUT INPUT CLK2p/DIFFIO_RX_C1p CLK2n/DIFFIO_RX_C1n HC210W-EP2S30 F484 Pin , CLKUSR nWS nRS HC210W-EP2S30 F484 Pin List N20 N19 P21 P20 N16 N15 R22 R21 P17 P16 R20 , PLL6_OUT0p PLL6_OUT0n PLL6_FBp/OUT2p PLL6_FBn/OUT2n HC210W-EP2S30 F484 Pin List R15 U15 Y14 W14 , PLL_ENA nCEO HC210W-EP2S30 F484 Pin List AB7 AA7 U10 V10 AB6 AA6 Y6 Y5 AB5 AA5 T9 R9 U9 , CLK10p CLK10n HC210W-EP2S30 F484 Pin List P6 P5 T2 T1 P4 P8 P7 R2 R1 N8 N7 P3 P2 N4 ... | Original |
13 pages, |
F484-pin EP2S30 AA19 HC210W HC210W abstract |
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| Abstract: Boundary-Scan Register Length Device Boundary-Scan Register Length HC210W 1050 HC210 HC210 1050 , ) LSB (1 Bit) (2) HC210W 0000 0010 0000 1100 0001 000 0110 1110 1 HC210 HC210 0000 ... | Original |
6 pages, |
HC240 HC230 HC220 HC210 h jtag H51017-2 H51017-2 abstract |
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| Abstract: Boundary-Scan Register Length Device Boundary-Scan Register Length HC210W 1050 HC210 HC210 1050 , ) LSB (1 Bit) (2) HC210W 0000 0010 0000 1100 0001 000 0110 1110 1 HC210 HC210 0000 ... | Original |
6 pages, |
HC240 HC230 HC220 HC210 h jtag H51017-2 H51017-2 abstract |
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| Abstract: Maximum -10 10 uA all -10 10 uA HC210W 0.09 (3) (5) A HC210 HC210 0.09 (3 , ) A VI = ground, no load, no toggling inputs HC210W 3 (3) (5) mA HC210 HC210 3 (3 , Typical Maximum Unit HC210W 3 (3) (5) mA HC210 HC210 3 (3) (5) mA HC220 HC220 3 (3 , when using series or differential on-chip termination for HC210W devices only. . Table 4Â29. Series On-Chip Termination Specification for I/O Banks Supporting Memory Interface IOEs for HC210W Notes ... | Original |
50 pages, |
SSTL-18 HC240 HC230 HC220 HC210 H51018-3 H51018-3 abstract |
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| Abstract: characterization. External memory interface performance on the HC210W HardCopy II device is limited to 150 MHz for , Figure 1. I/O Bank, DQS Circuitry & PLL Placement in HC210/HC210W/HC220 Devices Bank 3 Memory Interface , HardCopy II Devices (Part 1 of 2) Feature MIIO banks HC210W, HC210 HC210, HC220 HC220 HC230 HC230, HC240 HC240 Top (1 , of 2) Feature HC210W, HC210 HC210, HC220 HC220 HC230 HC230, HC240 HC240 1 2 Total number of DLLs in device Notes to Table 2: (1) (2) HC210W/HC210/HC220 can only implement the one-PLL normal mode data path ... | Original |
20 pages, |
SSTL-18 HC240 HC230 HC220 HC210 EP2S30 datasheet abstract |
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| Abstract: features. Table 2Â1. HardCopy II Family Overview (Part 1 of 2) Feature ASIC gates (2) HC210W (1 , Overview (Part 2 of 2) Feature HC210W (1) HC220 HC220 HC230 HC230 HC240 HC240 EP2S30 EP2S30 EP2S60 EP2S60 EP2S90 EP2S90 FPGA , EP2S180 EP2S180 Notes to Table 2Â1: (1) (2) (3) (4) (5) HC210W devices use a wire bond package. All , Embedded Memory Resources Feature HC210W HC210 HC210 HC220 HC220 HC230 HC230 HC240 HC240 M4K RAM blocks (4 Kbits , density (Table 2Â5). Table 2Â5. HardCopy II PLLs Feature HC210W HC210 HC210 HC220 HC220 HC230 HC230 HC240 HC240 ... | Original |
28 pages, |
HC240 HC230 HC220 HC210 EP2S90 EP2S60 EP2S30 EP2S180 H51016-2 H51016-2 abstract |
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| Abstract: HC210W - 0.09 (3) (5) A HC210 HC210 - 0.09 (3) (5) A HC220 HC220 - 0.19 (3 , Minimum Typical Maximum - 0.52 (3) (5) A HC210W - 3 (3) (5) mA HC210 HC210 - , ) Device Minimum Typical Maximum Unit VCCIO supply current (standby) HC210W RCONF(4 , termination specification when using series or differential on-chip termination for HC210W devices only. , HC210W Notes (1), (2), (3) Resistance Tolerance Symbol 25 RS 3.3/2.5 Description Conditions ... | Original |
50 pages, |
SSTL-18 HC240 HC230 HC220 HC210 H51018-3 H51018-3 abstract |
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