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HC126A

Catalog Datasheet MFG & Type PDF Document Tags

HC126A

Abstract: HC125A , they are compatible with LSTTL outputs. The HC125A and HC126A noninverting buffers are designed to be , have four separate output enables that are active­low (HC125A) or active­high (HC126A). N SUFFIX , HC126A Active­High Output Enables OE1 A2 OE2 2 3 Y1 1 5 2 A1 6 Y2 4 , HC126A Inputs Output A OE Y H L X H H L H L Z MC74HC125A MC74HC126A , OE (HC126A) GND VCC 50% GND tPHL tPLH VCC 50% tPZL tPLZ 90% 50% 10
Motorola
Original
LS125 LS126 MC74HCXXXAN MC74HCXXXAD DL129 MC74HC125A/D

74HC125A

Abstract: 74HC126A outputs. The HC125A and HC126A noninverting buffers are designed to be used with 3-state memory address , are activelow (HC125A) or active-high (HC126A). Output Drive Capability: 15 LSTTL Loads Outputs , LOGIC DIAGRAM HC125A Active-Low Output Enables HC126A Active-High Output Enables t 1 · 14 3 , FUNCTION TABLE HC125A HC126A Inputs A H L X OE H H L Output Y H L Z Inputs A OE L L H H L X Y4 A3 10 , Device) 11E D I L3b7SSE Güñüiati M | Vcc 3 - HC126A (1/4 of the Device) ¡ M S r it r W M l
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OCR Scan
74HC125A 74HC126A Y410 MC54JHC125A/D MC54/74HC125A MC54/74HC126A HC125 HC126 MC54HCXXXAJ
Abstract: outputs. The HC125A and HC126A noninverting buffers are designed to be used with 3-state memory address , are active-low (HC125A) or active-high (HC126A). · · · · · · Output Drive Capability: 15 LSTTL Loads , ctive-Low Output Enables HC126A Active-High Output Enables M C 74H C 125A M C 74H C 126A N SUFFIX 14 , PIN 7 = GND FUNCTION TABLE HC125A Inputs A H L X OE L L H O utput Y H L Z A H L X HC126A Inputs OE , Vcc GND OE (HC126A) INPUT A 10% -
OCR Scan
14-LEAD 948G-01 MC74H 1-80CM41-2447 1-B00-774-1848

MC74HC125AD

Abstract: hc126a and HC126A noninverting buffers are designed to be used with 3­state memory address drivers, clock , (HC125A) or active­high (HC126A). http://onsemi.com MARKING DIAGRAMS 14 PDIP­14 N SUFFIX CASE 646 , Complexity: 72 FETs or 18 Equivalent Gates LOGIC DIAGRAM HC125A HC126A Active­Low Output Enables Active­High , ­14 TSSOP­14 Shipping 2000 / Box 55 / Rail 2500 / Reel 96 / Rail 2500 / Reel HC126A FUNCTION TABLE , VCC GND VCC GND tPHL 90% 50% 10% tTLH tTHL OUTPUT Y OE (HC126A) 50% GND tPZL tPLZ OUTPUT Y 50% tPZH
ON Semiconductor
Original
MC74HC125AD MC74HC125ADR2 MC74HC12 MC74HC125ADT MC74HC125ADTEL MC74HC125ADTR2

74HC125A

Abstract: 74HC126A HC126A noninverting buffers are designed to be used w ith 3-state m em ory address drivers, clock drivers , (HC125A) or active-high (HC126A). Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CM , HC126A Active-High Output Enables 0E1 [ 1 · A1[ Y1[ 2 3 14 ] Vcc 13 ] 0E4 12 ] A4 11 ] V4 10 ] 0E3 9 , HC125A Inputs A OE L L H H L X HC126A Inputs A H L X Output Y H L Z Output Y H L Z OE H , HC126A (1/4 of the Device) Vcc 5 MOTOROLA HIGH-SPEED CMOS LOGIC DATA 5-104
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OCR Scan
54/74H C54/74HC126A C74HCXXXAN C74HCXXXAD

HC125A

Abstract: HC126A outputs. The HC125A and HC126A noninverting buffers are designed to be used with 3-state memory address , are active-low (HC125A) or active-high (HC126A). â'¢ Output Drive Capability: 15 LSTTL loads  , DIAGRAM HC125A Active-Low Output Enables Al OE1 A2 OE2 A3 OE3 A4 OE4 10 12 13 Y1 HC126A Active-High Output , * 14 Al [ 2 13 Y1 [ 3 12 0E2 0 4 11 A2C 5 10 Y2 [ 6 9 GND [ 7 8 FUNCTION TABLE HC125A HC126A , % J 10% * tTLH -tpHL ' Vcc GND V "iTHL Figure 1. OE (HC125A) OE (HC126A) OUTPUTY OUTPUT Y A -L 50% y
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OCR Scan
PIN14 3120E2

HC125A

Abstract: HC126A , they are compatible with LSTTL outputs. The HC125A and HC126A noninverting buffers are designed to be , have four separate output enables that are active­low (HC125A) or active­high (HC126A). N SUFFIX , HC126A Active­High Output Enables OE1 A2 OE2 2 3 Y1 1 5 A1 OE1 6 Y2 4 , HC126A Inputs Output A OE Y H L X H H L H L Z MOTOROLA 2 High­Speed , WAVEFORMS OE (HC125A) tr tf OUTPUT Y GND VCC 90% 50% 10% INPUT A OE (HC126A) GND
Motorola
Original
DSA0038472
Abstract: HC125A and HC126A noninverting buffers are designed to be used with 3â'state memory address drivers , are activeâ'low (HC125A) or activeâ'high (HC126A). http://onsemi.com MARKING DIAGRAMS 14 , A4 OE2 4 11 5 10 OE3 Y2 6 9 HC126A Activeâ'High Output Enables Y4 , Y4 13 OE4 A2 A3 OE3 12 A4 Output 8 10 OE3 HC126A Inputs Y2 , tf GND VCC 90% 50% 10% INPUT A VCC OE (HC126A) GND 50% GND tPHL tPLH ON Semiconductor
Original

HC126A

Abstract: HC125A outputs. The HC125A and HC126A noninverting buffers are designed to be used with 3 -s ta te m em ory , enables that are a ctive -low (HC125A) or a c tive -high (HC126A). · · · · · · · Output Drive Capability , utput Enables HC126A A ctive-H ig h O utput Enables OE1 [ A1 [ Y1 [ OE2 [ A1 A1 A2 [ Y2[ 0E1 0E1 GND , FUNCTION TABLE 0E2 OE2 HC125A A3 Y3 A3 Y3 HC126A Inputs < Inputs A H L X OE L L H Output Y H , MC74HC125A MC74HC126A H C125A (1/4 OF TH E DEVICE) VCC HC126A (1/4 OF TH E DEVICE) vcc MOTOROLA
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OCR Scan
C74HC126A HC12SA

HC126A

Abstract: HC125A and HC126A noninverting buffers are designed to be used with 3-state memory address drivers, clock , (HC125A) or active-high (HC126A). http://onsemi.com MARKING DIAGRAMS 14 PDIP-14 N SUFFIX CASE 646 , Complexity: 72 FETs or 18 Equivalent Gates LOGIC DIAGRAM HC125A HC126A Active-Low Output Enables Active-High , -14 TSSOP-14 Shipping 2000 / Box 55 / Rail 2500 / Reel 96 / Rail 2500 / Reel HC126A FUNCTION TABLE , , MC74HC126A SWITCHING WAVEFORMS VCC GND VCC GND tPHL 90% 50% 10% tTLH tTHL OUTPUT Y OE (HC126A) 50% GND tPZL
ON Semiconductor
Original
SOIC-14 DL129/D

74hc125a

Abstract: 74HC126A HC125A and HC126A noninverting buffers are designed to be used w ith 3-state m em ory address drivers , activelow (HC125A) or active-high (HC126A). · · · · · · Output Drive Capability: 15 LSTTL Loads Outputs , Output Enables HC126A Active-High Output Enables 0E1 [ A ll VI [ 1 · 2 3 14 Í VCC 13 ] 0 E 4 12 ] A4 , FUNCTION TABLE HC125A HC126A Inputs U J ol < Output Y H L Z A3 · Inputs A H L X OE L L H Output Y , ) VCC HC126A (1/4 of the Device) Vcc 5 MOTOROLA HIGH-SPEED C M O S LOGIC DATA 5-109
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OCR Scan
C54HCXXXAJ

hc126a

Abstract: MC74HC125AD and HC126A noninverting buffers are designed to be used with 3-state memory address drivers, clock , (HC125A) or active-high (HC126A). Features http://onsemi.com MARKING DIAGRAMS 14 14 1 PDIP-14 N SUFFIX , Y4 8 Y3 6 Y2 LOGIC DIAGRAM HC125A Active-Low Output Enables A1 2 3 Y1 HC126A Active-High Output Enables A1 2 3 Y1 FUNCTION TABLE HC125A Inputs A H L X OE L L H Output Y H L Z A H L X HC126A , , MC74HC126A SWITCHING WAVEFORMS VCC 50% GND VCC GND tPHL 90% 50% 10% tTLH tTHL OE (HC126A) 50% GND tPZL
ON Semiconductor
Original
MC74HC126 AEC-Q100

MC74HC125AD

Abstract: MC74HC125ADR2 HC125A and HC126A noninverting buffers are designed to be used with 3-state memory address drivers , active-low (HC125A) or active-high (HC126A). MARKING DIAGRAMS 14 PDIP-14 N SUFFIX CASE 646 14 1 , 11 Y4 13 OE4 A2 A3 OE3 12 A4 Output Y2 OE2 9 OE3 HC126A , HC126A Active-High Output Enables A4 OE4 2 3 Y1 1 5 6 Y2 4 9 8 Y3 10
ON Semiconductor
Original
MC74HC125ANG MC74HC125ADG MC74HC125AN SOEIAJ-14 74HC12

hc126a

Abstract: MC74HC125AD and HC126A noninverting buffers are designed to be used with 3-state memory address drivers, clock , (HC125A) or active-high (HC126A). Features http://onsemi.com MARKING DIAGRAMS 14 14 1 PDIP-14 N SUFFIX , Y4 8 Y3 6 Y2 LOGIC DIAGRAM HC125A Active-Low Output Enables A1 2 3 Y1 HC126A Active-High Output Enables A1 2 3 Y1 FUNCTION TABLE HC125A Inputs A H L X OE L L H Output Y H L Z A H L X HC126A , OE (HC126A) 50% GND tPZL OUTPUT Y 50% tPZH OUTPUT Y 50% tPHZ 90% tPLZ 10% HIGH IMPEDANCE VOL VOH HIGH
ON Semiconductor
Original

hc126a

Abstract: MC74HC125AD and HC126A noninverting buffers are designed to be used with 3­state memory address drivers, clock , (HC125A) or active­high (HC126A). http://onsemi.com MARKING DIAGRAMS 14 PDIP­14 N SUFFIX CASE 646 , Complexity: 72 FETs or 18 Equivalent Gates LOGIC DIAGRAM HC125A HC126A Active­Low Output Enables Active­High , ­14 TSSOP­14 Shipping 2000 / Box 55 / Rail 2500 / Reel 96 / Rail 2500 / Reel HC126A FUNCTION TABLE , , MC74HC126A SWITCHING WAVEFORMS VCC GND VCC GND tPHL 90% 50% 10% tTLH tTHL OUTPUT Y OE (HC126A) 50% GND tPZL
ON Semiconductor
Original

MC74HC125AD

Abstract: MC74HC125ADR2 HC125A and HC126A noninverting buffers are designed to be used with 3-state memory address drivers , active-low (HC125A) or active-high (HC126A). http://onsemi.com MARKING DIAGRAMS 14 PDIP-14 N SUFFIX , HC126A Inputs 6 4 A3 A1 OE1 5 A2 OE2 Inputs Y1 1 OE1 FUNCTION TABLE 3 HC126A Active-High Output Enables A4 OE4 2 3 Y1 1 5 6 Y2 4 9 8 , OUTPUT Y OE (HC125A) VCC OE (HC126A) GND 50% GND tPZL 90% 50% 10% tPLZ HIGH
ON Semiconductor
Original
y413 5,6 A4 MC74HC125ADTG

HC126A

Abstract: HC125A LSTTL outputs. The HC125A and HC126A noninverting buffers are designed to be used with 3­state memory , enables that are active­low (HC125A) or active­high (HC126A). · · · · · · · MARKING DIAGRAMS , Standard No. 7A Chip Complexity: 72 FETs or 18 Equivalent Gates LOGIC DIAGRAM HC125A HC126A , Y Package MC74HC12xAN Output OE March, 2000 ­ Rev. 9 3 Device HC126A A , (HC125A) tr OUTPUT Y GND VCC 90% 50% 10% INPUT A VCC OE (HC126A) GND 50% GND
ON Semiconductor
Original
MC74HC12XADTR2 A4411

HC125a

Abstract: MC74HC125AD LSTTL outputs. The HC125A and HC126A noninverting buffers are designed to be used with 3-state memory , enables that are active-low (HC125A) or active-high (HC126A). MARKING DIAGRAMS 14 PDIP-14 N SUFFIX , 10 11 Y4 13 OE4 A2 A3 OE3 12 A4 Output Y2 OE2 9 OE3 HC126A , HC126A Active-High Output Enables A4 OE4 2 3 Y1 1 5 6 Y2 4 9 8 Y3 10 , % INPUT A OUTPUT Y OE (HC125A) VCC OE (HC126A) GND 50% GND tPZL 90% 50% 10
ON Semiconductor
Original

HC125A

Abstract: hc126a , they are compatible with LSTTL outputs. The HC125A and HC126A noninverting buffers are designed to be , have four separate output enables that are active­low (HC125A) or active­high (HC126A). · Output , OE2 2 3 HC126A Active­High Output Enables 1 2 A1 Y1 6 4 MC74HCXXXAN , Output HC126A Inputs Output A OE Y A OE Y H L X L L H H L Z H , SWITCHING WAVEFORMS OE (HC125A) tr tf OUTPUT Y GND VCC 90% 50% 10% INPUT A OE (HC126A
Motorola
Original
MC74HCXXXADT
Abstract: and HC126A noninverting buffers are designed to be used with 3-state memory address drivers, clock , (HC125A) or active-high (HC126A). Features http://onsemi.com MARKING DIAGRAMS 14 14 1 PDIP-14 N SUFFIX , 4 9 10 12 13 11 Y4 8 Y3 6 Y2 LOGIC DIAGRAM HC125A Active-Low Output Enables A1 2 3 Y1 HC126A , HC126A Inputs OE H H L Output Y H L Z OE3 A4 OE4 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ , VCC 50% GND VCC GND tPHL 90% 50% 10% tTLH tTHL OE (HC126A) 50% GND tPZL OUTPUT Y 50% tPZH OUTPUT Y 50 ON Semiconductor
Original
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