HBD854/D DL150/D AN784 AN843 AR450 DO-35 DO-41 MIL-STD-750 1N4728 1N4001 1N821 - Datasheet Archive

 

Handbook HBD854/D Rev. 0, Jun-2005 © SCILLC, 2005 Previous Edition © 2001 as Excerpted from DL150/D "All Rights

 

TVS/Zener Theory and Design Considerations Handbook HBD854/D HBD854/D Rev. 0, Jun-2005 © SCILLC, 2005 Previous Edition © 2001 as Excerpted from DL150/D DL150/D "All Rights Reserved'' http://onsemi.com 1 Technical Information, Application Notes and Articles Zener Diode Theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Zener Diode Fabrication Techniques . . . . . . . . . . . . . . . 8 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Zener Diode Characteristics . . . . . . . . . . . . . . . . . . . . . 18 Temperature Compensated Zeners . . . . . . . . . . . . . . . 30 Basic Voltage Regulation Using Zener Diodes . . . . . 34 Zener Protective Circuits and Techniques: Basic Design Considerations . . . . . . . . . . . . . . . . . 44 Zener Voltage Sensing Circuits and Applications . . . 54 Miscellaneous Applications of Zener Type Devices . . . . . . . . . . . . . . . . . . . . . . . . . 61 Transient Voltage Suppression . . . . . . . . . . . . . . . . . . 63 AN784 AN784 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 AN843 AN843 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Design Considerations and Performance of Temperature Compensated Zener Diodes . . . . . . 97 MOSORBs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 AR450 AR450 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Measurement of Zener Voltage to Thermal Equilibrium with Pulsed Test Current . . . . . . . . . . 119 http://onsemi.com 2 ZENER DIODE THEORY INTRODUCTION now see. Silicon is a tetravalent element, one with four valence electrons in the outer shell; all are virtually locked into place by the covalent bonds of the crystal lattice structure, as shown schematically in Figure 1a. When controlled amounts of donor impurities (Group V elements) such as phosphorus are added, the pentavalent phosphorus atoms entering the lattice structure provide extra electrons not required by the covalent bonds. These impurities are called donor impurities since they "donate" a free electron to the lattice. These donated electrons are free to drift from negative to positive across the crystal when a field is applied, as shown in Figure 1b. The "N" nomenclature for this kind of conductivity implies "negative" charge carriers. In P-type conductivity, the charges that carry electric current across the crystal act as if they were positive charges. We know that electricity is always carried by drifting electrons in any material, and that there are no mobile positively charged carriers in a solid. Positive charge carriers can exist in gases and liquids in the form of positive ions but not in solids. The positive character of the current flow in the semiconductor crystal may be thought of as the movement of vacancies (called holes) in the covalent lattice. These holes drift from positive toward negative in an electric field, behaving as if they were positive carriers. P-type conductivity in semiconductors result from adding acceptor impurities (Group III elements) such as boron to silicon to the semiconductor crystal. In this case, boron atoms, with three valence electrons, enter the tetravalent silicon lattice. Since the covalent bonds cannot be satisfied by only three electrons, each acceptor atom leaves a hole in the lattice which is deficient by one electron. These holes readily accept electrons introduced by external sources or created by radiation or heat, as shown in Figure 1c. Hence the name acceptor ion or acceptor impurity. When an external circuit is connected, electrons from the current source "fill up" these holes from the negative end and jump from hole to hole across the crystal or one may think of this process in a slightly different but equivalent way, that is as the displacement of positive holes toward the negative terminal. It is this drift of the positively charged holes which accounts for the term P-type conductivity. When semiconductor regions of N- and P-type conductivities are formed in a semiconductor crystal adjacent to each other, this structure is called a PN junction. Such a junction is responsible for the action of both zener diodes and rectifier devices, and will be discussed in the next section. The zener diode is a semiconductor device unique in its mode of operation and completely unreplaceable by any other electronic device. Because of its unusual properties it fills a long-standing need in electronic circuitry. It provides, among other useful functions, a constant voltage reference or voltage control element available over a wide spectrum of voltage and power levels. The zener diode is unique among the semiconductor family of devices because its electrical properties are derived from a rectifying junction which operates in the reverse breakdown region. In the sections that follow, the reverse biased rectifying junction, some of the terms associated with it, and properties derived from it will be discussed fully. The zener diode is fabricated from the element silicon. Special techniques are applied in the fabrication of zener diodes to create the required properties. This manual was prepared to acquaint the engineer, the equipment designer and manufacturer, and the experimenter with the fundamental principles, design characteristics, applications and advantages of this important semiconductor device. SEMICONDUCTOR THEORY The active portion of a zener diode is a semiconductor PN junction. PN junctions are formed in various kinds of semiconductor devices by several techniques. Among these are the widely used techniques known as alloying and diffusion which are utilized in fabricating zener PN junctions to provide excellent control over zener breakdown voltage. At the present time, zener diodes use silicon as the basic material in the formation of their PN junction. Silicon is in Group IV of the periodic table (tetravalent) and is classed as a "semiconductor" due to the fact that it is a poor conductor in a pure state. When controlled amounts of certain "impurities" are added to a semiconductor it becomes a better conductor of electricity. Depending on the type of impurity added to the basic semiconductor, its conductivity may take two different forms, called P- and N-type respectively. N-type conductivity in a semiconductor is much like the conductivity due to the drift of free electrons in a metal. In pure silicon at room temperature there are too few free electrons to conduct current. However, there are ways of introducing free electrons into the crystal lattice as we shall http://onsemi.com 3 junction interface toward the negative N-type side. Conversely, electrons in the N-type are readily attracted by the positive polarity in the other direction. When a PN junction is reverse biased, the P-type side is made more negative than the N-type side. (See Figure 2b.) At voltages below the breakdown of the junction, there is very little current flow across the junction interface. At first thought one would expect no reverse current under reverse bias conditions, but several effects are responsible for this small current. Under this condition the positive holes in the P-type semiconductor are repelled from the junction interface by the positive polarity applied to the N side, and conversely, the electrons in the N material are repelled from the interface by the negative polarity of the P side. This creates a region extending from the junction interface into both P- and N-type materials which is completely free of charge carriers, that is, the region is depleted of its charge carriers. Hence, this region is usually called the depletion region. Although the region is free of charge carriers, the P-side of the depletion region will have an excess negative charge due to the presence of acceptor ions which are, of course, fixed in the lattice; while the N-side of the depletion region has an excess positive charge due to the presence of donor ions. These opposing regions of charged ions create a strong electric field across the PN junction responsible for the creation of reverse current. The semiconductor regions are never perfect; there are always a few free electrons in P material and few holes in N material. A more significant factor, however, is the fact that great magnitudes of electron-hole pairs may be thermally generated at room temperatures in the semiconductor. When these electron-hole pairs are created within the depletion region, then the intense electric field mentioned in the above paragraph will cause a small current to flow. This small current is called the reverse saturation current, and tends to maintain a relatively constant value for a fixed temperature at all voltages. The reverse saturation current is usually negligible compared with the current flow when the junction is forward biased. Hence, we see that the PN junction, when not reverse biased beyond breakdown voltage, will conduct heavily in only one direction. When this property is utilized in a circuit we are employing the PN junction as a rectifier. Let us see how we can employ its reverse breakdown characteristics to an advantage. As the reverse voltage is increased to a point called the voltage breakdown point and beyond, current conduction across the junction interface increases rapidly. The break from a low value of the reverse saturation current to heavy conductance is very sharp and well defined in most PN junctions. It is called the zener knee. When reverse voltages greater than the voltage breakdown point are applied to the PN junction, the voltage drop across the PN junction remains essentially constant at the value of the breakdown voltage for a relatively wide range of currents. This region ELECTRONS ARE LOCKED IN COVALENT BONDS Si Si Si Si Si Si Si (a) Lattice Structures of Pure Silicon Si Si LOCKED COVALENT BOND ELECTRONS Si P Si - Si Si APPLIED FIELD FREE ELECTRON FROM PHOSPHOROUS ATOM DRIFTS TOWARD APPLIED POSITIVE POLE. (b) N-Type Silicon Si INCOMPLETED COVALENT BOND Si + B Si Si - Si Si APPLIED FIELD THIS ELECTRON JUMPS INTO HOLE LEFT BY BORON ATOM. HOLE POSITION IS DISPLACED TO RIGHT. THIS RESULTS IN A DRIFT OF HOLES TOWARD THE NEGATIVE POLE, GIVING THEM THE CHARACTER OF MOBILE POSITIVE CHARGES. (c) P-Type Silicon Figure 1. Semiconductor Structure THE SEMICONDUCTOR DIODE In the forward-biased PN junction, Figure 2a, the P region is made more positive than the N region by an external circuit. Under these conditions there is a very low resistance to current flow in the circuit. This is because the holes in the positive P-type material are very readily attracted across the http://onsemi.com 4 P CHARGES FROM BOTH P AND N REGIONS DRIFT ACROSS JUNCTION AT VERY LOW APPLIED VOLTAGES. N (a) Forward-Based PN Junction LARGE CURRENT APPLIED FIELD N P VERY SMALL CURRENT AT APPLIED VOLTAGES BELOW THE CRITICAL BREAKDOWN LEVEL ONLY A FEW CHARGES DRIFT ACROSS THE INTERFACE. (b) Reverse-Biased PN Junction SEVERAL VOLTS APPLIED FIELD Figure 2. Effects of Junction Bias beyond the voltage breakdown point is called the zener control region. VREV VBREAKDOWN ZENER CONTROL REGION: VOLTAGE BREAKDOWN MECHANISMS Figure 3 depicts the extension of reverse biasing to the point where voltage breakdown occurs. Although all PN junctions exhibit a voltage breakdown, it is important to know that there are two distinct voltage breakdown mechanisms. One is called zener breakdown and the other is called avalanche breakdown. In zener breakdown the value of breakdown voltage decreases as the PN junction temperature increases; while in avalanche breakdown the value of the breakdown voltage increases as the PN junction temperature increases. Typical diode breakdown characteristics of each category are shown in Figure 4. The factor determining which of the two breakdown mechanisms occurs is the relative concentrations of the impurities in the materials which comprise the junction. If two different resistivity P-type materials are placed against two separate but equally doped low-resistivity pieces of N-type materials, the depletion region spread in the low resistivity P-type material will be smaller than the depletion region spread in the high resistivity P-type material. Moreover, in both situations little of the resultant depletion width lies in the N material if its resistivity is low compared to the P-type material. In other words, the depletion region always spreads principally into the material having the highest resistivity. Also, the electric field (voltage per unit IREV SLOPE Figure 3. Reverse Characteristic Extended to Show Breakdown Effect length) in the less resistive material is greater than the electric field in the material of greater resistivity due to the presence of more ions/unit volume in the less resistive material. A junction that results in a narrow depletion region will therefore develop a high field intensity and breakdown by the zener mechanism. A junction that results in a wider depletion region and, thus, a lower field intensity will break down by the avalanche mechanism before a zener breakdown condition can be reached. The zener mechanism can be described qualitatively as follows: because the depletion width is very small, the application of low reverse bias (5 volts or less) will cause a field across the depletion region on the order of 3 x 105V/cm. A field of such high magnitude exerts a large force on the http://onsemi.com 5 4 VREV (VOLTS) 3 2 1 30 25 VREV (VOLTS) 20 15 10 5 IREV IREV 25°C 65°C 65°C 25°C (A) (B) ZENER BREAKDOWN OF A PN FUNCTION AVALANCHE BREAKDOWN OF A PN FUNCTION Figure 4. Typical Breakdown Diode Characteristics. Note Effects of Temperature for Each Mechanism before combining with a carrier of opposite conductivity). Therefore, when temperature is increased, the increased lattice vibration shortens the distance a carrier travels before colliding and thus requires a higher voltage to get it across the depletion region. As established earlier, the applied reverse bias causes a small movement of intrinsic electrons from the P material to the potentially positive N material and intrinsic holes from the N material to the potentially negative P material (leakage current). As the applied voltage becomes larger, these electrons and holes increasingly accelerate. There are also collisions between these intrinsic particles and bound electrons as the intrinsic particles move through the depletion region. If the applied voltage is such that the intrinsic electrons do not have high velocity, then the collisions take some energy from the intrinsic particles, altering their velocity. If the applied voltage is increased, collision with a valence electron will give considerable energy to the electron and it will break free of its covalent bond. Thus, one electron by collision, has created an electron-hole pair. These secondary particles will also be accelerated and participate in collisions which generate new electron-hole pairs. This phenomenon is called carrier multiplication. Electron-hole pairs are generated so quickly and in such large numbers that there is an apparent avalanche or self-sustained multiplication process (depicted graphically in Figure 5). The junction is said to be in breakdown and the current is limited only by resistance external to the junction. Zener diodes above 7 to 8 volts exhibit avalanche breakdown. As junction temperature increases, the voltage breakdown point for the avalanche mechanism increases. This effect can be explained by considering the vibration displacement of atoms in their lattice increases, and this increased displacement corresponds to an increase in the probability that intrinsic particles in the depletion region will collide with the lattice atoms. If the probability of an intrinsic particle-atom collision increases, then the probability that a given intrinsic particle will obtain high momentum valence electrons of a silicon atom, tending to separate them from their respective nuclei. Actual rupture of the covalent bonds occurs when the field approaches 3 x 105V/cm. Thus, electron-hole pairs are generated in large numbers and a sudden increase of current is observed. Although we speak of a rupture of the atomic structure, it should be understood that this generation of electron-hole pairs may be carried on continuously as long as an external source supplies additional electrons. If a limiting resistance in the circuit external to the diode junction does not prevent the current from increasing to high values, the device may be destroyed due to overheating. The actual critical value of field causing zener breakdown is believed to be approximately 3 x 105V/cm. On most commercially available silicon diodes, the maximum value of voltage breakdown by the zener mechanism is 8 volts. In order to fabricate devices with higher voltage breakdown characteristics, materials with higher resistivity, and consequently, wider depletion regions are required. These wide depletion regions hold the field strength down below the zener breakdown value (3 x 105V/cm). Consequently, for devices with breakdown voltage lower than 5 volts the zener mechanism predominates, between 5 and 8 volts both zener and an avalanche mechanism are involved, while above 8 volts the avalanche mechanism alone takes over. The decrease of zener breakdown voltage as junction temperature increases can be explained in terms of the energies of the valence electrons. An increase of temperature increases the energies of the valence electrons. This weakens the bonds holding the electrons and consequently, less applied voltage is necessary to pull the valence electrons from their position around the nuclei. Thus, the breakdown voltage decreases as the temperature increases. The dependence on temperature of the avalanche breakdown mechanism is quite different. Here the depletion region is of sufficient width that the carriers (electrons or holes) can suffer collisions before traveling the region completely i.e., the depletion region is wider than one mean-free path (the average distance a carrier can travel http://onsemi.com 6 REVERSE-BIASED PN JUNCTION IN AVALANCHE LARGE CURRENT N P WHEN THE APPLIED VOLTAGE IS ABOVE THE BREAKDOWN POINT, A FEW INJECTED ELECTRONS RECEIVE ENOUGH ACCELERATION FROM THE FIELD TO GENERATE NEW ELECTRONS BY COLLISION. DURING THIS PROCESS THE VOLTAGE DROP ACROSS THE JUNCTION REMAINS CONSTANT. R S RS ABSORBS EXCESS VOLTAGE. CONSTANT VOLTAGE DROP Figure 5. PN Junction in Avalanche Breakdown a different symbol. For the leakage current region, i.e. non-conducting region, between 0 volts and VZ, the reverse current is denoted by the symbol IR; but for the zener control region, VR VZ, the reverse current is denoted by the symbol IZ. IR is usually specified at a reverse voltage VR 0.8 VZ. The PN junction breakdown voltage, VZ, is usually called the zener voltage, regardless whether the diode is of the zener or avalanche breakdown type. Commercial zener diodes are available with zener voltages from about 1.8 V - 400 V. For most applications the zener diode is operated well into the breakdown region (IZT to IZM). Most manufacturers give an additional specification of IZK (= 5 mA in Figure 6) to indicate a minimum operating current to assure reasonable regulation. This minimum current IZK varies in the various types of zener diodes and, consequently, is given on the data sheets. The maximum zener current IZM should be considered the maximum reverse current recommended by the manufacturer. Values of IZM are usually given in the data sheets. Between the limits of IZK and IZM, which are 5 mA and 1400 mA (1.4 Amps) in the example of Figure 6, the voltage across the diode is essentially constant, and VZ. This plateau region has, however, a large positive slope such that the precise value of reverse voltage will change slightly as a function of IZ. For any point on this plateau region one may calculate an impedance using the incremental magnitudes of the voltage and current. This impedance is usually called the zener impedance ZZ, and is specified for most zener diodes. Most manufacturers measure the maximum zener impedance at two test points on the plateau region. The first is usually near the knee of the zener plateau, ZZK, and the latter point near the midrange of the usable zener current excursion. Two such points are illustrated in Figure 6. This section was intended to introduce the reader to a few of the major terms used with zener diodes. A complete description of these terms may be found in chapter four. In chapter four a full discussion of zener leakage, DC breakdown, zener impedance, temperature coefficients and many other topics may be found. decreases, and it follows that the low momentum intrinsic particles are less likely to ionize the lattice atoms. Naturally, increased voltage increases the acceleration of the intrinsic particles, providing higher mean momentum and more electron-hole pairs production. If the voltage is raised sufficiently, the mean momentum becomes great enough to create electron-hole pairs and carrier multiplication results. Hence, for increasing temperature, the value of the avalanche breakdown voltage increases. VOLT-AMPERE CHARACTERISTICS The zener volt-ampere characteristics for a typical 30 volt zener diode is illustrated in Figure 6. It shows that the zener diode conducts current in both directions; the forward current IF being a function of forward voltage VF. Note that IF is small until VF 0.65 V; then IF increases very rapidly. For VF > 0.65 V IF is limited primarily by the circuit resistance external to the diode. IZK = 5 mA VZ 5 IR ZZ K IZT 0 420 mA 0.5 ZZT IZM 1.40 A 30 20 10 VR (VOLTS) 0 REVERSE CHARACTERISTIC 0.5 1 VF (VOLTS) 1 1.5 1.5 REVERSE CURRENT (AMPS) 10 I F (AMPS) 15 FORWARD CHARACTERISTIC TYPICAL Figure 6. Zener Diode Characteristics The reverse current is a function of the reverse voltage VR but for most prNO TAGactical purposes is zero until the reverse voltage approaches VZ, the PN junction breakdown voltage, at which time the reverse current increases very rapidly. Since the reverse current is small for VR < VZ, but great for VR > VZ each of the current regions is specified by http://onsemi.com 7 ZENER DIODE FABRICATION TECHNIQUES INTRODUCTION have the same surge carrying capability as diffused diodes. The manufacturing process begins with the growing of high quality silicon crystals. Crystals for ON Semiconductor zener diodes are grown using the Czochralski technique, a widely used process which begins with ultra-pure polycrystalline silicon. The polycrystalline silicon is first melted in a nonreactive crucible held at a temperature just above the melting point. A carefully controlled quantity of the desired dopant impurity, such as phosphorus or boron is added. A high quality seed crystal of the desired crystalline orientation is then lowered into the melt while rotating. A portion of this seed crystal is allowed to melt into the molten silicon. The seed is then slowly pulled and continues to rotate as it is raised from the melt. As the seed is raised, cooling takes place and material from the melt adheres to it, thus forming a single crystal ingot. With this technique, ingots with diameters of several inches can be fabricated. A brief exposure to the techniques used in the fabrication of zener diodes can provide the engineer with additional insight using zeners in their applications. That is, an understanding of zener fabrication makes the capabilities and limitations of the zener diode more meaningful. This chapter discusses the basic steps in the fabrication of the zener from crystal growing through final testing. ZENER DIODE WAFER FABRICATION The major steps in the manufacture of zeners are provided in the process flow in Figure 1. It is important to point out that the manufacturing steps vary somewhat from manufacturer to manufacturer, and also vary with the type of zener diode produced. This is driven by the type of package required as well as the electrical characteristics desired. For example, alloy diffused devices provide excellent low voltage reference with low leakage characteristics but do not SILICON CRYSTAL GROWING WAFER PREPARATION OXIDE PASSIVATION WAFER THINNING ANODE METALLIZATION JUNCTION FORMATION CATHODE METALLIZATION WAFER TESTING WAFER DICING TEST LEAD FINISH ASSEMBLY MARK TEST PACKAGE SHIP Figure 1. General Flow of the Zener Diode Process http://onsemi.com 8 SILICON DIOXIDE SELECTIVELY REMOVED SILICON DIOXIDE GROWTH SiO2 Si (a) (b) DOPANT ATOMS DEPOSITED ONTO THE EXPOSED SILICON DOPANT ATOMS DIFFUSE INTO SILICON BUT NOT APPRECIABLY INTO THE SILICON DIOXIDE (c) (d) Figure 2. Basic Fabrication Steps in the Silicon Planar Process: a) oxide formation, b) selective oxide removal, c) deposition of dopant atoms, d) junction formation by diffusion of dopant atoms. Dopant is then introduced onto the wafer surface using various techniques such as aluminum alloy for low voltage devices, ion-implantation, spin-on dopants, or chemical vapor deposition. Once the dopant is deposited, the junctions are formed in a subsequent high temperature (1100 to 1250 degrees celcius are typical) drive-in. The resultant junction profile is determined by the background concentration of the starting substrate, the amount of dopant placed at the surface, and amount of time and temperature used during the dopant drive-in. This junction profile determines the electrical characteristics of the device. During the drive-in cycle, additional passivation oxide is grown providing additional protection for the devices. After junction formation, the wafers are then processed through what is called a getter process. The getter step utilizes high temperature and slight stress provided by a highly doped phosphosilicate glass layer introduced into the backside of the wafers. This causes any contaminants in the area of the junction to diffuse away from the region. This serves to improve the reverse leakage characteristic and the stability of the device. Following the getter process, a second photo resist step opens the contact area in which the anode metallization is deposited. Metal systems for ON Semiconductor's zener diodes are determined by the requirements of the package. The metal systems are deposited in ultra-clean vacuum chambers utilizing electron-beam evaporation techniques. Once the metal is deposited, photo resist processing is utilized to form the desired patterns. The wafers are then lapped to their final thickness and the cathode metallization deposited using the same e-beam process. Once the single-crystal silicon ingot is grown, it is tested for doping concentration (resistivity), undesired impurity levels, and minority carrier lifetime. The ingot is then sliced into thin, circular wafers. The wafers are then chemically etched to remove saw damage and polished in a sequence of successively finer polishing grits until a mirror-like defect free surface is obtained. The wafers are then cleaned and placed in vacuum sealed wafer carriers to prevent any contamination from getting on them. At this point, the wafers are ready to begin device fabrication. Zener diodes can be manufactured using different processing techniques such as planar processing or mesa etched processing. The majority of ON Semiconductor zener diodes are manufactured using the planar technique as shown in Figure 2. The planar process begins by growing an ultra-clean protective silicon dioxide passivation layer. The oxide is typically grown in the temperature range of 900 to 1200 degrees celcius. Once the protective layer of silicon dioxide has been formed, it must be selectively removed from those areas into which dopant atoms will be introduced. This is done using photolithographic techniques. First a light sensitive solution called photo resist is spun onto the wafer. The resist is then dried and a photographic negative or mask is placed over the wafer. The resist is then exposed to ultraviolet light causing the molecules in it to cross link or polymerize becoming very rigid. Those areas of the wafer that are protected by opaque portions of the mask are not exposed and are developed away. The oxide is then etched forming the exposed regions in which the dopant will be introduced. The remaining resist is then removed and the wafers carefully cleaned for the doping steps. http://onsemi.com 9 a solder disc is placed into each cavity and then a die is put in on top. A solder disc is put in on top of the die. Another assembly boat containing only leads is mated to the boat containing the leads, die, and two solder discs. The boats are passed through the assembly furnace; this operation requires only one pass through the furnace. After assembly, the leads on the Surmetic 30s, 40s and MOSORBs are plated with a tin-lead alloy making them readily solderable and corrosion resistant. The quality of the wafers is closely monitored throughout the process by using statistical process control techniques and careful microscopic inspections at critical steps. Special wafer handling equipment is used throughout the manufacturing process to minimize contamination and to avoid damaging the wafers in any way. This further enhances the quality and stability of the devices. Upon completion of the fabrication steps, the wafers are electrically probed, inspected, and packaged for shipment to the assembly operations. All ON Semiconductor zener diode product is sawn using 100% saw-through techniques stringently developed to provide high quality silicon die. Double Slug (DO-35 DO-35 and DO-41 DO-41) Double slugs receive their name from the dumet slugs, one attached to one end of each lead. These slugs sandwich the pre-tinned die between them and are hermetically sealed to the glass envelope or body during assembly. Figure 4 shows typical assembly. The assembly begins with the copper clad steel leads being loaded into assembly "boats." Every other boat load of leads has a glass body set over the slug. A pre-tinned die is placed into each glass body and the other boat load of leads is mated to the boat holding the leads, body and die. These mated boats are then placed into the assembly furnace where the total mass is heated. Each glass body melts; and as the boat proceeds through the cooling portion of the furnace chamber, the tin which has wetted to each slug solidifies forming a bond between the die and both slugs. The glass hardens, attaching itself to the sides of the two slugs forming the hermetic seal. The above illustrates how the diodes are completely assembled using a single furnace pass minimizing assembly problems. The encapsulated devices are then processed through lead finish. This consists of dipping the leads in molten tin/lead solder alloy. The solder dipped leads produce an external finish which is tarnish-resistant and very solderable. ZENER DIODE ASSEMBLY Surmetic 30, 40 and MOSORB The plastic packages (Surmetic 30, 40 and MOSORBs) are assembled using oxygen free high conductivity copper leads for efficient heat transfer from the die and allowing maximum power dissipation with a minimum of external heatsinking. Figure 3 shows typical assembly. The leads are of nail head construction, soldered directly to the die, which further enhances the heat dissipating capabilities of the package. The Surmetic 30s, 40s and MOSORBs are basically assembled in the same manner; the only difference being the MOSORBs are soldered together using a solder disc between the lead and die whereas the Surmetic 30s and Surmetic 40s utilize pre-soldered leads. Assembly is started on the Surmetic 30 and 40 by loading the leads into assembly boats and pre-soldering the nail heads. After pre-soldering, one die is then placed into each cavity of one assembly boat and another assembly boat is then mated to it. Since the MOSORBs do not use pre-soldered leads, the leads are put into the assembly boat, OFHC COPPER LEAD, SOLDER PLATED PLASTIC (THERMO SET) ENCAPSULATED LEAD, STEEL, CU CLAD SOLDER DIPPED NAILHEAD LEAD SLUG DUMET GLASS SLEEVE Sn Pb ZENER DIE PASSIVATED ZENER DIE NAILHEAD LEAD OFHC COPPER LEAD, SOLDER PLATED Figure 3. Double-Slug Plastic Zener Construction Figure 4. Double Slug Glass Zener Construction http://onsemi.com 10 ZENER DIODE TEST, MARK AND PACKAGING parameters as the units are being tested to ensure that the lot is testing well to the process average and compared against other lots of the same voltage. After testing, the units are marked as required by the specification. The markers are equipped to polarity orient the devices as well as perform 100% redundant test prior to packaging. After marking, the units are packaged either in "bulk" form or taped and reeled or taped and ammo packed to accommodate automatic insertion. Double Slug, Surmetic 30, 40 and MOSORB After lead finish, all products are final tested, whether they are double slug or of Surmetic construction, all are 100 percent final tested for zener voltage, leakage current, impedance and forward voltage drop. Process average testing is used which is based upon the averages of the previous lots for a given voltage line and package type. Histograms are generated for the various http://onsemi.com 11 RELIABILITY INTRODUCTION distributions will be centered within the specification limits with a product distribution of plus or minus Six Sigma about mean. Six Sigma capability, shown graphically in Figure 1, details the benefit in terms of yield and outgoing quality levels. This compares a centered distribution versus a 1.5 sigma worst case distribution shift. New product development at ON Semiconductor requires more robust design features that make them less sensitive to minor variations in processing. These features make the implementation of SPC much easier. A complete commitment to SPC is present throughout ON Semiconductor. All managers, engineers, production operators, supervisors and maintenance personnel have received multiple training courses on SPC techniques. Manufacturing has identified 22 wafer processing and 8 assembly steps considered critical to the processing of zener products. Processes, controlled by SPC methods, that have shown significant improvement are in the diffusion, photolithography and metallization areas. To better understand SPC principles, brief explanations have been provided. These cover process capability, implementation and use. ON Semiconductor's Quality System maintains "continuous product improvement" goals in all phases of the operation. Statistical process control (SPC), quality control sampling, reliability audits and accelerated stress testing techniques monitor the quality and reliability of its products. Management and engineering skills are continuously upgraded through training programs. This maintains a unified focus on Six Sigma quality and reliability from the inception of the product to final customer use. STATISTICAL PROCESS CONTROL ON Semiconductor's Discrete Group is continually pursuing new ways to improve product quality. Initial design improvement is one method that can be used to produce a superior product. Equally important to outgoing product quality is the ability to produce product that consistently conforms to specification. Process variability is the basic enemy of semiconductor manufacturing since it leads to product variability. Used in all phases of ON Semiconductor's product manufacturing, STATISTICAL PROCESS CONTROL (SPC) replaces variability with predictability. The traditional philosophy in the semiconductor industry has been adherence to the data sheet specification. Using SPC methods assures the product will meet specific process requirements throughout the manufacturing cycle. The emphasis is on defect prevention, not detection. Predictability through SPC methods requires the manufacturing culture to focus on constant and permanent improvements. Usually these improvements cannot be bought with state-of-the-art equipment or automated factories. With quality in design, process and material selection, coupled with manufacturing predictability, ON Semiconductor can produce world class products. The immediate effect of SPC manufacturing is predictability through process controls. Product centered and distributed well within the product specification benefits ON Semiconductor with fewer rejects, improved yields and lower cost. The direct benefit to ON Semiconductor's customers includes better incoming quality levels, less inspection time and ship-to-stock capability. Circuit performance is often dependent on the cumulative effect of component variability. Tightly controlled component distributions give the customer greater circuit predictability. Many customers are also converting to just-in-time (JIT) delivery programs. These programs require improvements in cycle time and yield predictability achievable only through SPC techniques. The benefit derived from SPC helps the manufacturer meet the customer's expectations of higher quality and lower cost product. Ultimately, ON Semiconductor will have Six Sigma capability on all products. This means parametric -6 -5s -4 -3 -2 -1 0 1 2 3 4 5 6 Standard Deviations From Mean Distribution Centered At ± 3 2700 ppm defective 99.73% yield Distribution Shifted ± 1.5 66810 ppm defective 93.32% yield At ± 4 63 ppm defective 99.9937% yield 6210 ppm defective 99.379% yield At ± 5 0.57 ppm defective 99.999943% yield 233 ppm defective 99.9767% yield At ± 6 0.002 ppm defective 99.9999998% yield 3.4 ppm defective 99.99966% yield Figure 1. AOQL and Yield from a Normal Distribution of Product With 6 Capability PROCESS CAPABILITY One goal of SPC is to ensure a process is CAPABLE. Process capability is the measurement of a process to produce products consistently to specification requirements. The purpose of a process capability study is to separate the inherent RANDOM VARIABILITY from ASSIGNABLE CAUSES. Once completed, steps are taken to identify and eliminate the most significant assignable causes. Random variability is generally present in the system and does not fluctuate. Sometimes, these are considered basic limitations associated with the machinery, materials, personnel skills or manufacturing methods. Assignable cause inconsistencies relate to time variations in yield, performance or reliability. http://onsemi.com 12 ? ? ? ? ? ? ? ? ? ? ? PREDICTION PREDICTION TIME TIME SIZE SIZE Process "under control" - all assignable causes are removed and future distribution is predictable. Figure 2. Impact of Assignable Causes on Process Predictable In control assignable causes eliminated Lower Specification Limit TIME Upper Specification Limit TIME Out of control (assignable causes present) SIZE In control and capable (variation from random variability reduced) In control but not capable (variation from random variability excessive) SIZE Figure 3. Difference Between Process Control and Process Capability SPC IMPLEMENTATION AND USE Traditionally, assignable causes appear to be random due to the lack of close examination or analysis. Figure 2 shows the impact on predictability that assignable cause can have. Figure 3 shows the difference between process control and process capability. A process capability study involves taking periodic samples from the process under controlled conditions. The performance characteristics of these samples are charted against time. In time, assignable causes can be identified and engineered out. Careful documentation of the process is key to accurate diagnosis and successful removal of the assignable causes. Sometimes, the assignable causes will remain unclear requiring prolonged experimentation. Elements which measure process variation control and capability are Cp and Cpk respectively. Cp is the specification width divided by the process width or Cp = (specification width) / 6. Cpk is the absolute value of the closest specification value to the mean, minus the mean, divided by half the process width or Cpk = | closest specification - X / 3. At ON Semiconductor, for critical parameters, the process capability is acceptable with a Cpk = 1.33. The desired process capability is a Cpk = 2 and the ideal is a Cpk = 5. Cpk, by definition, shows where the current production process fits with relationship to the specification limits. Off center distributions or excessive process variability will result in less than optimum conditions. The Discrete Group uses many parameters that show conformance to specification. Some parameters are sensitive to process variations while others remain constant for a given product line. Often, specific parameters are influenced when changes to other parameters occur. It is both impractical and unnecessary to monitor all parameters using SPC methods. Only critical parameters that are sensitive to process variability are chosen for SPC monitoring. The process steps affecting these critical parameters must be identified also. It is equally important to find a measurement in these process steps that correlates with product performance. This is called a critical process parameter. Once the critical process parameters are selected, a sample plan must be determined. The samples used for measurement are organized into RATIONAL SUBGROUPS of approximately 2 to 5 pieces. The subgroup size should be such that variation among the samples within the subgroup remain small. All samples must come from the same source e.g., the same mold press operator, etc. Subgroup data should be collected at appropriate time intervals to detect variations in the process. As the process begins to show improved stability, the interval may be increased. The data collected must be carefully documented and maintained for later correlation. Examples of common documentation entries would include operator, machine, time, settings, product type, etc. http://onsemi.com 13 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 1 154 153 UCL = 152.8 152 151 X = 150.4 150 149 LCL = 148.0 148 147 UCL = 7.3 7 6 5 4 R = 3.2 3 2 1 LCL = 0 0 Figure 4. Example of Process Control Chart Showing Oven Temperature Data problems with piece to piece variability related to the process. The X chart can often identify changes in people, machines, methods, etc. The source of the variability can be difficult to find and may require experimental design techniques to identify assignable causes. Some general rules have been established to help determine when a process is OUT-OF-CONTROL. Figure 5a shows a control chart subdivided into zones A, B, and C corresponding to 3 sigma, 2 sigma, and 1 sigma limits respectively. In Figure 5b through Figure 5e four of the tests that can be used to identify excessive variability and the presence of assignable causes are shown. As familiarity with a given process increases, more subtle tests may be employed successfully. Once the variability is identified, the cause of the variability must be determined. Normally, only a few factors have a significant impact on the total variability of the process. The importance of correctly identifying these factors is stressed in the following example. Suppose a process variability depends on the variance of five factors A, B, C, D and E. Each has a variance of 5, 3, 2, 1 and 0.4 respectively. Once the plan is established, data collection may begin. The data collected will generate X and R values that are plotted with respect to time. X refers to the mean of the values within a given subgroup, while R is the range or greatest value minus least value. When approximately 20 or more X and R values have been generated, the average of these values is computed as follows: X = (X + X2 + X3 + .)/K R = (R1 + R2 + R3 + .)/K where K = the number of subgroups measured. The values of X and R are used to create the process control chart. Control charts are the primary SPC tool used to signal a problem. Shown in Figure 4, process control charts show X and R values with respect to time and concerning reference to upper and lower control limit values. Control limits are computed as follows: R R X X upper lower upper lower control control control control limit limit limit limit = UCLR = D4 R LCLR = D3 R = UCLX = X + A2 R = LCLX = X - A Since: Where D4, D3 and A2 are constants varying by sample size, with values for sample sizes from 2 to 10 shown in the following partial table: Control charts are used to monitor the variability of critical process parameters. The R chart shows basic tot = A2 + B2 + C2 + D2 + E2 52 + 32 + 22 + 12 + (0.4)2 = 6.3 tot = n 2 3 4 5 6 7 8 9 10 D4 3.27 2.57 2.28 2.11 2.00 1.92 1.86 1.82 1.78 D3 * * * * * 0.08 0.14 0.18 0.22 A2 1.88 1.02 0.73 0.58 0.48 0.42 0.37 0.34 0.31 * For sample sizes below 7, the LCLR would technically be a negative number; in those cases there is no lower control limit; this means that for a subgroup size 6, six "identical" measurements would not be unreasonable. http://onsemi.com 14 be identified and eliminated in the most expeditious manner possible. After assignable causes have been eliminated, new control limits are calculated to provide a more challenging variability criteria for the process. As yields and variability improve, it may become more difficult to detect improvements because they become much smaller. When all assignable causes have been eliminated and the points remain within control limits for 25 groups, the process is said to be in a state of control. Now if only D is identified and eliminated then; s tot = 52 + 32 + 22 + (0.4)2 = 6.2 This results in less than 2% total variability improvement. If B, C and D were eliminated, then; tot = 52 + (0.4)2 = 5.02 This gives a considerably better improvement of 23%. If only A is identified and reduced from 5 to 2, then; tot = 22 + 32 + 22 + 12 + (0.4)2 = 4.3 Identifying and improving the variability from 5 to 2 gives us a total variability improvement of nearly 40%. Most techniques may be employed to identify the primary assignable cause(s). Out-of-control conditions may be correlated to documented process changes. The product may be analyzed in detail using best versus worst part comparisons or Product Analysis Lab equipment. Multi-variance analysis can be used to determine the family of variation (positional, critical or temporal). Lastly, experiments may be run to test theoretical or factorial analysis. Whatever method is used, assignable causes must SUMMARY ON Semiconductor is committed to the use of STATISTICAL PROCESS CONTROLS. These principles, used throughout manufacturing, have already resulted in many significant improvements to the processes. Continued dedication to the SPC culture will allow ON Semiconductor to reach the Six Sigma and zero defect capability goals. SPC will further enhance the commitment to TOTAL CUSTOMER SATISFACTION. UCL A ZONE A (+ 3 SIGMA) UCL B ZONE B (+ 2 SIGMA) ZONE C (+ 1 SIGMA) C CENTERLINE ZONE C (- 1 SIGMA) C ZONE B (- 2 SIGMA) B ZONE A (- 3 SIGMA) A LCL Figure 5a. Control Chart Zones A LCL Figure 5b. One Point Outside Control Limit Indicating Excessive Variability UCL A B B C C C C B UCL B A A LCL Figure 5c. Two Out of Three Points in Zone A or Beyond Indicating Excessive Variability LCL Figure 5d. Four Out of Five Points in Zone B or Beyond Indicating Excessive Variability UCL A B C C B A LCL Figure 5e. Seven Out of Eight Points in Zone C or Beyond Indicating Excessive Variability http://onsemi.com 15 RELIABILITY STRESS TESTS HIGH TEMPERATURE STORAGE LIFE (HTSL) High temperature storage life testing is performed to accelerate failure mechanisms which are thermally activated through the application of extreme temperatures. Typical Test Conditions: TA = 70°C to 200°C, no bias, t = 24 to 2500 hours Common Failure Modes: Parametric shifts in leakage Common Failure Mechanisms: Bulk die and diffusion defects Military Reference: MIL-STD-750 MIL-STD-750, Method 1032 The following gives brief descriptions of the reliability tests commonly used in the reliability monitoring program. Not all of the tests listed are performed on each product. Other tests may be performed when appropriate. In addition some form of preconditioning may be used in conjunction with the following tests. AUTOCLAVE (aka, PRESSURE COOKER) Autoclave is an environmental test which measures device resistance to moisture penetration and the resultant effects of galvanic corrosion. Autoclave is a highly accelerated and destructive test. Typical Test Conditions: TA = 121°C, rh = 100%, p = 1 atmosphere (15 psig), t = 24 to 96 hours Common Failure Modes: Parametric shifts, high leakage and/or catastrophic Common Failure Mechanisms: Die corrosion or contaminants such as foreign material on or within the package materials. Poor package sealing INTERMITTENT OPERATING LIFE (IOL) The purpose of this test is the same as SSOL in addition to checking the integrity of both wire and die bonds by means of thermal stressing. Typical Test Conditions: TA = 25°C, Pd = Data Book maximum rating, Ton = Toff = of 50°C to 100°C, t = 42 to 30000 cycles Common Failure Modes: Parametric shifts and catastrophic Common Failure Mechanisms: Foreign material, crack and bulk die defects, metallization, wire and die bond defects Military Reference: MIL-STD-750 MIL-STD-750, Method 1037 HIGH HUMIDITY HIGH TEMPERATURE BIAS (H3TB or H3TRB) This is an environmental test designed to measure the moisture resistance of plastic encapsulated devices. A bias is applied to create an electrolytic cell necessary to accelerate corrosion of the die metallization. With time, this is a catastrophically destructive test. Typical Test Conditions: TA = 85°C to 95°C, rh = 85% to 95%, Bias = 80% to 100% of Data Book max. rating, t = 96 to 1750 hours Common Failure Modes: Parametric shifts, high leakage and/or catastrophic Common Failure Mechanisms: Die corrosion or contaminants such as foreign material on or within the package materials. Poor package sealing Military Reference: MIL-STD-750 MIL-STD-750, Method 1042 MECHANICAL SHOCK This test is used to determine the ability of the device to withstand a sudden change in mechanical stress due to abrupt changes in motion as seen in handling, transportation, or actual use. Typical Test Conditions: Acceleration = 1500 g's, Orientation = X1, Y1, Y2 plane, t = 0.5 msec, Blows = 5 Common Failure Modes: Open, short, excessive leakage, mechanical failure Common Failure Mechanisms: Die and wire bonds, cracked die, package defects Military Reference: MIL-STD-750 MIL-STD-750, Method 2015 HIGH TEMPERATURE REVERSE BIAS (HTRB) MOISTURE RESISTANCE The purpose of this test is to align mobile ions by means of temperature and voltage stress to form a high-current leakage path between two or more junctions. Typical Test Conditions: TA = 85°C to 150°C, Bias = 80% to 100% of Data Book max. rating, t = 120 to 1000 hours Common Failure Modes: Parametric shifts in leakage Common Failure Mechanisms: Ionic contamination on the surface or under the metallization of the die Military Reference: MIL-STD-750 MIL-STD-750, Method 1039 The purpose of this test is to evaluate the moisture resistance of components under temperature/humidity conditions typical of tropical environments. Typical Test Conditions: TA = -10°C to 65°C, rh = 80% to 98%, t = 24 hours/cycle, cycle = 10 Common Failure Modes: Parametric shifts in leakage and mechanical failure Common Failure Mechanisms: Corrosion or contaminants on or within the package materials. Poor package sealing Military Reference: MIL-STD-750 MIL-STD-750, Method 1021 http://onsemi.com 16 SOLDERABILITY and transitions between temperature extremes. This testing will also expose excessive thermal mismatch between materials. Typical Test Conditions: TA = -65°C to 200°C, cycle = 10 to 1000 Common Failure Modes: Parametric shifts and catastrophic Common Failure Mechanisms: Wire bond, cracked or lifted die and package failure Military Reference: MIL-STD-750 MIL-STD-750, Method 1051 The purpose of this test is to measure the ability of device leads/terminals to be soldered after an extended period of storage (shelf life). Typical Test Conditions: Steam aging = 8 hours, Flux = R, Solder = Sn60, Sn63 Common Failure Modes: Pin holes, dewetting, non-wetting Common Failure Mechanisms: Poor plating, contaminated leads Military Reference: MIL-STD-750 MIL-STD-750, Method 2026 THERMAL SHOCK (LIQUID TO LIQUID) SOLDER HEAT The purpose of this test is to evaluate the ability of the device to withstand both exposure to extreme temperatures and sudden transitions between temperature extremes. This testing will also expose excessive thermal mismatch between materials. Typical Test Conditions: TA = 0°C to 100°C, cycles = 10 to 1000 Common Failure Modes: Parametric shifts and catastrophic Common Failure Mechanisms: Wire bond, cracked or lifted die and package failure Military Reference: MIL-STD-750 MIL-STD-750, Method 1056 This test is used to measure the ability of a device to withstand the temperatures as may be seen in wave soldering operations. Electrical testing is the endpoint criterion for this stress. Typical Test Conditions: Solder Temperature = 260°C, t = 10 seconds Common Failure Modes: Parameter shifts, mechanical failure Common Failure Mechanisms: Poor package design Military Reference: MIL-STD-750 MIL-STD-750, Method 2031 STEADY STATE OPERATING LIFE (SSOL) VARIABLE FREQUENCY VIBRATION The purpose of this test is to evaluate the bulk stability of the die and to generate defects resulting from manufacturing aberrations that are manifested as time and stress-dependent failures. Typical Test Conditions: TA = 25°C, PD = Data Book maximum rating, t = 16 to 1000 hours Common Failure Modes: Parametric shifts and catastrophic Common Failure Mechanisms: Foreign material, crack die, bulk die, metallization, wire and die bond defects Military Reference: MIL-STD-750 MIL-STD-750, Method 1026 This test is used to examine the ability of the device to withstand deterioration due to mechanical resonance. Typical Test Conditions: Peak acceleration = 20 g's, Frequency range = 20 Hz to 20 kHz, t = 48 minutes. Common Failure Modes: Open, short, excessive leakage, mechanical failure Common Failure Mechanisms: Die and wire bonds, cracked die, package defects Military Reference: MIL-STD-750 MIL-STD-750, Method 2056 TEMPERATURE CYCLING (AIR TO AIR) The purpose of this test is to evaluate the ability of the device to withstand both exposure to extreme temperatures http://onsemi.com 17 ZENER DIODE CHARACTERISTICS At first glance the zener diode is a simple device consisting of one P-N junction with controlled breakdown voltage properties. However, when considerations are given to the variations of temperature coefficient, zener impedance, thermal time response, and capacitance, all of which are a function of the breakdown voltage (from 1.8 to 400 V), a much more complicated picture arises. In addition to the voltage spectrum, a variety of power packages are on the market with a variation of dice area inside the encapsulation. This chapter is devoted to sorting out the important considerations in a "typical" fashion. For exact details, the data sheets must be consulted. However, much of the information contained herein is supplemental to the data sheet curves and will broaden your understanding of zener diode behavior. Specifically, the following main subjects will be detailed: Basic DC Volt-Ampere Characteristics Impedance versus Voltage and Current Temperature Coefficient versus Voltage and Current Power Derating Mounting Thermal Time Response - Effective Thermal Impedance Surge Capabilities Frequency Response - Capacitance and Switching Effects FORWARD CURRENT INTRODUCTION REVERSE VOLTAGE FORWARD CHARACTERISTIC REVERSE CURRENT LEAKAGE REGION BREAKDOWN REGION FORWARD VOLTAGE Figure 1. Typical Zener Diode DC V-I Characteristics (Not to Scale) While the common form of the diode equation suggests that IR is constant, in fact IR is itself strongly temperature dependent. The rapid increase in IR with increasing temperature dominates the decrease contributed by the exponential term in the diode equation. As a result, the forward current increases with increasing temperature. Figure 2 shows a forward characteristic temperature dependence for a typical zener. These curves indicate that for a constant current, an increase in temperature causes a decrease in forward voltage. The voltage temperature coefficient values are typically in the range of -1.4 to -2 mV/°C. BASIC ZENER DIODE DC VOLT-AMPERE CHARACTERISTICS 1000 500 I F , FORWARD CURRENT (mA) Reverse and forward volt-ampere curves are represented in Figure 1 for a typical zener diode. The three areas - forward, leakage, and breakdown - will each be examined. FORWARD DC CHARACTERISTICS The forward characteristics of a zener diode are essentially identical with an "ordinary" rectifier and is shown in Figure 2. The volt-ampere curve follows the basic diode equation of IF = IReqV/KT where KT/q equals about 0.026 volts at room temperature and IR (reverse leakage current) is dependent upon the doping levels of the P-N junction as well as the area. The actual plot of VF versus IF deviates from the theoretical due to slightly "fixed" series resistance of the lead wire, bonding contacts and some bulk effects in the silicon. 200 100 50 20 10 TJ = 150°C 100°C 25°C -55°C 5 2 1 0.3 0.4 0.5 0.6 0.7 0.8 0.9 VF, FORWARD VOLTAGE (VOLTS) Figure 2. Typical Forward Characteristics of Zener Diodes http://onsemi.com 18 1 LEAKAGE DC CHARACTERISTICS 1000 500 I Z , ZENER CURRENT (mA) When reverse voltage less than the breakdown is applied to a zener diode, the behavior of current is similar to any back-biased silicon P-N junction. Ideally, the reverse current would reach a level at about one volt reverse voltage and remain constant until breakdown is reached. There are both theoretical and practical reasons why the typical V-I curve will have a definite slope to it as seen in Figure 3. Multiplication effects and charge generation sites are present in a zener diode which dictate that reverse current (even at low voltages) will increase with voltage. In addition, surface charges are ever present across P-N junctions which appear to be resistive in nature. The leakage currents are generally less than one microampere at 150°C except with some large area devices. Quite often a leakage specification at 80% or so of breakdown voltage is used to assure low reverse currents. 20 10 5 2 1 0.5 0.2 0.1 25 T = -55°C 26 25°C 27 100°C 28 29 150°C 30 31 32 VZ, ZENER VOLTAGE (VOLTS) Figure 4. Typical Zener Characteristic Variation with Temperature An exaggerated view of the knee region is shown in Figure 5. As can be seen, the breakdown or avalanche current does not increase suddenly, but consists of a series of smoothly rising current versus voltage increments each with a sudden break point. 10000 1000 TJ = 150°C CURRENT 100 10 ZENER CURRENT IR , REVERSE LEAKAGE CURRENT (nA) T = TJ T = TA 200 100 50 25°C 1 -55°C 0.1 0 4 6 12 16 20 VOLTAGE EXAGGERATED V-I OF KNEE REGION VR, REVERSE VOLTAGE (VOLTS) Figure 3. Typical Leakage Current versus Voltage ZENER VOLTAGE VOLTAGE BREAKDOWN Figure 5. Exaggerated V-I Characteristics of the Knee Region At some definite reverse voltage, depending on the doping levels (resistivity) of the P-N junction, the current will begin to avalanche. This is the so-called "zener" or "breakdown" area and is where the device is usually biased during use. A typical family of breakdown curves showing the effect of temperature is illustrated in Figure 4. Between the minimum currents shown in Figure 4 and the leakage currents, there is the "knee" region. The avalanche mechanism may not occur simultaneously across the entire area of the P-N junction, but first at one microscopic site, then at an increasing number of sites as further voltage is applied. This action can be accounted for by the "microplasma discharge" theory and correlates with several breakdown characteristics. At the lowest point, the zener resistance (slope of the curve) would test high, but as current continues to climb, the resistance decreases. It is as though each discharge site has high resistance with each succeeding site being in parallel until the total resistance is very small. In addition to the resistive effects, the micro plasmas may act as noise generators. The exact process of manufacturing affects how high the noise will be, but in any event there will be some noise at the knee, and it will diminish considerably as current is allowed to increase. Since the zener impedance and the temperature coefficient are of prime importance when using the zener diode as a reference device, the next two sections will expand on these points. http://onsemi.com 19 ZENER IMPEDANCE 100 ZENER CURRENT (mA) The slope of the VZ - IZ curve (in breakdown) is defined as zener impedance or resistance. The measurement is generally done with a 60 Hz (on modern, computerized equipment this test is being done at 1 kHz) current variation whose value is 10% in rms of the dc value of the current. (That is, IZ peak to peak = 0.282 IZ.) This is really not a small signal measurement but is convenient to use and gives repeatable results. The zener impedance always decreases as current increases, although at very high currents (usually beyond IZ max) the impedance will approach a constant. In contrast, the zener impedance decreases very rapidly with increasing current in the knee region. On Semiconductor specifies most zener diode impedances at two points: IZT and IZK. The term IZT usually is at the quarter power point, and IZK is an arbitrary low value in the knee region. Between these two points a plot of impedance versus current on a log-log scale is close to a straight line. Figure 6 shows a typical plot of ZZ versus IZ for a 20 volt-500 mW zener. The worst case impedance between IZT and IZK could be approximated by assuming a straight line function on a log-log plot; however, at currents above IZT or below IZK a projection of this line may give erroneous values. 0.1 2 1 3 4 5 6 7 8 ZENER VOLTAGE (VOLTS) Figure 7. Zener Current versus Zener Voltage (Low Voltage Region) Possibly the plots shown in Figure 8 of zener impedance versus voltage at several constant IZ's more clearly points out this effect. It is obvious that zener diodes whose breakdowns are about 7 volts will have remarkably low impedance. 200 Z Z , DYNAMIC IMPEDANCE (OHMS) ZENER IMPEDANCE (OHMS) 1 0.01 1000 ZZK(MAX) 10 APPROXIMATE MAXIMUM LINE 100 ZZT(MAX) 10 100 70 50 1 mA TA = 25°C IZ(ac) = 0.1 IZ(dc) 30 20 10 mA 10 7 5 20 mA 3 2 2 3 5 7 10 20 30 50 70 100 200 VZ, ZENER VOLTAGE (VOLTS) 1 0.1 1 10 Figure 8. Dynamic Zener Impedance (Typical) versus Zener Voltage 100 ZENER CURRENT (mA) However, this is not the whole picture. A zener diode figure of merit as a regulator could be ZZ/VZ. This would give some idea of what percentage change of voltage could be expected for some given change in current. Of course, a low ZZ/VZ is desirable. Generally zener current must be decreased as voltage is increased to prevent excessive power dissipation; hence zener impedance will rise even higher and the "figure of merit" will become higher as voltage increases. This is the case with IZT taken as the test point. However, if IZK is used as a comparison level in those devices which keep a constant IZK over a large range of voltage, the "figure of merit" will exhibit a bowl-shaped curve - first decreasing and then increasing as voltage is increased. Typical plots are shown in Figure 9. The conclusion can be reached that for uses where wide swings of current may occur and the quiescent bias current must be high, the lower voltage zener will provide best regulation, Figure 6. Zener Impedance versus Zener Current The impedance variation with voltage is much more complex. First of all, zeners below 6 volts or so exhibit "field emission" breakdown converting to "avalanche" at higher currents. The two breakdowns behave somewhat differently with "field emission" associated with high impedance and negative temperature coefficients and "avalanche" with lower impedance and positive temperature coefficients. A V-I plot of several low voltage 500 mW zener diodes is shown in Figure 7. It is seen that at some given current (higher for the lower voltage types) there is a fairly sudden decrease in the slope of V/I. Apparently, this current is the transition from one type of breakdown to the other. Above 6 volts the curves would show a gradual decrease of V/I rather than an abrupt change, as current is increased. http://onsemi.com 20 9.3 volts at 75°C for all useful current levels (disregarding impedance effects). As was mentioned, the situation is further complicated by the normal deviation of TC at a given current. For example, for 7.5 mA the normal spread of TC (expressed in %/°C) is shown in Figure 11. This is based on limited samples and in no manner implies that all On Semiconductor zeners between 2 and 12 volts will exhibit this behavior. At other current levels similar deviations would occur. 100 400 mW, ZZK(MAX) AT 0.25 mA 0.85 mA 1.3 mA 10 W, ZZK(MAX) AT 1 mA 10 12.5 mA 3.8 mA SEE NOTE BELOW 1.7 mA 1 +0.08 TEMPERATURE COEFFICIENT (%/° C) ZENER IMPEDANCE (MAX)/ZENER VOLTAGE but for low power applications, the best performance could be obtained between 50 and 100 volts. 400 mW, ZZT(MAX) 250 mA 0.1 10 75 mA 17 mA 28 mA 10 W, ZZT(MAX) 30 50 70 90 110 130 150 ZENER VOLTAGE (VOLTS) (NOTE: CURVE IS APPROXIMATE, ACTUAL ZZ(MAX) IS ROUNDED OFF TO NEAREST WHOLE NUMBER ON A DATA SHEET) Figure 9. Figure of Merit: ZZ(Max)/VZ versus VZ (400 mW & 10 W Zeners) +0.04 +0.02 -0.02 -0.04 -0.06 MAX 2 4 6 8 10 12 14 Figure 11. Temperature Coefficient Spread versus Zener Voltage Obviously, all of these factors make it very difficult to attempt any calculation of precise voltage shift due to temperature. Except in devices with specified maximum T.C., no "worse case" design is possible. Information concerning the On Semiconductor temperature compensated or reference diodes is given in Chapter 4. Typical temperature characteristics for a broad range of voltages is illustrated in Figure 12. This graphically shows the significant change in voltage for high voltage devices (about a 20 volt increase for a 100°C increase on a 200 volt device). 6 VZ REFERENCE AT IZ = IZT & TA = 25°C 3 2 1 100 0.01 mA 10 mA 0 30 mA -1 0.1 mA V Z (+25 °C TO +125 °C) TC , TEMPERATURE COEFFICIENTS (mV/° C) 0 ZENER VOLTAGE (VOLTS) 7 1 mA -2 -3 MIN TYPICAL -0.08 -0.10 Below three volts and above eight volts the zener voltage change due to temperature is nearly a straight line function and is almost independent of current (disregarding self-heating effects). However, between three and eight volts the temperature coefficients are not a simple affair. A typical plot of TC versus VZ is shown in Figure 10. 4 IZT = 7.5 mA 0 TEMPERATURE COEFFICIENT 5 MAX TYPICAL MIN +0.06 2 3 4 5 6 7 8 9 10 11 12 VZ, ZENER VOLTAGE (VOLTS) Figure 10. Temperature Coefficient versus Zener Voltage at 25°C Conditions Typical Any attempt to predict voltage changes as temperature changes would be very difficult on a "typical" basis. (This, of course, is true to a lesser degree below three volts and above eight volts since the curve shown is a typical one and slight deviations will exist with a particular zener diode.) For example, a zener which is 5 volts at 25°C could be from 4.9 to 5.05 volts at 75°C depending on the current level. Whereas, a zener which is 9 volts at 25°C would be close to 10 1 NOTE: DV IS + ABOVE 5 VOLTS - BELOW 4.3 VOLTS BETWEEN 4.3 & 5 VOLTS VARIES ABOUT + 0.08 VOLTS 0.1 0.01 1 2 3 5 10 50 100 200 ZENER VOLTAGE (VOLTS) Figure 12. Typical Temperature Characteristics http://onsemi.com 21 1,000 PD , MAXIMUM POWER DISSIPATION (WATTS) POWER DERATING AND MOUNTING The zener diode like any other semiconductor has a maximum junction temperature. This limit is somewhat arbitrary and is set from a reliability viewpoint. Most semiconductors exhibit an increasing failure rate as temperature increases. At some temperature, the solder will melt or soften and the failure rate soars. The 175°C to 200°C junction temperature rating is quite safe from solder failures and still has a very low failure rate. In order that power dissipated in the device will never cause the junction to rise beyond 175°C or 200°C (depending on the device), the relation between temperature rise and power must be known. Of course, the thermal resistance (RJA or RJL) is the factor which relates power and temperature in the well known "Thermal Ohm's Law'' relation: T = TJ - TA = RJAPZ where TJ TA TL RJA RJL PZ 1 L = 1/8 L = 3/8 0.75 0.50 0.25 0 20 40 60 80 100 120 140 160 180 200 TL, LEAD TEMPERATURE (°C) Figure 14. Power Temperature Derating Curve (2) A lead mounted device can have its power rating increased by shortening the lead length and "heatsinking" the ends of the leads. This effect is shown in Figure 15, for the 1N4728 1N4728, 1 watt zener diode. Each zener has a derating curve on its data sheet and steady state power can be set properly. However, temperature increases due to pulse use are not so easily calculated. The use of "Transient Thermal Resistance" would be required. The next section expounds upon transient thermal behavior as a function of time and surge power. = Junction temperature = Ambient temperature = Lead temperature = Thermal resistance junction to ambient = Thermal resistance junction to lead = Zener power dissipation Obviously, if ambient or lead temperature is known and the appropriate thermal resistance for a given device is known, the junction temperature could be precisely calculated by simply measuring the zener dc current and voltage (PZ = IZVZ). This would be helpful to calculate voltage change versus temperature. However, only maximum and typical values of thermal resistance are given for a family of zener diodes. So only "worst case" or typical information could be obtained as to voltage changes. The relations of equations 1 and 2 are usually expressed as a graphical derating of power versus the appropriate temperature. Maximum thermal resistance is used to generate the slope of the curve. An example of a 400 milliwatt device derated to the ambient temperature and a 1 watt device derated to the lead temperature are shown in Figures 13 and 14. PD , POWER DISSIPATION (MILLIWATTS) L = LEAD LENGTH TO HEAT SINK L = 1 (1) T = TJ - TL = RJLPZ and 1.25 RqJL, JUNCTION-TO-LEAD THERMAL RESISTANCE (°C/W) 175 150 125 100 75 50 25 0 500 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 L, LEAD LENGTH TO HEAT SINK (INCH) 400 Figure 15. Typical 1N4728 1N4728 Thermal Resistance versus Lead Length 300 THERMAL TIME RESPONSE Early studies of zener diodes indicated that a "thermal time constant" existed which allowed calculation of temperature rise as a function of power pulse height, width, and duty cycle. More precise measurements have shown that temperature response as a function of time cannot be represented as a simple time constant. Although as shown in the preceding section, the steady state conditions are analogous in every way to an electrical resistance; a simple "thermal capacitance" placed across the resistor is not the true equivalent circuit. Probably a series of parallel R-C 200 100 0 25 50 75 100 125 150 TA, AMBIENT TEMPERATURE (°C) 175 200 Figure 13. 400 mW Power Temperature Derating Curve http://onsemi.com 22 networks or lumped constants representing a thermal transmission line would be more accurate. Fortunately a concept has developed in the industry wherein the exact thermal equivalent circuit need not be found. If one simply accepts the concept of a thermal resistance which varies with time in a predictable manner, the situation becomes very practical. For each family of zener diodes, a "worst case" transient thermal resistance curve may be generated. The main use of this transient RJL curve is when the zener is used as a clipper or a protective device. First of all, the power wave shape must be constructed. (Note, even though the power-transient thermal resistance indicates reasonable junction temperatures, the device still may fail if the peak current exceeds certain values. Apparently a current crowding effect occurs which causes the zener to short. This is discussed further in this section.) PEAK TEMPERATURE RISE AVERAGE TEMPERATURE RISE AMBIENT TEMPERATURE PEAK POWER (PP) T T1 Figure 17. Relation of Junction Temperature to Power Pulses This method will predict the temperature rise at the end of the power pulse after the chain of pulses has reached equilibrium. In other words, the average power will have caused an average temperature rise which has stabilized, but a temperature "ripple" is present. TRANSIENT POWER-TEMPERATURE EFFECTS A typical transient thermal resistance curve is shown in Figure 16. This is for a lead mounted device and shows the effect of lead length to an essentially infinite heatsink. To calculate the temperature rise, the power surge wave shape must be approximated by its rectangular equivalent as shown in Figure 17. In case of an essentially non-recurrent pulse, there would be just one pulse, and T = RT1 Pp. In the general case, it can be shown that Example: (Use curve in Figure 16) Then T = [DRJA (ss) + (1 - D) RT1 + T + RT1 - RT] PP where D RT1 = Duty cycle in percent = Transient thermal resistance at the time equal to the pulse width = Transient thermal resistance at the time RT equal to pulse interval RT1 + T = Transient thermal resistance at the time equal to the pulse interval = plus one more pulse width. RJA(ss) or RJL(ss) = Steady state value of thermal RJA(ss) or RJL(ss) = resistance RJL(t), JUNCTION-TO-LEAD TRANSIENT THERMAL RESISTANCE (°C/W) 10 ÉÉ ÉÉ 30 20 L HEAT SINK 7 5 3 5 10 20 50 100 200 RT1 = 1.8°C/W RT = 5.8°C/W RT1 + T = 6°C/W SURGE FAILURES If no other considerations were present, it would be a simple matter to specify a maximum junction temperature no matter what pulses are present. However, as has been noted, apparently other fault conditions prevail. The same group of devices for which the transient thermal curves were generated were tested by subjecting them to single shot power pulses. A failure was defined as a significant shift of leakage or zener voltage, or of course opens or shorts. Each device was measured before and after the applied pulse. Most failures were shifts in zener voltage. The results are shown in Figure 18. Attempts to correlate this to the transient thermal resistance work quite well on a typical basis. For example, assuming a value for 1 ms of 90 watts and 35 watts at 10 ms, the predicted temperature rise would be 180°C and 190°C. But on a worst case basis, the temperature rises would be about one half these values or junction temperatures, on the order of 85°C to 105°C, which are obviously low. Apparently at very high power levels a current restriction occurs causing hot spots. There was no apparent correlation L = 1 L = 1/32 500 1000 2000 5000 10k PP = 5 watt (Lead length 1/32) D = 0.1 T1 = 10 ms T = 100 ms RJA(ss) = 12°C/W (for 1/32 lead length) T = [0.1 x 12 + (1 - 0.1) 6 + 1.8 - 5.8] 5 T = 13°C Or at TA = 25°, TJ = 38°C peak FOR JL(t) VALUES AT PULSE WIDTHS LESS THAN 3.0 ms, THE ABOVE CURVE CAN BE EXTRAPOLATED DOWN TO 10 s AT A CONTINUING SLOPE OF 1/2 3 2 1 And L ÉÉ ÉÉ 100 70 50 T1 AVERAGE POWER = T PP 30k PW, PULSE WIDTH (ms) Figure 16. Typical Transient Thermal Resistance (For Axial Lead Zener) http://onsemi.com 23 FREQUENCY AND PULSE CHARACTERISTICS of zener voltage or current on the failure points since each group of failures contained a mixture of voltages. The zener diode may be used in applications which require a knowledge of the frequency response of the device. Of main concern are the zener resistance (usually specified as "impedance") and the junction capacitance. The capacitance curves shown in this section are typical. POWER (WATTS) 1000 100 TYPICAL ZENER CAPACITANCE Since zener diodes are basically PN junctions operated in the reverse direction, they display a capacitance that decreases with increasing reverse voltage. This is so because the effective width of the PN junction is increased by the removal of charges (holes and electrons) as reverse voltage is increased. This decrease in capacitance continues until the zener breakdown region is entered; very little further capacitance change takes place, owing to the now fixed voltage across the junction. The value of this capacitance is a function of the material resistivity, , (amount of doping - which determines VZ nominal), the diameter, D, of junction or dice size (determines amount of power dissipation), the voltage across the junction VC, and some constant, K. This relationship can be expressed as: WORSE CASE 10 1 0.00001 0.0001 0.001 0.01 0.1 1 TIME OF PULSE (SECONDS) Figure 18. One Shot Power Failure Axial Lead Zener Diode VOLTAGE VERSUS TIME Quite often the junction temperature is only of academic interest, and the designer is more concerned with the voltage behavior versus time. By using the transient thermal resistance, the power, and the temperature coefficient, the designer could generate VZ versus time curves. The On Semiconductor zener diode test group has observed device voltages versus time until the thermal equilibrium was reached. A typical curve is shown for a lead mounted low wattage device in Figure 19 where the ambient temperature was maintained constant. It is seen that voltage stabilizes in about 100 seconds for 1 inch leads. Since information contained in this section may not be found on data sheets it is necessary for the designer to contact the factory when using a zener diode as a surge suppressor. Additional information on transient suppression application is presented elsewhere in this book. CC = ZENER VOLTAGE (VOLTS) 165 164 163 162 161 0.1 1 10 KD4 n KD4 pVC VC After the junction enters the zener region, capacitance remains relatively fixed and the AC resistance then decreases with increasing zener current. TEST CIRCUIT CONSIDERATIONS: A capacitive bridge was used to measure junction capacitance. In this method the zener is used as one leg of a bridge that is balanced for both DC at a given reverse voltage and for AC (the test frequency 1 MHz). After balancing, the variable capacitor used for balancing is removed and its value measured on a test instrument. The value thus indicated is the zener capacitance at reverse voltage for which bridge balance was obtained. Figure 20 shows capacitance test circuit. Figure 21 is a plot of junction capacitance for diffused zener diode units versus their nominal operating voltage. Capacitance is the value obtained with reverse bias set at one-half the nominal VZ. The plot of the voltage range from 6.8 V to 200 V, for three dice sizes, covers most On Semiconductor diffused-junction zeners. Consult specific data sheets for capacitance values. Figures 22, 23, and 24 show plots of capacitance versus reverse voltage for units of various voltage ratings in each of the three dice sizes. Junction capacitance decreases as reverse voltage increases to the zener region. This change in capacitance can be expressed as a ratio which follows a one-third law, and C1/C2 = (V2/V1)1/3. This law holds only from the zener voltage down to about 1 volt, where the curve begins to flatten out. Figure 25 shows this for a group of low wattage units. 166 160 0.01 100 TIME (SECONDS) Figure 19. Zener Voltage (Typical) versus Time for Step Power Pulses (500 mW Lead Mounted Devices) http://onsemi.com 24 0.1 F DC POWER SUPPLY HP NO. 712A 1k 1% VDC 1k 1% 1k 1% 1k 1% 10/50 pF ZENER X UNDER TEST SIGNAL GEN TEK NO. 190A VAC 100 W HI-GAIN DIFF SCOPE NULL IND TEK TYPE D C1 1 MHz IV BAL READ S1 CAP DECADE 0-.09 mF 100 pF STEPS C 1% R = ZR R L/C METER TEK 140 C2 10/150 pF Figure 20. Capacitance Test Circuit 1,000 LOW WATTAGE UNITS AVG. FOR 10 UNITS EACH C Z , CAPACITANCE (PICOFARADS) C Z , CAPACITANCE (PICOFARADS) @ VZ/ 2 10,000 HIGH WATTAGE MEDIUM WATTAGE 1,000 100 LOW WATTAGE 10 1 10 100 10 VOLTS 20 VOLTS 100 50 VOLTS 100 VOLTS 10 1,000 1 10 100 VZ, NOMINAL UNIT VOLTAGE (VOLTS) VR, REVERSE VOLTAGE (VOLTS) Figure 21. Capacitance versus Voltage Figure 22. Capacitance versus Reverse Voltage 10,000 MEDIUM WATTAGE UNITS AVG. FOR 10 UNITS EACH C Z , CAPACITANCE (PICOFARADS) C Z , CAPACITANCE (PICOFARADS) 10,000 10 VOLTS 1,000 20 VOLTS 50 VOLTS 100 VOLTS 100 10 1 10 100 20 VOLTS 1,000 50 VOLTS 100 VOLTS 100 1,000 HIGH WATTAGE UNITS AVG. FOR 10 UNITS EACH 10 VOLTS 1 10 VR, REVERSE VOLTAGE (VOLTS) VR, REVERSE VOLTAGE (VOLTS) Figure 23. Capacitance versus Reverse Voltage Figure 24. Capacitance versus Reverse Voltage http://onsemi.com 25 100 C Z, CAPACITANCE (PICOFARADS) 1,000 LOW WATTAGE UNITS 10 VOLTS 100 50 VOLTS 100 VOLTS 10 0.1 1 100 10 VR, REVERSE VOLTAGE (VOLTS) Figure 25. Flattening of Capacitance Curve at Low Voltages mA DC DC SUPPLY HP 712A 1k READ Rx = SIGNAL GEN HP 650A 0.1 F 1k 600 S1 A 10M E1 - E2 E2 SET E1 READ 100 pF RX = ZZ E2 SET S1 B AC VTVM HP 400H R2 1 DC VTVM HP 412A Figure 26. Impedance Test Circuit ZENER IMPEDANCE (3) Measure the voltage across the entire network by switching S1. The ratio of these two AC voltages is then a measure of the impedance ratio. This can be expressed simply as RX = [(E1 - E2)/E2] R2. Zener impedance appears primarily as composed of a current-dependent resistance shunted by a voltage-dependent capacitor. Figure 26 shows the test circuit used to gather impedance data. This is a voltage-impedance ratio method of determining the unknown zener impedance. The operation is as follows: Section A of S1 provides a dummy load consisting of a 10-M resistor and a 100 pF capacitor. This network is required to simulate the input impedance of the AC VTVM while it is being used to measure the AC IR drop across R2. This method has been found accurate up to about three megahertz; above this frequency, lead inductances and strap capacitance become the dominant factors. (1) Adjust for desired zener IZDC by observing IR drop across the 1-ohm current-viewing resistor R2. (2) Adjust IZAC to 100 A by observing AC IR drop across R2. http://onsemi.com 26 HIGH FREQUENCY AND SWITCHING CONSIDERATIONS Figure 27 shows typical impedance versus frequency relationships of 6.8 volt 500 mW zener diodes at various DC zener currents. Before the zener breakdown region is entered, the impedance is almost all reactive, being provided by a voltage-dependent capacitor shunted by a very high resistance. When the zener breakdown region is entered, the capacitance is fixed and now is shunted by current-dependent resistance. For comparison, Figure 27 also shows the plot for a 680 pF capacitor XC, a 1K 1% nonreactive resistor, R, and the parallel combination of these two passive elements, ZT. At frequencies about 100 kHz or so and switching speeds above 10 microseconds, shunt capacitance of zener diodes begins to seriously effect their usefulness. The upper photo of Figure 28 shows the output waveform of a symmetrical peak limiter using two zener diodes back-to-back. The capacitive effects are obvious here. In any application where the signal is recurrent, the shunt capacitance limitations can be overcome, as lower photo of Figure 28 shows. This is done by operating fast diodes in series with the zener. Upon application of a signal, the fast diode conducts in the forward direction charging the shunt zener capacitance to the level where the zener conducts and limits the peak. When the signal swings the opposite direction, the fast diode becomes back-biased and prevents fast discharge of shunt capacitance. The fast diode remains back-biased when the signal reverses again to the forward direction and remains off until the input signal rises and exceeds the charge level of the capacitor. When the signal exceeds this level, the fast diode conducts as does the zener. Thus, between successive cycles or pulses the charge in the shunt capacitor holds off the fast diode, preventing capacitive loading of the signal until zener breakdown is reached. Figures 29 and 30 show this method applied to fast-pulse peak limiting. Z Z , ZENER IMPEDANCE (OHMS) 10,000 1,000 IZMA 0.25 0.50 XC , 680 pF ZT R, 1K 1% DC 1K & 680 pF 1.00 100 2 10 1 10 2.50 5 10 20 100 1 kHz 10 kHz 100 kHz 1 MHz 10 MHz FREQUENCY (Hz) Figure 27. Zener Impedance versus Frequency RS ei eo 5 V/cm 0.5 s/cm RS ei 5 V/cm 0.5 s/cm Figure 28. Symmetrical Peak Limiter http://onsemi.com 27 eo 2 V/cm 200 eo ei 10 V Z 50 eo ei 20 ns/cm Figure 29. Shunt Clipper 2 V/cm 200 ei eo ei eo 50 0.001 20 ns/cm Figure 30. Shunt Clipper with Clamping Network http://onsemi.com 28 Figure 31 is a photo of input-output pulse waveforms using a zener alone as a series peak clipper. The smaller output waveform shows the capacitive spike on the leading edge. Figure 32 clearly points out the advantage of the clamping network. 0 2 V/cm eo 10 VZ ei 50 200 eo ei 20 ns/cm Figure 31. Basic Series Clipper .001 2 V/cm eo 10 VZ ei ei 50 20 ns/cm Figure 32. Series Clipper with Clamping Network http://onsemi.com 29 200 eo TEMPERATURE COMPENSATED ZENERS TEMPERATURE CHARACTERISTICS OF THE P-N JUNCTION AND COMPENSATION INTRODUCTION A device which provides reference voltages in a special manner is a reference diode. As was discussed in the preceding chapters, the zener diode has the unique characteristic of exhibiting either a positive or a negative temperature coefficient, or both. By properly employing this phenomenon in conjunction with other semiconductor devices, it is possible to manufacture a zener reference element exhibiting a very low temperature coefficient when properly used. This type of low temperature coefficient device is referred to as a reference diode. The voltage of a forward biased P-N junction, at a specific current, will decrease with increasing temperature. Thus, a device so biased displays a negative temperature coefficient (Figure 1). A P-N junction in avalanche (above 5 volts breakdown) will display a positive temperature coefficient; that is, voltage will increase as temperature increases. Due to energy levels of a junction which breaks down below 5 volts, the temperature coefficient is negative. It follows that various combinations of forward biased junctions and reverse biased junctions may be arranged to achieve temperature compensation. From Figure 2 it can be seen that if the absolute value of voltage change (V) is the same for both the forward biased diode and the zener diode where the temperature has gone from 25°C to 100°C, then the total voltage across the combination will be the same at both temperatures since one V is negative and the other positive. Furthermore, if the rate of increase (or decrease) is the same throughout the temperature change, voltage will remain constant. The non-linearity associated with the voltage temperature characteristics is a result of this rate of change not being a perfect match. INTRODUCTION TO REFERENCE DIODES The temperature characteristics of the zener diode are discussed in a previous chapter, where it was shown that change in zener voltage with temperature can be significant under severe ambient temperature changes (for example, a 100 V zener can change 12.5 volts from 0 to 125°C). The reference diode (often called the temperature compensated zener or the TC zener) is specially designed to minimize these specific temperature effects. Design of temperature compensated zeners make possible devices with voltage changes as low as 5 mV from -55 to +100°C, consequently, the advantages of the temperature compensated zener are obvious. In critical applications, as a voltage reference in precision dc power supplies, in high stability oscillators, in digital voltmeters, in frequency meters, in analog-to-digital converters, or in other precision equipment, the temperature compensated zener is a necessity. Conceivably temperature compensated devices can be designed for any voltage but present devices with optimum voltage temperature characteristics are limited to specific voltages. Each family of temperature compensated zeners is designed by careful selection of its integral parts with special attention to the use conditions (temperature range and current). A distinct operating current is associated with each device. Consequently, changes from the specified operating current can only degrade the voltage-temperature relationships. This will be discussed in more detail later. The device "drift" or voltage-time stability is critical in some reference applications. Typically zeners and TC zeners offer stability of better than 500 parts per million per 1000 hours. VREF = VZ + VZ + VD - VD THE METHODS OF TEMPERATURE COMPENSATION The effect of temperature is shown in Figure 1. The forward characteristic does not vary significantly with reverse voltage breakdown (zener voltage) rating. A change in ambient temperature from 25° to 100°C produces a shift in the forward curve in the direction of lower voltage (a negative temperature coefficient - in this case about 150 mV change), while the same temperature change produces approximately 1.9 V increase in the zener voltage (a positive coefficient). By combining one or more silicon diodes biased in the forward direction with the P-N biased zener diode as shown in Figure 3, it is possible to compensate almost completely for the zener temperature coefficient. Obviously, with the example shown, 13 junctions would be needed. Usually reference diodes are low voltage devices, using zeners with 6 to 8 volts breakdown and one or two forward diodes. http://onsemi.com 30 450 IF (mA) 150 mV FORWARD CHARACTERISTIC TYPICAL (ALL TYPES) 100°C 25°C 150 VZ (VOLTS) 20 30 300 10 0.5 1 1.5 VF (VOLTS) 15 IZ (mA) 1.9 V 100°C 30 25°C 45 Figure 1. Effects of Temperature on Zener Diode Characteristics DIRECTION OF CURRENT FLOW FORWARD-BIASED PN JUNCTION + REVERSE-BIASED ZENER JUNCTION PACKAGE OUTLINE 25°C 100°C 25°C - -V -V 100°C 7.5 mA 25°C - 7.5 mA +V +V 100°C +V - 100°C 25°C Figure 2. Principle of Temperature Compensation + SILICON JUNCTION DIODES ZENER DIODES - Figure 3. Zener Temperature Compensation with Silicon Forward Junctions http://onsemi.com 31 TEMPERATURE COEFFICIENT STABILITY In ac regulator and clipper circuits where zener diodes are normally connected cathode to cathode, the forward biased diode during each half cycle can be chosen with the correct forward temperature coefficient (by stacking, etc.) to correctly compensate for the temperature coefficient of the reverse-biased zener diode. It is possible to compensate for voltage drift with temperature using this method to the extent that zener voltage stabilities on the order of 0.001%/°C are quite feasible. This technique is sometimes employed where higher wattage devices are required or where the zener is compensated by the emitter base junction of a transistor stage. Consider the example of using discrete components, 1N4001 1N4001 rectifier and ON Semiconductor 5 Watt zener, to obtain compensated voltage-temperature characteristics. Examination of the curve in Figure 4 indicates that a 10 volt zener diode exhibits a temperature coefficient of approximately +5.5 mV/°C. At a current level of 100 mA a temperature coefficient of approximately -2.0 mV/°C is characteristic of the 1N4001 1N4001 rectifiers. A series connection of three silicon 1N4001 1N4001 rectifiers produces a total temperature coefficient of approximately -6 mV/°C and a total forward drop of approximately 2.17 volts at 25°C. The combination of three silicon rectifiers and the 10 volt zener diode produces a device with a coefficient of approximately -0.5 mV/°C and a total breakdown voltage at 100 mA of approximately 12.2 volts. Calculation shows this to be a temperature stability of -0.004%/°C. * 0.5 mV 5C 12.2 V Figure 5 shows the voltage-temperature characteristics of the TC diode. It can be seen that the voltage drops slightly with increasing temperature. 6.326 7 mV/ C 4 ° -1 -2 0 1 2 3 4 5 6 7 8 9 10 25 62 100 -6 This non-linearity of the voltage temperature characteristic leads to a definition of a representative design parameter VZ. For each device type there is a specified maximum change allowable. The voltage temperature stability measurement consists of voltage measurement at specified temperatures (for the 1N821 1N821 Series the temperatures are -55, 0, +25, +75, and +100°C). The voltage readings at each of the temperatures is compared with readings at the other temperatures and the largest voltage change between any of the specified temperatures determines the exact device type. For devices registered prior to complete definition of the voltage temperature stability measurement, the allowable maximum voltage change over the temperature range is derived from the calculation converting %/°C to mV over the temperature range. Under this standard definition, %/°C is merely a nomenclature and the meaningful allowable voltage deviation to be expected becomes the designed parameter. 0 -3 -10 Figure 5. Voltage versus Temperature, Typical for ON Semiconductor 1N827 1N827 Temperature Compensated Zener Diode ONE FORWARD 1 -55 TEMPERATURE (°C) TWO FORWARDS 2 6.318 -5 THREE FORWARDS ALLOY-DIFFUSED JUNCTION 3 6.320 6.314 100 DIFFUSED JUNCTION 6.322 6.316 ZENER VOLTAGE (10 mA AT 25°C) 5 mV CHANGE FROM 25°C VOLTAGE VOLTAGE (VOLTS) 6.324 The temperature compensated zener employs the technique of specially selected dice. This provides optimum voltage temperature characteristics by close control of dice resistivities. 6 6 5 4 3 2 1 0 -1 -2 -3 -4 11 12 13 VOLTS Figure 4. http://onsemi.com 32 CURRENT -6.6 Thus far, temperature compensated zeners have been discussed mainly with regard to temperature and voltage. However, the underlying assumption throughout the previous discussion was that current remained constant. There is a significant change in the temperature coefficient of a unit depending on how much above or below the test current the device is operated. A particular unit with a 0.01%/°C temperature coefficient at 7.5 mA over a temperature range of -55°C to +100°C could possibly have a 0.0005%/°C temperature coefficient at 11 mA. In fact, there is a particular current which can be determined for each individual unit that will give the lowest TC. Manufacturing processes are designed so that the yields of low TC units are high at the test specification for current. A unit with a high TC at the test current can have a low TC at some other current. A look at the volt-ampere curves at different temperatures illustrates this point clearly (see Figure 6). -6.6 -6.5 -6.4 VOLTAGE (VOLTS) -6.3 -6.2 -6.1 -6 CURRENT -5.9 +100 IMAX Figure 7. Effects of Poorly Regulated Current The three volt-ampere curves do not usually cross over at exactly the same point. However, this does not take away from the argument that current regulation is probably the most critical consideration when using temperature-compensated units. ZENER IMPEDANCE AND CURRENT REGULATION Zener impedance is defined as