HT46R51/HT46R52 HA0003E HT93LC46 HA0004E HA0084E HT46R52 HT46R51 0000H 256-N - Datasheet Archive

 

A/D Type 8-Bit OTP MCU Technical Document · Tools Information · FAQs · Application Note - HA0003E

 

HT46R51/HT46R52 HT46R51/HT46R52 A/D Type 8-Bit OTP MCU Technical Document · Tools Information · FAQs · Application Note - HA0003E HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 HT93LC46 EEPROM - HA0004E HA0004E HT48 & HT46 MCU UART Software Implementation Method - HA0084E HA0084E NiMH Battery Charger Demo Board - Using the HT46R52 HT46R52 Features · Low-power fully static CMOS design · On-chip crystal and RC oscillator · Operating voltage: · 6-level subroutine nesting fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V · Watchdog Timer · Low voltage reset function · Program Memory: · HALT function 1K´14 OTP (HT46R51 HT46R51) 2K´14 OTP (HT46R52 HT46R52) · Up to 0.5ms instruction cycle with 8MHz system clock at VDD=5V · Data memory: 88´8 RAM · 1-channel 8-bit PWM output shared with an I/O line · A/D converter: 12bits´5Ch · PFD function External A/D converter reference voltage input pin · Bit manipulation instruction · 14 bidirectional I/O lines · Table read instruction · 1 interrupt input shared with an I/O line · 63 powerful instructions · 8-bit programmable timer/event counter with over- · All instructions in one or two machine cycles flow interrupt and 7-stage prescaler · 18-pin DIP, 20-pin SOP/SSOP package General Description verter, Pulse Width Modulation function, HALT and wake-up functions, watchdog timer, as well as low cost, enhance the versatility of these devices to suit a wide range of A/D application possibilities such as sensor signal processing, chargers, motor driving, industrial control, consumer products, subsystem controllers, etc. The HT46R51/HT46R52 HT46R51/HT46R52 are 8-bit high performance, RISC architecture microcontroller devices specifically designed for A/D applications that interface directly to analog signals, such as those from sensors. The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, multi-channel A/D con- Rev. 1.40 1 July 12, 2005 HT46R51/HT46R52 HT46R51/HT46R52 Block Diagram IN T P ro g ra m R O M P ro g ra m C o u n te r M T M R C T M R In te rru p t C ir c u it S T A C K IN T C M M P B P W D T P r e s c a le r U X D A T A M e m o ry P A X M W D T A L U O S R E V D V S P D C 1 S D S P o rt B A C C O p tio n R O M O T P O n ly fS X Y S /4 W D T O S C U V D D X V R E F P B 0 /A N 0 ~ P B 4 /A N 4 P B C S h ifte r T im in g G e n e ra to r O S C 2 M A /D C o n v e rte r P B U P A 0 ~ P A 2 , P A 3 /P F D P A 4 /T M R , P A 5 /IN T P A 6 ~ P A 7 P o rt A M U X S T A T U S Y S T M R P A C In s tr u c tio n D e c o d e r fS P r e s c a le r E N /D IS W D T S In s tr u c tio n R e g is te r U P o rt D P D 0 /P W M P D C Pin Assignment P A 3 /P F D 1 2 0 P A 3 /P F D 1 1 8 P A 4 /T M R P A 2 2 1 9 P A 5 /IN T P A 2 2 1 7 P A 5 /IN T P A 1 3 1 8 P A 6 P A 0 P D 0 /P W M 4 1 7 5 1 6 P A 7 O S C 2 V R E F V S S 6 1 5 O S C 1 7 1 4 V D D 8 1 3 P A 4 /T M R P A 1 3 1 6 P A 6 P A 0 P D 0 /P W M 4 1 5 5 1 4 P A 7 O S C 2 V S S 6 1 3 O S C 1 P B 0 /A N 0 7 1 2 V D D P B 0 /A N 0 P B 1 /A N 1 P B 2 /A N 2 8 1 1 P B 1 /A N 1 9 1 2 9 1 0 R E S P B 3 /A N 3 R E S P B 4 /A N 4 P B 2 /A N 2 1 0 1 1 P B 3 /A N 3 H T 4 6 R 5 1 /H T 4 R 5 2 1 8 D IP -A Rev. 1.40 H T 4 6 R 5 1 /H T 4 R 5 2 2 0 S O P -A /S S O P -A 2 July 12, 2005 HT46R51/HT46R52 HT46R51/HT46R52 Pin Description Pin Name PA0~PA2 PA3/PFD PA4/TMR PA5/INT PA6~PA7 I/O Options Description I/O Pull-high Wake-up PA3 or PFD Bidirectional 8-bit input/output port. Each individual bit on this port can be configured as a wake-up input by configuration option. Software instructions determine if the pin is a CMOS output or Schmitt trigger input. Configuration options determine which pins on this port have pull-high resistors. The PFD, TMR and external interrupt input are pin-shared with PA3, PA4, and PA5 respectively. Pull-high Bidirectional 5-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high resistor. Configuration options determine which pins on this port have pull-high resistors. PB is pin-shared with the A/D input pins. The A/D inputs are selected via software instructions Once selected as an A/D input, the I/O function and pull-high resistor functions are disabled automatically. PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 I/O PD0/PWM I/O Bidirectional 1-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with or without pull-high resistor. One configuration Pull-high PD0 or PWM option determines which pin on this port has pull-high resistor. PD0 is pin-shared with the PWM output selected via configuration option. OSC1 OSC2 I O OSC1, OSC2 are connected to an external RC network or external crystal (deterCrystal or RC mined by configuration option) for the internal system clock. For external RC system clock operation, OSC2 is an output pin for 1/4 system clock. RES I ¾ Schmitt trigger reset input, active low VDD ¾ ¾ Positive power supply VSS ¾ ¾ Negative power supply, ground I ¾ A/D Converter Reference Input voltage pins. Connect this pin to the desired A/D reference voltage. The VREF pin is connected to VDD for the 18-pin DIP package VREF Absolute Maximum Ratings Supply Voltage .VSS-0.3V to VSS+6.0V Storage Temperature .-50°C to 125°C Input Voltage.VSS-0.3V to VDD+0.3V Operating Temperature.-40°C to 85°C Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Symbol Parameter VDD Operating Voltage IDD1 Operating Current ISTB1 ¾ Standby Current (WDT Enabled) Rev. 1.40 Min. Typ. Max. Unit fSYS=4MHz 2.2 ¾ 5.5 V fSYS=8MHz 3.3 ¾ 5.5 V No load, fSYS=4MHz ADC disabled ¾ 0.6 1.5 mA ¾ 2 4 mA No load, fSYS=4MHz ADC disabled ¾ 0.8 1.5 mA ¾ 2.5 4 mA No load, fSYS=8MHz ADC disabled ¾ 4 8 mA ¾ ¾ 5 mA ¾ ¾ 10 mA VDD Operating Current (RC OSC) IDD3 Test Conditions Operating Current (Crystal OSC) IDD2 Ta=25°C 3V 5V 3V 5V 5V Conditions 3V No load, system HALT 5V 3 July 12, 2005 HT46R51/HT46R52 HT46R51/HT46R52 Symbol Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit ¾ ¾ 1 mA ¾ ¾ 2 mA ISTB2 Standby Current (WDT & AD Disabled) 3V VIL1 Input Low Voltage for I/O Ports, TMR and INT ¾ ¾ 0 ¾ 0.3VDD V VIH1 Input High Voltage for I/O Ports, TMR and INT ¾ ¾ 0.7VDD ¾ VDD V VIL2 Input Low Voltage (RES) ¾ ¾ 0 ¾ 0.4VDD V VIH2 Input High Voltage (RES) ¾ ¾ 0.9VDD ¾ VDD V VLVR Low Voltage Reset Voltage ¾ Configuration option: 3V 2.7 3 3.3 V IOL I/O Port Sink Current IOH I/O Port Source Current RPH Pull-high Resistance of I/O Ports No load, system HALT 5V 3V 5V 3V 5V VOL=0.1VDD VOH=0.9VDD 3V ¾ 5V 4 8 ¾ mA 10 20 ¾ mA -2 -4 ¾ mA -5 -10 ¾ mA 20 60 100 kW 10 30 50 kW VAD A/D Input Voltage ¾ ¾ 0 ¾ VREF V VREF ADC Input Reference Voltage Range ¾ ¾ 1.2 ¾ VDD V DNL ADC Differential Non-Linear ¾ ¾ ¾ ¾ ±2 LSB INL ADC Integral Non-Linear ¾ ¾ ¾ ±2.5 ±4 LSB ¾ ¾ ¾ ¾ 12 Bits ¾ 0.5 1 mA ¾ 1.5 3 mA RESOLU Resolution IADC Additional Power Consumption if A/D Converter is Used 3V ¾ 5V A.C. Characteristics Symbol Parameter fSYS System Clock (Crystal OSC) fTIMER Timer I/P Frequency (TMR) Ta=25°C Test Conditions Conditions VDD Min. Typ. Max. Unit ¾ 2.2V~5.5V 400 ¾ 4000 kHz ¾ 3.3V~5.5V 400 ¾ 8000 kHz ¾ 2.2V~5.5V 0 ¾ 4000 kHz ¾ 3.3V~5.5V kHz tRES External Reset Low Pulse Width ¾ 8000 90 180 ms 32 65 130 ms ¾ Watchdog Oscillator Period ¾ ¾ 5V tWDTOSC 0 45 ¾ 3V 1 ¾ ¾ ms ¾ 1024 ¾ tSYS tSST System Start-up Timer Period ¾ tINT Interrupt Pulse Width ¾ ¾ 1 ¾ ¾ ms tAD A/D Clock Period ¾ ¾ 1 ¾ ¾ ms tADC A/D Conversion Time ¾ ¾ ¾ 80 ¾ tAD tADCS A/D Sampling Time ¾ ¾ ¾ 32 ¾ tAD Wake-up from HALT Note: tSYS=1/fSYS Rev. 1.40 4 July 12, 2005 HT46R51/HT46R52 HT46R51/HT46R52 Functional Description Execution Flow For HT46R52 HT46R52, the program counter (PC) is 11 bits wide and controls the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 2048 addresses. The system clock for the microcontroller is derived from either a crystal or an RC oscillator. The system clock is internally divided into four non-overlapping clocks. One instruction cycle consists of 4 system clock cycles. After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. Instruction fetching and execution are pipelined in such a way that a fetch and decoding takes an instruction cycle while execution take the next instruction cycle. The pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction changes the program counter, two cycles are required to complete the instruction. When executing a jump instruction, conditional skip execution, loading register, subroutine call or return from subroutine, initial reset, internal interrupt, external interrupt or return from interrupts, the PC manipulates the program transfer by loading the address corresponding to each instruction. Program Counter - PC For HT46R51 HT46R51, the program counter (PC) is 10 bits wide and controls the sequence in which the instructions stored in the program ROM are executed. The contents of the PC can specify a maximum of 1024 addresses. S y s te m C lo c k T 1 T 2 T 3 T 4 T 1 The conditional skip is activated by instructions. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed to the next instruction. T 2 T 3 T 4 T 1 T 2 T 3 T 4 O S C 2 ( R C o n ly ) P C P C P C + 1 F e tc h IN S T (P C ) E x e c u te IN S T (P C -1 ) P C + 2 F e tc h IN S T (P C + 1 ) E x e c u te IN S T (P C ) F e tc h IN S T (P C + 2 ) E x e c u te IN S T (P C + 1 ) Execution Flow Mode Program Counter *b10 *b9 *b8 *b7 *b6 *b5 *b4 *b3 *b2 *b1 *b0 Initial Reset 0 0 0 0 0 0 0 0 0 0 0 External Interrupt 0 0 0 0 0 0 0 0 1 0 0 Timer/Event Counter Overflow 0 0 0 0 0 0 0 1 0 0 0 A/D Converter Interrupt 0 0 0 0 0 0 0 1 1 0 0 @3 @2 @1 @0 Skip Program Counter+2 Loading PCL PC10 PC9 PC8 @7 @6 @5 @4 Jump, Call Branch #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 Return from Subroutine S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Program Counter Note: *b10~*b0: Program counter bits S10~S0: Stack register bits #10~#0: Instruction code bits @7~@0: PCL bits, PC10~PC8: Original PC counter, remain unchanged For the HT46R51 HT46R51, since the program counter is 10 bits wide (b0~b9), the b10 columns in the table are not applicable. For the HT46R52 HT46R52, since the program counter is 11 bits wide (b0~b10) Rev. 1.40 5 July 12, 2005 HT46R51/HT46R52 HT46R51/HT46R52 · Location 00CH The lower byte of the PC (PCL) is a readable and writeable register (06H). Moving data into the PCL performs a short jump. The destination is within 256 locations. Location 00CH is reserved for the A/D converter interrupt service program. If an A/D converter interrupt results from an end of A/D conversion, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH. When a control transfer takes place, an additional dummy cycle is required. · Table location Any location in the program memory can be used as look-up tables. The instructions ²TABRDC [m]² (the current page) and ²TABRDL [m]² (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to TBLH (08H). The lower-order byte table pointer TBLP (07H) are read/write registers, which indicate the table locations. Before accessing the table, the location has to be placed in TBLP. The TBLH is read only and cannot be restored. If the main routine and the ISR (interrupt service routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be changed by the table read instruction used in the ISR. Errors can occur. Given this, using the table read instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read instruction has to be applied in both main routine and the ISR, the interrupt should be disabled prior to the table read instruction. It will not be enabled until the TBLH in the main routine has been backed-up. All table related instructions require 2 cycles to complete the operation. Program Memory - EPROM The program memory is used to store the program instructions which are to be executed. It also contains data, table, and interrupt entries, and is organized into 1024´14 (HT46R51 HT46R51) or 2048´14 (HT46R52 HT46R52) bits, addressed by the Program Counter and table pointer. Certain locations in the ROM are reserved for special usage: · Location 000H This location is reserved for program initialization. After a chip reset, the program always begins execution at location 000H. · Location 004H This location is reserved for the external interrupt service program. If the INT input pin is activated, the interrupt is enabled and the stack is not full, the program begins execution at this location. · Location 008H This location is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a timer/event counter overflow, and the interrupt is enabled and the stack is not full, the program begins execution at location 008H. 0 0 0 H 0 0 4 H 0 0 8 H 0 0 C H 0 0 0 H D e v ic e In itia liz a tio n P r o g r a m E x te r n a l In te r r u p t S u b r o u tin e 0 0 8 H T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e A /D 0 0 C H C o n v e r te r In te r r u p t S u b r o u tin e 0 1 0 H T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e A /D C o n v e r te r In te r r u p t S u b r o u tin e 0 1 4 H P ro g ra m M e m o ry 0 1 8 H P ro g ra m M e m o ry 0 1 8 H n 0 0 H n F F H L o o k - u p T a b le ( 2 5 6 w o r d s ) 3 0 0 H 3 F F H E x te r n a l In te r r u p t S u b r o u tin e 0 1 0 H 0 1 4 H n 0 0 H n F F H D e v ic e In itia liz a tio n P r o g r a m 0 0 4 H L o o k - u p T a b le ( 2 5 6 w o r d s ) 7 0 0 H L o o k - u p T a b le ( 2 5 6 w o r d s ) N o te : n = 0 ~ 3 7 F F H 1 4 b its H T 4 6 R 5 1 L o o k - u p T a b le ( 2 5 6 w o r d s ) N o te : n = 0 ~ 7 1 4 b its H T 4 6 R 5 2 Program Memory Rev. 1.40 6 July 12, 2005 HT46R51/HT46R52 HT46R51/HT46R52 Instruction Table Location b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 TABRDC [m] P10 P9 P8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [m] 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 Table Location Note: b10~b0: Table location bits P10~P8: Current program counter bits @7~@0: Table pointer bits For the Ht46R51, since the program counter is 10 bits wide (b0~b9), the b10 column in the table are not applicable For the HT46R52 HT46R52, since the program counter is 11 bits wide (b0~b10) Stack Register - STACK 0 0 H M P 0 0 2 H In d ir e c t A d d r e s s in g R e g is te r 1 0 3 H M P 1 0 4 H 0 5 H A C C 0 6 H P C L 0 7 H T B L P 0 8 H T B L H 0 9 H 0 A H S T A T U S 0 B H IN T C 0 C H 0 D H T M R 0 E H T M R C 0 F H If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt is serviced. This feature prevents stack overflow, allowing the programmer to use the structure more easily. If the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent 6 return addresses are stored). 1 0 H 1 1 H 1 2 H P A 1 3 H S p e c ia l P u r p o s e D A T A M E M O R Y P A C 1 4 H P B 1 5 H P B C 1 6 H P C 1 7 H P C C 1 8 H P D 1 9 H P D C 1 A H Data Memory - RAM P W M 1 B H The data memory (RAM) is designed with 111´8 bits and is divided into two functional groups, namely; special function registers (23´8 bits) and general purpose data memory (88´8bit) most of which are readable/writable, although some are read only. Of the two types of functional groups, the special function registers consist of an Indirect addressing register 0 (00H), a Memory pointer register 0 (MP0;01H), an Indirect addressing register 1 (02H), a Memory pointer register 1 (MP1;03H), an Accumulator (ACC;05H), a Program counter lower-order byte register (PCL;06H), a Table pointer (TBLP;07H), a Table higher-order byte register (TBLH;08H), a Status register (STATUS;0AH), an Interrupt control register (INTC;0BH), a Timer/Event Counter (TMR:0DH), a Timer/Event Counter control register (TMRC;0EH), PWM data register (PWM;1AH), the A/D Rev. 1.40 In d ir e c t A d d r e s s in g R e g is te r 0 0 1 H This is a special part of the memory which is used to save the contents of the program counter only. The stack is organized into 6 levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At the state of a subroutine call or an interrupt acknowledgment, the contents of the program counter are pushed onto the stack. At the end of the subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. 1 C H 1 D H 1 E H 1 F H 2 0 H A D R L 2 1 H A D R H 2 2 H A D C R 2 3 H A C S R 2 4 H 2 7 H 2 8 H G e n e ra l P u rp o s e D a ta M e m o ry (8 8 B y te s ) : U n u s e d R e a d a s "0 0 " 7 F H RAM Mapping 7 July 12, 2005 HT46R51/HT46R52 HT46R51/HT46R52 · Arithmetic operations (ADD, ADC, SUB, SBC, DAA) result lower-order byte register (ADRL;20H), the A/D result higher-order byte register (ADRH;21H), the A/D control register (ADCR;22H), the A/D clock setting register (ACSR;23H), I/O registers (PA;12H, PB;14H, PD;18H) and I/O control registers (PAC;13H, PBC;15H, PDC;19H). The remaining space before the 28H is reserved for future expanded usage and reading these locations will return the result ²00H². The general purpose data memory, addressed from 28H to 7FH, is used for data and control information under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by ²SET [m].i² and ²CLR [m].i². They are also indirectly accessible through memory pointer registers (MP0;01H or MP1;03H). · Logic operations (AND, OR, XOR, CPL) · Rotation (RL, RR, RLC, RRC) · Increment and Decrement (INC, DEC) · Branch decision (SZ, SNZ, SIZ, SDZ .) The ALU not only saves the results of a data operation but also changes the status register. Status Register - STATUS This 8-bit register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). It also records the status information and controls the operation sequence. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO and PDF flags. Addition operations related to the status register may give different results from those intended. The TO flag can be affected only by system power-up, a WDT time-out or executing the ²HALT² or ²CLR WDT² instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or a system power-up. Indirect Addressing Register Location 00H and 02H are indirect addressing registers that are not physically implemented. Any read/write operation of [00H] ([02H]) will access the data memory pointed to by MP0 (MP1). Reading location 00H (02H) itself indirectly will return the result ²00H². Writing indirectly results in no operation. The memory pointer registers (MP0 and MP1) are 7-bit registers. The accumulator closely relates to ALU operations. It is also mapped to location ²05H² of the data memory which can operate with immediate data. The data movement between two data memories has to pass through the accumulator. The Z, OV, AC, and C flags reflect the status of the latest operations. On entering the interrupt sequence or executing the subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status is important, and if the subroutine is likely to corrupt the status register, the programmer should take precautions and save it properly. Arithmetic and Logic Unit - ALU Interrupts This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions: The device provides an external interrupt, an internal timer/event counter interrupt, and an A/D converter interrupt. The interrupt control register (INTC;0BH) con- Accumulator - ACC Bit No. Label Function 0 C C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. 1 AC AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. 2 Z 3 OV OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. 4 PDF PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction. 5 TO TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set by a WDT time-out. 6, 7 ¾ Unused bit, read as ²0² Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. Status (0AH) Register Rev. 1.40 8 July 12, 2005 HT46R51/HT46R52 HT46R51/HT46R52 routine call to location ²0CH² will occur. The related interrupt request flag (ADF) will be reset and the EMI bit cleared to disable further interrupts. tains the interrupt control bits to set the enable/disable and the interrupt request flags. Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This scheme may prevent any further interrupt nesting. Other interrupt requests may occur during this interval but only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the EMI bit and the corresponding bit of the INTC may be set to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate service is desired, the stack must be prevented from becoming full. During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the ²RETI² instruction is executed or the EMI bit and the related interrupt control bit are set to 1 (if the stack is not full). To return from the interrupt subroutine, ²RET² or ²RETI² may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not. Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests the following table shows the priority that is applied. These can be masked by resetting the EMI bit. All these kinds of interrupts have a wake-up capability. As an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack, followed by a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto the stack. If the contents of the register or status register (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the contents should be saved in advance. Priority Vector External Interrupt Interrupt Source 1 04H Timer/Event Counter Overflow 2 08H A/D Converter Interrupt 3 0CH The timer/event counter interrupt request flag (TF), external interrupt request flag (EIF), A/D converter request flag (ADF), enable timer/event counter bit (ETI), enable external interrupt bit (EEI), enable A/D converter interrupt bit (EADI), and enable master interrupt bit (EMI) constitute an interrupt control register (INTC) which are located at ²0BH² in the data memory. EMI, EEI, ETI, and EADI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the interrupt request flags (TF, EIF, and ADF) are set, they will remain in the INTC register until the interrupts are serviced or cleared by a software instruction. External interrupts are triggered by a high to low transition of INT and the related interrupt request flag (EIF; bit 4 of the INTC) will be set. When the interrupt is enabled, the stack is not full and the external interrupt is active, a subroutine call to location ²04H² will occur. The interrupt request flag (EIF) and EMI bits will be cleared to disable other interrupts. The internal Timer/Event Counter interrupt is initialized by setting the Timer/Event Counter interrupt request flag (TF; bit 5 of the INTC), which is normally caused by a timer overflow. After the interrupt is enabled, and the stack is not full, and the TF bit is set, a subroutine call to location ²08H² occurs. The related interrupt request flag (TF) is reset, and the EMI bit is cleared to disable further maskable interrupts. It is recommended that a program does not use the ²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and enabling the interrupt is not well controlled, the original control sequence will be damaged once the ²CALL² operates in the interrupt subroutine. The A/D converter interrupt is initialized by setting the A/D converter request flag (ADF; bit 6 of the INTC), caused by an end of A/D conversion. When the interrupt is enabled, the stack is not full and the ADF is set, a subBit No. Label 0 EMI Controls the master (global) interrupt (1= enable; 0= disable) Function 1 EEI Controls the external interrupt (1= enable; 0= disable) 2 ETI Controls the Timer/Event Counter interrupt (1= enable; 0= disable) 3 EADI 4 EIF External interrupt request flag (1= active; 0= inactive) 5 TF Internal Timer/Event Counter request flag (1= active; 0= inactive) 6 ADF 7 ¾ Control the A/D converter interrupt (1= enable; 0= disable) A/D converter request flag (1= active; 0= inactive) For test mode used only. Must be written as ²0²; otherwise may result in unpredictable operation. INTC (0BH) Register Rev. 1.40 9 July 12, 2005 HT46R51/HT46R52 HT46R51/HT46R52 Oscillator Configuration Watchdog Timer - WDT There are two oscillator circuits in the microcontroller. The clock source of the WDT is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4) decided by options. This timer is designed to prevent a software mal-function or sequence jumping to an unknown location with unpredictable results. The watchdog timer can be disabled by an option. If the watchdog timer is disabled, all the executions related to the WDT result in no operation. V D D 4 7 0 p F O S C 1 O S C 1 O S C 2 fS Y S O S C 2 /4 C r y s ta l O s c illa to r R C The WDT clock (fS) is further divided by an internal counter to give longer watchdog time-outs. The division ratio is fixed by an internal counter which gives a 215 fixed division ratio. O s c illa to r System Oscillator Both of them are designed for system clocks, namely the external RC oscillator and the external Crystal oscillator, which are determined by options. No matter what oscillator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator and ignores an external signal to conserve power. Once an internal WDT oscillator (RC oscillator with period of 65ms normally) is selected, it is divided by 216 to get the time-out period of approximately 4.3s. This time-out period may vary with temperature, VDD and process variations. If the WDT oscillator is disabled, the WDT clock may still come from the instruction clock and operate in the same manner except that in the HALT state the WDT may stop counting and lose its protecting purpose. In this situation the logic can only be restarted by external logic. If the device operates in a noisy environment, using the on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock. If an RC oscillator is used, an external resistor between OSC1 and VSS is required and the resistance must range from 30kW to 750kW. The system clock, divided by 4, is available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC oscillator provides the most cost effective solution. However, the frequency of oscillation may vary with VDD, temperatures and the chip itself due to process variations. It is therefore not suitable for timing sensitive operations where an accurate oscillator frequency is desired. The WDT overflow under normal operation will initialize a ²chip reset² and set the status bit TO. Whereas in the HALT mode, the overflow will initialize a ²warm reset² wherein only the Program Counter and SP are reset to zero. To clear the contents of the WDT, three methods are adopted; external reset (a low level to RES), software instructions, or a HALT instruction. The software instructions include ²CLR WDT² and the other set CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the option ²CLR WDT times selection option². If the ²CLR WDT² is selected (i.e. CLRWDT times equal one), any execution of the CLR WDT instruction will clear the WDT. In case ²CLR WDT1² and ²CLR WDT2² are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT; otherwise, the WDT may reset the chip because of time-out. If the Crystal oscillator is used, a crystal across OSC1 and OSC2 is needed to provide the feedback and phase shift required for the oscillator, and no other external components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1 and OSC2 are required (If the oscillator can be disabled by options to conserve power). The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if the system enters the power down mode, the system clock is stopped, but the WDT oscillator still works with a period of approximately 65ms at 5V. The WDT oscillator can be disabled by option to conserve power. C L R W D T 1 F la g C L R W D T 2 F la g C o n tro l L o g ic 1 o r 2 In s tr u c tio n s fS Y S /4 W D T O s c illa to r W D T S o u rc e C o n fig u r a tio n O p tio n C L R fS 8 - b it C o u n te r fS /2 8 7 - b it C o u n te r ¸ 2 W D T T im e - o u t (2 15/fS ~ 2 16/fS ) Watchdog Timer Rev. 1.40 10 July 12, 2005 HT46R51/HT46R52 HT46R51/HT46R52 The WDT time-out period is fixed to fs/216, because the ²CLR WDT² or ²CLR WDT1² and ²CLR WDT2² instructions will clear the whole counter of the WDT. To minimize power consumption, all the I/O pins should be carefully managed before entering the HALT status. Power Down Operation - HALT There are three ways in which a reset may occur: The HALT mode is initialized by the ²HALT² instruction and results in the following. · RES reset during normal operation · The system oscillator is turned off but the WDT oscil- · WDT time-out reset during normal operation · · · · Reset · RES reset during HALT lator keeps running (if the WDT oscillator or the real time clock is selected). The contents of the on-chip RAM and registers remain unchanged The WDT and WDT prescaler will be cleared to zero. If the WDT clock source is from the RTC/WDT oscillator, the WDT will remain active, and if the WDT clock source is fSYS/4, the WDT will stop running. All of the I/O ports maintain their original status The PDF flag is set and the TO flag is cleared The WDT time-out during HALT differs from other chip reset conditions, for it can perform a ²warm reset² that resets only the Program Counter and SP, leaving the other circuits at their original state. Some registers remain unaffected during any other reset conditions. Most registers are reset to the ²initial condition² when the reset conditions are met. Examining the PDF and TO flags, the program can distinguish between different ²chip resets². The system quits the HALT mode by way of an external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset causes a device initialization and the WDT overflow performs a ²warm reset². After examining the TO and PDF flags, the cause for a chip reset can be determined. The PDF flag is cleared by system power-up or by executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. On the other hand, the TO flag is set if the WDT time-out occurs, and causes a wake-up that only resets the Program Counter and SP, and leaves the others in their original status. TO RESET Conditions 0 0 RES reset during power-up u u RES reset during normal operation 0 1 RES wake-up HALT 1 u WDT time-out during normal operation 1 1 WDT wake-up HALT Note: ²u² stands for ²unchanged² To guarantee that the system oscillator is started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the system awakes from the HALT state. When a system reset occurs, the SST delay is added during the reset period. Any wake-up from the HALT will enable the SST delay. An extra option load time delay is added during system reset (Power-up, WDT time-out at normal mode or RES reset). The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit in port A can be independently selected to wake-up the device by options. Awakening from an I/O port stimulus, the program resumes execution of the next instruction. On the other hand, awakening from an interrupt, two sequence may occur. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the program resumes execution at the next instruction. But if the interrupt is enabled, and the stack is not full, the regular interrupt response takes place. When an interrupt request flag is set before entering the ²HALT² status, the system cannot be awakened using that interrupt. If wake-up events occur, it takes 1024 tSYS (system clock period) to resume normal operation. In other words, a dummy period is inserted after the wake-up. If the wake-up results from an interrupt acknowledgment, the actual interrupt subroutine execution is delayed by more than one cycle. However, if the Wake-up results in the next instruction execution, the execution will be performed immediately after the dummy period is finished. Rev. 1.40 PDF The functional unit chip reset status are shown below. Program Counter Interrupt Disable Prescaler, Divider Cleared WDT Clear. After master reset, WDT begins counting Timer/Event Counter Off Input/Output Ports Input mode Stack Pointer 11 000H Points to the top of the stack July 12, 2005 HT46R51/HT46R52 HT46R51/HT46R52 V V D D D D 0 .0 1 m F * R E S 1 0 0 k W R E S C h ip S T + tO P D R e s e t 1 0 k W Reset Timing Chart 0 .1 m F * H A L T W D T Reset Circuit Note: tS S S T T im e - o u t ²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. W D T T im e - o u t R e s e t R E S W a rm R e s e t E x te rn a l C o ld R e s e t S S T 1 0 - b it R ip p le C o u n te r O S C 1 P o w e r - o n D e te c tio n Reset Configuration The register states are summarized below: Register Reset(Power On) WDT Time-out RES Reset (Normal Operation) (Normal Operation) RES Reset (HALT) WDT Time-out (HALT)* TMR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMRC 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H MP0 -xxx xxxx -xxx xxxx -xxx xxxx -xxx xxxx -uuu uuuu MP1 -xxx xxxx -xxx xxxx -xxx xxxx -xxx xxxx -uuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu STATUS -00 xxxx -1u uuuu -uu uuuu -01 uuuu -11 uuuu Program Counter INTC -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu PA 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu PB -1 1111 -1 1111 -1 1111 -1 1111 -u uuuu PBC -1 1111 -1 1111 -1 1111 -1 1111 -u uuuu PD - -1 - -1 - -1 - -1 - -u PDC - -1 - -1 - -1 - -1 - -u PWM xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRL xxxx - xxxx - xxxx - xxxx - uuuu - ADRH xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADCR 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu ACSR - -00 - -00 - -00 - -00 - -uu Note: ²*² stands for ²warm reset² ²u² stands for ²unchanged² ²x² stands for ²unknown² Rev. 1.40 12 July 12, 2005 HT46R51/HT46R52 HT46R51/HT46R52 Timer/Event Counter flows, the counter is reloaded from the timer/event counter register and issues an interrupt request, as in the other two modes, i.e., event and timer modes. Only one timer/event counter (TMR) are implemented in the microcontroller. The timer/event counter contains an 8-bit programmable count-up counter and the clock may come from an external source or an internal clock source. An internal clock source comes from fSYS. The external clock input allows the user to count external events, measure time intervals or pulse widths, or to generate an accurate time base. To enable the counting operation, the Timer ON bit (TON; bit 4 of the TMRC) should be set to ²1². In the pulse width measurement mode, the TON is automatically cleared after the measurement cycle is completed. But in the other two modes, the TON can only be reset by instructions. The overflow of the timer/event counter is one of the wake-up sources and can also be applied to a PFD (Programmable Frequency Divider) output at PA3 by options. No matter what the operation mode is, writing a ²0² to ETI (bit2 of the INTC) disables the related interrupt service. When the PFD function is selected, executing ²SET [PA].3² instruction to enable the PFD output and executing ²CLR [PA].3² instruction to disable the PFD output. There are two registers related to the Timer/event counter; TMR (0DH), TMRC (0EH). Writing TMR will transfer the specified data to timer/event counter registers. Reading the TMR will read the contents of the timer/event counter. The TMRC is a control register, which defines the operating mode, counting enable or disable and an active edge. The TM0 and TM1 bits define the operation mode. The event count mode is used to count external events, which means that the clock source is from an external (TMR) pin. The timer mode functions as a normal timer with the clock source coming from the internal selected clock source. Finally, the pulse width measurement mode can be used to count the high or low level duration of the external signal (TMR), and the counting is based on the internal selected clock source. In the case of timer/event counter OFF condition, writing data to the timer/event counter preload register also reloads that data to the timer/event counter. But if the timer/event counter is turn on, data written to the timer/event counter is kept only in the timer/event counter preload register. The timer/event counter still continues its operation until an overflow occurs. In the event count or timer mode, the timer/event counter starts counting at the current contents in the timer/event counter and ends at FFH. Once an overflow occurs, the counter is reloaded from the timer/event counter preload register, and generates an interrupt request flag (TF; bit 5 of the INTC ). In the pulse width measurement mode with the values of the TON and TE bits equal to 1, after the TMR has received a transient from low to high (or high to low if the TE bit is ²0²), it will start counting until the TMR returns to the original level and resets the TON. The measured result remains in the timer/event counter even if the activated transient occurs again. In other words, only 1-cycle measurement can be made until the TON is set. The cycle measurement will re-operate as long as it receives further transient pulse. In this operation mode, the timer/event counter begins counting not according to the logic level but to the transient edges. In the case of counter over- When the timer/event counter (TMR) is read, the clock is blocked to avoid errors, as this may results in a counting error. Blocking of the clock issue should be taken into account by the programmer. It is strongly recommended to load a desired value into the TMR register first, before turning on the related timer/event counter, for proper operation since the initial value of TMR is unknown. Due to the timer/event scheme, the programmer should pay special attention on the instruction to enable then disable the timer for the first time, whenever there is a need to use the timer/event function, to avoid unpredictable result. After this procedure, the timer/event function can be operated normally. The bit0~bit2 of the TMRC can be used to define the pre-scaling stages of the internal clock sources of the timer/event counter. The definitions are as shown. The overflow signal of the timer/event counter can be used to generate the PFD signal. The timer prescaler is also used as the PWM counter. D a ta B u s P r e lo a d R e g is te r P S C 2 ~ P S C 0 fS Y S 8 - s ta g e p r e s c a le r T M 1 R e lo a d T M 0 T im e r /E v e n t C o u n te r M o d e C o n tro l T im e r /E v e n t C o u n te r T O N T M R in p u t 8 - B it T im e r /E v e n t C o u n te r O v e r flo w to In te rru p t ¸ 2 P F D T E 8-Bit Timer/Event Counter Structure Rev. 1.40 13 July 12, 2005 HT46R51/HT46R52 HT46R51/HT46R52 Bit No. 0 1 2 Label Function Defines the prescaler stages, PSC2, PSC1, PSC0= 000: fINT=fSYS 001: fINT=fSYS/2 010: fINT=fSYS/4 011: fINT=fSYS/8 100: fINT=fSYS/16 101: fINT=fSYS/32 110: fINT=fSYS/64 111: fINT=fSYS/128 PSC0 PSC1 PSC2 3 TE 4 TON 5 ¾ 6 7 Defines the TMR active edge of the timer/event counter: In Event Counter Mode (TM1,TM0)=(0,1): 1:count on falling edge; 0:count on rising edge In Pulse Width measurement mode (TM1,TM0)=(1,1): 1: start counting on the rising edge, stop on the falling edge; 0: start counting on the falling edge, stop on the rising edge TM0 TM1 Enable/disable timer counting (0=disable; 1=enable) Unused bit, read as ²0² Defines the operating mode, TM1, TM0: 01=Event count mode (external clock) 10=Timer mode (internal clock) 11=Pulse width measurement mode 00=Unused TMRC (0EH) Register Input/Output Ports There are 14 bidirectional input/output lines in the microcontroller, labeled as PA, PB and PD, which are mapped to the data memory of [12H], [14H] and [18H] respectively. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, that is, the inputs must be ready at the T2 rising edge of instruction ²MOV A,[m]² (m=12H, 14H or 18H). For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Each I/O line has its own control register (PAC, PBC, PDC) to control the input/output configuration. With this control register, CMOS output or Schmitt trigger input with or without pull-high resistor structures can be reconfigured dynamically under software control. To function as an input, the corresponding latch of the control register must write ²1². The input source also depends on the control register. If the control register bit is ²1², the input will read the pad state. If the control register bit V C o n tr o l B it D a ta B u s W r ite C o n tr o l R e g is te r C K W r ite D a ta R e g is te r P A P A P A P A P A P A P B P D Q S C h ip R e s e t R e a d C o n tr o l R e g is te r P U Q D D D D a ta B it Q D 0 ~ P 3 /P 4 /T 5 /IN 6 7 0 /A 0 /P A 2 F D M R T N 0 ~ P B 4 /A N 4 W M Q C K S M M [P A 3 , P F D ] o r [P D 0 ,P W M ] R e a d D a ta R e g is te r U E N U X (P F D o r P W M ) X S y s te m W a k e -u p ( P A o n ly ) W a k e -u p IN T fo r P A 5 O n ly Input/Output Ports Rev. 1.40 14 July 12, 2005 HT46R51/HT46R52 HT46R51/HT46R52 is ²0², the contents of the latches will move to the internal bus. The latter is possible in the ²read-modify-write² instruction. The PB can also be used as A/D converter inputs. The A/D function will be described later. There is a PWM function shared with PD0. If the PWM function is enabled, the PWM signal will appear on PD0 (if PD0 is operating in output mode). The I/O functions of PD0 are as shown. For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, 15H and 19H. I/O Mode After a chip reset, these input/output lines remain at high levels or floating state (dependent on pull-high options). Each bit of these input/output latches can be set or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H or 18H) instructions. PD0 If the PFD option is selected, the output signal in output mode of PA3 will be the PFD signal generated by the timer/event counter overflow signal. The input mode always remain in its original functions. Once the PFD option is selected, the PFD output signal is controlled by the PA3 data register only. The I/O functions of PA3 are shown below. Logical Input PA3 Note: Logical Input PFD (Timer on) Parameter X 0 0 1 U X ON N 0 0 X ON N 1 PFD DC 64 The modulation frequency, cycle frequency and cycle duty of the PWM output signal are summarized in the following table. X X DC+1 64 i³AC Frequency OFF Duty Cycle Modulation cycle i (i=0~3) The definitions of the PFD control signal and PFD output frequency are listed in the following table. OFF AC (0~3) i