500 MILLION PARTS FROM 12000 MANUFACTURERS

DATASHEET SEARCH ENGINE

Top Results

Part Manufacturer Description Datasheet BUY
78029013A Intersil Corporation DATACOM, MANCHESTER ENCODER/DECODER, CQCC28, CERAMIC, LCC-28 visit Intersil
SNJ54HC148FK Texas Instruments 8-Line To 3-Line Priority Encoders 20-LCCC -55 to 125 visit Texas Instruments
SN54LS148W-00 Texas Instruments LS SERIES, 8-BIT ENCODER, CDFP16 visit Texas Instruments
SN54LS148W-10 Texas Instruments LS SERIES, 8-BIT ENCODER, CDFP16 visit Texas Instruments
SN54LS148W Texas Instruments LS SERIES, 8-BIT ENCODER, CDFP16 visit Texas Instruments
SN74LS147J-00 Texas Instruments LS SERIES, 9-BIT ENCODER, CDIP16 visit Texas Instruments

H.261 encoder chip

Catalog Datasheet MFG & Type PDF Document Tags

dwa 108 a

Abstract: 27mhz remote control IC synchronization signals. The output can go to a GUI chip, an NTSC/PAL encoder or can be transferred to the , /PAL Encoders or Video Over PCI to GUI · Fully Compliant with the ITU H.261 Standard · Encoder and , . This clock comes from the H.221 processor to facilitate data transfers to/from the P64 H.261 encoder , DISPLAY SCALER ENCODER SCALER DRAM INTERFACE BUS VIDEO OUTPUT BUS I/F H.261 INTERFACE , HMP8364 S E M I C O N D U C T O R PRELIMINARY H.261 Video CODEC June 1997 Features
Harris Semiconductor
Original
HMP8112 dwa 108 a 27mhz remote control IC H261 MD31 dwa 108 ISO9000 1-800-4-HARRIS
Abstract: ITU H.261 Standard â'¢ Encoder and Decoder on the Same Chip â'¢ Supports Simultaneous Encoding and , with proper syn­ chronization signals. The output can go to a GUI chip, an NTSC/PAL encoder or can , clock comes from the H.221 processor to facilitate data transfers to/from the P64 H.261 encoder/decoder , REMOTE DISPLAY SCALER ENCODER SCALER D R AM INTERFACE , BUS VIDEO OUTPUT BUS l/F H.261 , function. The output of the Encode Scaler goes to the H.261 Encoder. The outputs of the Local Display -
OCR Scan
Abstract: P64 H.261 encoder/decoder chip. 3.6 Video Output Port PIN NAME TYPE NO. DESCRIPTION , signals. The output can go to a GUI chip, an NTSC/PAL encoder or can be transferred to the graphics , PCI to GUI â'¢ Fully Compliant with the ITU H.261 Standard â'¢ Encoder and Decoder on the Same , function. The output of the Encode Scaler goes to the H .261 Encoder. The outputs of the Local Display , HMP8364 S E M IC O N D U C T O R PRELIMINARY H.261 Video CODEC June 1997 Features -
OCR Scan

ECHO canceller IC

Abstract: h221 /PAL video encoder (HMP8156). The H.320 (ISDN) VCS chip set supports up to 30 frames per second of CIF , Conferencing chip set. The PCI interface supports control and data flows between the host system and the H.261 , HMP8320VCS S E M I C O N D U C T O R ADVANCE INFORMATION Video Conference Solution Chip Set , Conference Solution) chip set is fully compliant with the ITU-T H.320 Teleconferencing standard and designed to run with a host processor. The VCS chip set consists of four Harris ICs: the video codec
Harris Semiconductor
Original
HMP8201 ECHO canceller IC h221 HMP8112A

H.261 encoder chip

Abstract: TMS320C80 motion-picture-sequence coding. 3. H.261 tries to balance the hardware complexities between the encoder and the decoder , quantization (VQ) may have a rather simple decoder but must have a more complex encoder. 4. H.261 , signal decoder. The signal encoder is not completely specified by the H.261 standard but is expected to , TaskResume functions. There are just two major functions that get the bitstream from the H.261 encoder and , from encoder * / H261FecDecodeBuffer (dbuffer, bitrate); / * Decode the dbuffer bitstream * / H.261
Texas Instruments
Original
TMS320C80 H.261 encoder chip mpeg coder audio layer 2 TMS320C82 at&t video decoder mpeg SPRA161

ti 261

Abstract: PX-64 motion-picture-sequence coding. 3. H.261 tries to balance the hardware complexities between the encoder and the decoder , quantization (VQ) may have a rather simple decoder but must have a more complex encoder. 4. H.261 , signal decoder. The signal encoder is not completely specified by the H.261 standard but is expected to , three parallel processors, PP0 ­ PP2, are used solely for the H.261 video encoder/decoder , (); BufferInstallMalloc (MemAlloc,MemFree); 2. Initialize the H.261 FEC: H261FecInit(); 3. Create the encoder and
Texas Instruments
Original
ti 261 PX-64 motion camera Video controller TMS320C80 mean absolute difference H.261 decoder chip

Video controller TMS320C80

Abstract: H.261 motion-picture-sequence coding. 3. H.261 tries to balance the hardware complexities between the encoder and the decoder , quantization (VQ) may have a rather simple decoder but must have a more complex encoder. 4. H.261 , signal decoder. The signal encoder is not completely specified by the H.261 standard but is expected to , TaskResume functions. There are just two major functions that get the bitstream from the H.261 encoder and , from encoder * / H261FecDecodeBuffer (dbuffer, bitrate); / * Decode the dbuffer bitstream * / H.261
Texas Instruments
Original
H.261 videostream decoders 1995 jpeg codec

H.261 encoder chip

Abstract: convert run length coded data from the VP2611 encoder into an H.261 compatible bitstream. The serial port , VPB261 H.261 Evaluation Board Application Note AN146 - 2.1 June 1996 FEATURES s Complete evaluation and prototyping system for Mitel Semiconductor H.261 Video Compression/Decompression chipset , . The data is colour space converted, filtered and coded to H.261 specification and passed to the , a different H.261 decoder if desired. It is also possible to input H.261 data from another system
Mitel Semiconductor
Original
VP510 VP8708 VP101 VP520

H.261 encoder chip

Abstract: ARRAY MICROSYSTEMS collaboration (T.120) performance. Based on Array's proprietary VideoFLOW® H.261 Codec chip technology, the , tightly couple with and accelerate Microsoft NetMeeting ­ by utilizing Array's hardware to execute H.261 , communication solution for delivering digital video and audio content over an Intranet. With Array's H.261 , compression chip set ­ based on Array's proprietary VideoFLOW technology ­ for optimum performance and , core of the MPEG-1 and H.261 compression tasks ­ performing up to 7 billion operations per second
Array Microsystems
Original
ARRAY MICROSYSTEMS 176x120 H.261 codec chip Video graphic array VIDEO TO SVGA ENCODER videoflow VF300-C VF300
Abstract: CCITT H.261 requirements 40/30 MHz data rate for decoder and encoder Internal BCH decoding buffers 44 , International Consultative Committee for Telephones and Telegraphs (CCITT) recommendation H.261. The forward , second are supported for both the encoder and decoder in full duplex mode. The device processes , user supplied frame bit. The encoder appends 18 bits of redundant check bits to every 493 bits of , char­ acterization. When internal framing and synchronization is selected, the encoder appends a -
OCR Scan
L64715
Abstract: and encoder Internal BCH decoding buffers 44-pin PLCC (Plastic Leaded Chip Carrier) package © 1 9 9 , erly CCITT) recommendation H.261. The forw ard error correcting code is a 2-error correcting BCH code. The device contains both an encoder and a decoder for full duplex operation. The device processes , user supplied frame bit. The encoder appends 18 bits of redundant check bits to every 493 bits of mes , acterization. W hen internal fram ing and synchronization is selected, the encoder appends a single fra m ing -
OCR Scan

CL404A

Abstract: CL4010 , higher-perfonnance chip for all C-Cube encoder and codec applications.1 The VRP3 is separated into two distinct , Description Multimedia Accelerators H.261 Video Codec MPEG-1 Video Encoder Advanced MPEG-1 Video Encoder MPEG , ) Coprocessors: 2 GigaOp motion estimator Variable-length encoder/decoder Video interfaces perform on-chip , (implement DRAM refresh logic on chip). Two Mbytes of interleaved DRAM per chip is typical in most applica , per line and outputs the video on video interface B. The VRP3 as an Encoder The VRP3 accepts a digital
-
OCR Scan
CL4010 CL404A C-Cube VRP3 inverse quantization CL4020 CL4040 CL4000 40-MH CLM4120

BCH code

Abstract: are supported for both the encoder and decoder in full duplex mode. i if a - L64715 Chip , -T SS H.261 requirements 30 M H z data rate for d ecoder and encoder Internal BC H decoding buffers , (formerly CCITT) recom m endation H.261. The forward error correcting code is a 2-error correcting BCH code. The device contains both an encoder and a decoder for full duplex operation. The device p ro c e sse s , u se r supplied frame bit. The encoder a ppends 18 bits of redundant ch e ck bits to every 493 bits
-
OCR Scan
BCH code L6471S

C-Cube CL4000

Abstract: CLM4200 , higher-performance chip for all C-Cube encoder and codec applications.1 The VRP3 is separated into two distinct , -3 Products Description Multimedia Accelerators H.261 Video Codec MPEG-1 Video Encoder Advanced MPEG-1 Video , arithmetic operations per second (MOPS) Coprocessors: s 2 GigaOp motion estimator s Variable-length encoder , signals needed to drive local DRAM array (implement DRAM refresh logic on chip). Two Mbytes of interleaved DRAM per chip is typical in most applications. 3.3V operation from VDD1, and 5V input tolerance from
-
Original
C-Cube CL4000 CLM4200 programmable pipeline microcode memory video encoder mpeg VIDEO CAPTURE CARD USER MANUALS CLM4440

H.261 decoder chip

Abstract: combined video NTSC source which is usually glossed over by people offering single chip or software solutions to H.261 , AN206 An Overview of the H.261 Application Note AN206 - 1.1 October 1995 THE REQUIREMENT H.261 , contents and the accuracy of the decoder, but leaves room for differentiation in the encoder and pre/post , provides scope for 30 B channels. H.261 thus describes video coding and decoding methods at rates of p x 64 , will quality start to suffer. H.261 only covers the video side of a video phone system. Audio can use
Mitel Semiconductor
Original
combined video of4801

H.261 decoder chip

Abstract: H.261 encoder chip NTSC source which is usually glossed over by people offering single chip or software solutions to H.261 , AN206 An Overview of the H.261 Application Note AN206 - 1.1 October 1995 THE REQUIREMENT H.261 , contents and the accuracy of the decoder, but leaves room for differentiation in the encoder and pre/post , provides scope for 30 B channels. H.261 thus describes video coding and decoding methods at rates of p x 64 , will quality start to suffer. H.261 only covers the video side of a video phone system. Audio can use
Zarlink Semiconductor
Original
Videophone

H.261 encoder chip

Abstract: H.261 codec chip source which is usually glossed over by people offering single chip or software solutions to H.261 , reference to the previous frame. The H.261 specification does not demand that the encoder uses motion , RESOLUTION Y 360 X 288 Cr/Cb 180 x 144 Fig.3 Complete H.261 Encoder Using the Chipset SYSTEM , AN206 An Overview of the H.261 Application Note AN206 - 1.1 October 1995 THE REQUIREMENT H.261 , contents and the accuracy of the decoder, but leaves room for differentiation in the encoder and pre/post
Zarlink Semiconductor
Original
VP610 CCIR601 G711 T120 VP2612 VP2614
Abstract: encoder appends a single fra m ­ ing bit, as specified in CCITT recom m endation H.261, to each BCH , CCITT H.261 requirem ents 30 MHz data rate fo r decoder and encoder Internal BCH decoding buffers 44 , (Consultative Committee on International Telephones and Telegraphs) recom m endation H.261. The forw ard error correcting code is a 2-error correcting BCH code. The device contains both an encoder and a decoder fo r , second are supported fo r both the encoder and decoder in full duplex mode. The device processes -
OCR Scan
Abstract: ITU-TSS H.261 requirements 30 MHz data rate for decoder and encoder Internal BCH decoding buffers 44 , ) recommendation H.261. The forward error correcting code is a 2-error correcting BCH code. The device contains both an encoder and a decoder for full duplex operation. The device processes blocks of 512 bits. Each , . The encoder appends 18 bits of redundant check bits to every 493 bits of message to form the BCH , and synchronization is selected, the encoder appends a single framing bit, as specified in ITU-TSS -
OCR Scan

H261

Abstract: VP2611 Pin Quad Flatpack ASSOCIATED PRODUCTS s VP2611 H.261 Encoder s VP2615 H.261 Decoder , chip-set for video conferencing, video telephony, and multimedia applications. This chip set implements , this Chip Enable should be used. PIN DESCRIPTIONS DBUS7:0 The input data bus from VP2611. The data type is defined by the value present on DMODE3:0 TXE2 Active low chip enable for the Transmission buffer. This is used for the optional second memory chip, if a 512kBit buffer is being used
Zarlink Semiconductor
Original
VP520S HB3923-2 DS3511 TXA10 TXA11 TXA12
Showing first 20 results.