GT-24002 128-PQPF 0-700C - Datasheet Archive

 

GT-24002 Printing Line Buffer FIFO Preliminary TM March 1995, Rev.1 (PrintFIFO ) Galileo Technology, Inc. NOTE: Always contact

 

B&W and Color GT-24002 GT-24002 Printing Line Buffer FIFO Preliminary TM March 1995, Rev.1 (PrintFIFO ) Galileo Technology, Inc. NOTE: Always contact Galileo Technology for possible updates before starting a design. FEATURES · Video synchronization control signals to the print engine · Programmable vertical and horizontal page margin size · Programmable page margin color · Easy programming through a simple 8-bit CPU interface or through a serial SPI-compatible port · Burst read and write of any size data blocks - Flag triggers after every 512 bytes · Speeds of up to 33MHz on both the Frame bus and the Video buses · 128-PQPF 128-PQPF package · Synchronous line buffer for CMY, CMYK, Bi Level Color, Gray Scale, and Black & White printing devices · Designed for printers, typesetters, RIPs, and digital copiers · 4416 byte dual port line buffer · Fast SRAM-based FIFO technology · Data width matching from 32-bits to 8-bits for color and gray scale printing · Data width matching from 32-bits to 1-bit for black & white, bi-level color and half-tone printing · Duplex printing support · High bandwidth between the frame buffer and the engine FData 32 FClk REG FStrobe* FRst* OE* Control Logic 1104 X 32 FIFO REG VClk VStrobe* Serial Parallel Interface VRst* VidEn* LineSync* PageSync* LV* VTranInt* NLC VMC HMC LLC CR MCR 4 (SPI) 4 PA[3:0] 8 PD[7:0] PRd* 32->8 PWr* MUX 8->1 VOE* 8 VData 1 VSData 1735 N. First St. #308, San Jose, CA 95112, Tel (408)451-1400, Fax (408)451-1404 1 GT-24002 GT-24002 Printing Line Buffer FIFO OVERVIEW The PrintFIFOTM is a line buffer with data width matching, and with synchronization functions for printing engines. Printers, digital copiers, RIPs, and typesetters that print one of the following formats can use the PrintFIFO: CMY, CMYK, Bi-Level Color, Gray Scale, Half-Toning, and Black & White. The large size (4416 bytes) of the PrintFIFO can hold a complete 8-bit per dot line for 11" wide paper at 400dpi, or several lines of bi-level data. True dual-ported technology (SRAM-based) allows for simultaneous access to the device from both the frame bus and the video bus. Both buses have synchronous interfaces, but they are completely asynchronous from each other. Data is typically burst into the PrintFIFO in large data blocks. A flag that gets triggered after 512 bytes (128 FIFO entries) are read from the video port, is provided for data flow control. At the maximum synchronous rate of 33MHz the bandwidth supported to the printer is 133MBytes/sec. The PrintFIFO supports the generating of page boundaries on all sides of the page independent of the bit map boundaries in the frame buffer. The PrintFIFO supports programmable size upper and left page margins through two on chip margin counters. Right and bottom margins can be created as well through the on-chip Line Length and Number of Lines counters. The color for the page margin can be programmed through the Margin Color Register (MCR). The PrintFIFO will synchronize the timing of the output of the margin color and the video data. The PrintFIFO includes the control logic to interface and synchronize to the printing engine, both at the line level and the page level. The PrintFIFO can be programmed to work with both bigendian and little-endian formats on the frame side. Duplex printing (two sides) is supported by programming the shift direction of the video data (LSB to MSB or MSB to LSB). The PrintFIFO can be programmed through one of two buses, a simple 8-bit parallel bus, or a serial 4-wire bus compatible with the SPI bus. 2 Galileo Technology, Inc. Galileo Technology, Inc. GT-24002 GT-24002 Printing Line Buffer FIFO PD[7:0] Logic Symbol PA[3:0] 1.1 PRd* PIN INFORMATION PWr* 1 Parallel Interface VClk VStrobe* VOE* VRst* FData[31:0] FClk FStrobe* VidEn* Video Interface Frame Interface LV* VSData FRst* VData[7:0] LineSync* General PageSync* OE* SCS* SClk SDIn Serial Interface SDOut VTranInt* 3 Galileo Technology, Inc. GT-24002 GT-24002 Printing Line Buffer FIFO 1.2 Pin Assignment Table Pin name Sync to Type Drive Description General OE* I Global Output Enable. When HIGH, it will put all the outputs and I/O pins in a high impedance state. It is used for in-circuit board testing in the manufacturing process. In normal operation, it needs to be LOW. Frame Interface FStrobe* FClk I Frame Strobe. When FStrobe* is LOW, data is written into the FIFO on every rising edge of FClk that follows the rising edge of FClk that sampled FStrobe* LOW. FRst* FClk I Frame Reset. When FRst* is LOW, the internal write pointer of the Frame side will be set to the first location of the RAM array. I Frame Clock. Reset and write cycles on the FData bus are executed synchronously to FClk. The state of FRst* and FStrobe* is latched by the rising edge of FClk. I Frame Buffer Data[31:0]. Data inputs for the 32-bit Frame port bus. VStrobe* I Video Strobe. When VStrobe* is LOW, data is read from the FIFO on every rising edge of VClk that sampled Vstrobe* LOW. VOE* I Video Output Enable. When VOE* is LOW, the outputs of the video data buses VData and VSData are active. If VOE* is HIGH, the video data buses will be in high impedance state. I Video Reset. When VRst* is LOW, the internal read pointer of the video side will be set to the first location of the RAM array. I Video Clock. Read and reset cycles on the VData bus are executed synchronously to VClk. The state of VidEn*, VRst*, VOE*, and VStrobe* is latched by the rising edge of VClk. The LV* output is driven synchronously with VClk. FClk FData[31:0] FClk Video Interface VRst* VClk VClk VData[7:0] VClk O Video Data. Data outputs for the 8-bit video bus. VSData VClk O Video Serial Data. One bit serial output. This pin stays in a LOW state when Bi-Level mode is not selected. LineSync* I Line Synchronization. A synchronization signal from the engine indicating the beginning of a line. PageSync* I Page Synchronization. A synchronization signal from the engine, indicating a page start. LV* VClk O Line Valid. LV* indicates valid data (including margin) is being driven by the FIFO onto the Video data bus. This signal is undefined until the first PageSync*. VidEn* VClk I Video Enable. When inactive, the FIFO will output the contents of the MCR on the Video Data bus. This pin enables the user to force print the margin. 4 Galileo Technology, Inc. GT-24002 GT-24002 Printing Line Buffer FIFO Pin name Sync to Type Drive Description VTranInt* VClk O Video Transfer Interrupt. This signal will pulse for one VClk when 128 FIFO entries (512 bytes) have been read. It will also pulse when the Line Length Counter reaches a value of zero. VTranInt* is undefined until the first PageSync* SDIn SClk I Serial Data Input. A serial stream to program the FIFO is shifted into the SDIn pin. The least significant bit is shifted in first, on the rising edge of SClk SDOut SClk O Serial Data Output. The same serial stream that is shifted into SDIn is shifted out on the SDOut pin. The least significant bit is shifted out first, on the falling edge of SClk. SDOut is tri-stated when SCS* is HIGH. I Serial Clock. Data is shifted into the FIFO on the rising edge and is shifted out on the falling edge. SClk does not have a minimum frequency requirement. Serial Interface SClk (PWr*) Note - PWr* shares the pin with SClk. SCS* I Serial Chip Select. Data is sampled on the SDin pin on the rising edge of SClk when SCS* is Low. The falling edge of SCS* is treated as a serial interface reset. SDOut is tristated when SCS* is not active. I Parallel Port Write. On the rising edge of PWr*, data on the PD[7:0] bus will be written into the programmable register addressed by PA[3:0]. Parallel Interface PWr* (SClk) Note - PWr* shares the pin with SClk. PRd* I Parallel Port Read. When PRd* is active, data from the register that is addressed by PA[3:0] will be driven onto PD[7:0]. PA[3:0] I Parallel Port Address. Address for the FIFO's internal registers. PD[7:0] I/O Parallel Port Data. Data pins to program or read the contents of the internal registers. 5 Galileo Technology, Inc. GT-24002 GT-24002 Printing Line Buffer FIFO 2 FUNCTIONAL DESCRIPTION Frame port. The Line Valid (LV*) signal indicates if the data on the video bus is valid. Data will not be valid if it is read from the FIFO but the FIFO is empty. 2.1 Frame Interface The PrintFIFO requires the initialization of internal mechanisms (e.g. the address counters) before starting operation. The video reset is executed by activating VRst* for one VClk. The frame interface includes a 32-bit data bus and the control signals to synchronously write to the PrintFIFO. The data on the Fdata[31:0] pins is sampled one FClk after FStrobe* is sampled active by the PrintFIFO. 2.3 Serial Interface Reset is required before starting operation and can be applied during normal operation as well. The Frame reset is executed by activating FRst* for one FClk cycle. The Frame reset initializes the FIFO write pointer to the beginning of the FIFO. The internal registers can be programmed through the serial interface. The serial interface is compliant with Motorola's SPI protocol. All serial interface signals are synchronous to SClk. Serial data read and write can be executed concurrently using DOut and DIn respectively. The FIFO write address increments with each FClk cycle in which FStrobe* is sampled active. The write address counter will wrap around from 1104 to 0. · Duplex (two-sided) printing is supported both for the 8-bit video data and for the 1-bit video data. For the 8-bit video, data can be shifted out as the Most Significant Byte first or Least Significant Byte first on the VData bus. For the 1-bit video, data can be shifted out as the Most Significant Bit first or Least Significant Bit first on the VSData bus. The direction of the bytes and the bits can be set by programming the Configuration Register. There are two status signals that can help in flow control and as error indication. The VTranInt* is asserted as a one cycle pulse every 128 FIFO entries (512 bytes) are read from the Video port. It can be used to trigger the CPU or a DMA controller to move data into the PrintFIFO 6 7 tle first en di a bi -le n ve l ift lit Video data can have two sources: the internal FIFO and the Margin Color Register. The contents of the Margin Color Register will be driven onto the video bus while the Margin Counters are not in terminal count and when the Line Length and Number of Lines counters are at terminal count. The data from the FIFO will be driven onto the video bus when the Line Length counter is counting. The Video Enable (VidEn*) signal can force the content of the MCR register onto the video data bus irrespective of the value of the counters. For example, consider the following stream of bits: sh The PageSync* and LineSync* synchronization signals from the engine, indicate to the PrintFIFO when to load and start the Vertical Margin Counter and the Horizontal Margin Counter respectively. Data will be valid on the VData or VSData buses one cycle after VStrobe* and VOE* are sampled LOW (in most systems VOE* will be tied to VSS). io n The video includes an optional 8-bit or 1-bit wide data output, control signals to synchronously output the video data, and synchronization signals to a printer engine. Each internal register can be written and read through the SPI. The register address and data are shifted into the PrintFIFO through the SDIn pin, and at the same time are shifted out on the SDOut pin. The address of the internal register (to be written or read) is contained in the first 8 bits of each SPI operation. When SCS* is active, the PrintFIFO samples the data or address on the SDin pin on each rising edge of SClk, and the same data or address bit is shifted out on the falling edge of SClk. The SPI is in RESET state each time SCS* is inactive. ur at Video Interface sa t 2.2 Serial Interface Read / Write and Reset 100, 0001, 1001, 0001, 0000 Shifting Order When these are fed to the SDin pin as SCS* is asserted, they will program the Control Register to the following mode of operation: bi-level video; little endian data; shift bit 7 first on bit direction; and MCR will be on VData[7:0] in saturation mode. The bits are shifted in from right to left where 0001,0000 is the Control register address. 2.4 Parallel interface The internal registers can be programmed through the parallel interface as well. The parallel interface is not synchronous to any of the clocks. The parallel data read and write must be executed exclusively, since both operations use the same data port (PD[7:0]). · Parallel Interface Read / Write A register write through the parallel port is performed by Galileo Technology, Inc. GT-24002 GT-24002 Printing Line Buffer FIFO placing the register address on PA[3:0], and data on PD[7:0], and asserting PWr*. The data will be latched on the rising edge of PWr*. A register read is performed by placing the register address on PA[3:0], asserting PRd* and reading the result from PD[7:0]. 2.5 · Internal Registers Vertical Margin Counter (VMC) The VMC is a 12-bit counter that counts the number of margin lines at the top of a page. The VMC starts counting at PageSync*, and counts every LineSync* until it reaches terminal count. It is reloaded at PageSync* with its initial value. · Horizontal Margin Counter (HMC) The HMC is a 12-bit counter that counts the number of left margin dots. The HMC starts counting at LineSync*, and counts every VStrobe*, until it reaches terminal count. It is reloaded at LineSync* with its initial value. · Line Length Counter (LLC) The LLC is a 22-bit counter that counts the "meaningful" dots in a line (the line width does not include right margin). The LLC starts counting at (HMC=0), and counts every VStrobe*, until it reaches terminal count. It is reloaded at LineSync* with its initial value. · Number of lines Counter (NLC) The NLC is a 22-bit counter that counts the "meaningful" lines (lines to be printed excluding upper margin) on a page. The NLC starts counting at (VMC=0), counts every LineSync*, until it reaches terminal count. It is reloaded at PageSync* with its initial value. · Margin Color Register (MCR) The MCR register will output its value when one of the following is true: VMC 0 LLC = 0 HMC 0 NLC = 0 or when VidEn* is not active. 7 Galileo Technology, Inc. GT-24002 GT-24002 Printing Line Buffer FIFO 3 REGISTER TABLES The following registers can be programmed and read by the user. The registers include a control register to set the PrintFIFO to the chosen mode of operation; counter values for the number of pixels and lines of valid data; counter values for the number of dots in the margins of the page; and a color register for the margins. The registers can be programmed or read via a serial port compatible with Motorola's SPI or via a simple parallel interface. 3.1 Register Map For Serial Programming Register Number of Bits a Address b Control Register 19 0x10 Vertical Margin Counter 20 0x30 Horizontal Margin Counter 20 0x50 Line Length Counter 30 0x70 Number of Lines Counter 30 0x90 32 0xb0 Margin Color Registerc a. The number of bits includes the 8 bits of the register address. b. The Least Significant Bit (LSB) is shifted first (both for the address and the register contents). c. The MCR data has to be padded with 16-bits of zero (for example, MCR data of 0x55 must be written as 0x550000, since the LSB is shifted first). 3.2 Register Map for Parallel Programming Bits No. of Bits Register Address [7:0] 8 Control Register 0x0 [10:8] 3 Control Register 0x1 [7:0] 8 Vertical Margin Counter 0x2 [11:8] 4 Vertical Margin Counter 0x3 [7:0] 8 Horizontal Margin Counter 0x4 [11:8] 4 Horizontal Margin Counter 0x5 [7:0] 8 Line Length Counter 0x6 [15:8] 8 Line Length Counter 0x7 [21:16] 6 Line Length Counter 0x8 [7:0] 8 Number of Lines Counter 0x9 [15:8] 8 Number of Lines Counter 0xa [21:16] 6 Number of Lines Counter 0xb [7:0] 8 Margin Color Register 0xc 8 Galileo Technology, Inc. 3.3 GT-24002 GT-24002 Printing Line Buffer FIFO Control Register (CR) The CR Bits specify the different modes of the PrintFIFO. Bit Name Function 0 Bi/Co Output to the engine is Bi-Level (1 Bit) or Color (8 Bit). 0 - FIFO in Color mode. 1 - FIFO in Bi-Level mode. 1 Reserved Must be "0" 2 Reserved Must be "0" 3 ByteDir Big / Little Endian 0 - Big Endian (Byte 0 on FData[31:24]) 1 - Little Endian (Byte 0 on FData [7:0]) 4 BitDir Bit Direction 0 - Shift Bit 0 first 1 - Shift Bit 7 first Effective when working in Bi-Level mode only. 5-7 Reserved Must be "0". 8-9 Reserved Must be 0. 10 Sat Saturation mode. Effective only when in Bi-Level print mode. 0 - VData[7:0] presents the contents of MCR. 1 - VData[7:0] presents the contents of the VSData pin multiplied 8 times. Note - this Bit should be 0 when not in Bi-Level print mode. Note - all internal registers are not initialized and need to be written before operation begins. 9 Galileo Technology, Inc. GT-24002 GT-24002 Printing Line Buffer FIFO 4 PINOUT TABLES 4.1 128 pin PQFP (sorted by name) Pin # Signal Name Pin # Signal Name Pin # Signal Name Pin # Signal Name 106 FClk 118 FData[17] 65 LV* 72 SDIn 84 FData[0] 119 FData[18] 74 OE* 73 SDOut 87 FData[1] 120 FData[19] 30 PA[0] 55 VClk 88 FData[2] 121 FData[20] 47 PA[1] 20 VData[0] 89 FData[3] 125 FData[21] 60 PA[2] 21 VData[1] 92 FData[4] 126 FData[22] 67 PA[3] 22 VData[2] 94 FData[5] 127 FData[23] 68 PageSync* 27 VData[3] 95 FData[6] 128 FData[24] 102 PD[0] 28 VData[4] 96 FData[7] 1 FData[25] 122 PD[1] 29 VData[5] 97 FData[8] 2 FData[26] 24 PD[2] 31 VData[6] 98 FData[9] 3 FData[27] 4 PD[3] 32 VData[7] 99 FData[10] 5 FData[28] 86 PD[4] 78 VidEn* 100 FData[11] 6 FData[29] 77 PD[5] 46 VOE* 111 FData[12] 7 FData[30] 93 PD[6] 79 VRst* 114 FData[13] 8 FData[31] 38 PD[7] 33 VSData 115 FData[14] 15 FRst* 112 PRd* 108 VStrobe* 116 FData[15] 109 FStrobe* 53 SClk/PWr* 57 VTranInt* 117 FData[16] 66 LineSync* 71 SCS* VSS pins - 12, 13, 14, 16, 17, 18, 19, 25, 44, 51, 54, 69, 75, 76, 85, 90, 101, 103, 104, 107, 123 VDD pins - 9, 10, 11, 23, 26, 45, 52, 56, 70, 80, 81, 82, 83, 91, 105, 110, 113, 124 N.C - 34, 35, 36, 37, 39, 40, 41, 42, 43, 48, 49, 50, 58, 59, 61, 62, 63, 64 10 Galileo Technology, Inc. 4.2 GT-24002 GT-24002 Printing Line Buffer FIFO 128 pin PQFP (sorted by number) Pin # Signal Name Pin # Signal Name Pin # Signal Name Pin # Signal Name 1 FData[25] 33 VSData 65 LV* 97 FData[8] 2 FData[26] 34 N.C. 66 LineSync* 98 FData[9] 3 FData[27] 35 N.C. 67 PA[3] 99 FData[10] 4 PD[3] 36 N.C. 68 PageSync* 100 FData[11] 5 FData[28] 37 N.C. 69 VSS 101 VSS 6 FData[29] 38 PD[7] 70 VDD 102 PD[0] 7 FData[30] 39 N.C. 71 SCS* 103 VSS 8 FData[31] 40 N.C. 72 SDIn 104 VSS 9 VDD 41 N.C. 73 SDOut 105 VDD 10 VDD 42 N.C. 74 OE* 106 FClk 11 VDD 43 N.C. 75 VSS 107 VSS 12 VSS 44 VSS 76 VSS 108 VStrobe* 13 VSS 45 VDD 77 PD[5] 109 FStrobe* 14 VSS 46 VOE* 78 VidEn* 110 VDD 15 FRst* 47 PA[1] 79 VRst* 111 FData[12] 16 VSS 48 N.C. 80 VDD 112 PRd* 17 VSS 49 N.C. 81 VDD 113 VDD 18 VSS 50 N.C. 82 VDD 114 FData[13] 19 VSS 51 VSS 83 VDD 115 FData[14] 20 VData[0] 52 VDD 84 FData[0] 116 FData[15] 21 VData[1] 53 SClk/PWr* 85 VSS 117 FData[16] 22 VData[2] 54 VSS 86 PD[4] 118 FData[17] 23 VDD 55 VClk 87 FData[1] 119 FData[18] 24 PD[2] 56 VDD 88 FData[2] 120 FData[19] 25 VSS 57 VTranInt* 89 FData[3] 121 FData[20] 26 VDD 58 N.C. 90 VSS 122 PD[1] 27 VData[3] 59 N.C. 91 VDD 123 VSS 28 VData[4] 60 PA[2] 92 FData[4] 124 VDD 29 VData[5] 61 N.C. 93 PD[6] 125 FData[21] 30 PA[0] 62 N.C. 94 FData[5] 126 FData[22] 31 VData[6] 63 N.C. 95 FData[6] 127 FData[23] 32 VData[7] 64 N.C 96 FData[7] 128 FData[24] 11 Galileo Technology, Inc. GT-24002 GT-24002 Printing Line Buffer FIFO 5 AC TIMING CHARACTERISTICS (TC= 0-700C 0-700C; VDD= +5V, +/- 5%; CL=50pf) Symbol Signals Description Min t1 FClk,VClk,SClk Pulse width HIGH or LOW 13 ns t2 FClk,VClk,SClk Clock period 30 ns t3 FStrobe*, FRst*, FData Setup to FClk 10 ns t4 VStrobe*, VOE*, VRst*, VidEn* Setup to VClk 13 ns t5a VData, VSData, LV*, VTranInt* Valid delay, Drive delay 2 t6 VData, VSData, LV* Float delay t7 SCS* Setup to SClk 18 ns t8 SDIn Setup to SClk 10 ns t9 SDOut Valid delay, Drive delay from SClk falling edge 2 t10 SDOut Float delay from SCS* t11 PRd*, PWr* Pulse width LOW 90 ns t12 PD Setup to PWr* rising edge 10 ns t13 PD Valid delay from PRd* falling edge 4 t14 PD Float delay from PRd* t15 PA Setup to PWr* or PRd* falling edge PageSync* Asynchronous LineSync* Asynchronous NOTES: a @ C = 25pf L - Rise and Fall times are 2ns - Hold times are 2ns for all input signals 12 Max Unit 15 ns 15 ns 15 ns 15 ns ns 15 30 25 ns ns Galileo Technology, Inc. GT-24002 GT-24002 Printing Line Buffer FIFO t2 t1 t1 FClk t3 FRst* Frame Port Reset t3 FClk FStrobe* t3 FData Frame Port Write 13 Galileo Technology, Inc. GT-24002 GT-24002 Printing Line Buffer FIFO t4 t5 t2 t6 VClk VStrobe* VOE* VData t5 LV* Video Port Read t15 PA PWr* Address t11 t12 PD Data Parallel Programming - Write 14 Galileo Technology, Inc. GT-24002 GT-24002 Printing Line Buffer FIFO t15 Address PA t11 PRd* t14 t13 PD Data Parallel Programming - Read t8 t7 SClk SCS* SDIn D0 D1 D2 t10 t9 SDout D0 D1 D2 Serial Port Input/Output 15 Galileo Technology, Inc. GT-24002 GT-24002 Printing Line Buffer FIFO 6 DC ELECTRICAL SPECIFICATIONS (TC= 0-700C 0-700C; VDD= +5V, +/- 5%) Symbol Parameter Min. Max. Unit VIH Input HIGH Voltage 2.0 VDD+0.5 V VIL Input LOW Voltage -0.5 0.8 V VOH Output HIGH Voltage 2.4 VOL Output LOW Voltage IIN Input Leakage Current IOZ 3-State Output Leakage Current ICC Conditions V 0.4 V -10 10 uA VIN = VDD or VSS -10 10 uA VOUT = VDD or VSS Operating Current 180 mA VDD = 5V, Ta=25C CinClk Clk Input Capacitance 7.5 pF Cin Input Capacitance 7.5 pF Cout Output Capacitance 7.5 pF Cio Transceiver Capacitance 7.5 pF 16 Galileo Technology, Inc. 7 APPLICATIONS 7.1 GT-24002 GT-24002 Printing Line Buffer FIFO Bi-Level Printing The application shown below is the block diagram of a bi-level printer ( black&white, color, or half-tone ) using the PrintFIFO. The PrintFIFO is programmed through the parallel interface. Eight data bits of the I/O bus are connected to the parallel port directly and the read (PRd*) and write (PWr*) signals are generated by a PAL. The SPI protocol can be used as an alternative to the parallel programming if the 4 SPI pins are used (not shown in the diagram). The application shown does not use the control signals VOE*, and VidEn*, and they should be connected to VSS. The status signal LV* is not used and can be left disconnected. The FClk used is the I/O bus clock and the I/O data bus is connected directly to the Frame port. VTranInt* is used by the CPU or by a DMA controller to trigger data writes into the PrintFIFO. Both the VRst* and the FRst* are connected to the system reset in this example. The synchronization signals to the engine are connected directly to the PrintFIFO. CPU Frame Buffer System Memory Controller I/O BUS FData[31:0] VTranInt* LV* VRst* NC FRst* FClk FIFO Write Control VOE* GT-24002 GT-24002 VidEn* FStrobe* PWr* Registers Programming PRd* Control VClk PData[7:0] PageSync* LineSync* VSData Print Engine 17 Galileo Technology, Inc. GT-24002 GT-24002 Printing Line Buffer FIFO 7.2 Color Printing The application shown below is a color CMY or CMYK printer using the PrintFIFO (a similar diagram would be used in a gray-scale printer). The example shown uses some optional signals that are not used in the bi-level printing example. In this example the control logic resets (FRst*) the FIFO write counter when the entire line is written into the FIFO, and resets (VRst*) the read counter after the entire line is read from the video port. The PrintFIFO is programmed via an SPI controller. CPU Frame Buffer System Memory Controller FData[31:0] VTranInt* FClk LV* FIFO Write Control FStrobe* GT-24002 GT-24002 VStrobe* FRst* VOE* VidEn* VRst* SCS* SPI SDIn* LineSync* SClk VClk PageSync* VData[7:0] Print Engine 18 Video Control Galileo Technology, Inc. GT-24002 GT-24002 Printing Line Buffer FIFO 8 PACKAGING 8.1 128-Pin Quad Flat Pack (QFP, EIAJ) 32.15 30.80 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 CPF Galileo 128-pin QFP GT-24002 GT-24002 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 32.15 30.80 28.00 0.10 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 28.00 0.10 0.80 TYP 0.35 0.10 1.60 TYP 19 Galileo Technology, Inc. GT-24002 GT-24002 Printing Line Buffer FIFO 8.2 128 - Pin Quad Flat Pack Expanded View (QFP, EIAJ) 32.15 30.80 0°-8° 2.125 1.350 2.125 1.350 0.18 ± 0.05 3.42 ± 0.25 0.25 0.35 ± 0.10 0.88 ± 0.15 0.36 0.15 Galileo Technology, Inc. 20 1735 N. First St. #308 San Jose, CA 95112 USA Tel (408) 451-1400 Fax (408) 451-1404 SEATING PLANE