GS9091B 259M-C SMPTE352M GS9091 RP168 STG719 GS9090B RP165 - Datasheet Archive

 

Key Features Description · SMPTE 259M-C compliant descrambling and NRZI to NRZ decoding (with bypass) · DVB-ASI

 

GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Key Features Description · SMPTE 259M-C 259M-C compliant descrambling and NRZI to NRZ decoding (with bypass) · DVB-ASI 8b/10b decoding The GS9091B GS9091B is a 270Mb/s equalizing and reclocking deserializer with an internal FIFO. It provides a complete receive solution for SD-SDI and DVB-ASI applications. · Integrated Cable Equalizer · 500m typical equalization of Belden 1694A cable · Integrated line-based FIFO for data alignment/delay, clock phase interchange, DVB-ASI data packet extraction and clock rate interchange, and ancillary data packet extraction · Integrated VCO and reclocker · User selectable additional processing features including: TRS, ANC data checksum, and EDH CRC error detection and correction programmable ANC data detection illegal code remapping · Internal flywheel for noise immune H, V, F extraction · Automatic standards detection and indication · Enhanced Gennum Serial Peripheral Interface (GSPI) · JTAG test interface · Polarity insensitive for DVB-ASI and SMPTE signals · +1.8V core power supply with optional +1.8V or +3.3V I/O power supply · Small footprint (11mm x 11mm) · Low power operation (typically 350mW) · Pb-free and RoHS compliant Applications · SMPTE 259M-C 259M-C Serial Digital Interfaces · DVB-ASI Serial Digital Interfaces GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 In addition to equalizing, reclocking and deserializing the input data stream, the GS9091B GS9091B performs NRZI -to-NRZ decoding, descrambling as per SMPTE 259M-C 259M-C, and word alignment when operating in SMPTE mode. When operating in DVB-ASI mode, the device will word align the data to K28.5 sync characters and 8b/10b decode the received stream. The integrated equalizer is optimized for 270Mb/s and can typically equalize up to 500m of Belden 1694A cable. Both the equalizer and the internal reclocker are fully compatible with both SMPTE and DVB-ASI input streams. The GS9091B GS9091B includes a range of data processing functions such as EDH support (error detection and handling), and automatic standards detection. The device can also detect and extract SMPTE 352M payload identifier packets and independently identify the received video standard. This information is read from internal registers via the host interface port. The GS9091B GS9091B also incorporates a video line-based FIFO. This FIFO may be used in four user-selectable modes to carry out tasks such as data alignment / delay, clock phase interchange, MPEG packet extraction and clock rate interchange, and ancillary data packet extraction. Parallel data outputs are provided in 10-bit multiplexed format, with the associated parallel clock output signal operating at 27MHz. The device may also be used in a low-latency data pass through mode where only descrambling and word alignment will be performed in SMPTE mode. www.gennum.com 1 of 71 Proprietary & Confidential Functional Block Diagram RD_CLK RD_RESET ASI sync detect Reclocker S->P SMPTE sync detect DDI Equalizer IOPROC_EN Programmable I/O LOCK detect pll_lock DDI STAT[3:0] FW_EN DVB_ASI AUTO/MAN SMPTE_BYPASS LOCKED PCLK LFLF+ LB_CONT EQ_BYPASS carrier_detect SMPTE Descramble, Word Alignment and Flywheel DVB-ASI Word Alignment and 8b/10b Decode Power On Reset DOUT[9:0] TRS Check CSUM Check ANC Data Detection TRS Correct CSUM Correct EDH Check & Correct Illegal Code Remap DATA_ERROR FIFO HOST Interface / JTAG test JTAG_EN CS_TMS SCLK_TCK SDIN_TDI SDOUT_TDO RESET GS9091B GS9091B Functional Block Diagram GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 2 of 71 Proprietary & Confidential Revision History Version ECR 0 PCN Date Changes and/or Modifications 139930 November 2006 New Document. 1 144807 April 2007 Converting to Data Sheet. Modified Electrical Characteristics. 2 150199 July 2008 DVB_ASI operation specification change in Auto mode. 50711 Contents Key Features .1 Applications.1 Description.1 Functional Block Diagram .2 1. Pin Out.5 1.1 Pin Assignment.5 2. Electrical Characteristics . 12 2.1 DC Electrical Characteristics . 12 2.2 AC Electrical Characteristics . 14 2.3 Solder Reflow Profiles. 16 2.4 Host Interface Map. 17 2.4.1 Host Interface Map (R/W registers) . 19 2.4.2 Host Interface Map (Read only registers) . 21 3. Detailed Description. 23 3.1 Functional Overview. 23 3.2 Cable Equalization . 24 3.3 Clock and Data Recovery. 24 3.3.1 Internal VCO and Phase Detector. 24 3.4 Serial-To-Parallel Conversion . 24 3.5 Modes Of Operation . 24 3.5.1 Lock Detect . 25 3.5.2 Auto Mode. 27 3.5.3 Manual Mode . 27 3.6 SMPTE Functionality . 28 3.6.1 SMPTE Descrambling and Word Alignment . 28 3.6.2 Internal Flywheel . 28 3.6.3 Switch Line Lock Handling. 29 3.6.4 HVF Timing Signal Generation . 30 3.7 DVB-ASI Functionality . 31 GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 3 of 71 Proprietary & Confidential 3.7.1 DVB-ASI 8b/10b Decoding. 32 3.7.2 Status Signal Outputs . 32 3.8 Data-Through Functionality . 32 3.9 Additional Processing Features . 33 3.9.1 FIFO Load Pulse . 33 3.9.2 Ancillary Data Detection and Indication. 34 3.9.3 EDH Packet Detection. 35 3.9.4 EDH Flag Detection. 36 3.9.5 SMPTE 352M Payload Identifier. 39 3.9.6 Automatic Video Standard and Data Format Detection . 40 3.9.7 Error Detection and Indication . 41 3.9.8 Additional SMPTE Mode Processing . 46 3.10 Internal FIFO Operation . 49 3.10.1 Video Mode . 49 3.10.2 DVB-ASI Mode . 51 3.10.3 Ancillary Data Extraction Mode . 54 3.10.4 Bypass Mode. 56 3.11 Parallel Data Outputs. 57 3.11.1 Parallel Data Bus Output Buffers. 57 3.11.2 Parallel Output in SMPTE Mode. 58 3.11.3 Parallel Output in DVB-ASI Mode. 58 3.11.4 Parallel Output in Data-Through Mode. 58 3.12 Programmable Multi-Function Outputs. 58 3.13 GS9091B GS9091B Low-latency Mode. 60 3.14 GSPI Host Interface. 61 3.14.1 Command Word Description . 61 3.14.2 Data Read and Write Timing . 62 3.14.3 Configuration and Status Registers. 64 3.15 JTAG operation . 65 3.16 Device Power Up. 66 4. References & Relevant Standards . 67 5. Application Information . 68 5.1 Typical Application Circuit . 68 6. Package & Ordering Information . 69 6.1 Package Dimensions. 69 6.2 Packaging Data. 70 6.3 Marking Diagram. 70 6.4 Ordering Information. 70 GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 4 of 71 Proprietary & Confidential 1. Pin Out 1.1 Pin Assignment 1 2 3 4 5 6 7 8 9 10 A LF+ NC LB_ CONT VCO_ VDD VBG FIFO_EN AUTO/ MAN LOCKED PCLK DOUT9 B LF- PLL_ VDD PLL_ GND VCO_ GND NC FW_EN CORE _VDD SMPTE_ DVB_ASI DOUT8 BYPASS C ANA_ VDD ANA_ VDD NC NC NC NC NC D ANA_ GND ANA_ GND NC CORE _GND CORE _GND E EQ_GND TERM NC CORE _GND F SDI HEAT_ SINK_ GND HEAT_ SINK_ GND G SDI HEAT_ SINK_ GND H EQ_VDD HEAT_ SINK_ GND J AGC+ K AGC- IO_VDD NC DOUT7 IO_GND IO_GND NC NC DOUT6 CORE _GND IO_GND IO_GND NC IO_VDD DOUT5 CORE _GND CORE _GND IO_GND IO_GND NC IO_VDD DOUT4 HEAT_ SINK_ GND CORE _GND CORE _GND IO_GND IO_GND NC NC DOUT3 HEAT_ SINK_ GND NC NC NC NC IO_VDD RD_ RESET DOUT2 EQ_ JTAG_EN BYPASS CS_ TMS SDOUT _TDO CORE _VDD DATA_ ERROR STAT2 STAT3 DOUT1 RESET SCLK _TCK SDIN _TDI STAT0 STAT1 NC IOPROC _EN RD_CLK DOUT0 Figure 1-1: Pin Assignment GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 5 of 71 Proprietary & Confidential Table 1-1: Ball List and Description Ball Name Timing Type Description A1 LF+ Analog Input Loop filter component connection. Connect to LF- through a 4.4nF capacitor. A2, B5, C3, C4, C5, C6, C7, C9, D3, D8, D9, E3, E8, F8, G8, G9, H4, H5, H6, H7, K2 NC ­ ­ No connect. Not connected internally. LB_CONT Analog Input CONTROL SIGNAL INPUT A3 Control voltage to fine-tune the loop bandwidth of the PLL. A4 VCO_VDD Analog Input Power Power supply connection for Voltage-Controlled-Oscillator. Connect to +1.8V DC. A5 VBG Analog Input Bandgap filter capacitor. Connect to GND as shown in Typical Application Circuit. A6 FIFO_EN Non Synchronous Input CONTOL SIGNAL INPUT Signal levels are LVCMOS / LVTTL compatible. Used to enable / disable the internal FIFO. When FIFO_EN is HIGH, the internal FIFO will be enabled. Data will be clocked out of the device on the rising edge of the RD_CLK input pin if the FIFO is in video mode or DVB-ASI mode. When FIFO_EN is LOW, the internal FIFO is bypassed and parallel data is clocked out on the rising edge of the PCLK output. A7 AUTO/MAN Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS / LVTTL compatible. When set HIGH, the GS9091B GS9091B will operate in Auto mode. The SMPTE_BYPASS pin becomes an output status signal set by the device. In this mode, the GS9091B GS9091B will automatically detect, reclock, deserialize, and process SMPTE compliant input data. When set LOW, the GS9091B GS9091B will operate in Manual mode. The DVB_ASI and SMPTE_BYPASS pins become input control signals. In this mode, the application layer must set these two external pins for the correct reception of either SMPTE or DVB-ASI data. Manual mode also supports the reclocking and deserializing of data not conforming to SMPTE or DVB-ASI streams. A8 LOCKED Synchronous with PCLK Output STATUS SIGNAL OUTPUT Signal levels are LVCMOS / LVTTL compatible. The LOCKED pin will be HIGH whenever the device has correctly received and locked to SMPTE compliant data in SMPTE mode or DVB-ASI compliant data in DVB-ASI mode, or when the reclocker has achieved lock in Data-Through mode. It will be LOW otherwise. When the pin is LOW, all digital output signals will be forced to logic LOW levels. A9 PCLK ­ Output PIXEL CLOCK OUTPUT Signal levels are LVCMOS / LVTTL compatible. 27MHz parallel clock output. GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 6 of 71 Proprietary & Confidential Table 1-1: Ball List and Description (Continued) Ball A10, B10, C10, D10, E10, F10, G10, H10, J10, K10 Name Timing Type Description DOUT[9:0] Synchronous with RD_CLK or PCLK Output PARALLEL VIDEO DATA BUS Signal levels are LVCMOS / LVTTL compatible. When the internal FIFO is enabled and configured for either video mode or DVB-ASI mode, parallel data will be clocked out of the device on the rising edge of RD_CLK. When the internal FIFO is in bypass mode, parallel data will be clocked out of the device on the rising edge of PCLK. DOUT9 is the MSB and DOUT0 is the LSB. B1 LF- Analog Input Loop filter component connection. Connect to LF+ through a 4.4nF capacitor. B2 PLL_VDD Analog Input Power Power supply connection for phase-locked loop. Connect to +1.8V DC. Input Ground connection for phase-locked loop. Connect to GND. B3 PLL_GND Analog Power B4 VCO_GND Analog Input Power Ground connection for Voltage-Controlled-Oscillator. Connect to GND. B6 FW_EN Non Synchronous Input CONTOL SIGNAL INPUT Signal levels are LVCMOS / LVTTL compatible. Used to enable or disable the noise immune flywheel of the device. When set HIGH, the internal flywheel is enabled. This flywheel is used in the extraction of timing signals, the generation of TRS signals, the automatic detection of video standards, and in manual switch line lock handling. When set LOW, the internal flywheel is disabled. Timing based TRS errors will not be detected. B7, J6 B8 CORE_VDD SMPTE_BYPASS Non Synchronous Input Non Synchronous Input / Output Power supply for digital logic blocks. Connect to +1.8V DC. Power CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT Signal levels are LVCMOS / LVTTL compatible. This pin is an input set by the application layer in Manual mode, and an output set by the device in Auto mode. Auto Mode (AUTO/MAN = HIGH): The SMPTE_BYPASS pin will be HIGH only when the device has locked to a SMPTE compliant data stream. It will be LOW otherwise. When the pin is LOW, no I/O processing features are available. Manual Mode (AUTO/MAN = LOW): When the application layer sets this pin HIGH in conjunction with DVB_ASI = LOW, the device will be configured to operate in SMPTE mode. All I/O processing features may be enabled in this mode. When SMPTE_BYPASS is set LOW, the device will not support the descrambling, decoding, or word alignment of received SMPTE data. No I/O processing features will be available. GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 7 of 71 Proprietary & Confidential Table 1-1: Ball List and Description (Continued) Ball B9 Name Timing Type Description DVB_ASI Non Synchronous Input / Output CONTROL SIGNAL INPUT / STATUS SIGNAL OUTPUT Signal levels are LVCMOS / LVTTL compatible. This pin and its function are only supported in Manual mode (AUTO/MAN = LOW). When the application layer sets this pin HIGH, the device will be configured to operate in DVB-ASI mode. The SMPTE_BYPASS pin will be ignored. When set LOW, the device will not support the decoding or word alignment of received DVB-ASI data. C1, C2 C8, E9, F9, H8 ANA_VDD Analog Input Power Power supply connection for analog core. Connect to +3.3V DC. IO_VDD Non Synchronous Input Power supply for digital I/O. Power For a 3.3V tolerant I/O, connect pins to either +1.8V DC or +3.3V DC. For a 5V tolerant I/O, connect pins to a +3.3V DC. D1, D2 ANA_GND Analog Input Power Ground connection for analog core. Connect to GND. D4, D5, E4, E5, F4, F5, G4, G5 CORE_GND Non Synchronous Input Ground connection for digital logic blocks. Connect to GND. D6, D7, E6, E7, F6, F7, G6, G7 IO_GND Non Synchronous Input Power Ground connection for digital I/O. Connect to GND. E1 EQ_GND Analog Input Power Ground connection for equalizer core. Connect to GND. E2 TERM Analog Input Termination for serial digital input. AC couple to ANA_GND SDI, SDI Analog Input Serial digital differential input pair. HEAT_SINK_GND Analog Input Power Heat sink connection. Connect to main ground plane of application board. H1 EQ_VDD Analog Input Power Power supply connection for equalizer core. Connect to +3.3V DC. H9 RD_RESET Synchronous with RD_CLK Input FIFO READ RESET Signal levels are LVCMOS / LVTTL compatible. F1, G1 F2, F3, G2, G3, H2, H3 Power Valid input only when the device is in SMPTE mode (SMPTE_BYPASS = HIGH and DVB-ASI = LOW), and the internal FIFO is configured for video mode (Section 3.10.1). A HIGH to LOW transition will reset the FIFO pointer to address zero of the memory. J1, K1 AGC+, AGC- Analog GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 Input External AGC capacitor connection. Connect J1 and K1 together through a 1uF capacitor. 8 of 71 Proprietary & Confidential Table 1-1: Ball List and Description (Continued) Ball J2 Name Timing Type Description EQ_BYPASS Analog Input CONTOL SIGNAL INPUT Signal levels are 3.3V CMOS / LVTTL compatible. Equalizer bypass. When EQ_BYPASS is HIGH, the equalizer stages are bypassed. When EQ_BYPASS is LOW, normal operation of the equalizer stages resumes. J3 JTAG_EN Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS / LVTTL compatible. Used to select JTAG Test Mode or Host Interface Mode. When set HIGH, CS_TMS, SCLK_TCK, SDOUT_TDO, and SDIN_TDI are configured for JTAG boundary scan testing. When set LOW, CS_TMS, SCLK_TCK, SDOUT_TDO, and SDIN_TDI are configured as GSPI pins for normal host interface operation. J4 CS_TMS Synchronous with SCLK_TCK Input CONTROL SIGNAL INPUT Signal levels are LVCMOS / LVTTL compatible. Chip Select / Test Mode Select Host Mode (JTAG_EN = LOW): CS_TMS operates as the host interface chip select, CS, and is active LOW. JTAG Test Mode (JTAG_EN = HIGH): CS_TMS operates as the JTAG test mode select, TMS, and is active HIGH. J5 SDOUT_TDO Synchronous with SCLK_TCK Output CONTROL SIGNAL INPUT Signal levels are LVCMOS / LVTTL compatible. Serial Data Output / Test Data Output Host Mode (JTAG_EN = LOW): SDOUT_TDO operates as the host interface serial output, SDOUT, used to read status and configuration information from the internal registers of the device. JTAG Test Mode (JTAG_EN = HIGH): SDOUT_TDO operates as the JTAG test data output, TDO. J7 DATA_ERROR Synchronous with PCLK Output STATUS SIGNAL OUTPUT. Signal levels are LVCMOS / LVTTL compatible. The DATA_ERROR pin will be LOW when an error within the received data stream has been detected by the device. This pin is an inverted logical `OR'ing of all detectable errors listed in the internal ERROR_STATUS register. Once an error is detected, DATA_ERROR will remain LOW until the start of the next video frame / field, or until the ERROR_STATUS register is read via the host interface. The DATA_ERROR pin will be HIGH when the received data stream has been detected without error. NOTE: It is possible to program which error conditions are monitored by the device by setting appropriate bits in the ERROR_MASK register HIGH. All error conditions are detected by default. GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 9 of 71 Proprietary & Confidential Table 1-1: Ball List and Description (Continued) Ball K3 Name Timing Type Description IOPROC_EN Non Synchronous Input CONTROL SIGNAL INPUT Signal Levels are LVCMOS / LVTTL compatible. Used to enable or disable the I/O processing features. When set HIGH, the following I/O processing features of the device are enabled: · Illegal Code Remapping · EDH CRC Error Correction · Ancillary Data Checksum Error Correction · TRS Error Correction · EDH Flag Detection To enable a subset of these features, keep IOPROC_EN HIGH and disable the individual feature(s) in the IOPROC_DISABLE register accessible via the host interface. When set LOW, the device will enter low-latency mode. NOTE: When the internal FIFO is configured for Video mode or Ancillary Data Extraction mode, IOPROC_EN must be set HIGH (see Section 3.10). K4 RESET Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS / LVTTL compatible. Used to reset the internal operating conditions to default setting or to reset the JTAG test sequence. Host Mode (JTAG_EN = LOW): When asserted LOW, all functional blocks will be set to default conditions and all input and output signals become high impedance. When set HIGH, normal operation of the device resumes 10usec after the LOW-to-HIGH transition of the RESET signal. JTAG Test Mode (JTAG_EN = HIGH): When asserted LOW, all functional blocks will be set to default and the JTAG test sequence will be held in reset. When set HIGH, normal operation of the JTAG test sequence resumes. K5 SCLK_TCK Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS / LVTTL compatible. Serial Data Clock / Test Clock. All JTAG / Host Interface address and data are shifted into/out of the device synchronously with this clock. Host Mode (JTAG_EN = LOW): SCLK_TCK operates as the host interface serial data clock, SCLK. JTAG Test Mode (JTAG_EN = HIGH): SCLK_TCK operates as the JTAG test clock, TCK. GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 10 of 71 Proprietary & Confidential Table 1-1: Ball List and Description (Continued) Ball K6 Name Timing Type Description SDIN_TDI Synchronous with SCLK_TCK Input CONTROL SIGNAL INPUT Signal levels are LVCMOS / LVTTL compatible. Serial Data Input / Test Data Input Host Mode (JTAG_EN = LOW): SDIN_TDI operates as the host interface serial input, SDIN, used to write address and configuration information to the internal registers of the device. JTAG Test Mode (JTAG_EN = HIGH): SDIN_TDI operates as the JTAG test data input, TDI. K7, K8, J8, J9 STAT[0:3] Synchronous with PCLK or RD_CLK Output MULTI FUNCTION I/O PORT Signal levels are LVCMOS / LVTTL compatible. Programmable multi-function outputs. By programming the bits is the IO_CONFIG register, each pin can output one of the following signals: · H · V · F · FIFO_LD · ANC · EDH_DETECT · FIFO_FULL · FIFO_EMPTY These pins are set to certain default values depending on the configuration of the device and the internal FIFO mode selected. See Section 3.12 for details. K9 RD_CLK ­ Input FIFO READ CLOCK Signal levels are LVCMOS / LVTTL compatible. The application layer clocks the parallel data out of the FIFO on the rising edge of RD_CLK. GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 11 of 71 Proprietary & Confidential 2. Electrical Characteristics Table 2-1: Absolute Maximum Ratings Parameter Value/Units Supply Voltage Core -0.3V to +2.1V Supply Voltage I/O -0.3V to +3.47V Input Voltage Range (LF+, LF-, LB_CONT, VBG) -0.5V to +2.3V Input Voltage Range (SDI, SDI, AGC+, AGC-, EQ_BYPASS) -0.5V to +3.6V Input Voltage Range (All Other) -0.5V to +5.25V Ambient Operating Temperature -20°C < TA < 85°C Storage Temperature -40°C < TSTG < 125°C ESD protection on all pins (see Note 1) 1kV NOTES: 1. MIL STD 883 ESD protection will be applied to all pins on the device. Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions or at any other condition beyond those indicated in the AC/DC Electrical Characteristic sections is not implied. 2.1 DC Electrical Characteristics Table 2-2: DC Electrical Characteristics VDD = 1.8V ±5%, 3.3V ±5%; TA = 0°C to 70°C, unless otherwise specified. Typical values: VCC = 1.8V, 3.3V and TA =25°C Parameter Symbol Condition Min Typ Max Units Notes System Operating Temperature Range TA ­ 0 25 70 °C 1 Core Power Supply Voltage CORE_VDD ­ 1.71 1.8 1.89 V ­ Analog Core Power Supply Voltage ANA_VDD ­ 3.13 3.3 3.47 V ­ Digital I/O Buffer Power Supply Voltage IO_VDD 1.8V Operation 1.71 1.8 1.89 V ­ IO_VDD 3.3V Operation 3.13 3.3 3.47 V ­ PLL Power Supply Voltage PLL_VDD ­ 1.71 1.8 1.89 V ­ VCO Power Supply Voltage VCO_VDD ­ 1.71 1.8 1.89 V ­ Equalizer Power Supply Voltage EQ_VDD ­ 3.13 3.3 3.47 V ­ Core Supply Current IDD Total 1.8V Supply ­ 64 80 mA 2 Total 3.3V Supply ­ 69 92 mA 3 GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 12 of 71 Proprietary & Confidential Table 2-2: DC Electrical Characteristics (Continued) VDD = 1.8V ±5%, 3.3V ±5%; TA = 0°C to 70°C, unless otherwise specified. Typical values: VCC = 1.8V, 3.3V and TA =25°C Parameter PD Typ Max Units Notes I/O Supply, 1.8V Operation ­ 4.5 8 mA 4 ­ 8.5 14 mA 4 CORE_VDD = 1.8V IO_VDD = 1.8V ­ 350 ­ mW ­ CORE_VDD = 1.89V IO_VDD = 3.47V Power Dissipation IIO Min I/O Supply, 3.3V Operation I/O Supply Current Symbol Condition ­ ­ 490 mW ­ Digital I/O Input Voltage, Logic LOW VIL 1.8V Operation or 3.3V Operation ­ ­ 0.35 x IO_VDD V ­ Input Voltage, Logic HIGH VIH 1.8V Operation or 3.3V Operation 0.65 x IO_VDD ­ ­ V ­ Output Voltage, Logic LOW VOL IOL = 8mA @ 3.3V, 4mA @ 1.8V ­ ­ 0.4 V ­ Output Voltage, Logic HIGH VOH IOL = -8mA @ 3.3V, -4mA @ 1.8V IO_VDD - 0.4 ­ ­ V ­ EQ_BYPASS Input Voltage VIL Logic LOW ­ ­ 0.8 V ­ VIH Logic HIGH 2.4 ­ ­ V ­ Input Common Mode Voltage VCMIN TA = 25°C ­ 1.75 ­ V ­ Input Resistance ­ single ended ­ 1.64 ­ k ­ Serial Digital Inputs NOTES 1. 2. 3. 4. All DC and AC electrical parameters within specification. Maximum supply current at TA = 0°C and VDD = 1.89V supply. Maximum supply current at TA = 75°C and VDD = 3.47V supply. I/O currents are based on output drivers driving one CMOS load. GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 13 of 71 Proprietary & Confidential 2.2 AC Electrical Characteristics Table 2-3: AC Electrical Characteristics VDD = 1.8V ±5%, 3.3V ±5%; TA = 0°C to 70°C, unless otherwise specified. Typical values: VCC = 1.8V, 3.3V and TA =25°C Parameter Symbol Condition Min Typ Max Units Notes Input Voltage Swing VSDI TA =25°C, differential 720 800 950 mVp-p 1 Lock Time (Asynchronous Switch) tLOCK TA =25°C, 500m of Belden 1694A ­ 560 ­ us 2 Serial Input Data Rate DRSDI ­ ­ 270 ­ Mb/s ­ DVB-ASI Payload Data Rate DRASI 204 byte mode ­ ­ 213.9 Mb/s 3,5 188 byte mode ­ ­ 213.7 Mb/s 4,5 ­ 500 ­ m ­ System Serial Digital Input Achievable Cable Length ­ Belden 1694A Cable 270MHz Input Return Loss ­ ­ 15 ­ ­ dB 6 Input Capacitance ­ single ended ­ 1 ­ pF ­ Parallel Output Clock Frequency fPCLK ­ ­ 27 ­ MHz ­ Parallel Output Clock Duty Cycle DCPCLK ­ 40 ­ 60 % ­ Variation of Parallel Output Clock (from 27MHz) ­ Device Unlocked -7 ­ +7 % 7 Output Data Hold Time tOH With 15pF load 3.0 ­ ­ ns 8 Output Delay Time tOD With 15pF load ­ ­ 10.0 ns 8 GSPI Input Clock Frequency fGSPI ­ ­ ­ 54.0 MHz ­ GSPI Clock Duty Cycle DCGSPI ­ 40 ­ 60 % ­ GSPI Setup Time tGS ­ 1.5 ­ ­ ns ­ Parallel Output TA = 5°C to 45°C GSPI GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 14 of 71 Proprietary & Confidential Table 2-3: AC Electrical Characteristics (Continued) VDD = 1.8V ±5%, 3.3V ±5%; TA = 0°C to 70°C, unless otherwise specified. Typical values: VCC = 1.8V, 3.3V and TA =25°C Parameter Symbol Condition GSPI Hold Time tGH ­ Min Typ Max Units Notes 1.5 ­ ­ ns ­ NOTES 1. 0m cable length. 2. Time from input no-data to data switch and LOCKED pin set HIGH. 3. Transmission format includes 204 byte data packets preceded by two K28.5 synchronization characters. Payload data rate excludes the two K28.5 synchronization characters. 4. Transmission format includes 188 byte data packets preceded by two K28.5 synchronization characters. Payload data rate excludes the two K28.5 synchronization characters. 5. Maximum payload is achieved via data packet mode,however, any combination of burst and packet mode is supported as long as each byte or packet is preceded by two K28.5 characters. 6. 5MHz to 270MHz. 7. When the serial input to the GS9091B GS9091B is removed, the PCLK output signal will continue to operate at 27MHz and the internal VCO will remain at this frequency within +/-7% over the range 5oC to 45oC. Over the full operating temperature range (0oC to 70oC), the VCO may deviate from 27MHz up to +/-13%. 8. Timing includes the following outputs: DOUT[9:0], H, V, F, ANC, EDH_DETECT, FIFO_FULL, FIFO_EMPTY, FIFO_LD, WORDERR, SYNCOUT. When the FIFO is enabled, the outputs are measured with respect to RD_CLK. GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 15 of 71 Proprietary & Confidential 2.3 Solder Reflow Profiles The device is manufactured with Matte-Sn terminations and is compatible with both standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed using the maximum Pb-free reflow profile shown in Figure 2-1. The recommended standard eutectic reflow profile is shown in Figure 2-2. Temperature 60-150 sec. 20-40 sec. 260°C 250°C 3°C/sec max 217°C 6°C/sec max 200°C 150°C 25°C Time 60-180 sec. max 8 min. max Figure 2-1: Maximum Pb-free Solder Reflow Profile (Preferred) 60-150 sec. Temperature 10-20 sec. 230°C 220°C 3°C/sec max 183°C 6°C/sec max 150°C 100°C 25°C Time 120 sec. max 6 min. max Figure 2-2: Standard Eutectic Solder Reflow Profile GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 16 of 71 Proprietary & Confidential 28h FIFO_LD_POSITION[12:0] 24h 23h 22h 21h 20h 1Fh 1Eh 1Dh 1Ch 1Bh 1Ah 19h 18h 17h 16h 15h 14h 13h FF_PIXEL_END_F1[12:0] FF_PIXEL_START_F1[12:0] FF_PIXEL_END_F0[12:0] FF_PIXEL_START_F0[12:0] AP_PIXEL_END_F1[12:0] AP_PIXEL_START_F1[12:0] AP_PIXEL_END_F0[12:0] AP_PIXEL_START_F0[12:0] FF_LINE_END_F1[10:0] FF_LINE_START_F1[10:0] FF_LINE_END_F0[10:0] FF_LINE_START_F0[10:0] AP_LINE_END_F1[10:0] AP_LINE_START_F1[10:0] AP_LINE_END_F0[10:0] AP_LINE_START_F0[10:0] RASTER_STRUCTURE4[10:0] RASTER_STRUCTURE3[12:0] Not Used Not Used 14 Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used 15 Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used 13 b12 Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used b12 b12 b12 b12 b12 b12 b12 b12 Not Used b12 12 GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 25h ERROR_MASK_REGISTER 26h 27h Address Register Name Table 2-4: Host Interface Map 2.4 Host Interface Map b11 Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used b11 b11 b11 b11 b11 b11 b11 b11 Not Used b11 11 b10 b10 b10 b10 b10 b10 b10 b10 b10 b10 b10 b10 b10 b10 b10 b10 b10 b10 Not Used b10 10 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 Not Used b9 9 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 Not Used b8 8 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 Not Used b7 7 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 VD_STD_ ERR_ MASK b6 6 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 FF_CRC_ ERR_ MASK b5 5 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 AP_CRC_ ERR_ MASK b4 4 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 CCS_ERR_ MASK b2 2 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 EAV_ERR _MASK b0 0 17 of 71 SAV_ERR_ MASK b1 1 Proprietary & Confidential LOCK_ ERR_ MASK b3 3 12h 11h 10h 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h 08h 07h 06h 05h 04h 03h 02h 01h 00h RASTER_STRUCTURE2[12:0] RASTER_STRUCTURE1[10:0] VIDEO_FORMAT_OUT_B(4,3) VIDEO_FORMAT_OUT_A(2,1) ANC_TYPE(5)[15:0] ANC_TYPE(4)[15:0] ANC_TYPE(3)[15:0] ANC_TYPE(2)[15:0] ANC_TYPE(1)[15:0] ANC_LINE_B[10:0] ANC_LINE_A[10:0] FIFO_FULL_OFFSET FIFO_EMPTY_OFFSET IO_CONFIG DATA_FORMAT EDH_FLAG_OUT EDH_FLAG_IN ERROR_STATUS IOPROC_DISABLE Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used b15 b15 b15 b15 b15 VFO2-b7 VFO4-b7 Not Used Not Used 15 Not Used Not Used ANC-UES _IN ANC-UES Not Used Not Used Not Used Not Used Not Used Not Used b14 b14 b14 b14 b14 VFO2-b6 VFO4-b6 Not Used Not Used 14 Not Used Not Used ANC-IDA _IN ANC-IDA Not Used Not Used Not Used Not Used Not Used Not Used b13 b13 b13 b13 b13 VFO2-b5 VFO4-b5 Not Used Not Used 13 Not Used Not Used ANC-IDH _IN ANC-IDH Not Used ANC_ DATA_ SWITCH Not Used Not Used Not Used Not Used b12 b12 b12 b12 b12 VFO2-b4 VFO4-b4 Not Used b12 12 Not Used Not Used ANC-EDA _IN ANC-EDA EDH_ FLAG_ UPDATE STAT3_ CONFIG b2 ANC_ DATA_ DELETE Not Used Not Used Not Used b11 b11 b11 b11 b11 VFO2-b3 VFO4-b3 Not Used b11 11 Not Used Not Used ANC-EDH _IN ANC-EDH AP_CRC_ V STAT3_ CONFIG b1 Not Used Not Used b10 b10 b10 b10 b10 b10 b10 VFO2-b2 VFO4-b2 b10 b10 10 ANC_PKT _EXT Not Used FF-UES_IN FF-UES FF_CRC_V STAT3_ CONFIG b0 b9 b9 b9 b9 b9 b9 b9 b9 b9 VFO2-b1 VFO4-b1 b9 b9 9 GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 NOTE: Addresses 02Ch to 42Bh store the contents of the internal FIFO. The contents may be accessed in Ancillary Data Extraction mode (see Section 3.10.3). Address Register Name Table 2-4: Host Interface Map (Continued) FIFO_ MODE b1 Not Used FF-IDA_IN FF-IDA EDH_ DETECT STAT2_ CONFIG b2 b8 b8 b8 b8 b8 b8 b8 b8 b8 VFO2-b0 VFO4-b0 b8 b8 8 FIFO_ MODE b0 Not Used FF-IDH_IN FF-IDH VERSION_ 352M STAT2_ CONFIG b1 b7 b7 b7 b7 b7 b7 b7 b7 b7 VFO1-b7 VFO3-b7 b7 b7 7 H_ CONFIG VD_STD_ ERR FF-EDA_I N FF-EDA Not Used STAT2_ CONFIG b0 b6 b6 b6 b6 b6 b6 b6 b6 b6 VFO1-b6 VFO3-b6 b6 b6 6 Not Used FF_CRC_ ERR FF-EDH_I N FF-EDH Not Used STAT1_ CONFIG b2 b5 b5 b5 b5 b5 b5 b5 b5 b5 VFO1-b5 VFO3-b5 b5 b5 5 Not Used AP_CRC_ ERR AP-UES_I N AP-UES STD_ LOCK STAT1_ CONFIG b1 b4 b4 b4 b4 b4 b4 b4 b4 b4 VFO1-b4 VFO3-b4 b4 b4 4 EDH_CRC _INS CCS_ERR AP-IDH_I N AP-IDH DATA_ FORMAT b2 STAT0_ CONFIG b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 VFO1-b2 VFO3-b2 b2 b2 2 TRS_IN EAV_ERR AP-EDH_I N AP-EDH DATA_ FORMAT b0 STAT0_ CONFIG b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 VFO1-b0 VFO3-b0 b0 b0 0 18 of 71 ANC_ CSUM_ INS SAV_ERR AP-EDA_I N AP-EDA DATA_ FORMAT b1 STAT0_ CONFIG b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 VFO1-b1 VFO3-b1 b1 b1 1 Proprietary & Confidential ILLEGAL_ REMAP LOCK_ ERR AP-IDA_I N AP-IDA DATA_ FORMAT b3 STAT1_ CONFIG b0 b3 b3 b3 b3 b3 b3 b3 b3 b3 VFO1-b3 VFO3-b3 b3 b3 3 28h FIFO_LD_POSITION[12:0] 24h 23h 22h 21h 20h 1Fh 1Eh 1Dh 1Ch 1Bh 1Ah 19h 18h 17h 16h 15h FF_PIXEL_END_F1[12:0] FF_PIXEL_START_F1[12:0] FF_PIXEL_END_F0[12:0] FF_PIXEL_START_F0[12:0] AP_PIXEL_END_F1[12:0] AP_PIXEL_START_F1[12:0] AP_PIXEL_END_F0[12:0] AP_PIXEL_START_F0[12:0] FF_LINE_END_F1[10:0] FF_LINE_START_F1[10:0] FF_LINE_END_F0[10:0] FF_LINE_START_F0[10:0] AP_LINE_END_F1[10:0] AP_LINE_START_F1[10:0] AP_LINE_END_F0[10:0] AP_LINE_START_F0[10:0] 15 14 13 b12 b12 b12 b12 b12 b12 b12 b12 b12 12 GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 12h 13h 14h 25h ERROR_MASK_REGISTER 26h 27h Address Register Name Table 2-5: Host Interface Map (R/W registers) 2.4.1 Host Interface Map (R/W registers) b11 b11 b11 b11 b11 b11 b11 b11 b11 11 b10 b10 b10 b10 b10 b10 b10 b10 b10 b10 b10 b10 b10 b10 b10 b10 b10 10 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 b9 9 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 b8 8 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 b7 7 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 b6 VD_STD_ ERR_ MASK b6 6 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 b5 FF_CRC_ ERR_ MASK b5 5 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 b4 AP_CRC_ ERR_ MASK b4 4 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b3 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 CCS_ERR_ MASK b2 2 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 EAV_ERR _MASK b0 0 19 of 71 SAV_ERR_ MASK b1 1 Proprietary & Confidential LOCK_ ERR_ MASK b3 3 0Ch 0Bh 0Ah 09h 08h 07h 06h 05h 04h ANC_TYPE(3)[15:0] ANC_TYPE(2)[15:0] ANC_TYPE(1)[15:0] ANC_LINE_B[10:0] ANC_LINE_A[10:0] FIFO_FULL_OFFSET FIFO_EMPTY_OFFSET IO_CONFIG DATA_FORMAT 00h 01h 02h b15 b15 b15 b15 b15 15 b14 b14 b14 b14 b14 14 b13 b13 b13 b13 b13 13 ANC_ DATA_ SWITCH b12 b12 b12 b12 b12 12 EDH_ FLAG_ UPDATE STAT3_ CONFIG b2 ANC_ DATA_ DELETE b11 b11 b11 b11 b11 11 STAT3_ CONFIG b1 ANC_PKT _EXT STAT3_ CONFIG b0 b9 b9 b9 b9 b10 b10 b9 b9 b9 b9 b9 9 b10 b10 b10 b10 b10 10 GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 NOTE: Addresses 02Ch to 42Bh store the contents of the internal FIFO. The contents may be accessed in Ancillary Data Extraction mode (see Section 3.10.3). IOPROC_DISABLE 0Dh ANC_TYPE(4)[15:0] 03h 0Eh 0Fh 10h 11h Address ANC_TYPE(5)[15:0] Register Name Table 2-5: Host Interface Map (R/W registers) (Continued) FIFO_ MODE b1 STAT2_ CONFIG b2 b8 b8 b8 b8 b8 b8 b8 b8 b8 8 FIFO_ MODE b0 STAT2_ CONFIG b1 b7 b7 b7 b7 b7 b7 b7 b7 b7 7 H_ CONFIG STAT2_ CONFIG b0 b6 b6 b6 b6 b6 b6 b6 b6 b6 6 STAT1_ CONFIG b2 b5 b5 b5 b5 b5 b5 b5 b5 b5 5 STAT1_ CONFIG b1 b4 b4 b4 b4 b4 b4 b4 b4 b4 4 EDH_CRC _INS STAT0_ CONFIG b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 2 TRS_IN STAT0_ CONFIG b0 b0 b0 b0 b0 b0 b0 b0 b0 b0 0 20 of 71 ANC_ CSUM_ INS STAT0_ CONFIG b1 b1 b1 b1 b1 b1 b1 b1 b1 b1 1 Proprietary & Confidential ILLEGAL_ REMAP STAT1_ CONFIG b0 b3 b3 b3 b3 b3 b3 b3 b3 b3 3 13h 12h 11h RASTER_STRUCTURE3[12:0] RASTER_STRUCTURE2[12:0] RASTER_STRUCTURE1[10:0] 15 14 13 GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h Address RASTER_STRUCTURE4[10:0] Register Name b12 b12 12 Table 2-6: Host Interface Map (Read only registers) b11 b11 11 2.4.2 Host Interface Map (Read only registers) b9 b9 b9 9 b9 b10 b10 b10 10 b10 b8 b8 b8 b8 8 b7 b7 b7 b7 7 b6 b6 b6 b6 6 b5 b5 b5 b5 5 b4 b4 b4 b4 4 b3 b3 b3 b3 3 b1 b1 b1 b1 1 21 of 71 b0 b0 b0 b0 0 Proprietary & Confidential b2 b2 b2 b2 2 10h 0Fh VIDEO_FORMAT_OUT_B(4,3) VIDEO_FORMAT_OUT_A(2,1) 03h 02h 01h EDH_FLAG_OUT EDH_FLAG_IN ERROR_STATUS Not Used Not Used VFO2-b7 VFO4-b7 15 ANC-UES _IN ANC-UES VFO2-b6 VFO4-b6 14 ANC-IDA _IN ANC-IDA VFO2-b5 VFO4-b5 13 ANC-IDH _IN ANC-IDH VFO2-b4 VFO4-b4 12 ANC-EDA _IN ANC-EDA VFO2-b3 VFO4-b3 11 ANC-EDH _IN ANC-EDH AP_CRC_ V VFO2-b2 VFO4-b2 10 FF-UES_IN FF-UES FF_CRC_V VFO2-b1 VFO4-b1 9 GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 NOTE: Addresses 02Ch to 42Bh store the contents of the internal FIFO. The contents may be accessed in Ancillary Data Extraction mode (see Section 3.10.3). 00h 04h DATA_FORMAT 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh Address Register Name Table 2-6: Host Interface Map (Read only registers) (Continued) FF-IDA_IN FF-IDA EDH_ DETECT VFO2-b0 VFO4-b0 8 FF-IDH_IN FF-IDH VERSION_ 352M VFO1-b7 VFO3-b7 7 VD_STD_ ERR FF-EDA_I N FF-EDA VFO1-b6 VFO3-b6 6 FF_CRC_ ERR FF-EDH_I N FF-EDH VFO1-b5 VFO3-b5 5 AP_CRC_ ERR AP-UES_I N AP-UES STD_ LOCK VFO1-b4 VFO3-b4 4 CCS_ERR AP-IDH_I N AP-IDH DATA_ FORMAT b2 VFO1-b2 VFO3-b2 2 EAV_ERR AP-EDH_I N AP-EDH DATA_ FORMAT b0 VFO1-b0 VFO3-b0 0 22 of 71 SAV_ERR AP-EDA_I N AP-EDA DATA_ FORMAT b1 VFO1-b1 VFO3-b1 1 Proprietary & Confidential LOCK_ ERR AP-IDA_I N AP-IDA DATA_ FORMAT b3 VFO1-b3 VFO3-b3 3 3. Detailed Description · Functional Overview · Cable Equalization · Clock and Data Recovery · Serial-To-Parallel Conversion · Modes Of Operation · SMPTE Functionality · DVB-ASI Functionality · Data-Through Functionality · Additional Processing Features · Internal FIFO Operation · Parallel Data Outputs · Programmable Multi-Function Outputs · GS9091B GS9091B Low-latency Mode · GSPI Host Interface · JTAG operation · Device Power Up 3.1 Functional Overview The GS9091B GS9091B is a 270Mb/s equalizing and reclocking deserializer with an internal FIFO and programmable multi-function output port. The device has two basic modes of operation. In Auto mode, the GS9091B GS9091B can automatically detect SMPTE data streams at its input. In Manual mode, the device can be set to process SMPTE or DVB/ASI data streams. The digital signal processing core handles ancillary data detection/indication, error detection and handling (EDH), SMPTE352M SMPTE352M extraction, and automatic video standards detection. These features are all enabled by default, but may be individually disabled via internal registers accessible through the GSPI host interface. The provided programmable multi-function output pins may be configured to output various status signals including H, V, and F timing, ancillary data detection, EDH detection, and a FIFO load pulse. The internal FIFO supports 4 modes of operation, which may be used for data alignment, data delay, MPEG packet extraction, or ancillary data extraction. The GS9091B GS9091B contains a JTAG interface for boundary scan test implementations. GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 23 of 71 Proprietary & Confidential 3.2 Cable Equalization The input signal passes through a variable gain equalizing stage whose frequency response closely matches the inverse of the cable loss characteristic. The serial data signal may be connected to the input pins (SDI/SDI) in either a differential or single ended configuration. AC coupling of the inputs is recommended, as the SDI and SDI inputs are internally biased at approximately 1.8V. The cable equalization block is powered by the EQ_VDD and EQ_GND pins. The cable equalizer can be bypassed by setting the EQ_BYPASS pin HIGH. 3.3 Clock and Data Recovery The GS9091B GS9091B contains an integrated clock and data recovery block. The function of this block is to lock to the input data stream, extract a clean clock, and retime the serial digital data to remove high frequency jitter. The operating centre frequency of the reclocker is 270Mb/s. 3.3.1 Internal VCO and Phase Detector The GS9091B GS9091B uses an internal VCO and PFD as part of the reclocker's phase-locked loop. Each block requires a +1.8V DC power supply, which is supplied via the VCO_VDD / VCO_GND and PLL_VDD / PLL_GND pins. 3.4 Serial-To-Parallel Conversion The function of this block is to extract 10-bit parallel data words from the reclocked serial data stream and simultaneously present them to the SMPTE and DVB-ASI word alignment blocks. 3.5 Modes Of Operation The GS9091B GS9091B has two basic modes of operation: Auto mode and Manual mode. Auto mode is enabled when AUTO/MAN is set HIGH, and Manual mode is enabled when AUTO/MAN is set LOW. As indicated in Figure 3-1. DVB_ASI and data through are only supported in Manual mode. In Auto mode (AUTO/MAN = HIGH), the GS9091B GS9091B will automatically detect, equalize, reclock, deserialize, and process SMPTE 259M-C 259M-C input data. In Manual mode (AUTO/MAN = LOW), the SMPTE_BYPASS and DVB_ASI pins must be set as per Table 3-2 for the correct reception of either SMPTE or DVB-ASI data. Manual mode also supports the equalizing, reclocking and deserializing of 270Mb/s data not conforming to SMPTE or DVB-ASI streams. GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 24 of 71 Proprietary & Confidential Auto Mode (Section 3.6.2) GS9091 GS9091 SMPTE Functionality (section 3.7) SMPTE Functionality (section 3.7) Manual Mode (Section 3.6.3) DVB-ASI Functionality (section 3.8) Data-Through Functionality (Section 3.9) Figure 3-1: GS9091B GS9091B's Modes of Operation 3.5.1 Lock Detect Once the reclocker has locked to the received serial digital data stream, the lock detect block of the GS9091B GS9091B searches for the appropriate sync words, and indicates via the LOCKED output pin when the device has successfully achieved lock. The LOCKED pin is designed to be stable. It will not toggle during the locking process, nor will it glitch during a SMPTE synchronous switch. The lock detection process is summarized in Figure 3-2. GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 25 of 71 Proprietary & Confidential Power Up or RESET Valid Serial Digital Input? Device sets LOCKED pin LOW NO (Input data invalid) YES Device in Auto Mode? (Section 3.6.2) (Device in Manual Mode) YES Internal reclocker locked? NO Device sets SMPTE_BYPASS pin LOW Device outputs 27MHz +/- 7% clock on PCLK pin YES NO SMPTE TRS words detected? NO Device sets all other output pins LOW YES SMPTE_BYPASS and DVB_ASI pins must be set to support different functionalities (Section 3.6.3). Device sets LOCKED pin HIGH Device sets SMPTE_BYPASS status pin (Section 3.6.2) Device outputs accurate 27MHz clock on PCLK pin Figure 3-2: Lock Detection Process The lock detection algorithm (Figure 3-2) first determines if the input is a 270Mb/s serial digital data stream. When the serial data input signal is considered invalid, the LOCKED pin will be set LOW, and all device outputs will be forced LOW, except PCLK. If a valid serial digital input signal has been detected, and the device is in Auto mode, the lock algorithm will attempt to detect the presence of SMPTE TRS words. Assuming that a valid 270Mb/s SMPTE signal has been applied to the device, the LOCKED pin will be set HIGH. GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 26 of 71 Proprietary & Confidential For serial inputs that do not conform to SMPTE or DVB-ASI formats, the device can achieve the locked state in manual mode. In Auto mode, the LOCKED signal will be asserted LOW, the parallel outputs will be latched to logic LOW, and the SMPTE_BYPASS output signal will also be set LOW. In Manual mode, the SMPTE_BYPASS and DVB_ASI input pins must be set LOW. If the GS9091B GS9091B achieves lock to the input data signal, data will be passed directly to the parallel outputs without any further processing (see Section 3.8). 3.5.2 Auto Mode The GS9091B GS9091B is in Auto mode when the AUTO/MAN input pin is set HIGH. In this mode, SMPTE_BYPASS becomes an output status pin, as shown in Table 3-1. Table 3-1: Auto Mode Output Status Signals Pin Settings Format SMPTE_BYPASS SD SMPTE HIGH NOT SMPTE LOW 3.5.3 Manual Mode The GS9091B GS9091B is in Manual mode when the AUTO/MAN input pin is set LOW. In this mode, the SMPTE_BYPASS and DVB_ASI pins become input signals, and the operating mode of the device is set by these pins as shown in Table 3-2 . Table 3-2: Manual Mode Input Status Signals Pin Settings Format SMPTE_BYPASS DVB_ASI SD SMPTE HIGH LOW DVB-ASI X HIGH NOT SMPTE OR DVB-ASI (Data-Through mode)* LOW LOW *NOTE: See Section 3.8 for more detail on Data-Through mode GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 27 of 71 Proprietary & Confidential 3.6 SMPTE Functionality The GS9091B GS9091B is in SMPTE mode once the device has detected two SMPTE TRS sync words. The GS9091B GS9091B will remain in SMPTE mode until six SMPTE TRS sync words fail to be detected. TRS word detection is a continuous process, and the device will identify both 8-bit and 10-bit TRS words. In Auto mode, the GS9091B GS9091B sets the SMPTE_BYPASS pin HIGH to indicate that it has locked to a SMPTE input data stream. When operating in Manual mode, the DVB_ASI pin must be set LOW and the SMPTE_BYPASS pin must be set HIGH in order to enable SMPTE operation. 3.6.1 SMPTE Descrambling and Word Alignment The GS9091B GS9091B performs NRZI-to-NRZ decoding, descrambling according to SMPTE 259M-C 259M-C, and word alignment of the data to the TRS sync words when in SMPTE mode. NOTE: When 8-bit data is embedded into the SMPTE signal, the source must have the two LSBs of the 10-bit stream set to logic LOW in order for word alignment to function correctly. 3.6.2 Internal Flywheel The GS9091B GS9091B has an internal flywheel for the generation of internal / external timing signals, the detection and correction of certain error conditions, and the automatic detection of video standards. The flywheel is only operational in SMPTE mode. The flywheel 'learns' the video standard by timing the horizontal and vertical reference information contained in the TRS ID words of the received video stream. The flywheel maintains information about the total line length, active line length, total number of lines per field / frame, and total active lines per field / frame for the received video stream. Full synchronization of the flywheel to the received video standard therefore requires one complete video frame. Once synchronization has been achieved, the flywheel will continue to monitor the received TRS timing information to maintain synchronization. The FW_EN input pin controls the synchronization mechanism of the flywheel. When this input signal is LOW, the flywheel will re-synchronize all pixel and line based counters on every received TRS ID word. When FW_EN is set to logic HIGH, re-synchronization occurs when the flywheel detects three to four consecutive video lines containing mistimed TRS information. This provides a measure of noise immunity to internal and external timing signal generation. The flywheel will be disabled if the device loses lock, or a LOW-to-HIGH transition occurs on the RESET pin. GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 28 of 71 Proprietary & Confidential 3.6.3 Switch Line Lock Handling The principle of switch line lock handling is that the switching of synchronous video sources will only disturb the horizontal timing and alignment of the stream, whereas the vertical timing remains in synchronization. 3.6.3.1 Automatic Switch Line Lock Handling The GS9091B GS9091B also implements automatic switch line lock handling. By utilizing both the synchronous switch point defined in SMPTE RP168 RP168, and the automatic video standards detect function, the device automatically re-synchronizes the flywheel at the switch point. This will occur whether or not the device has detected TRS word errors. Word alignment re-synchronization will also take place at this time. Automatic switch line lock handling will occur regardless of the setting of the FW_EN pin. The switch line is defined as follows: · for 525 line interlaced systems: re-sync takes place at the end of lines 10 & 273 · for 625 line interlaced systems: re-sync takes place at the end of lines 6 & 319 A full list of 270Mb/s video standards and switching lines is shown in Table 3-3. At every PCLK cycle the device samples the FW_EN pin. When the FW_EN pin is set LOW anywhere within the active line, the flywheel will re-synchronize immediately to the next TRS word. 3.6.3.2 Manual Switch Line Lock Handling The ability to manually re-synchronize the flywheel is also important when switching asynchronous sources or to implement other non-standardized video switching functions. To account for the horizontal disturbance caused by a synchronous switch, it is necessary to re-synchronize the flywheel immediately after the switch has taken place. Rapid re-synchronization of the GS9091B GS9091B to the new video standard can be achieved by disabling the flywheel (setting the FW_EN pin to logic LOW) after the switch, and re-enabling the flywheel after the next TRS word. Table 3-3: Switch Line Position for 270MB/s Digital Systems System Video Format Sampling Signal Standard Parallel Interface Serial Interface Switch Line Number SDTI 720x576/50 (2:1) 4:2:2 BT.656 BT.656 + 305M 259M-C 259M-C 6, 319 720x483/59.94 (2:1) 4:2:2 125M 125M + 305M 259M-C 259M-C 10, 273 525 720x483/59.94 (2:1) 4:2:2 125M 125M 259M-C 259M-C 10, 273 625 720x576/50 (2:1) 4:2:2 BT.656 125M 259M-C 259M-C 6, 319 GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 29 of 71 Proprietary & Confidential 3.6.4 HVF Timing Signal Generation The GS9091B GS9091B extracts timing parameters, and outputs them to the F, V and H pins, from either the received TRS signals (FW_EN = LOW) or from the internal flywheel-timing generator (FW_EN = HIGH). Horizontal blanking period (H), vertical blanking period (V), and field odd / even timing (F) are extracted and are available for output on any of the multi-function output port pins, if so programmed (see Section 3.12). The H signal timing is configurable via the H_CONFIG bit of the internal IOPROC_DISABLE register as either active line-based blanking, or TRS-based blanking (see Table 3-14 in Section 3.9.8). Active line-based blanking is enabled when the H_CONFIG bit is set LOW. In this mode, the H output is HIGH for the entire horizontal blanking period, including the EAV and SAV TRS words. This is the default H timing used by the device. When H_CONFIG is set HIGH, TRS based blanking is enabled. In this case, the H output will be HIGH for the entire horizontal blanking period as indicated by the H bit in the received TRS ID words. The timing of these signals is shown in Figure 3-3. NOTE 1: When the internal FIFO is configured for video mode, the H, V, and F signals will be timed to the data output from the FIFO (see Section 3.10.1). NOTE 2: When the GS9091B GS9091B is configured for Low-latency mode, the H, V, and F output timing will be TRS-based as shown in Section 3.13. Active line-based timing is not available in this mode, and the setting of the H_CONFIG host interface bit will be ignored. PCLK Y/Cr/Cb DATA OUT 3FF 000 000 XYZ (eav) 3FF 000 000 XYZ (sav) H V F H SIGNAL TIMING: H_CONFIG = LOW H_CONFIG = HIGH Figure 3-3: H,V,F Timing GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 30 of 71 Proprietary & Confidential 3.7 DVB-ASI Functionality DVB_ASI functionality is only supported in Manual mode. In Manual mode, the DVB_ASI pin must be set to logic HIGH in order to enable DVB-ASI operation. The SMPTE_BYPASS pin will be ignored. When using DVB-ASI mode, the use of application circuit in Figure 3-4 on page 31 is suggested. The use of this application circuit will prevent the internal PLL from false locking to a DVB-ASI signal harmonic rather than the 270MHz fundamental. This application circuit will detect the false lock state and restart the on-chip PLL. The application circuit does this by detecting if the LOCK has been de-asserted for longer than ~700s, and if so resets the PLL by discharging the loop filter capacitor through a CMOS switch. The applications circuit below show how this can be implemented by using a STG719 STG719 switch as a reference. Other low leakage CMOS switches may also be substituted within the circuit. STG719 STG719 1 In 1 6 5 D 4 S1 LF- S2 2 LF+ 6 5 GS9090B GS9090B GS9091B GS9091B RESTART_PLL 3 STG719 STG719 LOCKED OUT IN FPGA or Microcontroller GPIO Figure 3-4: GS9091B GS9091B False Lock Restart Circuit The circuit above can be implemented using either a small state machine in an FPGA or general purpose I/O on a microcontroller in combination with some firmware. Typically, a system using the GS9091B GS9091B will have an existing FPGA and/or microcontroller that may have some spare I/O that can be used to implement the false lock restart circuit. The choice of method will depend on what spare system resources are available. In either case, the waveform shown in Figure 3-5 on page 31 represents how the PLL restart must be driven. The delay values of 700s and 20s are nominal but the values can be longer. In the case where the SDI inputs are not driven with a valid DVB-ASI signal, the RESTART_PLL signal should be repeated indefinitely as long as LOCKED remains de-asserted. DDI VALID DVB-ASI INPUT SIGNAL VALID DVB-ASI INPUT SIGNAL POWER_OK LOCKED RESTART_PLL ~700µs ~20µs ~700µs ~20µs Figure 3-5: GS9091B GS9091B False Lock Restart Circuit Waveforms of False Lock After Power-up and False Lock After a Signal Switch. GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 31 of 71 Proprietary & Confidential 3.7.1 DVB-ASI 8b/10b Decoding The GS9091B GS9091B will word align the data to the K28.5 sync characters, and 8b/10b decode and bit-swap the data to achieve bit alignment with the data outputs. NOTE: DVB-ASI sync words must be immediately followed by an MPEG packet header for word alignment to correctly function. The extracted 8-bit data will be presented to DOUT [7:0], bypassing all internal SMPTE mode data processing. 3.7.2 Status Signal Outputs In DVB-ASI mode, the DOUT9 and DOUT8 pins will be configured as DVB-ASI status signals WORDERR and SYNCOUT respectively. SYNCOUT will be HIGH whenever a K28.5 sync character is present on the output. WORDERR will be HIGH whenever the device has detected an illegal 8b/10b code word or there is a running disparity error. 3.8 Data-Through Functionality The GS9091B GS9091B may be configured to operate as a simple serial-to-parallel converter. In this mode, the data is output to the parallel output without performing any decoding, descrambling, or word-alignment. Data-Through functionality is enabled when the AUTO/MAN, SMPTE_BYPASS, and DVB_ASI input pins are set to logic LOW. Under these conditions, the GS9091B GS9091B allows 270Mb/s input data not conforming to SMPTE or DVB-ASI streams to be reclocked and deserialized. If the device is in Data-Through mode, and the reclocker locks to the data stream, the LOCKED pin will be representative of the serial digital input data frequency. GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 32 of 71 Proprietary & Confidential 3.9 Additional Processing Features The GS9091B GS9091B contains additional processing features that are available in SMPTE mode only (see Section 3.6). 3.9.1 FIFO Load Pulse To aid in the implementation of auto-phasing and line synchronization functions, the GS9091B GS9091B will generate a FIFO load pulse to reset line-based FIFO storage. This FIFO_LD signal is available for output on one of the multi-function output port pins, if so programmed (see Section 3.12). The FIFO_LD pulse is an active LOW signal which will assert LOW for one PCLK period, generating a FIFO write reset signal. This signal is co-timed to the SAV XYZ code word present on the output data bus. This ensures that the next PCLK cycle will correspond with the first active sample of the video line. NOTE: When the internal FIFO of the GS9091B GS9091B is set to operate in video mode, the FIFO_LD pulse can be used to drive the RD_RESET input to the device (see Section 3.10.1). Figure 3-6 shows the default timing relationship between the FIFO_LD signal and the output video data. PCLK Y'CbCr DATA 3FF 000 000 XYZ FIFO_LD Figure 3-6: FIFO_LD Pulse Timing 3.9.1.1 Programmable FIFO Load Position The position of the FIFO_LD pulse can be moved in PCLK increments from its default position at the SAV XYZ code word to a maximum of one full line from the default position. The offset number of PCLK's must be programmed in the FIFO_LD_POSITION[12:0] internal register (address 28h), via the host interface. The FIFO_LD_POSITION[12:0] register is designed to accommodate the longest SD line length. If a value greater than the maximum line length at the operating SD standard is programmed in this register, the FIFO_LD pulse will not be generated. After a device reset, the FIFO_LD_POSITION[12:0] register is set to zero and the FIFO_LD pulse will assume the default timing. GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 33 of 71 Proprietary & Confidential 3.9.2 Ancillary Data Detection and Indication The GS9091B GS9091B will detect all types of ancillary data in either the vertical or horizontal data spaces. The ANC status signal is provided to indicate the position of ancillary data in the output data stream. This signal is available for output on the multi-function output port pins (see Section 3.12). The ANC status signal is synchronous with PCLK and can be used as a clock enable to external logic, or as a write enable to an external FIFO or other memory device. The ANC signal will be asserted HIGH whenever ancillary data is detected in the video data stream (see Figure 3-7). Both 8-bit and 10-bit ancillary data preambles will be detected by the GS9091B GS9091B. NOTE: When the internal FIFO is configured for video mode, the ANC signal will be timed to the data output from the FIFO (see Section 3.10.1). PCLK Y'CbCr DATA 000 3FF 3FF DID DBN DC ANC DATA ANC DATA CSUM BLANK ANC Figure 3-7: ANC Status Signal 3.9.2.1 Programmable Ancillary Data Detection The GS9091B GS9091B will detect all types of ancillary data by default. In addition, up to five different ancillary data types can be programmed for detection. This is accomplished by programming the ANC_TYPE registers with the DID and/or SDID values, via the host interface, for each data type to be detected (see Table 3-4). The GS9091B GS9091B will compare the received DID and/or SDID with the programmed values and assert ANC only if an exact match is found. If the DID or SDID values are set to zero in the ANC_TYPE register, a comparison or match for that codeword will not be made. For example, if the DID is programmed but the SDID is set to zero, the device will detect all ancillary data types matching the DID value, regardless of the SDID. If both DID and SDID values are non-zero, then the received ancillary data type must match both the DID and SDID cases before the device will assert ANC HIGH. In the case where all five DID and SDID values are set to zero, the GS9091B GS9091B will detect all ancillary data types. This is the default setting after a device reset. If greater than one, but less than five, DID and/or SDID values have been programmed, then only those matching ancillary data types will be detected and indicated. NOTE: See SMPTE 291M for a definition of ancillary data terms. GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 34 of 71 Proprietary & Confidential Table 3-4: Host Interface Description for Programmable Ancillary Data Type registers Register Name Bit Name Description R/W Default ANC_TYPE 1 Address: 0Ah 15-8 ANC_TYPE1[15:8] Used to program the DID for ancillary data detection at ANC output R/W 0 7-0 ANC_TYPE1[7:0] Used to program the SDID for ancillary data detection at ANC output. Should be set to zero if no SDID is present in the ancillary data packet to be detected. R/W 0 15-8 ANC_TYPE2[15:8] Used to program the DID for ancillary data detection at ANC output R/W 0 7-0 ANC_TYPE2[7:0] Used to program the SDID for ancillary data detection at ANC output. Should be set to zero if no SDID is present in the ancillary data packet to be detected. R/W 0 15-8 ANC_TYPE3[15:8] Used to program the DID for ancillary data detection at ANC output R/W 0 7-0 ANC_TYPE3[7:0] Used to program the SDID for ancillary data detection at ANC output. Should be set to zero if no SDID is present in the ancillary data packet to be detected. R/W 0 15-8 ANC_TYPE4[15:8] Used to program the DID for ancillary data detection at ANC output R/W 0 7-0 ANC_TYPE4[7:0] Used to program the SDID for ancillary data detection at ANC output. Should be set to zero if no SDID is present in the ancillary data packet to be detected. R/W 0 15-8 ANC_TYPE5[15:8] Used to program the DID for ancillary data detection at ANC output R/W 0 7-0 ANC_TYPE5[7:0] Used to program the SDID for ancillary data detection at ANC output. Should be set to zero if no SDID is present in the ancillary data packet to be detected. R/W 0 ANC_TYPE 2 Address: 0Bh ANC_TYPE 3 Address: 0Ch ANC_TYPE 4 Address: 0Dh ANC_TYPE 5 Address: 0Eh 3.9.3 EDH Packet Detection The GS9091B GS9091B will determine if EDH packets are present in the incoming video data and assert the EDH_DETECT output status signal appropriately. EDH_DETECT will be set HIGH when EDH packets have been detected and will remain HIGH until EDH packets are no longer present. The signal will be set LOW at the end of the vertical blanking (falling edge of V) if an EDH packet has not been received and detected during vertical blanking. EDH_DETECT can be programmed to be available for output on the multi-function output port pins (see Section 3.12). The EDH_DETECT bit is also available in the DATA_FORMAT register at address 04h (see Table 3-7). GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 35 of 71 Proprietary & Confidential 3.9.4 EDH Flag Detection As described in Section 3.9.3, the GS9091B GS9091B can detect EDH packets in the received data stream. The EDH flags for ancillary data, active picture, and full field areas are extracted from the detected EDH packets and placed in the EDH_FLAG_IN register at address 02h (Table 3-5). When the EDH_FLAG_UPDATE bit in the DATA_FORMAT register 04h (Table 3-7) is set HIGH, the GS9091B GS9091B will update the ancillary data, full field, and active picture EDH flags according to SMPTE RP165 RP165. The updated EDH flags are available in the EDH_FLAG_OUT register at address 03h (Table 3-6). The EDH packet output from the device will contain the updated flags. One set of flags is provided for both fields 1 and 2. Field 1 flag data will be overwritten by field 2 flag data. When EDH packets are not detected, the UES flags in the EDH_FLAG_OUT register will be set HIGH to signify that the received signal does not support Error Detection and Handling. In addition, the EDH_DETECT bit will be set LOW. These flags are set regardless of the setting of the EDH_FLAG_UPDATE bit. EDH_FLAG_OUT and EDH_FLAG_UPDATE may be read by the host interface at any time during the received frame except on the lines defined in SMPTE RP165 RP165, where these flags are updated. The GS9091B GS9091B will indicate the CRC validity for both active picture and full field CRCs. The AP_CRC_V bit in the DATA_FORMAT register indicates the active picture CRC validity, and the FF_CRC_V bit indicates the full field CRC validity (see Table 3-7). When EDH_DETECT = LOW, these bits will be cleared. The EDH_FLAG_OUT and EDH_FLAG_UPDATE register values remain set until overwritten by the decoded flags in the next received EDH packet in the following field. When an EDH packet is not detected during vertical blanking, the flag registers will be cleared at the end of the vertical blanking period. GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 36 of 71 Proprietary & Confidential Table 3-5: Host Interface Description for EDH Flag Registers Register Name Bit Name Description EDH_FLAG_IN 15 ­ 14 Default Not Used ­ ­ ANC-UES_IN Ancillary Unknown Error Status Flag R 0 13 ANC-IDA_IN Ancillary Internal device error Detected Already Flag. R 0 12 ANC-IDH_IN Ancillary Internal device error Detected Here Flag. R 0 11 ANC-EDA_IN Ancillary Error Detected Already Flag. R 0 10 ANC-EDH_IN Ancillary Error Detected Here Flag. R 0 9 FF-UES_IN Full Field Unknown Error Status Flag. R 0 8 FF-IDA_IN Full Field Internal device error Detected Already Flag. R 0 7 FF-IDH_IN Full Field Internal device error Detected Here Flag. R 0 6 FF-EDA_IN Full Field Error Detected Already Flag. R 0 5 FF-EDH_IN Full Field Error Detected Here Flag. R 0 4 AP-UES_IN Active Picture Unknown Error Status Flag. R 0 3 AP-IDA_IN Active Picture Internal device error Detected Already Flag. R 0 2 AP-IDH_IN Active Picture Internal device error Detected Here Flag R 0 1 AP-EDA_IN Active Picture Error Detected Already Flag. R 0 0 Address: 02h R/W AP-EDH_IN Active Picture Error Detected Here Flag. R 0 GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 37 of 71 Proprietary & Confidential Table 3-6: Host Interface Description for EDH Flag Registers Register Name Bit Name Description EDH_FLAG_OUT 15 ­ 14 Default Not Used ­ ­ ANC-UES Ancillary Unknown Error Status Flag R 0 13 ANC-IDA Ancillary Internal device error Detected Already Flag. R 0 12 ANC-IDH Ancillary Internal device error Detected Here Flag. R 0 11 ANC-EDA Ancillary Error Detected Already Flag. R 0 10 ANC-EDH Ancillary Error Detected Here Flag. R 0 9 FF-UES Full Field Unknown Error Status Flag. R 0 8 FF-IDA Full Field Internal device error Detected Already Flag. R 0 7 FF-IDH Full Field Internal device error Detected Here Flag. R 0 6 FF-EDA Full Field Error Detected Already Flag. R 0 5 FF-EDH Full Field Error Detected Here Flag. R 0 4 AP-UES Active Picture Unknown Error Status Flag. R 0 3 AP-IDA Active Picture Internal device error Detected Already Flag. R 0 2 AP-IDH Active Picture Internal device error Detected Here Flag R 0 1 AP-EDA Active Picture Error Detected Already Flag. R 0 0 Address: 03h R/W AP-EDH Active Picture Error Detected Here Flag. R 0 GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 38 of 71 Proprietary & Confidential Table 3-7: Host Interface Description for Data Format Register Register Name Description 15-12 ­ Not Used 11 EDH_FLAG_UPDATE When set HIGH by the application layer, the device will update the ancillary data, full field, and active picture EDH flags according to SMPTE RP165 RP165. AP_CRC_V 9 R/W Default ­ ­ R/W 0 Active Picture CRC Valid bit. R 0 FF_CRC_V Full Field CRC Valid bit. R 0 8 EDH_DETECT Set HIGH by the device when EDH packets are detected in the incoming video data. R 0 7 VERSION_352M Indicates whether decoded SMPTE 352M packet is version 0 or version 1. See Section 3.9.5. R 0 6-5 ­ Not Used ­ ­ 4 STD_LOCK Standard Lock bit. This bit will be set HIGH when the flywheel has achieved full synchronization to the received video standard. See Section 3.9.6. R 0 3-0 Address: 04h Name 10 DATA_FORMAT Bit DATA_FORMAT[3:0] Displays the data format being carried on the serial digital interface. See Section 3.9.6.1. R 0 3.9.5 SMPTE 352M Payload Identifier The GS9091B GS9091B can receive and detect the presence of the SMPTE 352M payload identifier. Upon detection of this packet, the device will extract the four words contained in the packet to the VIDEO_FORMAT_OUT_A and VIDEO_FORMAT_OUT_B registers at addresses 10h and 0fh (Table 3-8). The device will also indicate the version of the payload packet in bit 7 of the DATA_FORMAT register (Table 3-7). When bit 7 is set HIGH the received SMPTE 352M packet is version 1, otherwise it is version 0. The VIDEO_FORMAT registers will only be updated if the received checksum is the same as the locally calculated checksum. If the device loses lock to the input data stream (LOCKED = LOW), or if the SMPTE_BYPASS pin is asserted LOW, the VIDEO_FORMAT_OUT_A and VIDEO_FORMAT_OUT_B registers will be cleared to zero, indicating an undefined format. This is also the default setting after a device reset. GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 39 of 71 Proprietary & Confidential Table 3-8: Host Interface Description for SMPTE 352M Payload Identifier Registers Register Name Bit Name Description VIDEO_FORMAT_OUT_B Address: 10h 15-8 SMPTE 352M Byte 4 7-0 Default Data will be available in this register when Video Payload Identification Packets are detected in the data stream. R 0 SMPTE 352M Byte 3 Data will be available in this register when Video Payload Identification Packets are detected in the data stream. R 0 15-8 SMPTE 352M Byte 2 Data will be available in this register when Video Payload Identification Packets are detected in the data stream. R 0 7-0 VIDEO_FORMAT_OUT_A Address: 0Fh R/W SMPTE 352M Byte 1 Data will be available in this register when Video Payload Identification Packets are detected in the data stream. R 0 3.9.6 Automatic Video Standard and Data Format Detection The GS9091B GS9091B can detect the input video standard and data format by using the timing parameters extracted from the received TRS ID. Total samples per line, active samples per line, total lines per frame, and active lines per field are all calculated and presented to the host interface via the RASTER_STRUCTURE registers (Table 3-9). Also associated with the RASTER_STRUCTURE registers is the STD_LOCK status bit. The GS9091B GS9091B will set STD_LOCK HIGH when the flywheel has achieved full synchronization to the received video standard. STD_LOCK is stored in the DATA_FORMAT register (Table 3-7). The four RASTER_STRUCTURE registers, as well as the STD_LOCK status bit will default to zero after a device reset, or if the device loses lock to the input data stream (LOCKED = LOW). Table 3-9: Host Interface Description for Raster Structure Registers Register Name Bit Name Description RASTER_STRUCTURE1 Address: 11h 15-11 ­ 10-0 ­ ­ RASTER_STRUCTURE1[10:0] Total Lines Per Frame R 0 15-13 ­ Not Used ­ ­ RASTER_STRUCTURE2[12:0] Total Words Per Line R 0 15-13 ­ Not Used ­ ­ RASTER_STRUCTURE3[12:0] Words Per Active Line R 0 15-11 ­ Not Used ­ ­ 10-0 RASTER_STRUCTURE4 Address: 14h Not Used 12-0 RASTER_STRUCTURE3 Address: 13h Default 12-0 RASTER_STRUCTURE2 Address: 12h R/W RASTER_STRUCTURE4[10:0] Active Lines Per Field R 0 GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 40 of 71 Proprietary & Confidential 3.9.6.1 Data Format Indication The GS9091B GS9091B can extract the data format being carried on the serial digital interface (i.e. SDTI, SDI, or DVB-ASI). This information is represented by bits 0 to 3 of the DATA_FORMAT register (Table 3-7). DATA_FORMAT[3:0] register codes are shown in Table 3-10. The DATA_FORMAT[3:0] register defaults to Fh (undefined) after a system reset. The register will also be set to its default value if the device is not locked (LOCKED = LOW), or if both SMPTE_BYPASS and DVB_ASI pins are LOW. Table 3-10: Data Format Register Codes Data Format[3:0] Data Format Applicable Standards 0h SDTI DVCPRO - No ECC SMPTE 321M 1h SDTI DVCPRO - ECC SMPTE 321M 2h SDTI DVCAM SMPTE 322M 3h SDTI CP SMPTE 326M 4h Other SDTI fixed block size ­ 5h Other SDTI variable block size ­ 6h SDI ­ 7h DVB-ASI ­ 8h ~ Eh Reserved ­ Unknown data format ­ Fh 3.9.7 Error Detection and Indication The GS9091B GS9091B contains a number of error detection functions to enhance operation of the device when operating in SMPTE mode. These functions, except lock error detection, will not be available in DVB-ASI mode (Section 3.7) or Data-Through mode (Section 3.8). The ERROR_STATUS register is at address 01h (Table 3-11). All bits, except the LOCK_ERR bit, will be cleared at the start of each video field or when read by the host interface, whichever condition occurs first. All bits, with the exception of the LOCK_ERR, will also be cleared if a change in the video standard is detected, if the device loses lock to the input data stream (LOCKED = LOW), or if the SMPTE_BYPASS pin is asserted LOW. The ERROR_STATUS register, including the LOCK_ERR bit, will be set LOW during a system reset (RESET = LOW). GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 41 of 71 Proprietary & Confidential The ERROR_MASK register (Table 3-12) is available to indivudally mask each error type in the ERROR_STATUS register. Each error type may be individually masked by setting its corresponding bit HIGH. The bits of the ERROR_MASK register will default to '0' after a device reset, thus allowing all error types to be detected. The DATA_ERROR signal pin indicates the status of the ERROR_STATUS register. This output pin is an inverted logical OR of each error status flag stored in the ERROR_STATUS register. DATA_ERROR will be set LOW by the device when an error condition that has not been masked is detected. Table 3-11: Host Interface Description for Error Status Register Register Name Bit Name Description ERROR_STATUS 15-7 ­ 6 Default Not Used ­ ­ VD_STD_ERR Video Standard Error Flag. Set HIGH when a mismatch between the received SMPTE 352M packets (version 1 or version 0) and the calculated video standard occurs. R 0 5 FF_CRC_ERR Full Field CRC Error Flag. Set HIGH when a Full Field (FF) CRC mismatch has been detected in Field 1 or 2 R 0 4 AP_CRC_ERR Active Picture CRC Error Flag. Set HIGH when an Active Picture (AP) CRC mismatch has been detected in Field 1 or 2. R 0 3 LOCK_ERR Lock Error Flag. Set HIGH whenever the LOCKED pin is LOW (indicating the device is not correctly locked). R 0 2 CS_ERR Checksum Error Flag. Set HIGH when ancillary data packet checksum error has been detected. R 0 1 SAV_ERR Start of Active Video Error Flag. Set HIGH when TRS errors are detected in either 8-bit or 10-bit TRS words. R 0 0 Address: 01h R/W EAV_ERR End of Active Video Error Flag. Set HIGH when TRS errors are detected in either 8-bit or 10-bit TRS words. R 0 GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 42 of 71 Proprietary & Confidential Table 3-12: Host Interface Description for Error Mask Register Register Name Bit Name Description ERROR_MASK 15-7 ­ Not Used 6 VD_STD_ERR_MASK Default ­ ­ Video Standard Error Flag Mask bit. R/W 0 FF_CRC_ERR_MASK Full Field CRC Error Flag Mask bit. R/W 0 4 AP_CRC_ERR_MASK Active Picture CRC Error Flag Mask bit R/W 0 3 LOCK_ERR_MASK Lock Error Flag Mask bit. R/W 0 2 CS_ERR_MASK Checksum Error Flag Mask bit. R/W 0 1 SAV_ERR_MASK Start of Active Video Error Flag Mask bit. R/W 0 0 Address: 25h R/W EAV_ERR_MASK End of Active Video Error Flag Mask bit. R/W 0 5 3.9.7.1 Video Standard Error Detection If a mismatch between the decoded SMPTE 352M packets and the calculated video standard occurs, the GS9091B GS9091B will indicate a video standard error by setting the VD_STD_ERR bit of the ERROR_STATUS register HIGH. The device will detect errors in both version 1 and version 0 352M packets. 3.9.7.2 EDH CRC Error Detection The GS9091B GS9091B calculates the Full Field (FF) and Active Picture (AP) CRC words according to SMPTE RP165 RP165 in support of Error Detection and Handling packets in SD signals. These calculated CRC values are compared with the received CRC values. If a mismatch is detected, the error is flagged in the AP_CRC_ERR and/or FF_CRC_ERR bits of the ERROR_STATUS register. These two flags are shared between fields 1 and 2. The AP_CRC_ERR bit will be set HIGH when an active picture CRC value mismatch has been detected in field 1 or 2. The FF_CRC_ERR bit will be set HIGH when a full field CRC value mismatch has been detected in field 1 or 2. EDH CRC errors will only be indicated when the device has correctly received EDH packets. SMPTE RP165 RP165 specifies the calculation ranges and scope of EDH data for standard 525 and 625 component digital interfaces. The GS9091B GS9091B will utilize these standard ranges by default. If the received video format does not correspond to 525 or 625 digital component video standards as determined by the flywheel pixel and line counters, the ranges will be based on the line and pixel ranges programmed by the host interface. In the absence of user-programmed calculation ranges, the ranges will be determined from the received TRS timing information. The registers available to the host interface for programming EDH calculation ranges include active picture and full field line/pixel start and end positions for both fields (Table 3-13). These registers default to '0' after a device reset. GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 43 of 71 Proprietary & Confidential If any or all of these register values are zero, then the EDH CRC calculation ranges will be determined from the flywheel generated timing. The first active and full field pixel will always be the first pixel after the SAV TRS code word. The last active and full field pixel will always be the last pixel before the start of the EAV TRS code words. Table 3-13: Host Interface Description for EDH Calculation Range Registers Register Name Bit Name Description AP_LINE_START_F0 Address: 15h 15-11 ­ Not Used 10-0 AP_LINE_START_F0[10:0] Field 0 Active Picture start line data used to set EDH calculation range outside of SMPTE RP 165 values. 15-11 ­ Not Used 10-0 AP_LINE_END_F0[10:0] Field 0 Active Picture end line data used to set EDH calculation range outside of SMPTE RP 165 values. 15-11 ­ Not Used 10-0 AP_LINE_START_F1[10:0] Field 1 Active Picture start line data used to set EDH calculation range outside of SMPTE RP 165 values. 15-11 ­ Not Used 10-0 AP_LINE_END_F1[10:0] Field 1 Active Picture end line data used to set EDH calculation range outside of SMPTE RP 165 values. 15-11 ­ Not Used 10-0 FF_LINE_START_F0[10:0] Field 0 Full Field start line data used to set EDH calculation range outside of SMPTE RP 165 values. 15-11 ­ Not Used 10-0 FF_LINE_END_F0[10:0] Field 0 Full Field end line data used to set EDH calculation range outside of SMPTE RP 165 values. 15-11 ­ Not Used 10-0 FF_LINE_START_F1[10:0] Field 1 Full Field start line data used to set EDH calculation range outside of SMPTE RP 165 values. 15-11 ­ Not Used 10-0 FF_LINE_END_F1[10:0] Field 1 Full Field end line data used to set EDH calculation range outside of SMPTE RP 165 values. 15-13 ­ Not Used 12-0 AP_PIXEL_START_F0[12:0] Field 0 Active Picture start pixel data used to set EDH calculation range outside of SMPTE RP 165 values. AP_LINE_END_F0 Address: 16h AP_LINE_START_F1 Address: 17h AP_LINE_END_F1 Address: 18h FF_LINE_START_F0 Address: 19h FF_LINE_END_F0 Address: 1Ah FF_LINE_START_F1 Address: 1Bh FF_LINE_END_F1 Address: 1Ch AP_PIXEL_START_F0 Address: 1Dh GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 R/W Default ­ ­ R/W 0 ­ ­ R/W 0 ­ ­ R/W 0 ­ ­ R/W 0 ­ ­ R/W 0 ­ ­ R/W 0 ­ ­ R/W 0 ­ ­ R/W 0 ­ ­ R/W 0 44 of 71 Proprietary & Confidential Table 3-13: Host Interface Description for EDH Calculation Range Registers (Continued) Register Name Bit Name Description AP_PIXEL_END_F0 Address: 1Eh 15-13 ­ Not Used 12-0 AP_PIXEL_END_F0[12:0] Field 0 Active Picture end pixel data used to set EDH calculation range outside of SMPTE RP 165 values. 15-13 ­ Not Used 12-0 AP_PIXEL_START_F1[12:0] Field 1 Active Picture start pixel data used to set EDH calculation range outside of SMPTE RP 165 values. 15-13 ­ Not Used 12-0 AP_PIXEL_END_F1[12:0] Field 1 Active Picture end pixel data used to set EDH calculation range outside of SMPTE RP 165 values. 15-13 ­ Not Used 12-0 FF_PIXEL_START_F0[12:0] Field 0 Full Field start pixel data used to set EDH calculation range outside of SMPTE RP 165 values. 15-13 ­ Not Used 12-0 FF_PIXEL_END_F0[12:0] Field 0 Full Field end pixel data used to set EDH calculation range outside of SMPTE RP 165 values. 15-13 ­ Not Used 12-0 FF_PIXEL_START_F1[12:0] Field 1 Full Field start pixel data used to set EDH calculation range outside of SMPTE RP 165 values. 15-13 ­ Not Used 12-0 FF_PIXEL_END_F1[12:0] Field 1 Full Field end pixel data used to set EDH calculation range outside of SMPTE RP 165 values. AP_PIXEL_START_F1 Address: 1Fh AP_PIXEL_END_F1 Address: 20h FF_PIXEL_START_F0 Address: 21h FF_PIXEL_END_F0 Address: 22h FF_PIXEL_START_F1 Address: 23h FF_PIXEL_END_F1 Address: 24h GS9091B GS9091B GenLINX® II 270Mb/s Deserializer for SDI and DVB-ASI Data Sheet 38910 - 2 July 2008 R/W Default ­ ­ R/W 0 ­ ­ R/W 0 ­ ­ R/W 0 ­ ­ R/W 0 ­ ­ R/W 0 ­ ­ R/W 0 ­ ­ R/W 0 45 of 71 Proprietary & Confidential 3.9.7.3 Lock Error Detection The LOCKED pin of the GS9091B GS9091B asserts HIGH when the device has correctly locked to the received data stream (see Section 3.5.1). The GS9091B GS9091B will also indicate lock error to the host interface when LOCKED = LOW by setting the LOCK_ERR bit in the ERROR_STATUS register HIGH (Table 3-11). 3.9.7.4 Ancillary Data Checksum Error Detection The GS9091B GS9091B will calculate checksums for all received ancillary data types and compare the calculated values to the received checksum words. If a mismatch is detected, the CS_ERR bit of the ERROR_STATUS register will be set HIGH (Table 3-11). Although the GS9091B GS9091B will calculate and compare checksum values for all ancillary data types by default, the host interface may be programmed to check only certain types of ancillary data checksums, as described in Section 3.9.2.1. 3.9.7.5 TRS Error Detection TRS error flags are generated by the GS9091B GS9091B when the received TRS H timing does not correspond to the internal flywheel timing, or when the received TRS Hamming codes are incorrect. These errors are flagged via the SAV_ERR and/or EAV_ERR bits of the ERROR_STATUS register (Table 3-11). Both 8-bit and 10-bit SAV and EAV errors are handled by the GS9091B GS9091B. NOTE: H timing based TRS errors will only be detected if the FW_EN pin is set HIGH. F & V timing errors are not detected or corrected. 3.9.8 Additional SMPTE Mode Processing The GS9091B GS9091B contains an additional processing block which is available in SMPTE mode only. The IOPROC_EN pin must be set HIGH to enable these functions. These functions, which are all enabled by default, may be enabled or disabled individually by setting bits 0 to 3 in t