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Abstract: GS8321Z18/32/36E-250/225/200/166/150/133 GS8321Z18/32/36E-250/225/200/166/150/133 165-Bump FP-BGA Commercial Temp Industrial Temp 36Mb Pipelined and Flow Through Synchronous NBT SRAM Features 250 MHz­133 MHz 1.8 V, 2.5 V, or 3.3 V VDD 1.8 V, 2.5 V, or 3.3 V I/O Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep m ... Original
datasheet

38 pages,
528.65 Kb

GS8321Z32E-250 GS8321Z18E-250 GS8321Z18E-225 GS8321Z18E-200 GS8321Z18E-166 GS8321Z18E-150 GS8321Z18E-133 GS8321Z18/32/36E-250/225/200/166/150/133 GS8321Z18/32/36E-250/225/200/166/150/133 abstract
datasheet frame
Abstract: GS8321Z18/32/36E-xxxV 165-Bump FP-BGA Commercial Temp Industrial Temp 36Mb Pipelined and Flow Through Synchronous NBT SRAM Features 250 MHz­133 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable, ZZ and Output Enable. O ... Original
datasheet

33 pages,
484.88 Kb

datasheet abstract
datasheet frame
Abstract: GS8321Z18/32/36E-xxxV 165-Bump FP-BGA Commercial Temp Industrial Temp 36Mb Pipelined and Flow Through Synchronous NBT SRAM Features 250 MHz­133 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable, ZZ and Output Enable. O ... Original
datasheet

32 pages,
727.24 Kb

datasheet abstract
datasheet frame
Abstract: GS8321Z18/32/36E-xxxV 165-Bump FP-BGA Commercial Temp Industrial Temp 36Mb Pipelined and Flow Through Synchronous NBT SRAM Features 250 MHz­133 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable, ZZ and Output Enable. O ... Original
datasheet

32 pages,
505.04 Kb

datasheet abstract
datasheet frame