NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: GS8321Z18/32/36E-250/225/200/166/150/133 GS8321Z18/32/36E-250/225/200/166/150/133 165-Bump FP-BGA Commercial Temp Industrial Temp 36Mb Pipelined and Flow Through Synchronous NBT SRAM Features 250 MHz133 MHz 1.8 V, 2.5 V, or 3.3 V VDD 1.8 V, 2.5 V, or 3.3 V I/O Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep m ... | Original |
38 pages, |
GS8321Z32E-250 GS8321Z18E-250 GS8321Z18E-225 GS8321Z18E-200 GS8321Z18E-166 GS8321Z18E-150 GS8321Z18E-133 GS8321Z18/32/36E-250/225/200/166/150/133 GS8321Z18/32/36E-250/225/200/166/150/133 abstract |
| Abstract: GS8321Z18/32/36E-xxxV 165-Bump FP-BGA Commercial Temp Industrial Temp 36Mb Pipelined and Flow Through Synchronous NBT SRAM Features 250 MHz133 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable, ZZ and Output Enable. O ... | Original |
33 pages, |
datasheet abstract |
| Abstract: GS8321Z18/32/36E-xxxV 165-Bump FP-BGA Commercial Temp Industrial Temp 36Mb Pipelined and Flow Through Synchronous NBT SRAM Features 250 MHz133 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable, ZZ and Output Enable. O ... | Original |
32 pages, |
datasheet abstract |
| Abstract: GS8321Z18/32/36E-xxxV 165-Bump FP-BGA Commercial Temp Industrial Temp 36Mb Pipelined and Flow Through Synchronous NBT SRAM Features 250 MHz133 MHz 1.8 V or 2.5 V VDD 1.8 V or 2.5 V I/O Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable, ZZ and Output Enable. O ... | Original |
32 pages, |
datasheet abstract |