GS816218A /GS816236A /GS816272A GS816218/36/72A GS816272A BGA--14 GS816218/36A - Datasheet Archive

 

GS816218A(B/D)/GS816236A(B/D)/GS816272A(C) 1M x 18, 512K x 36, 256K x 72 300 MHz­200 MHz 1.8 V or 2.5 V VDD 18Mb S/DCD Sync

 

Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) 1M x 18, 512K x 36, 256K x 72 300 MHz­200 MHz 1.8 V or 2.5 V VDD 18Mb S/DCD Sync Burst SRAMs 1.8 V or 2.5 V I/O 119-, 165-, & 209-Pin BGA Commercial Temp Industrial Temp Features · FT pin for user-configurable flow through or pipeline operation · Single/Dual Cycle Deselect selectable · IEEE 1149.1 JTAG-compatible Boundary Scan · ZQ mode pin for user-selectable high/low output drive · 1.8 V or 2.5 V +10%/­10% core power supply · 1.8 V or 2.5 V I/O supply · LBO pin for Linear or Interleaved Burst mode · Internal input resistors on mode pins allow floating mode pins · Default to SCD x18/x36 Interleaved Pipeline mode · Byte Write (BW) and/or Global Write (GW) operation · Internal self-timed write cycle · Automatic power-down for portable applications · JEDEC-standard 119-, 165-, and 209-bump BGA package Pipeline 3-1-1-1 2.5 V 1.8 V Flow Through 2-1-1-1 2.5 V 1.8 V tKQ tCycle Curr (x18) Curr (x36) Curr (x72) Curr (x18) Curr (x36) Curr (x72) -300 -275 -250 -225 -200 Unit 2.2 2.4 2.5 2.7 3.0 ns 3.3 3.6 4.0 4.4 5.0 ns 320 375 475 320 370 470 300 345 445 300 340 435 275 320 410 275 315 400 250 295 380 250 285 365 230 265 335 225 260 325 mA mA mA mA mA mA tKQ tCycle 5.0 5.0 5.25 5.25 5.5 5.5 6.0 6.0 6.5 6.5 ns ns Curr (x18) Curr (x36) Curr (x72) Curr (x18) Curr (x36) Curr (x72) 220 265 315 220 265 315 215 260 305 215 260 305 210 245 295 210 245 295 200 235 285 200 235 285 190 225 260 190 225 260 mA mA mA mA mA mA Functional Description Flow Through/Pipeline Reads The function of the Data Output register can be controlled by the user via the FT mode . Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register. SCD and DCD Pipelined Reads The GS816218/36/72A GS816218/36/72A is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input. Byte Write and Global Write Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs. FLXDriveTM The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details. Sleep Mode Applications The GS816218/36/72A GS816218/36/72A is a 18,874,368-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support. Controls Addresses, data I/Os, chip enable (E1), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edgetriggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent Rev: 1.01 3/2002 burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode. Core and Interface Voltages The GS816218/36/72A GS816218/36/72A operates on a 2.5 V or 1.8 V power supply. All input are 1.8 V and 2.5 V compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuits and are 1.8 V and 2.5 V compatible. 1/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ByteSafe is a Trademark of Giga Semiconductor, Inc. (GSI Technology). © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) GS816272A GS816272A Pad Out 209 Bump BGA-Top View (Package C) 1 2 3 4 5 6 7 8 9 10 11 A DQG5 DQG1 A15 E2 ADSP ADSC ADV E3 A17 DQB1 DQB5 B DQG6 DQG2 BC BG NC BW A16 BB BF DQB2 DQB6 C DQG7 DQG3 BH BD NC E1 NC BE BA DQB3 DQB7 D DQG8 DQG4 VSS NC NC G GW NC VSS DQB4 DQB8 E DQG9 DQC9 VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQF9 DQB9 F DQC4 DQC8 VSS VSS VSS ZQ VSS VSS VSS DQF8 DQF4 G DQC3 DQC7 VDDQ VDDQ VDD MCH VDD VDDQ VDDQ DQF7 DQF3 H DQC2 DQC6 VSS VSS VSS MCL VSS VSS VSS DQF6 DQF2 J DQC1 DQC5 VDDQ VDDQ VDD MCL VDD VDDQ VDDQ DQF5 DQF1 K NC NC CK NC VSS MCL VSS NC NC NC NC L DQH1 DQH5 VDDQ VDDQ VDD FT VDD VDDQ VDDQ DQA5 DQA1 M DQH2 DQH6 VSS VSS VSS MCL VSS VSS VSS DQA6 DQA2 N DQH3 DQH7 VDDQ VDDQ VDD SCD VDD VDDQ VDDQ DQA7 DQA3 P DQH4 DQH8 VSS VSS VSS ZZ VSS VSS VSS DQA8 DQA4 R DQD9 DQH9 VDDQ VDDQ VDD VDD VDD VDDQ VDDQ DQA9 DQE9 T DQD8 DQD4 VSS NC NC LBO PE NC VSS DQE4 DQE8 U DQD7 DQD3 NC A14 A13 A12 A11 A10 NC DQE3 DQE7 V DQD6 DQD2 A9 A8 A7 A1 A6 A5 A4 DQE2 DQE6 W DQD5 DQD1 TMS TDI A3 A0 A2 TDO TCK DQE1 DQE5 Rev 10 Rev: 1.01 3/2002 11 x 19 Bump BGA-14 BGA-14 x 22 mm2 Body-1 mm Bump Pitch 2/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) GS816272A GS816272A 209-Bump BGA Pin Description Pin Location Symbol Type Description W6, V6 A0, A1 I Address field LSBs and Address Counter Preset Inputs. W7, W5, V9, V8, V7, V5, V4, V3, U8, U7, U6, U5, U4, A3, B7, A9 An I Address Inputs L11, M11, N11, P11, L10, M10, N10, P10, R10 A10, B10, C10, D10, A11, B11, C11, D11, E11 J1, H1, G1, F1, J2, H2, G2, F2, E2 W2, V2, U2, T2, W1, V1, U1, T1, R1 W10, V10, U10, T10, W11, V11, U11, T11, R11 J11, H11, G11, F11, J10, H10, G10, F10, E10 A2, B2, C2, D2, A1, B1, C1, D1, E1 L1, M1, N1, P1, L2, M2, N2, P2, R2 DQA1­DQA9 DQB1­DQB9 DQC1­DQC9 DQD1­DQD9 DQE1­DQE9 DQF1­DQF9 DQG1­DQG9 DQH1­DQH9 I/O Data Input and Output pins (x36 Version) C9, B8, B3, C4, C8, B9, B4, C3 BA, BB, BC,BD, BE, BF, BG,BH I Byte Write Enable for DQA, DQB, DQC, DQD, DQE, DQF, DQG, DQH I/Os; active low B5, C5, C7, D4, D5, D8, K1, K2, K4, K8, K9, K10, K11, T4, T5, T8, U3, U9 NC - No Connect K3 CK I Clock Input Signal; active high D7 GW I Global Write Enable-Writes all bytes; active low C6, A8 E1, E3 I Chip Enable; active low A4 E2 I Chip Enable; active high D6 G I Output Enable; active low A7 ADV I Burst address counter advance enable; active low A5, A6 ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low P6 ZZ I Sleep Mode control; active high L6 FT I Flow Through or Pipeline mode; active low T6 LBO I Linear Burst Order mode; active low N6 SCD I Single Cycle Deselect/Dual Cycle Deselect Mode Control G6 MCH I Must Connect High H6, J6, K6, M6 MCL Rev: 1.01 3/2002 Must Connect Low 3/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) GS816272A GS816272A 209-Bump BGA Pin Description Pin Location Symbol Type Description T7 PE I Parity Bit Enable; active low (High = x16/32 Mode, Low = x18/36 Mode) B6 BW I Byte Enable; active low F6 ZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) W3 TMS I Scan Test Mode Select W4 TDI I Scan Test Data In W8 TDO O Scan Test Data Out W9 TCK I Scan Test Clock E5, E6, E7, G5, G7, J5, J7, L5, L7, N5, N7, R5, R6, R7 VDD I Core power supply D3, D9, F3, F4, F5, F7, F8, F9, H3, H4, H5, H7, H8, H9, K5, K7, M3, M4, M5, M7, M8, M9, P3, P4, P5, P7, P8, P9, T3, T9 VSS I I/O and Core Ground E3, E4, E8, E9, G3, G4, G8, G9, J3, J4, J8, J9, L3, L4, L8, L9, N3, N4, N8, N9, R3, R4, R8, R9 VDDQ I Output driver power supply Rev: 1.01 3/2002 4/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) 165 Bump BGA-x18 Commom I/O-Top View (Package D) 1 2 3 4 5 6 7 8 9 10 11 A NC A E1 BB NC E3 BW ADSC ADV A A19 A B NC A E2 NC BA CK GW G ADSP A NC B C NC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPA C D NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA D E NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA E F NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA F G NC DQB VDDQ VDD VSS VSS VSS VDD VDDQ NC DQA G H FT MCL NC VDD VSS VSS VSS VDD NC ZQ ZZ H J DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC J K DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC K L DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC L M DQB NC VDDQ VDD VSS VSS VSS VDD VDDQ DQA NC M N DQPB SCD VDDQ VSS NC A18 NC VSS VDDQ NC NC N P NC NC A A TDI A1 TDO A A A A17 P R LBO NC A A TMS A0 TCK A A A A R 11 x 15 Bump BGA-13mm x 15 mm Body-1.0 mm Bump Pitch Rev: 1.01 3/2002 5/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) 165 Bump BGA-x36 Common I/O-Top View (Package D) 1 2 3 4 5 6 7 8 9 10 11 A NC A E1 BC BB E3 BW ADSC ADV A NC A B NC A E2 BD BA CK GW G ADSP A NC B C DQPC NC VDDQ VSS VSS VSS VSS VSS VDDQ NC DQPB C D DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB D E DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB E F DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB F G DQC DQC VDDQ VDD VSS VSS VSS VDD VDDQ DQB DQB G H FT MCL NC VDD VSS VSS VSS VDD NC ZQ ZZ H J DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA J K DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA K L DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA L M DQD DQD VDDQ VDD VSS VSS VSS VDD VDDQ DQA DQA M N DQPD SCD VDDQ VSS NC A18 NC VSS VDDQ NC DQPA N P NC NC A A TDI A1 TDO A A A A17 P R LBO NC A A TMS A0 TCK A A A A R 11 x 15 Bump BGA-13mm x 15 mm Body-1.0 mm Bump Pitch Rev: 1.01 3/2002 6/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) GS816218/36A GS816218/36A 165-Bump BGA Pin Description Pin Location Symbol Type Description R6, P6 A0, A1 I Address field LSBs and Address Counter Preset Inputs A2, A10, B2, B10, P3, P4, P8, P9, P10, R3, R4, R8, R9, R10, R11 An I Address Inputs P11, N6 A17, A18 A11 A19 J10, K10, L10, M10, J11, K11, L11, M11, N11 G10, F10, E10, D10, G11, F11, E11, D11, C11 G2, F2, E2, D2, G1, F1, E1, D1, C1 DQA1­DQA9 DQC1­DQC9 J2, K2, L2, M2, J1, K1, L1, M1, N1 DQD1­DQD9 B5, A5, A4, B4 BA, BB, BC, BD M10, L10, K10, J10, G11, F11, E11, D11, C11 D2, E2, F2, G2, J1, K1, L1, M1, N1 DQA1­DQA9 DQC1­DQC9 B5, A4 Address Input I Address Input (x18 Version) I/O Data Input and Output pins. (x36 Version) I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version) I/O Data Input and Output pins (x18 Version) BA, BC I Byte Write Enable for DQA, DQB I/Os; active low (x18 Version) A1, B1, B11, C2, C10, H3, H9, N5, N7, N10, P1, P2, R2 NC - No Connect A5, B4, C1, D1, D10, E1, E10, F1, F10, G1, G10, J2, J11, K2, K11, L2, L11, M2, M11, N11 NC - No Connect (x18 Version) A11 NC - No Connect (x36 Version) B6 CK I Clock Input Signal; active high A7 BW I Byte Write-Writes all enabled bytes; active low B7 GW I Global Write Enable-Writes all bytes; active low A3 E1 I Chip Enable; active low A6 E3 I Chip Enable; active low (x36 version) B3 E2 I Chip Enable; active high (x36 version) B8 G I Output Enable; active low A9 ADV I Burst address counter advance enable; active l0w A8, B9 ADSC, ADSP I Address Strobe (Processor, Cache Controller); active low H11 ZZ I Sleep mode control; active high H1 FT I Flow Through or Pipeline mode; active low R1 LBO I Linear Burst Order mode; active low H10 ZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) R5 TMS I Scan Test Mode Select P5 TDI I Scan Test Data In Rev: 1.01 3/2002 DQB1­DQB9 7/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) GS816218/36A GS816218/36A 165-Bump BGA Pin Description Pin Location Symbol Type Description P7 TDO O Scan Test Data Out R7 TCK I Scan Test Clock H2 MCL - Must Connect Low N2 SCD - Single Cycle Deselect/Dual Cyle Deselect Mode Control D4, D8, E4, E8, F4, F8, G4, G8, H4, H8, J4, J8, K4, K8, L4, L8, M4, M8 VDD I Core power supply C4, C5, C6, C7, C8, D5, D6, D7, E5, E6, E7, F5, F6, F7, G5, G6, G7, H5, H6, H7, J5, J6, J7, K5, K6, K7, L5, L6, L7, M5, M6, M7, N4, N8 VSS I I/O and Core Ground C3, C9, D3, D9, E3, E9, F3, F9, G3, G9, J3, J9, K3, K9, L3, L9, M3, M9, N3, N9 VDDQ I Output driver power supply Rev: 1.01 3/2002 8/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) GS816236A GS816236A Pad Out 119 Bump BGA-Top View 1 3 4 5 6 7 A VDDQ A6 A7 ADSP A8 A9 VDDQ B NC A18 A4 ADSC A15 A17 NC C NC A5 A3 VDD A14 A16 NC D DQC4 DQC9 VSS ZQ VSS DQB9 DQB4 E DQC3 DQC8 VSS E1 VSS DQB8 DQB3 F VDDQ DQC7 VSS G VSS DQB7 VDDQ G DQC2 DQC6 BC ADV BB DQB6 DQB2 H DQC1 DQC5 VSS GW VSS DQB5 DQB1 J VDDQ VDD NC VDD NC VDD VDDQ K DQD1 DQD5 VSS CK VSS DQA5 DQA1 L DQD2 DQD6 BD SCD BA DQA6 DQA2 M VDDQ DQD7 VSS BW VSS DQA7 VDDQ N DQD3 DQD8 VSS A1 VSS DQA8 DQA3 P DQD4 DQD9 VSS A0 VSS DQA9 DQA4 R NC A2 LBO VDD FT A13 PE T NC NC A10 A11 A12 NC ZZ U Rev: 1.01 3/2002 2 VDDQ TMS TDI TCK TDO NC VDDQ 9/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) GS816218A GS816218A Pad Out 119 Bump BGA-Top View 1 2 3 4 5 6 7 A VDDQ A6 A7 ADSP A8 A9 VDDQ B NC A18 A4 ADSC A15 A17 NC C NC A5 A3 VDD A14 A16 NC D DQB1 NC VSS ZQ VSS DQA9 NC E NC DQB2 VSS E1 VSS NC DQA8 F VDDQ NC VSS G VSS DQA7 VDDQ G NC DQB3 BB ADV NC NC DQA6 H DQB4 NC VSS GW VSS DQA5 NC J VDDQ VDD NC VDD NC VDD VDDQ K NC DQB5 VSS CK VSS NC DQA4 L DQB6 NC NC SCD BA DQA3 NC M VDDQ DQB7 VSS BW VSS NC VDDQ N DQB8 NC VSS A1 VSS DQA2 NC P NC DQB9 VSS A0 VSS NC DQA1 R NC A2 LBO VDD FT A13 PE T NC A10 A11 NC A12 A19 ZZ U VDDQ TMS TDI TCK TDO NC VDDQ BPR1999 BPR1999.05.18 Rev: 1.01 3/2002 10/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) GS816218/36 GS816218/36 119-Bump BGA Pin Description Pin Location Symbol Type Description P4, N4 A0, A1 I Address field LSBs and Address Counter Preset Inputs R2, C3, B3, C2, A2, A3, A5, A6, T3, T5, R6, C5, B5, C6, B6, B2 An I Address Inputs T4 An T2, T6 NC - No Connect (x36 Version) T2, T6 An I Address Input (x18 Version) K7, L7, N7, P7, K6, L6, M6, N6 H7, G7, E7, D7, H6, G6, F6, E6 H1, G1, E1, D1, H2, G2, F2, E2 K1, L1, N1, P1, K2, L2, M2, N2 DQA1­DQA8 DQB1­DQB8 DQC1­DQC8 DQD1­DQD8 I/O Data Input and Output pins. (x36 Version) P6, D6, D2, P2 DQA9, DQB9, DQC9, DQD9 I/O Data Input and Output pins. (x36 Version) L5, G5, G3, L3 BA, BB, BC, BD I Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low (x36 Version) P7, N6, L6, K7, H6, G7, F6, E7, D6 D1, E2, G2, H1, K2, L1, M2, N1, P2 DQA1­DQA9 DQB1­DQB9 I/O Data Input and Output pins (x18 Version) L5, G3 BA, BB I Byte Write Enable for DQA, DQB I/Os; active low (x18 Version) B1, C1, R1, T1, U6, B7, C7, R7, J3, J5 NC - No Connect P6, N7, M6, L7, K6, H7, G6, E6, D7, D2, E1, F2, G1, H2, K1, L2, N2, P1, G5, L3, T4 NC - No Connect (x18 Version) K4 CK I Clock Input Signal; active high M4 BW I Byte Write-Writes all enabled bytes; active low H4 GW I Global Write Enable-Writes all bytes; active low E4 E1 I Chip Enable; active low F4 G I Output Enable; active low G4 ADV I Burst address counter advance enable; active low A4, B4 ADSP, ADSC I Address Strobe (Processor, Cache Controller); active low T7 ZZ I Sleep mode control; active high R5 FT I Flow Through or Pipeline mode; active low R3 LBO I Linear Burst Order mode; active low D4 ZQ I FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) L4 SCD I Single Cycle Deselect/Dual Cyle Deselect Mode Control U2 TMS I Scan Test Mode Select Rev: 1.01 3/2002 Address Input (x36 Version) 11/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) GS816218/36 GS816218/36 119-Bump BGA Pin Description Pin Location Symbol Type Description U3 TDI I Scan Test Data In U5 TDO O Scan Test Data Out U4 TCK I Scan Test Clock R7 PE I Parity Bit Enable; active low J2, C4, J4, R4, J6 VDD I Core power supply D3, E3, F3, H3, K3, M3, N3, P3, D5, E5, F5, H5, K5, M5, N5, P5 VSS I I/O and Core Ground A1, F1, J1, M1, U1, A7, F7, J7, M7, U7 VDDQ I Output driver power supply Rev: 1.01 3/2002 12/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) GS816218/36A GS816218/36A (PE = 0) Block Diagram Register A0­An D Q A0 A0 D0 Q0 A1 A1 D1 Q1 Counter Load A LBO ADV Memory Array CK ADSC ADSP Q D Register GW BW BA D Q 36 36 Register D Q BB 4 4 Register D Q Q Register D D Q D Q Register Register D Q Register BC BD Register D 36 Q 36 36 Register E1 D Q 4 32 36 Parity Encode Register D Q 4 Parity Compare FT G ZZ 36 Power Down SCD DQx1­DQx9 NC NC Control Note: Only x36 version shown for simplicity. Rev: 1.01 3/2002 13/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) GS816218/3A6 GS816218/3A6 (PE = 1) x32 Mode Block Diagram Register A0­An D Q A0 A0 D0 Q0 A1 A1 D1 Q1 Counter Load A LBO ADV Memory Array CK ADSC ADSP Q D Register GW BW BA D Q 36 36 4 Parity Encode Register D Q BB 32 4 Register D Q D Q D Q Register Register D Q Register BC BD Register D 32 Q 36 Register D Register E1 D 36 Q Q 4 32 32 Register D Register D Q Q Parity Encode 4 Parity Compare FT G ZZ 32 Power Down SCD DQx1­DQx8 NC NC Control Note: Only x36 version shown for simplicity. Rev: 1.01 3/2002 14/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Mode Pin Functions Mode Name Pin Name Burst Order Control LBO Output Register Control FT Power Down Control ZZ Single/Dual Cycle Deselect Control SCD Parity Enable PE FLXDrive Output Impedance Control ZQ State Function L Linear Burst H Interleaved Burst L Flow Through H or NC Pipeline L or NC Active H Standby, IDD = ISB L Dual Cycle Deselect H or NC Single Cycle Deselect L or NC Activate 9th I/O's (x18/36 Mode) H Deactivate 9th I/O's (x16/32 Mode) L High Drive (Low Impedance) H or NC Low Drive (High Impedance) Note: There arepull-up devices on the ZQ, SCD, and FT pins and pull-down device on the PE and ZZ pins, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Enable / Disable Parity I/O Pins This SRAM allows the user to configure the device to operate in Parity I/O active (x18, x36, or x72) or in Parity I/O inactive (x16, x32, or x64) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Grounding PE deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits generated and read into the ByteSafe parity circuits. Burst Counter Sequences Interleaved Burst Sequence Linear Burst Sequence A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 1st address 00 01 10 11 2nd address 01 10 11 00 2nd address 01 00 11 10 3rd address 10 11 00 01 3rd address 10 11 00 01 4th address 11 00 01 10 4th address 11 10 01 00 Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. BPR 1999.05.18 Rev: 1.01 3/2002 15/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Byte Write Truth Table Function GW BW BA BB BC BD Notes Read H H X X X X 1 Read H L H H H H 1 Write byte a H L L H H H 2, 3 Write byte b H L H L H H 2, 3 Write byte c H L H H L H 2, 3, 4 Write byte d H L H H H L 2, 3, 4 Write all bytes H L L L L L 2, 3, 4 Write all bytes L X X X X X Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes "C" and "D" are only available on the x36 version. Rev: 1.01 3/2002 16/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Synchronous Truth Table Operation Address Used State Diagram Key5 E1 ADSP ADSC ADV W3 DQ4 Deselect Cycle, Power Down None X H X L X X High-Z Read Cycle, Begin Burst External R L L X X X Q Read Cycle, Begin Burst External R L H L X F Q Write Cycle, Begin Burst External W L H L X T D Read Cycle, Continue Burst Next CR X H H L F Q Read Cycle, Continue Burst Next CR H X H L F Q Write Cycle, Continue Burst Next CW X H H L T D Write Cycle, Continue Burst Next CW H X H L T D Read Cycle, Suspend Burst Current X H H H F Q Read Cycle, Suspend Burst Current H X H H F Q Write Cycle, Suspend Burst Current X H H H T D Write Cycle, Suspend Burst Current H X H H T D Notes: 1. X = Don't Care, H = High, L = Low 2. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding 3. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as "Q" in the Truth Table above). 4. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. 5. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. 6. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.01 3/2002 17/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Simplified State Diagram X Deselect W R Simple Burst Synchronous Operation Simple Synchronous Operation W X R R First Write CW First Read CR CR W X R R X Burst Write Burst Read X CR CW CR Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs and assumes ADSP is tied high and ADV is tied low. Rev: 1.01 3/2002 18/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Simplified State Diagram with G X Deselect W R W X R R First Write CR CW W CW W X First Read X CR R Burst Write R CR CW W Burst Read X CW CR Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of "Dummy Reads" (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM's drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.01 3/2002 19/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Absolute Maximum Ratings (All voltages reference to VSS) Symbol Description Value Unit VDD Voltage on VDD Pins ­0.5 to 3.6 V VDDQ Voltage in VDDQ Pins ­0.5 to 3.6 V VCK Voltage on Clock Input Pin ­0.5 to 3.6 V VI/O Voltage on I/O Pins ­0.5 to VDDQ +0.5 ( 3.6 V max.) V VIN Voltage on Other Input Pins ­0.5 to VDD +0.5 ( 3.6 V max.) V IIN Input Current on Any Pin +/­20 mA IOUT Output Current on Any I/O Pin +/­20 mA PD Package Power Dissipation 1.5 W TSTG Storage Temperature ­55 to 125 o C TBIAS Temperature Under Bias ­55 to 125 o C Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Rev: 1.01 3/2002 20/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Power Supply Voltage Ranges Parameter Symbol Min. Typ. Max. Unit 2.5 V Supply Voltage VDD2 2.3 2.5 2.7 V 1.8 V Supply Voltage VDD1 1.6 1.8 2.0 V 2.5 V VDDQ I/O Supply Voltage VDDQ2 2.3 2.5 2.7 V 1.8 V VDDQ I/O Supply Voltage VDDQ1 1.6 1.8 2.0 Notes V Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be ­2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC. VDDQ2 Range Logic Levels Parameter Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD - VDD + 0.3 V 1 VDD Input Low Voltage VIL ­0.3 - 0.3*VDD V 1 VDDQ I/O Input High Voltage VIHQ 0.6*VDD - VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ ­0.3 - 0.3*VDD V 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be ­2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. VDDQ1 Range Logic Levels Parameter Symbol Min. Typ. Max. Unit Notes VDD Input High Voltage VIH 0.6*VDD - VDD + 0.3 V 1 VDD Input Low Voltage VIL ­0.3 - 0.3*VDD V 1 VDDQ I/O Input High Voltage VIHQ 0.6*VDD - VDDQ + 0.3 V 1,3 VDDQ I/O Input Low Voltage VILQ ­0.3 - 0.3*VDD V 1,3 Notes: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be ­2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC. 3. VIHQ (max) is voltage on VDDQ pins plus 0.3 V. Rev: 1.01 3/2002 21/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Recommended Operating Temperatures Parameter Symbol Min. Typ. Max. Unit Notes Ambient Temperature (Commercial Range Versions) TA 0 25 70 °C 2 Ambient Temperature (Industrial Range Versions) TA ­40 25 85 °C 2 Note: 1. The part numbers of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 2. Input Under/overshoot voltage must be ­2 V > Vi < VDDn+2 V not to exceed 3.6 V maximum, with a pulse width not to exceed 20% tKC. Undershoot Measurement and Timing Overshoot Measurement and Timing VIH 20% tKC VDD + 2.0 V VSS 50% 50% VDD VSS ­ 2.0 V 20% tKC VIL Capacitance (TA = 25oC, f = 1 MHZ, VDD = 2.5 V) Parameter Symbol Test conditions Typ. Max. Unit Input Capacitance CIN VIN = 0 V 4 5 pF Input/Output Capacitance CI/O VOUT = 0 V 6 7 pF Note: These parameters are sample tested. Package Thermal Characteristics Rating Layer Board Symbol Max Unit Notes Junction to Ambient (at 200 lfm) single RJA 40 °C/W 1,2 Junction to Ambient (at 200 lfm) four RJA 24 °C/W 1,2 Junction to Case (TOP) - RJC 9 °C/W 3 Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883 SPEC-883, Method 1012.1 Rev: 1.01 3/2002 22/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) AC Test Conditions Parameter Conditions Input high level VDD ­ 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level VDD/2 Output reference level VDDQ/2 Output load Fig. 1 Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Device is deselected as defined by the Truth Table. Output Load 1 DQ 30pF* 50 VDDQ/2 * Distributed Test Jig Capacitance DC Electrical Characteristics Parameter Symbol Test Conditions Min Max Input Leakage Current (except mode pins) IIL VIN = 0 to VDD ­1 uA 1 uA ZZ and PE Input Current IIN1 VDD VIN VIH 0 V VIN VIH ­1 uA ­1 uA 1 uA 100 uA FT, SCD, ZQ Input Current IIN2 VDD VIN VIL 0 V VIN VIL ­100 uA ­1 uA 1 uA 1 uA Output Leakage Current IOL Output Disable, VOUT = 0 to VDD ­1 uA 1 uA Output High Voltage VOH2 IOH = ­8 mA, VDDQ = 2.3 V VDDQ ­ 0.4 V - Output High Voltage VOH1 IOH = ­4 mA, VDDQ = 1.6 V VDDQ ­ 0.4 V - Output Low Voltage VOL2 IOL = 8 mA, VDD = 2.3 V - 0.4 V Output Low Voltage VOL1 IOL = 4 mA, VDD = 1.6 V - 0.4 V Rev: 1.01 3/2002 23/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Rev: 1.01 3/2002 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 24/49 - Device Deselected; All other inputs VIH or VIL Deselect Current 235 30 345 30 285 30 420 55 0 to 70°C 210 10 420 50 285 30 345 25 235 30 305 15 210 10 35 IDD IDDQ IDD IDDQ IDD IDDQ IDD IDDQ IDD IDDQ IDD IDDQ IDD IDDQ ISB Pipeline Flow Through Pipeline Flow Through Pipeline Flow Through Pipeline 35 IDD 70 IDD Pipeline Flow Through 95 ISB Flow Through Flow Through Pipeline IDDQ IDD IDDQ IDD IDDQ IDD IDDQ IDD IDDQ IDD Symbol 305 15 Flow Through Pipeline Flow Through Pipeline Mode 75 100 45 45 220 10 315 15 245 30 355 25 295 30 430 50 220 10 315 15 245 30 355 30 295 30 430 55 ­40 to 85°C -300 Notes: 1. IDD and IDDQ apply to any combination of VDD3, VDD2, VDDQ3, and VDDQ2 operation. 2. All parameters listed are worst case scenario. - ZZ VDD ­ 0.2 V (x18) (x36) (x72) (x18) (x36) (x72) Standby Current 1.8 V Operating Current Device Selected; All other inputs VIH or VIL Output open Device Selected; All other inputs VIH or VIL Output open Operating Current 2.5 V Test Conditions Parameter Operating Currents 70 90 35 35 205 10 285 15 230 30 315 25 275 30 388 45 205 10 285 15 230 30 315 30 275 30 388 55 0 to 70°C 75 95 45 45 215 10 295 15 240 30 325 25 285 30 398 45 215 10 295 15 240 30 325 30 285 30 398 55 ­40 to 85°C -275 60 85 35 35 200 10 260 15 215 30 290 25 265 30 355 45 200 10 260 15 215 30 290 30 265 30 355 55 0 to 70°C 65 90 45 45 210 10 270 15 225 30 300 25 275 30 365 45 210 10 270 15 225 30 300 30 275 30 365 55 ­40 to 85°C -250 60 80 35 35 190 10 235 15 205 30 265 20 255 30 325 40 190 10 235 15 205 30 265 30 255 30 325 55 0 to 70°C 65 85 45 45 200 10 245 15 215 30 275 20 265 30 335 40 200 10 245 15 215 30 275 30 265 30 335 55 ­40 to 85°C -225 50 75 35 35 180 10 215 10 200 25 240 20 235 25 290 35 180 10 215 15 200 25 240 25 235 25 290 45 0 to 70°C 55 80 45 45 190 10 225 10 210 25 250 20 245 25 300 35 190 10 225 15 210 25 250 25 245 25 300 45 ­40 to 85°C -200 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Unit Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) AC Electrical Characteristics Parameter Symbol Clock Cycle Time -300 -275 -250 -225 -200 Unit Max Min Max Min Max Min Max Min Max tKC 3.3 - 3.6 - 4.0 - 4.4 - 5.0 - ns Clock to Output Valid Pipeline Min tKQ - 2.2 - 2.4 - 2.5 - 2.7 - 3.0 ns Clock to Output Invalid tKQX 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - ns 1 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - ns tLZ Setup time tS 1.1 - 1.1 - 1.2 - 1.3 - 1.4 - ns Hold time tH 0.1 - 0.1 - 0.2 - 0.3 - 0.4 - ns Clock Cycle Time tKC 5.0 - 5.25 - 5.5 - 6.0 - 6.5 - ns Clock to Output Valid tKQ - 5.0 - 5.25 - 5.5 - 6.0 - 6.5 ns Clock to Output Invalid tKQX 3.0 - 3.0 - 3.0 - 3.0 - 3.0 - ns Clock to Output in Low-Z tLZ1 3.0 - 3.0 - 3.0 - 3.0 - 3.0 - ns Setup time tS 1.4 - 1.4 - 1.5 - 1.5 - 1.5 - ns Hold time tH 0.4 - 0.4 - 0.5 - 0.5 - 0.5 - ns Clock HIGH Time tKH 1.3 - 1.3 - 1.3 - 1.3 - 1.3 - ns Clock LOW Time tKL 1.5 - 1.5 - 1.5 - 1.5 - 1.5 - ns Clock to Output in High-Z tHZ1 1.5 2.3 1.5 2.3 1.5 2.3 1.5 2.5 1.5 3.0 ns G to Output Valid tOE - 2.3 - 2.3 - 2.3 - 2.5 - 3.0 ns G to output in Low-Z tOLZ1 0 - 0 - 0 - 0 - 0 - ns G to output in High-Z tOHZ1 - 2.3 - 2.3 - 2.3 - 2.5 - 3.0 ns ZZ setup time tZZS2 5 - 5 - 5 - 5 - 5 - ns ZZ hold time tZZH2 1 - 1 - 1 - 1 - 1 - ns ZZ recovery Flow Through Clock to Output in Low-Z tZZR 20 - 20 - 20 - 20 - 20 - ns Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above. Rev: 1.01 3/2002 25/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Write Cycle Timing Single Write Burst Write Deselected Write CK tS tH tKH tKL tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated write ADSC tS tH ADV tS tH A0­An ADV must be inactive for ADSP Write WR2 WR1 WR3 tS tH GW tS tH BW tS tH BA­BD WR2 WR1 WR1 tS tH WR3 WR3 E1 masks ADSP E1 E1 only sampled with ADSP or ADSC G tS tH DQA­DQD Rev: 1.01 3/2002 Hi-Z Write specified byte for 2A and all bytes for 2B, 2C& 2D D1A D2A D2B D2C D2D 26/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. D3A © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Flow Through Read Cycle Timing Single Read Burst Read tKL CK tKH tS tH tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH Suspend Burst Suspend Burst ADV tS tH A0­An RD1 RD2 RD3 tS tH tS tH GW BW BA­BD tS tH E1 masks ADSP E1 tOE tOHZ G tKQX tOLZ DQA­DQD Q1A Hi-Z Q2A tKQX Q2B Q2c Q2D Q3A tLZ tHZ tKQ Rev: 1.01 3/2002 27/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Flow Through Read-Write Cycle Timing Single Write Single Read Burst Read CK tS tH tKH tKL tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0­An WR1 RD1 tS RD2 tH GW tH tS BW tS tH BA­BD WR1 tS tH E1 masks ADSP E1 tOE tOHZ G tS tKQ DQA­DQD Hi-Z Q1A tH D1A Q2A Q2B Q2c Q2D Q2A Burst wrap around to it's initial state Rev: 1.01 3/2002 28/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Pipelined SCD Read Cycle Timing Single Read Burst Read CK tKH tS tH tKL tKC ADSP ADSP is blocked by E inactive tS tH ADSC initiated read ADSC tS tH Suspend Burst ADV tS tH A0­An RD2 RD1 RD3 tS tH tS tH GW BW BWA­BWD tS tH E1 masks ADSP E1 tOE G DQA­DQD tOHZ Hi-Z tKQX tKQX tOLZ Q1A Q2A Q2B Q2c Q2D Q3A tLZ tHZ tKQ Rev: 1.01 3/2002 29/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Pipelined SCD Read-Write Cycle Timing Single Write Single Read Burst Read tKL CK tS tH tKH tKC ADSP is blocked by E inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0­An WR1 RD1 RD2 tS tH GW tS tH BW tS tH BWA­ BWD WR1 tS tH E1 masks ADSP E1 tOE tOHZ G DQA­DQD Rev: 1.01 3/2002 Hi-Z tS tH tKQ Q1A D1A Q2A 30/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q2B Q2c Q2D © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Pipelined DCD Read Cycle Timing Single Read tKL Burst Read CK tS tH tKH tKC ADSP is blocked by E1 inactive ADSP tS tH ADSC initiated read ADSC tS tH Suspend Burst ADV tS tH A0­An RD1 RD3 RD2 tS tH tS tH GW BW BA­BD tS tH E1 masks ADSP E1 tOE G tOHZ Hi-Z tOLZ Q1A DQA­DQD tKQX Q2A tKQX Q2B Q2c Q2D Q3A tLZ tHZ tKQ Rev: 1.01 3/2002 31/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Pipelined DCD Read-Write Cycle Timing Single Write Burst Read Single Read tKL CK tS tH tKH tKC ADSP is blocked by E1 inactive ADSP tS tH ADSC initiated read ADSC tS tH ADV tS tH A0­An RD1 WR1 RD2 tS tH GW tS tH BW tS tH BA­BD WR1 tS tH E1 masks ADSP E1 tOE tOHZ G DQA­DQD Rev: 1.01 3/2002 Hi-Z tS tH tKQ Q1A D1A Q2A 32/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Q2B Q2c Q2D © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Sleep Mode During normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time. Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, ISB2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode. tKC tKH tKL ADSP ADSC tZZS ZZ ~ ~ ~ ~ tS tH ~ ~ CK tZZH ~~ ~~ ~ ~~ ~ ~ ~ ~ ~~ ~ ~ ~ Sleep Mode Timing Diagram tZZR Snooze Application Tips Single and Dual Cycle Deselect SCD devices (like this one) force the use of "dummy read cycles" (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention. JTAG Port Operation Overview The JTAG Port on this RAM operates in a manner that is compliant with IEEE Standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as JTAG). The JTAG Port input interface levels scale with VDD. The JTAG output drivers are powered by VDDQ. Disabling the JTAG Port It is possible to use this device without utilizing the JTAG port. The port is reset at power-up and will remain inactive unless Rev: 1.01 3/2002 33/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) clocked. TCK, TDI, and TMS are designed with internal pull-up circuits.To assure normal operation of the RAM with the JTAG Port unused, TCK, TDI, and TMS may be left floating or tied to either VDD or VSS. TDO should be left unconnected. JTAG Pin Descriptions Pin Pin Name I/O Description TCK Test Clock In Clocks all TAP events. All inputs are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS Test Mode Select In The TMS input is sampled on the rising edge of TCK. This is the command input for the TAP controller state machine. An undriven TMS input will produce the same result as a logic one input level. In The TDI input is sampled on the rising edge of TCK. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP Controller state machine and the instruction that is currently loaded in the TAP Instruction Register (refer to the TAP Controller State Diagram). An undriven TDI pin will produce the same result as a logic one input level. TDI Test Data In TDO Test Data Out Output that is active depending on the state of the TAP state machine. Output changes in Out response to the falling edge of TCK. This is the output side of the serial registers placed between TDI and TDO. Note: This device does not have a TRST (TAP Reset) pin. TRST is optional in IEEE 1149.1. The Test-Logic-Reset state is entered while TMS is held high for five rising edges of TCK. The TAP Controller is also reset automaticly at power-up. JTAG Port Registers Overview The various JTAG registers, refered to as Test Access Port orTAP Registers, are selected (one at a time) via the sequences of 1s and 0s applied to TMS as TCK is strobed. Each of the TAP Registers is a serial shift register that captures serial input data on the rising edge of TCK and pushes serial data out on the next falling edge of TCK. When a register is selected, it is placed between the TDI and TDO pins. Instruction Register The Instruction Register holds the instructions that are executed by the TAP controller when it is moved into the Run, Test/Idle, or the various data register states. Instructions are 3 bits long. The Instruction Register can be loaded when it is placed between the TDI and TDO pins. The Instruction Register is automatically preloaded with the IDCODE instruction at power-up or whenever the controller is placed in Test-Logic-Reset state. Bypass Register The Bypass Register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAM's JTAG Port to another device in the scan chain with as little delay as possible. Boundary Scan Register The Boundary Scan Register is a collection of flip flops that can be preset by the logic level found on the RAM's input or I/O pins. The flip flops are then daisy chained together so the levels found can be shifted serially out of the JTAG Port's TDO pin. The Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.01 3/2002 34/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) JTAG TAP Block Diagram 0 Bypass Register 2 1 0 Instruction Register TDI TDO ID Code Register 31 30 29 · · · · 2 1 0 Boundary Scan Register n · · · · · · · · · 2 1 0 TMS Test Access Port (TAP) Controller TCK Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Die Revision Code GSI Technology JEDEC Vendor ID Code I/O Configuration Not Used Presence Register ID Register Contents Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x72 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 x36 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 x32 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1 1 x18 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 1 0 1 1 0 0 1 1 x16 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 1 1 0 0 1 1 Tap Controller Instruction Set Overview There are two classes of instructions defined in the Standard 1149.1-1990; the standard (Public) instructions, and device specific (Private) instructions. Some Public instructions are mandatory for 1149.1 compliance. Optional Public instructions must be implemented in prescribed ways. The TAP on this device may be used to monitor all input and I/O pads, and can be used to load address, data or control signals into the RAM or to preload the I/O buffers. Rev: 1.01 3/2002 35/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) When the TAP controller is placed in Capture-IR state the two least significant bits of the instruction register are loaded with 01. When the controller is moved to the Shift-IR state the Instruction Register is placed between TDI and TDO. In this state the desired instruction is serially loaded through the TDI input (while the previous contents are shifted out at TDO). For all instructions, the TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. JTAG Tap Controller State Diagram 1 0 Test Logic Reset 0 Run Test Idle 1 Select DR 1 Select IR 0 0 1 1 Capture DR Capture IR 0 0 Shift DR 1 1 1 Shift IR 0 1 1 Exit1 DR 0 Exit1 IR 0 0 Pause DR 1 Exit2 DR 1 0 Pause IR 1 Exit2 IR 0 1 Update DR 1 0 Update IR 1 0 0 0 Instruction Descriptions BYPASS When the BYPASS instruction is loaded in the Instruction Register the Bypass Register is placed between TDI and TDO. This occurs when the TAP controller is moved to the Shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. SAMPLE/PRELOAD SAMPLE/PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the Instruction Register, moving the TAP controller into the Capture-DR state loads the data in the RAMs input and I/O buffers into the Boundary Scan Register. Boundary Scan Register locations are not associated with an input or I/O pin, and are loaded with the default state identified in the Boundary Scan Chain table at the end of this section of the datasheet. Because the RAM clock is independent from the TAP Clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e. in a metastable state). Although allowing the TAP to sample metastable inputs will not harm the device, repeatable results cannot be expected. RAM input signals must be Rev: 1.01 3/2002 36/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) stabilized for long enough to meet the TAPs input data capture set-up plus hold time (tTS plus tTH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the Boundary Scan Register. Moving the controller to ShiftDR state then places the boundary scan register between the TDI and TDO pins. EXTEST EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction register is loaded with all logic 0s. The EXTEST command does not block or override the RAM's input pins; therefore, the RAM's internal state is still determined by its input pins. Typically, the Boundary Scan Register is loaded with the desired pattern of data with the SAMPLE/PRELOAD command. Then the EXTEST command is used to output the Boundary Scan Register's contents, in parallel, on the RAM's data output drivers on the falling edge of TCK when the controller is in the Update-IR state. Alternately, the Boundary Scan Register may be loaded in parallel using the EXTEST command. When the EXTEST instruction is selected, the sate of all the RAM's input and I/O pins, as well as the default values at Scan Register locations not associated with a pin, are transferred in parallel into the Boundary Scan Register on the rising edge of TCK in the Capture-DR state, the RAM's output pins drive out the value of the Boundary Scan Register location with which each output pin is associated. IDCODE The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the Test-Logic-Reset state. SAMPLE-Z If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive drive state (high-Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. JTAG TAP Instruction Set Summary Instruction Code Description Notes EXTEST 000 Places the Boundary Scan Register between TDI and TDO. 1 IDCODE 001 Preloads ID Register and places it between TDI and TDO. 1, 2 SAMPLE-Z 010 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. Forces all RAM output drivers to High-Z. 1 RFU 011 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 SAMPLE/ PRELOAD 100 Captures I/O ring contents. Places the Boundary Scan Register between TDI and TDO. 1 GSI 101 GSI private instruction. 1 RFU 110 Do not use this instruction; Reserved for Future Use. Replicates BYPASS instruction. Places Bypass Register between TDI and TDO. 1 BYPASS 111 Places Bypass Register between TDI and TDO. 1 Notes: 1. Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.01 3/2002 37/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) JTAG Port Recommended Operating Conditions and DC Characteristics Parameter Symbol Min. Max. Unit Notes 3.3 V Test Port Input High Voltage VIHJ3 2.0 VDD3 +0.3 V 1 3.3 V Test Port Input Low Voltage VILJ3 ­0.3 0.8 V 1 2.5 V Test Port Input High Voltage VIHJ2 0.6 * VDD2 VDD2 +0.3 V 1 2.5 V Test Port Input Low Voltage VILJ2 ­0.3 0.3 * VDD2 V 1 TMS, TCK and TDI Input Leakage Current IINHJ ­300 1 uA 2 TMS, TCK and TDI Input Leakage Current IINLJ ­1 100 uA 3 TDO Output Leakage Current IOLJ ­1 1 uA 4 Test Port Output High Voltage VOHJ 1.7 - V 5, 6 Test Port Output Low Voltage VOLJ - 0.4 V 5, 7 Test Port Output CMOS High VOHJC VDDQ ­ 100 mV - V 5, 8 Test Port Output CMOS Low VOLJC - 100 mV V 5, 9 Notes: 1. Input Under/overshoot voltage must be ­2 V > Vi < VDDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tTKC. 2. VILJ VIN VDDn 3. 0 V VIN VILJn 4. Output Disable, VOUT = 0 to VDDn 5. The TDO output driver is served by the VDDQ supply. 6. IOHJ = ­4 mA 7. IOLJ = + 4 mA 8. IOHJC = ­100 uA 9. IOHJC = +100 uA JTAG Port AC Test Conditions Parameter Conditions Input high level 2.3 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level 1.25 V Output reference level 1.25 V 50 30pF* VT = 1.25 V * Distributed Test Jig Capacitance Notes: 1. Include scope and jig capacitance. 2. Test conditions as as shown unless otherwise noted. Rev: 1.01 3/2002 JTAG Port AC Test Load DQ 38/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) JTAG Port Timing Diagram tTKH tTKL tTKC TCK tTS tTH TMS TDI TDO tTKQ JTAG Port AC Electrical Characteristics Parameter Symbol Min Max Unit TCK Cycle Time tTKC 50 - ns TCK Low to TDO Valid tTKQ - 20 ns TCK High Pulse Width tTKH 20 - ns TCK Low Pulse Width tTKL 20 - ns TDI & TMS Set Up Time tTS 10 - ns TDI & TMS Hold Time tTH 10 - ns Rev: 1.01 3/2002 39/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) GS816218/36/72A GS816218/36/72A Boundary Scan Chain Order (Cont.) GS816218/36/72A GS816218/36/72A Boundary Scan Chain Order Order x72 x36 x18 PE 1 x72 x18 29 QA3 NC = 1 N11 n/a 30 DA3 PH = 0 N11 n/a 31 QE3 QA2 QA1 U10 L7 P7 32 DE3 DA2 DA1 U10 L7 P7 33 QA6 NC = 1 M10 n/a 34 DA6 PH = 0 M10 n/a 35 QE7 QA6 QA2 U11 L6 N6 36 DE7 DA6 DA2 U11 L6 N6 37 QA2 NC = 1 M11 n/a 38 DA2 PH = 0 M11 n/a 39 QE6 QA1 QA3 V11 K7 L6 40 DE6 DA1 DA3 V11 K7 L6 41 QA1 NC = 1 L11 n/a 42 DA1 PH = 0 L11 n/a 43 QE2 QA5 QA4 V10 K6 K7 44 DE2 DA5 DA4 V10 K6 K7 45 QA5 NC = 1 L10 n/a 46 DA5 PH = 0 L10 n/a P6 T7 Bump x72 x36 x18 T7 R7 2 A13 X U5 n/a 3 A11 X U7 n/a 4 A3 A10 W5 T3 5 A12 A11 U6 T4 6 A6 A12 V7 T5 7 A2 A13 W7 R6 8 A10 A14 U8 C5 9 A5 A15 V8 B5 10 A4 A16 V9 C6 11 QE9 QA9 NC = 1 R11 P6 n/a 12 DE9 DA9 PH = 0 R11 P6 n/a 13 QA9 NC = 1 R10 n/a 14 DA9 PH = 0 R10 n/a 15 QE5 QA4 NC = 1 W11 P7 n/a 16 DE5 DA4 PH = 0 W11 P7 n/a 17 QA4 NC = 1 P11 n/a 18 DA4 PH = 0 P11 n/a 19 QE1 QA3 NC = 1 W10 N7 n/a 20 DE1 DA3 PH = 0 W10 N7 n/a 21 QA8 NC = 1 P10 n/a 22 DA8 PH = 0 P10 n/a 23 QE4 QA8 NC = 1 T10 N6 n/a 24 DE4 DA8 PH = 0 T10 N6 n/a 25 QA7 NC = 1 N10 n/a 26 DA7 PH = 0 N10 n/a 27 QE8 QA7 NC = 1 T11 M6 n/a 28 DE8 DA7 PH = 0 T11 M6 n/a 47 ZZ 48 49 NC = 1 x72 PH = 0 x36 x18 n/a K11 J5 50 QB1 QA5 A10 H7 H6 51 DB1 DA5 A10 H7 H6 52 QF1 NC = 1 J11 n/a 53 DF1 PH = 0 J11 n/a 54 QB5 QA6 A11 H6 G7 55 DB5 DA6 A11 H6 G7 56 QF5 NC = 1 J10 n/a 57 DF5 PH = 0 J10 n/a 58 Rev: 1.01 3/2002 x36 Bump Order QB2 40/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. QA7 B10 G7 F6 © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) GS816218/36/72A GS816218/36/72A Boundary Scan Chain Order (Cont.) Order x72 x36 x18 DB2 59 DA7 Bump x72 x36 x18 B10 G7 F6 GS816218/36/72A GS816218/36/72A Boundary Scan Chain Order (Cont.) Order x72 x36 x18 Bump x72 x36 x18 89 ADV A7 G4 60 QF2 NC = 1 H11 n/a 90 ADSP A5 A4 61 DF2 PH = 0 H11 n/a 91 ADSC A6 B4 62 QB3 QB6 QA8 C10 G6 E7 92 G D6 F4 63 DB3 DB6 DA8 C10 G6 E7 93 BW B6 M4 64 QF6 NC = 1 H10 n/a 94 GW D7 H4 65 DF6 PH = 0 H10 n/a 95 BH NC = 1 C3 n/a 66 QB6 QB7 QA9 B11 F6 D6 96 BF NC = 1 B3 n/a 67 DB6 DB7 DA9 B11 F6 D6 97 BD NC = 1 B9 n/a 68 QF7 NC = 1 G10 n/a 98 BB NC = 1 C9 n/a 69 DF7 PH = 0 G10 n/a 99 K3 K4 70 QB4 QB3 NC = 1 D10 E7 n/a 100 71 DB4 DB3 PH = 0 D10 E7 n/a 101 72 QF3 NC = 1 G11 n/a 102 73 DF3 PH = 0 G11 n/a 103 74 QB7 QB8 NC = 1 C11 E6 n/a 104 BC BB NC = 1 B8 75 DB7 DB8 PH = 0 C11 E6 n/a 105 BE BC BB B4 76 QF8 NC = 1 F10 n/a 106 BG BD NC = 1 C4 77 DF8 PH = 0 F10 n/a 107 E2 78 QB8 QB4 NC = 1 D11 D7 n/a 108 79 DB8 DB4 PH = 0 D11 D7 n/a 109 A16 80 QF4 NC = 1 F11 n/a 110 A15 81 DF4 PH = 0 F11 n/a 111 QG9 QC9 NC = 1 E1 D2 n/a DC9 PH = 0 E1 D2 n/a CK NC = 1 PH = 0 n/a PH = 0 E3 n/a A17 A8 C8 BA A18 B6 L5 G5 n/a G3 L3 n/a A4 B2 C6 E4 A7 B7 A3 A6 A3 A2 E1 82 QB9 NC = 1 E11 D6 n/a 112 DG9 83 DB9 PH = 0 E11 D6 n/a 113 QC9 NC = 1 E2 n/a PH = 0 E2 n/a 84 QF9 NC = 1 E10 n/a 114 DC9 85 DF9 PH = 0 E10 n/a 115 QG4 QC4 NC = 1 D2 D1 n/a 116 DG4 DC4 PH = 0 D2 D1 n/a NC = 1 86 A19 n/a T6 87 NC = 1 A9 n/a A6 117 QC8 NC = 1 F2 n/a 88 A17 A8 A9 A5 118 DC8 PH = 0 F2 n/a Rev: 1.01 3/2002 41/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) GS816218/36/72A GS816218/36/72A Boundary Scan Chain Order (Cont.) Bump Order x72 x36 x18 119 QG8 QC3 120 DG8 DC3 121 QC4 NC = 1 F1 122 DC4 PH = 0 F1 123 QG7 QC8 NC = 1 C1 E2 124 DG7 DC8 PH = 0 C1 E2 125 QC7 NC = 1 G2 126 DC7 PH = 0 G2 127 QG3 QC7 NC = 1 C2 F2 128 DG3 DC7 PH = 0 C2 F2 129 QC3 NC = 1 G1 130 DC3 PH = 0 G1 131 QG6 QC2 QB1 B1 G1 132 DG6 DC2 DB1 B1 G1 133 QC6 NC = 1 H2 134 DC6 PH = 0 H2 135 QG5 QC6 QB2 A1 G2 136 DG5 DC6 DB2 A1 G2 137 QC2 NC = 1 H1 138 DC2 PH = 0 H1 139 QG2 QC1 QB3 B2 H1 140 DG2 DC1 DB3 B2 H1 141 QC1 NC = 1 J1 142 DC1 PH = 0 J1 143 QG1 QC5 QB4 A2 H2 144 DG1 DC5 DB4 A2 H2 145 QC5 NC = 1 J2 146 DC5 PH = 0 GS816218/36/72A GS816218/36/72A Boundary Scan Chain Order (Cont.) Order x72 x36 Bump x72 x36 x18 x72 x36 x18 NC = 1 D1 E1 n/a 149 PH = 0 D1 E1 n/a 150 QD2 QD1 QB5 V2 K1 K2 n/a 151 DD2 DD1 DB5 V2 K1 K2 n/a 152 QH1 NC = 1 L1 n/a n/a 153 DH1 PH = 0 L1 n/a n/a 154 QD1 QD5 QB6 W2 K2 L1 n/a 155 DD1 DD5 DB6 W2 K2 L1 n/a 156 QH5 NC = 1 L2 n/a n/a 157 DH5 PH = 0 L2 n/a n/a 158 QD5 QD2 QB7 W1 L1 M2 n/a 159 DD5 DD2 DB7 W1 L1 M2 n/a 160 QH2 NC = 1 M1 n/a D1 161 DH2 PH = 0 M1 n/a D1 162 QD6 QB8 V1 L2 N1 n/a 163 DD6 DB8 V1 L2 N1 n/a 164 QH6 NC = 1 M2 n/a E2 165 DH6 PH = 0 M2 n/a E2 166 QD7 QB9 U1 M2 P2 n/a 167 DD7 DB9 U1 M2 P2 n/a 168 QH4 NC = 1 P1 n/a G2 169 DH4 PH = 0 P1 n/a G2 170 QD3 NC = 1 U2 N1 n/a n/a 171 DD3 PH = 0 U2 N1 n/a n/a 172 QH7 NC = 1 N2 n/a H1 173 DH7 PH = 0 N2 n/a H1 174 QD4 QD8 NC = 1 T2 N2 n/a n/a 175 DD4 DD8 PH = 0 T2 N2 n/a J2 n/a 176 QH3 NC = 1 N1 n/a PH = 0 N1 n/a SCD 147 FT L6 R5 177 DH3 148 NC = 1 K9 J3 178 QD8 Rev: 1.01 3/2002 x18 QD4 42/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. N6 NC = 1 T1 L4 P1 n/a © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) GS816218/36/72A GS816218/36/72A Boundary Scan Chain Order (Cont.) Bump Order x72 x36 x18 179 DD8 DD4 PH = 0 180 QH8 NC = 1 P2 n/a 181 DH8 PH = 0 P2 n/a x72 x36 x18 T1 P1 n/a 182 QD9 NC = 1 R1 P2 n/a 183 DD9 PH = 0 R1 P2 n/a 184 QH9 NC = 1 R2 n/a 185 DH9 PH = 0 R2 n/a T6 R3 LBO 186 187 A9 A5 V3 C2 188 A14 A4 U4 B3 189 A8 A3 V4 C3 190 A7 A2 V5 R2 191 A1 V6 N4 192 A0 W6 P4 193 ZQ F6 D4 194 G D6 F4 Notes: 1. Depending on the package, some input pads of the scan chain may not be connected to any external pin. In such case: LBO = 1, ZQ = 1, PE = 0, SD = 0, ZZ = 0, FT = 1, and SCD = 1. 2. Every DQ pad consists of two scan registers-D is for input capture, and Q is for output capture. 3. A single register (#194) for controlling tristate of all the DQ pins is at the end of the scan chain (i.e., the last bit shifted in this tristate control is effective after JTAG EXTEST instruction is executed. 4. 1 = no connect, internally set to logic value 1 5. 0 = no connect, internally set to logic value 0 6. X = no connect, value is undefined 209 BGA Package Drawing (Package C) 14 mm x 22 mm Body, 1.0 mm Bump Pitch, 11 x 19 Bump Rev: 1.01 3/2002 43/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Array C A1 A Side View D aaa D1 b Symbol Min Typ Bottom View e Max Units 1.70 A E E1 e mm A1 0.40 0.50 0.60 mm b 0.50 0.60 0.70 mm c 0.31 0.36 0.38 mm D 21.9 22.0 22.1 mm 18.0 (BSC) D1 E 13.9 14.0 mm 14.1 mm E1 10.0 (BSC) mm e 1.00 (BSC) mm aaa 0.15 mm Rev 1.0 Rev: 1.01 3/2002 44/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Package Dimensions-165-Bump FPBGA (Package D) A1 CORNER TOP VIEW BOTTOM VIEW Ø0.10 M C Ø0.25 M C A B Ø0.40~0.50 (165x) 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H I J K L M N P R 1.0 14.0 15±0.07 1.0 A B C D E F G H I J K L M N P R A 1.0 1.0 10.0 B 0.15 C 0.45±0.05 0.25 C C Rev: 1.01 3/2002 SEATING PLANE 13±0.07 0.20(4x) 0.25~0.40 1.20 MAX. (0.26) A1 CORNER 45/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Package Dimensions-119-Pin PBGA 119-Bump BGA Package (Package B) A Pin 1 Corner 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U A B C D E F G H J K L M N P R T U G B S D R Bottom View Top View T Package Dimensions-119-Pin PBGA Nom. Max Width 13.9 14.0 14.1 Length 21.9 22.0 22.1 C Package Height (including ball) 1.73 1.86 1.99 D Ball Size 0.60 0.75 0.90 E Ball Height 0.50 0.60 0.70 F Package Height (excluding balls) 1.16 1.26 1.36 G Width between Balls K Package Height above board R Width of package between balls 7.62 S Length of package between balls 20.32 T E Min. B Variance of Ball Height 0.15 1.27 0.65 0.70 0.75 C F Description A K Symbol Unit: mm Side View Rev: 1.01 3/2002 46/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Ordering Information for GSI Synchronous Burst RAMs Org Part Number1 Type Package Speed2 (MHz/ns) TA3 1M x 18 GS816218AB-300 GS816218AB-300 S/DCD Pipeline/Flow Through 119 BGA 300/5 C 1M x 18 GS816218AB-275 GS816218AB-275 S/DCD Pipeline/Flow Through 119 BGA 275/5.25 C 1M x 18 GS816218AB-250 GS816218AB-250 S/DCD Pipeline/Flow Through 119 BGA 250/5.5 C 1M x 18 GS816218AB-225 GS816218AB-225 S/DCD Pipeline/Flow Through 119 BGA 225/6 C 1M x 18 GS816218AB-200 GS816218AB-200 S/DCD Pipeline/Flow Through 119 BGA 200/6.5 C 512K x 36 GS816236AB-300 GS816236AB-300 S/DCD Pipeline/Flow Through 119 BGA 300/5 C 512K x 36 GS816236AB-275 GS816236AB-275 S/DCD Pipeline/Flow Through 119 BGA 275/5.25 C 512K x 36 GS816236AB-250 GS816236AB-250 S/DCD Pipeline/Flow Through 119 BGA 250/5.5 C 512K x 36 GS816236AB-225 GS816236AB-225 S/DCD Pipeline/Flow Through 119 BGA 225/6 C 512K x 36 GS816236AB-200 GS816236AB-200 S/DCD Pipeline/Flow Through 119 BGA 200/6.5 C 256K x 72 GS816272AC-300 GS816272AC-300 S/DCD Pipeline/Flow Through 209 BGA 300/5 C 256K x 72 GS816272AC-275 GS816272AC-275 S/DCD Pipeline/Flow Through 209 BGA 275/5.25 C 256K x 72 GS816272AC-250 GS816272AC-250 S/DCD Pipeline/Flow Through 209 BGA 250/5.5 C 256K x 72 GS816272AC-225 GS816272AC-225 S/DCD Pipeline/Flow Through 209 BGA 225/6 C 256K x 72 GS816272AC-200 GS816272AC-200 S/DCD Pipeline/Flow Through 209 BGA 200/6.5 C 1M x 18 GS816218AD-300 GS816218AD-300 S/DCD Pipeline/Flow Through 165 BGA 300/5 C 1M x 18 GS816218AD-275 GS816218AD-275 S/DCD Pipeline/Flow Through 165 BGA 275/5.25 C 1M x 18 GS816218AD-250 GS816218AD-250 S/DCD Pipeline/Flow Through 165 BGA 250/5.5 C 1M x 18 GS816218AD-225 GS816218AD-225 S/DCD Pipeline/Flow Through 165 BGA 225/6 C 1M x 18 GS816218AD-200 GS816218AD-200 S/DCD Pipeline/Flow Through 165 BGA 200/6.5 C 512K x 36 GS816236AD-300 GS816236AD-300 S/DCD Pipeline/Flow Through 165 BGA 300/5 C 512K x 36 GS816236AD-275 GS816236AD-275 S/DCD Pipeline/Flow Through 165 BGA 275/5.25 C 512K x 36 GS816236AD-250 GS816236AD-250 S/DCD Pipeline/Flow Through 165 BGA 250/5.5 C 512K x 36 GS816236AD-225 GS816236AD-225 S/DCD Pipeline/Flow Through 165 BGA 225/6 C 512K x 36 GS816236AD-200 GS816236AD-200 S/DCD Pipeline/Flow Through 165 BGA 200/6.5 C 1M x 18 GS816218AB-300I GS816218AB-300I S/DCD Pipeline/Flow Through 119 BGA 300/5 I 1M x 18 GS816218AB-275I GS816218AB-275I S/DCD Pipeline/Flow Through 119 BGA 275/5.25 I 1M x 18 GS816218AB-250I GS816218AB-250I S/DCD Pipeline/Flow Through 119 BGA 250/5.5 I 1M x 18 GS816218AB-225I GS816218AB-225I S/DCD Pipeline/Flow Through 119 BGA 225/6 I 1M x 18 GS816218AB-200I GS816218AB-200I S/DCD Pipeline/Flow Through 119 BGA 200/6.5 I Status Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS816218AB-200IB GS816218AB-200IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.01 3/2002 47/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) Org Part Number1 Type Package Speed2 (MHz/ns) TA3 512K x 36 GS816236AB-300I GS816236AB-300I S/DCD Pipeline/Flow Through 119 BGA 300/5 I 512K x 36 GS816236AB-275I GS816236AB-275I S/DCD Pipeline/Flow Through 119 BGA 275/5.25 I 512K x 36 GS816236AB-250I GS816236AB-250I S/DCD Pipeline/Flow Through 119 BGA 250/5.5 I 512K x 36 GS816236AB-225I GS816236AB-225I S/DCD Pipeline/Flow Through 119 BGA 225/6 I 512K x 36 GS816236AB-200I GS816236AB-200I S/DCD Pipeline/Flow Through 119 BGA 200/6.5 I 256K x 72 GS816272AC-300I GS816272AC-300I S/DCD Pipeline/Flow Through 209 BGA 300/5 I 256K x 72 GS816272AC-275I GS816272AC-275I S/DCD Pipeline/Flow Through 209 BGA 275/5.25 I 256K x 72 GS816272AC-250I GS816272AC-250I S/DCD Pipeline/Flow Through 209 BGA 250/5.5 I 256K x 72 GS816272AC-225I GS816272AC-225I S/DCD Pipeline/Flow Through 209 BGA 225/6 I 256K x 72 GS816272AC-200I GS816272AC-200I S/DCD Pipeline/Flow Through 209 BGA 200/6.5 I 1M x 18 GS816218AD-300I GS816218AD-300I S/DCD Pipeline/Flow Through 165 BGA 300/5 I 1M x 18 GS816218AD-275I GS816218AD-275I S/DCD Pipeline/Flow Through 165 BGA 275/5.25 I 1M x 18 GS816218AD-250I GS816218AD-250I S/DCD Pipeline/Flow Through 165 BGA 250/5.5 I 1M x 18 GS816218AD-225I GS816218AD-225I S/DCD Pipeline/Flow Through 165 BGA 225/6 I 1M x 18 GS816218AD-200I GS816218AD-200I S/DCD Pipeline/Flow Through 165 BGA 200/6.5 I 512K x 36 GS816236AD-300I GS816236AD-300I S/DCD Pipeline/Flow Through 165 BGA 300/5 I 512K x 36 GS816236AD-275I GS816236AD-275I S/DCD Pipeline/Flow Through 165 BGA 275/5.25 I 512K x 36 GS816236AD-250I GS816236AD-250I S/DCD Pipeline/Flow Through 165 BGA 250/5.5 I 512K x 36 GS816236AD-225I GS816236AD-225I S/DCD Pipeline/Flow Through 165 BGA 225/6 I 512K x 36 GS816236AD-200I GS816236AD-200I S/DCD Pipeline/Flow Through 165 BGA 200/6.5 I Status Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS816218AB-200IB GS816218AB-200IB. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings. Rev: 1.01 3/2002 48/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc. Preliminary GS816218A GS816218A(B/D)/GS816236A /GS816236A(B/D)/GS816272A /GS816272A(C) 18Mb Sync SRAM Datasheet Revision History DS/DateRev. Code: Old; New Types of Changes Format or Content · Creation of new datasheet 816218A 816218A_r1 816218A 816218A_r1; 816218_r1_01 Rev: 1.01 3/2002 Page;Revisions;Reason Content · Updated Flow Through power numbers in table on page 1 and Operating Currents table · Updated Pipeline and Flow Through numbers in AC Characteristics table · Added 165-bump BGA package, pinout, and pinout description · Removed ByteSafe pins and references · Updated ZZ timing diagram · Updated AC Test Conditions table and removed Output Load 2 diagram 49/49 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. © 2001, Giga Semiconductor, Inc.