GS4911B/GS4910B GS4911B 10FID 64-PIN GS4910B 318-M RP174 125M/267M VG901101A - Datasheet Archive

 

HD/SD/Graphics Clock and Timing Generator with GENLOCK GS4911B/GS4910B Data Sheet Key Features Description Video Clock Synthesis

 

GS4911B/GS4910B GS4911B/GS4910B HD/SD/Graphics Clock and Timing Generator with GENLOCK GS4911B/GS4910B GS4911B/GS4910B Data Sheet Key Features Description Video Clock Synthesis The GS4911B GS4911B is a highly flexible, digitally controlled clock synthesis circuit and timing generator with genlock capability. It can be used to generate video and audio clocks and timing signals, and allows multiple devices to be genlocked to an input reference. · · · · · · Generates any video or graphics clock up to 165MHz Pre-programmed for 8 video and 13 graphics clocks Accuracy of free-running clock frequency limited only by crystal reference One differential and two single-ended video/graphics clock outputs Each clock may be individually delayed for skew control Video output clock may be directly connected to Gennum's serializers for a SMPTE-compliant HD-SDI output Audio Clock Synthesis (GS4911B GS4911B only) · · · Three audio clock outputs Generates any audio clock up to 512*96kHz Pre-programmed for 7 audio clocks Timing Generation · · · Generates up to 8 timing signals at a time Choose from 9 pre-programmed timing signals: H and V sync and blanking, F Sync, F Digital, AFS (GS4911B GS4911B only), Display Enable, 10FID 10FID, and up to 4 user-defined timing signals Pre-programmed to generate timing for 35 different video formats and 13 different graphic display formats Genlock Capability · · · · · · Clocks may be free-running or genlocked to an input reference with a variable offset step size of 100-200ps (depending on exact clock frequency) Variable timing offset step size of 100-200ps up to one frame Output may be cross-locked to a different input reference Freeze operation on loss of reference Optional crash or drift lock on application of reference Automatic input format detection General Features · · · · · Reduces design complexity and saves board space 9mm x 9mm package plus crystal reference replaces multiple VCXOs, PLLs and timing generators Pb-free and RoHS Compliant Low power operation typically 300mW 1.8V core and 1.8V or 3.3V I/O power supplies 64-PIN 64-PIN QFN package Applications · Video cameras; Digital audio and/or video recording/play back devices; Digital audio and/or video processing devices; Computer/video displays; DVD/MPEG devices; Digital Set top boxes; Video projectors; High definition video systems; Multi-media PC applications The GS4910B GS4910B includes all the features of the GS4911B GS4911B, but does not offer audio clocks or AFS pulse generation. The GS4911B/GS4910B GS4911B/GS4910B will recognize input reference signals conforming to 36 different video standards and 16 different graphic formats, and will genlock the output timing information to the incoming reference. The GS4911B/GS4910B GS4911B/GS4910B supports cross-locking, allowing the output to be genlocked to an incoming reference that is different from the output video standard selected. The user may select to output one of 8 different video sample clock rates or 13 different graphic display clock rates, or may program any clock frequency between 13.5MHz and 165MHz. The chosen clock frequency can be further divided using internal dividers, and is available on two video clock outputs and one LVDS video clock output pair. The video clocks are frequency and phased-locked to the horizontal timing reference, and can be individually delayed with respect to the timing outputs for clock skew control. Eight user-selectable timing outputs are provided that can automatically produce the following timing signals for 35 different video formats and 13 different graphics formats: HSync, Hblanking, VSync, Vblanking, F sync, F digital, AFS (GS4911B GS4911B only), DE, and 10FID 10FID. These timing outputs may be locked to the input reference signal for genlock timing and may be phase adjusted via internal registers. In addition, the GS4911B GS4911B provides three audio sample clock outputs that can produce audio clocks up to 512fs with fs ranging from 9.7kHz to 96kHz. Audio to video phasing is accomplished by an external 10FID 10FID input reference, a 10FID 10FID signal specified via internal registers, or a user-programmed audio frame sequence. The GS4911B/GS4910B GS4911B/GS4910B is Pb-free, and the encapsulation compound does not contain halogenated flame retardant (RoHS Compliant). 36655 - 4 April 2007 1 of 113 www.gennum.com LOCK_LOST VID_STD[5:0] GENLOCK ASR_SEL[2:0] X1 X2 GS4911B/GS4910B GS4911B/GS4910B Data Sheet user[4:1] 27MHz Input Reference Rate Identification and Control ref_rate REF_LOST Flywheel and Video Timing Generator AFS 10FID 10FID DE F digital F sync V blanking V sync TIMING_OUT_8 TIMING_OUT_7 TIMING_OUT_6 Crosspoint TIMING_OUT_4 TIMING_OUT_3 TIMING_OUT_2 H blanking H sync Clock Synthesis and Control TIMING_OUT_5 TIMING_OUT_1 PCLK1 Clock Phase Adjust pclk Video Clock Divide 3x Video Clock Delay Adjust PCLK2 PCLK3 PCLK3 aclk_512 aclk_384 Audio Clock Divide ACLK1 ACLK2 ACLK3 HSYNC VSYNC FSYNC 10FID 10FID CS_TMS SDIN_TDI SDOUT_TDO SCLK_TCLK JTAG/HOST Application Programming Interace GS4911B GS4911B Functional Block Diagram 36655 - 4 April 2007 2 of 113 LOCK_LOST VID_STD[5:0] GENLOCK X1 X2 GS4911B/GS4910B GS4911B/GS4910B Data Sheet user[4:1] 27MHz Input Reference Rate Identification and Control ref_rate REF_LOST Flywheel and Video Timing Generator 10FID 10FID DE F digital F sync V blanking V sync TIMING_OUT_8 TIMING_OUT_7 TIMING_OUT_6 Crosspoint TIMING_OUT_5 TIMING_OUT_4 TIMING_OUT_3 H blanking H sync TIMING_OUT_2 TIMING_OUT_1 Clock Synthesis and Control PCLK1 Clock Phase Adjust pclk Video Clock Divide 3x Video Clock Delay Adjust PCLK2 PCLK3 PCLK3 HSYNC VSYNC FSYNC 10FID 10FID CS_TMS SDIN_TDI SDOUT_TDO SCLK_TCLK JTAG/HOST Application Programming Interace GS4910B GS4910B Functional Block Diagram 36655 - 4 April 2007 3 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet Contents Key Features .1 Applications.1 Description .1 1. Pin Out .8 1.1 GS4911B GS4911B Pin Assignment .8 1.2 GS4910B GS4910B Pin Assignment .9 1.3 Pin Descriptions .10 1.4 Pre-Programmed Recognized Video and Graphics Standards .20 1.5 Output Timing Signals .25 2. Electrical Characteristics .29 2.1 Absolute Maximum Ratings .29 2.2 DC Electrical Characteristics .29 2.3 AC Electrical Characteristics .31 2.4 Solder Reflow Profiles .35 3. Detailed Description .36 3.1 Functional Overview .36 3.2 Modes of Operation .36 3.2.1 Genlock Mode.37 3.2.2 Free Run Mode.40 3.3 Output Timing Format Selection .42 3.4 Input Reference Signals .43 3.4.1 HSYNC, VSYNC, and FSYNC.43 3.4.2 10FID 10FID .44 3.4.3 Automatic Polarity Recognition .45 3.5 Reference Format Detector .45 3.5.1 Horizontal and Vertical Timing Characteristic Measurements .45 3.5.2 Input Reference Validity.45 3.5.3 Behaviour on Loss and Re-acquisition of the Reference Signal.47 3.5.4 Allowable Frequency Drift on the Reference .49 3.6 Genlock .50 3.6.1 Automatic Locking Process .50 3.6.2 Manual Locking Process.54 3.6.3 Adjustable Locking Time.58 3.6.4 Adjustable Loop Bandwidth .58 3.6.5 Locking to Digital Timing from a Deserializer .60 3.7 Clock Synthesis .61 3.7.1 Video Clock Synthesis .61 3.7.2 Audio Clock Synthesis (GS4911B GS4911B only) .63 3.8 Video Timing Generator .67 3.8.1 10 Field ID Pulse .67 36655 - 4 April 2007 4 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet 3.8.2 Audio Frame Synchronizing Pulse (GS4911B GS4911B only) .68 3.8.3 USER_1~4.69 3.8.4 TIMING_OUT Pins.71 3.9 Custom Clock Generation .72 3.9.1 Programming a Custom Video Clock.72 3.9.2 Programming a Custom Audio Clock (GS4911B GS4911B only) .73 3.10 Custom Output Timing Signal Generation .74 3.10.1 Custom Input Reference.74 3.11 Extended Audio Mode for HD Demux using the Gennum Audio Core .75 3.12 GSPI Host Interface .76 3.12.1 Command Word Description.77 3.12.2 Data Read and Write Timing .77 3.12.3 Configuration and Status Registers .79 3.13 JTAG .105 3.14 Device Power-Up .106 3.14.1 Power Supply Sequencing.106 3.15 Device Reset .106 4. Application Reference Design .107 4.1 GS4911B GS4911B Typical Application Circuit .107 4.2 GS4910B GS4910B Typical Application Circuit .108 5. References & Relevant Standards .109 6. Package & Ordering Information .110 6.1 Package Dimensions .110 6.2 Recommended PCB Footprint .111 6.3 Packaging Data .111 6.4 Ordering Information .112 7. Revision History .113 36655 - 4 April 2007 5 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet List of Figures GS4911B GS4911B Functional Block Diagram. 2 GS4910B GS4910B Functional Block Diagram. 3 Figure 1-1: XTAL1 and XTAL2 Reference Circuits .19 Figure 2-1: PCLK to TIMING_OUT Signal Output Timing .34 Figure 2-2: Maximum Pb-free Solder Reflow Profile (preferred) .35 Figure 2-3: Standard Pb Solder Reflow Profile .35 Figure 3-1: HD-SD Calculation .39 Figure 3-2: Output Accuracy and Modes of Operation .41 Figure 3-3: Example HSYNC, VSYNC, and FSYNC Analog Input Timing from a Sync Separator .43 Figure 3-4: Example H Blanking, V Blanking, and F Digital Input Timing from an SDI Deserializer .43 Figure 3-5: 10FID 10FID Input Timing .44 Figure 3-6: Internal Video Genlock Block .54 Figure 3-7: Internal Audio Genlock Block .56 Figure 3-8: Default 10FID 10FID Output Timing .67 Figure 3-9: Optional 10FID 10FID Output Timing .68 Figure 3-10: AFS Output Timing .69 Figure 3-11: USER Programmable Output Signal .70 Figure 3-12: Custom Timing Parameters .74 Figure 3-13: Audio Clock Block Diagram for HD Demux Operation .75 Figure 3-14: GSPI Application Interface Connection .76 Figure 3-15: Command Word Format .77 Figure 3-16: Data Word Format .77 Figure 3-17: GSPI Read Mode Timing .78 Figure 3-18: GSPI Write Mode Timing .78 Figure 3-19: In-Circuit JTAG .105 Figure 3-20: System JTAG .106 36655 - 4 April 2007 6 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet List of Tables Table 1-1: Pin Descriptions . 10 Table 1-2: Recognized Video and Graphics Standards . 21 Table 1-3: Output Timing Signals. 25 Table 2-1: DC Electrical Characteristics . 29 Table 2-2: AC Electrical Characteristics. 31 Table 2-3: Suggested External Crystal Specification . 34 Table 3-1: Clock_Phase_Offset[15:0] Encoding Scheme . 38 Table 3-2: Ambiguous Standard Identification . 47 Table 3-3: Max_Ref_Delta Encoding Scheme . 49 Table 3-4: Cross-reference Genlock Table . 52 Table 3-5: Integer Constant Value . 57 Table 3-6: Video Clock Phase Adjustment Host Settings . 62 Table 3-7: Audio Sample Rate Select . 63 Table 3-8: Audio Clock Divider. 64 Table 3-9: Encoding Scheme for AFS_Reset_Window . 65 Table 3-10: Audio Sampling Frequency to Video Frame Rate Synchronization . 66 Table 3-11: Crosspoint Select . 71 Table 3-12: GSPI Timing Parameters . 78 Table 3-13: Configuration and Status Registers . 79 Table 5-1: References & Relevant Standards. 109 36655 - 4 April 2007 7 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet 1. Pin Out LOCK_LOST REF_LOST 1 PCLK2 PCLK1 IO_VDD PCLK1&2_VDD PCLK1&2_GND PhS_VDD JTAG/HOST PhS_GND SDIN_TDI SCLK_TCLK SDOUT_TDO RESET CS_TMS IO_VDD GENLOCK NC 1.1 GS4911B GS4911B Pin Assignment 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 LVDS/PCLK3_GND 2 47 PCLK3 VID_PLL_VDD 3 46 PCLK3 VID_PLL_GND 4 45 LVDS/PCLK3_VDD XTAL_VDD 5 44 X1 6 43 CORE_VDD TIMING_OUT_8 42 TIMING_OUT_7 41 X2 8 CORE_GND GS4911B GS4911B 64-pin QFN (Top View) 7 XTAL_GND 9 40 TIMING_OUT_6 TIMING_OUT_5 ANALOG_VDD NC 10 39 TIMING_OUT_4 11 38 IO_VDD ANALOG_GND 12 37 TIMING_OUT_3 AUD_PLL_GND 13 36 TIMING_OUT_2 AUD_PLL_VDD 14 35 TIMING_OUT_1 10FID 10FID HSYNC 34 15 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ASR_SEL0 ASR_SEL1 ASR_SEL2 IO_VDD ACLK3 ACLK2 ACLK1 VID_STD5 VID_STD4 CORE_VDD VID_STD3 VID_STD2 VID_STD1 VID_STD0 NC FSYNC IO_VDD VSYNC Ground Pad (bottom of package) 36655 - 4 April 2007 8 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet LOCK_LOST REF_LOST 1 PCLK2 PCLK1 IO_VDD PCLK1&2_GND PhS_VDD PCLK1&2_VDD JTAG/HOST PhS_GND SDIN_TDI SCLK_TCLK SDOUT_TDO CS_TMS RESET IO_VDD GENLOCK NC 1.2 GS4910B GS4910B Pin Assignment 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 LVDS/PCLK3_GND 2 47 PCLK3 VID_PLL_VDD 3 46 PCLK3 VID_PLL_GND 4 45 LVDS/PCLK3_VDD XTAL_VDD 5 44 X1 6 43 CORE_VDD TIMING_OUT_8 X2 7 42 TIMING_OUT_7 41 40 TIMING_OUT_6 TIMING_OUT_5 XTAL_GND 8 CORE_GND GS4910B GS4910B 64-pin QFN (Top View) 9 ANALOG_VDD NC 10 39 TIMING_OUT_4 11 38 IO_VDD ANALOG_GND 12 37 TIMING_OUT_3 ANALOG_GND ANALOG_GND 10FID 10FID 13 36 TIMING_OUT_2 14 35 TIMING_OUT_1 34 15 16 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ANALOG_GND HSYNC ANALOG_GND ANALOG_GND IO_VDD NC NC NC VID_STD5 CORE_VDD VID_STD4 VID_STD3 VID_STD2 VID_STD1 VID_STD0 NC FSYNC VSYNC IO_VDD Ground Pad (bottom of package) 36655 - 4 April 2007 9 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet 1.3 Pin Descriptions Table 1-1: Pin Descriptions Pin Number 1 Name Timing Type Description LOCK_LOST Non Synchronous Output STATUS SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. This pin will be HIGH if the output is not genlocked to the input. The GS4911B/GS4910B GS4911B/GS4910B monitors the output pixel/line counters, as well as the internal lock status from the genlock block and asserts LOCK_LOST HIGH if it is determined that the output is not genlocked to the input. This pin will be LOW if the device successfully genlocks the output clock and timing signals to the input reference. If LOCK_LOST is LOW, the reference timing generator outputs will be phase locked to the detected reference signal, producing an output in accordance with the video standard selected by the VID_STD[5:0] pins. 2 REF_LOST Non Synchronous Output STATUS SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. This pin will be HIGH if: · No input reference signal is applied to the device; or · The input reference applied does not meet the minimum/maximum timing requirements described in Section 3.5.2 on page 46. This pin will be LOW otherwise. If the reference signal is removed when the device is in Genlock mode, REF_LOST will go HIGH and the GS4911B/GS4910B GS4911B/GS4910B will enter Freeze mode (see Section 3.2.1.2 on page 41). 3 VID_PLL_VDD ­ Power Supply Most positive power supply connection for the video clock synthesis internal block. Connect to +1.8V DC. 4 VID_PLL_GND ­ Power Supply Ground connection for the video clock synthesis internal block. Connect to GND. 5 XTAL_VDD ­ Power Supply Most positive power supply connection for the crystal buffer. Connect to either +1.8V DC or +3.3V DC. NOTE: Connect to +3.3V for minimum output PCLK jitter. 6 7 X1 X2 Non Synchronous Input Non Synchronous Output ANALOG SIGNAL INPUT Connect to a 27MHz crystal or a 27MHz external clock source. See Figure 1-1. ANALOG SIGNAL OUTPUT Connect to a 27MHz crystal, or leave this pin open circuit if an external clock source is applied to pin 6. See Figure 1-1. 8 XTAL_GND ­ Power Supply Ground connection for the crystal buffer. Connect to GND. 9 CORE_GND ­ Power Supply Ground connection for core and I/O. Solder to the ground plane of the application board. NOTE: The CORE_GND pin should be soldered to the same main ground plane as the exposed ground pad on the bottom of the device. 10 11, 20, 63 ANALOG_VDD ­ Power Supply Most positive power supply connection for the analog input block. Connect to +1.8V DC. NC ­ ­ Do not connect. 36655 - 4 April 2007 10 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description 12 ANALOG_GND ­ Power Supply Ground connection for the analog input block. Connect to GND. 13 AUD_PLL_GND (GS4911B GS4911B only) ­ Power Supply Ground connection for the audio clock synthesis internal block. Connect to GND. ANALOG_GND (GS4910B GS4910B only) ­ Power Supply Ground connection for the analog input block. Connect to GND. AUD_PLL_VDD (GS4911B GS4911B only) ­ Power Supply Most positive power supply connection for the audio clock synthesis internal block. Connect to +1.8V DC. ANALOG_GND (GS4910B GS4910B only) ­ Power Supply Ground connection for the analog input block. Connect to GND. 10FID 10FID Non Synchronous Input REFERENCE SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. 14 15 The 10FID 10FID external reference signal is applied to this pin by the application layer. 10FID 10FID defines the field in which the video and audio clock phase relationship is defined according to SMPTE 318-M 318-M. It is also used to define a 3:2 video cadence. NOTE: If the input reference format does not include a 10 Field ID signal, this pin should be held LOW. See Section 3.4.2 on page 45. 16 HSYNC Non Synchronous Input REFERENCE SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. The HSYNC external reference signal is applied to this pin by the application layer. When the GS4911B/GS4910B GS4911B/GS4910B is operating in Genlock mode, the device senses the polarity of the HSYNC input automatically, and references to the leading edge. If the user wishes to select one of the pre-programmed video and/or timing output signals provided by the device, then this signal must adhere to one of the 36 defined video or 16 different graphics display standards supported by the device. In this mode of operation, the HSYNC input provides a horizontal scanning reference signal. The HSYNC signal may have analog timing, such as from a sync separator, or may be digital such as from an SDI deserializer. Section 1.4 on page 20 describes the 36 video formats and 16 graphic formats recognized by the GS4911B/GS4910B GS4911B/GS4910B. 17 VSYNC Non Synchronous Input REFERENCE SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. The VSYNC external reference signal is applied to this pin by the application layer. When the GS4911B/GS4910B GS4911B/GS4910B is operating in Genlock mode, the device senses the polarity of the VSYNC input automatically, and references to the leading edge. If the user wishes to select one of the pre-programmed video and/or timing output signals provided by the device, then this signal must adhere to one of the 36 defined video or 16 different graphics display standards supported by the device. In this mode of operation, the VSYNC input provides a vertical scanning reference signal. The VSYNC signal may have analog timing, such as from a sync separator, or may be digital such as from an SDI deserializer. Section 1.4 on page 20 describes the 36 video formats and 16 graphic formats recognized by the GS4911B/GS4910B GS4911B/GS4910B. 18, 31, 38, 50, 62 IO_VDD ­ Power Supply Most positive power supply connection for the digital I/O signals. Connect to either +1.8V DC or +3.3V DC. NOTE: All five IO_VDD pins must be powered by the same voltage. 36655 - 4 April 2007 11 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 19 Name Timing Type Description FSYNC Non Synchronous Input REFERENCE SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. The FSYNC external reference signal is applied to this pin by the application layer. The first field is defined as the field in which the first broad pulse (also known as serration) is in the first half of a line. The FSYNC signal should be set HIGH during the first field for sync-based references. If the user wishes to select one of the pre-programmed video and/or timing output signals provided by the device, then this signal must adhere to one of the 36 defined video or 16 different graphics display standards supported by the device. In this mode of operation, the FSYNC input provides an odd/even field input reference. The FSYNC signal may have analog timing, such as from a sync separator, or may be digital such as from an SDI deserializer. Section 1.4 on page 20 describes the 36 video formats and 16 graphic formats recognized by the GS4911B/GS4910B GS4911B/GS4910B. For blanking-based references, the FSYNC signal should be set HIGH during the second field. NOTE: If the input reference format does not include an F sync signal, this pin should be held LOW. 27, 25, 24, 23, 22, 21 VID_STD[5:0] Non Synchronous Input CONTROL SIGNAL INPUTS Signal levels are LVCMOS/LVTTL compatible. Video Standard Select. Used to select the desired video/graphic display format for video clock and timing signal generation. 8 different video and 13 different graphic sample clocks, as well as 35 different video format and 13 different graphic format timing signal outputs may be selected using these pins. For details on the supported video standards and video clock frequency selection, please see Section 1.4 on page 20. 26, 44 CORE_VDD ­ 36655 - 4 Power Supply April 2007 Most positive power supply connection for the digital core. Connect to +1.8V DC. 12 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description 28, 29, 30 ACLK1 ­ Output ACLK2 CLOCK SIGNAL OUTPUTS Signal levels are LVCMOS/LVTTL compatible. ACLK3 Audio output clock signals. (GS4911B GS4911B only) ACLK1, ACLK2, and ACLK3 present audio sample rate clock outputs to the application layer. By default, after system reset, the audio clock output pins of the device provide clock signals as follows: ACLK1 = 256fs ACLK2 = 64fs ACLK3 = fs, where fs is the fundamental sampling frequency. The fundamental sampling frequency is selected using ASR_SEL[2:0]. Additional sampling frequencies may be programmed in the host interface. It is also possible to select different division ratios for each of the audio clock outputs by programming designated registers in the host interface. Clock outputs of 512fs, 384fs, 256fs, 192fs, 128fs, 64fs, fs and z bit are selectable on a pin-by-pin basis. NOTE: ACLK1-3 will have a 50% duty cycle, unless fs is selected as 96kHz and the host interface is configured such that one of the three ACLK pins is set to output a clock signal at 192fs or 384fs. If this is the case, then a 512fs clock will have a 33% duty cycle. These signals will be high impedance when ASR_SEL[2:0] = 000b. NC (GS4910B GS4910B only) 32, 33, 34 ­ ­ Do not connect. ASR_SEL[2:0] Non Synchronous Input CONTROL SIGNAL INPUTS Signal levels are LVCMOS/LVTTL compatible. (GS4911B GS4911B only) Audio Sample Rate Select. Used to select the fundamental sampling frequency, fs, of the audio clock outputs. See Table 3-7. When ASR_SEL[2:0] = 000b, audio clock generation will be disabled and the ACLK1 to ACLK3 pins will be high impedance. In this case, AUD_PLL_VDD (pin 14) may be connected to GND to minimize noise and power consumption. ANALOG_GND (GS4910B GS4910B only) 35 ­ Power Supply Ground connection for the analog input block. Connect to GND. TIMING_OUT_1 Synchronous with PCLK1 ~ PCLK3 Output TIMING SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Selectable timing output. Selectable from: H sync; H blanking; V sync; V blanking; F sync; F digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing (GS4911B GS4911B only); USER_1~4. See Section 1.5 on page 26 for signal descriptions. NOTE: Default output is H Sync. The current drive capability of this pin may be set high or low via designated registers in the host interface. By default, the current drive will be low. This signal will be high impedance when VID_STD[5:0] = 00h. 36655 - 4 April 2007 13 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 36 Name Timing Type Description TIMING_OUT_2 Synchronous with PCLK1 ~ PCLK3 Output TIMING SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Selectable timing output. Selectable from: H sync; H blanking; V sync; V blanking; F sync; F digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing (GS4911B GS4911B only); USER_1~4. See Section 1.5 on page 26 for signal descriptions. NOTE: Default output is H blanking. The current drive capability of this pin may be set high or low via designated registers in the host interface. By default, the current drive will be low. This signal will be high impedance when VID_STD[5:0] = 00h. 37 TIMING_OUT_3 Synchronous with PCLK1 ~ PCLK3 Output TIMING SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Selectable timing output. Selectable from: H sync; H blanking; V sync; V blanking; F sync; F digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing (GS4911B GS4911B only); USER_1~4. See Section 1.5 on page 26 for signal descriptions. NOTE: Default output is V Sync. The current drive capability of this pin may be set high or low via designated registers in the host interface. By default, the current drive will be low. This signal will be high impedance when VID_STD[5:0] = 00h. 39 TIMING_OUT_4 Synchronous with PCLK1 ~ PCLK3 Output TIMING SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Selectable timing output. Selectable from: H sync; H blanking; V sync; V blanking; F sync; F digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing (GS4911B GS4911B only); USER_1~4. See Section 1.5 on page 26 for signal descriptions. NOTE: Default output is V blanking. The current drive capability of this pin may be set high or low via designated registers in the host interface. By default, the current drive will be low. This signal will be high impedance when VID_STD[5:0] = 00h. 40 TIMING_OUT_5 Synchronous with PCLK1 ~ PCLK3 Output TIMING SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Selectable timing output. Selectable from: H sync; H blanking; V sync; V blanking; F sync; F digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing (GS4911B GS4911B only); USER_1~4. See Section 1.5 on page 26 for signal descriptions. NOTE: Default output is F Sync. The current drive capability of this pin may be set high or low via designated registers in the host interface. By default, the current drive will be low. This signal will be high impedance when VID_STD[5:0] = 00h. 36655 - 4 April 2007 14 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 41 Name Timing Type Description TIMING_OUT_6 Synchronous with PCLK1 ~ PCLK3 Output TIMING SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Selectable timing output. Selectable from: H sync; H blanking; V sync; V blanking; F sync; F digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing (GS4911B GS4911B only); USER_1~4. See Section 1.5 on page 26 for signal descriptions. NOTE: Default output is F digital. The current drive capability of this pin may be set high or low via designated registers in the host interface. By default, the current drive will be low. This signal will be high impedance when VID_STD[5:0] = 00h. 42 TIMING_OUT_7 Synchronous with PCLK1 ~ PCLK3 Output TIMING SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Selectable timing output. Selectable from: H sync; H blanking; V sync; V blanking; F sync; F digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing (GS4911B GS4911B only); USER_1~4. See Section 1.5 on page 26 for signal descriptions. NOTE: Default output is 10 Field ID (10FID 10FID). The current drive capability of this pin may be set high or low via designated registers in the host interface. By default, the current drive will be low. This signal will be high impedance when VID_STD[5:0] = 00h. 43 TIMING_OUT_8 Synchronous with PCLK1 ~ PCLK3 Output TIMING SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Selectable timing output. Selectable from: H sync; H blanking; V sync; V blanking; F sync; F digital; Display Enable; 10 field ID (film cadence); AFS video/audio timing (GS4911B GS4911B only); USER_1~4. See Section 1.5 on page 26 for signal descriptions. NOTE: Default output is Display Enable (DE). The current drive capability of this pin may be set high or low via designated registers in the host interface. By default, the current drive will be low. This signal will be high impedance when VID_STD[5:0] = 00h. 45 LVDS/PCLK3_VDD ­ 36655 - 4 Power Supply April 2007 Most positive power supply connection for PCLK3 output circuitry and LVDS driver. Connect to +1.8V DC. 15 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 46, 47 Name Timing Type Description PCLK3, PCLK3 ­ Output CLOCK SIGNAL OUTPUTS Signal levels are LVDS compatible. Differential video clock output signal. PCLK3/PCLK3 present a differential video sample rate clock output to the application layer. By default, after system reset, this output will operate at the fundamental frequency determined by the setting of the VID_STD[5:0] pins. It is possible to define other non-standard fundamental clock rates using the host interface. It is also possible to select different division ratios for the PCLK3/PCLK3 outputs by programming designated registers in the host interface. A clock output of the fundamental rate, fundamental rate ÷2, or fundamental rate ÷4 may be selected. The PCLK3/PCLK3 outputs will be high impedance when VID_STD[5:0] = 00h. 48 LVDS/PCLK3_GND ­ Power Supply Ground connection for PCLK3 output circuitry and LVDS driver. Connect to GND. 49 PCLK2 ­ Output CLOCK SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Video clock output signal. PCLK2 presents a video sample rate clock output to the application layer. By default, after system reset, the PCLK2 output pin will operate at the fundamental frequency determined by the setting of the VID_STD[5:0] pins. It is possible to define other non-standard fundamental clock rates using the host interface. It is also possible to select different division ratios for the PCLK2 output by programming designated registers in the host interface. A clock output of the fundamental rate, fundamental rate ÷2, or fundamental rate ÷4 may be selected. By setting designated registers in the host interface, the current drive capability of this pin may be set high or low. By default, the current drive will be low. It must be set high if the clock rate is greater than 100MHz. The PCLK2 output will be held LOW when VID_STD[5:0] = 00h. 51 PCLK1 ­ Output CLOCK SIGNAL OUTPUT Signal levels are LVCMOS/LVTTL compatible. Video clock output signal. PCLK1 presents a video sample rate clock output to the application layer. By default, after system reset, the PCLK1 output pin will operate at the fundamental frequency determined by the setting of the VID_STD[5:0] pins. It is possible to define other non-standard fundamental clock rates using the host interface. It is also possible to select different division ratios for the PCLK1 output by programming designated registers in the host interface. A clock output of the fundamental rate, fundamental rate ÷2, or fundamental rate ÷4 may be selected. By setting designated registers in the host interface, the current drive capability of this pin may be set high or low. By default, the current drive will be low. It must be set high if the clock rate is greater than 100MHz. The PCLK1 output will be held LOW when VID_STD[5:0] = 00h. 36655 - 4 April 2007 16 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description 52 PCLK1&2_GND ­ Power Supply Ground connection for PCLK1&2 circuitry. Connect to GND. 53 PCLK1&2_VDD ­ Power Supply Most positive power supply connection for PCLK1&2 circuitry. Connect to +1.8V DC. 54 PhS_VDD ­ Power Supply Most positive power supply connection for the video clock phase shift internal block. Connect to +1.8V DC. 55 PhS_GND ­ Power Supply Ground connection for the video clock phase shift internal block. Connect to GND. 56 JTAG/HOST Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to select JTAG Test Mode or Host Interface Mode. When set HIGH, CS_TMS, SCLK_TCLK, SDOUT_TDO, and SDIN_TDI are configured for JTAG boundary scan testing. When set LOW, CS_TMS, SCLK_TCLK, SDOUT_TDO, and SDIN_TDI are configured as GSPI pins for normal host interface operation. 57 SCLK_TCLK Non Synchronous Input SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Serial Data Clock / Test Clock. All JTAG / Host Interface address and data are shifted into/out of the device synchronously with this clock. Host Mode (JTAG/HOST = LOW): SCLK_TCLK operates as the host interface serial data clock, SCLK. JTAG Test Mode (JTAG/HOST = HIGH): SCLK_TCLK operates as the JTAG test clock, TCLK. 58 SDIN_TDI Synchronous with SCLK_TCLK Input SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Serial Data Input / Test Data Input. Host Mode (JTAG/HOST = LOW): SDIN_TDI operates as the host interface serial input, SDIN, used to write address and configuration information to the internal registers of the device. JTAG Test Mode (JTAG/HOST = HIGH): SDIN_TDI operates as the JTAG test data input, TDI. 59 SDOUT_TDO Synchronous with SCLK_TCLK Output SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Serial Data Output / Test Data Output. Host Mode (JTAG/HOST = LOW): SDOUT_TDO operates as the host interface serial output, SDOUT, used to read status and configuration information from the internal registers of the device. JTAG Test Mode (JTAG/HOST = HIGH): SDOUT_TDO operates as the JTAG test data output, TDO. 36655 - 4 April 2007 17 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet Table 1-1: Pin Descriptions (Continued) Pin Number 60 Name Timing Type Description CS_TMS Synchronous with SCLK_TCLK Input SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Chip Select / Test Mode Select. Host Mode (JTAG/HOST = LOW): CS_TMS operates as the host interface chip select, CS, and is active LOW. JTAG Test Mode (JTAG/HOST = HIGH): CS_TMS operates as the JTAG test mode select, TMS, and is active HIGH. 61 RESET Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Used to reset the internal operating conditions to their default settings or to reset the JTAG test sequence. Host Mode (JTAG/HOST = LOW): When asserted LOW, all host registers and functional blocks will be set to their default conditions. All input and output signals will become high impedance, except PCLK1 and PCLK2, which will be set LOW. When set HIGH, normal operation of the device will resume. The user must hold this pin LOW during power-up and for a minimum of 500 uS after the last supply has reached its operating voltage. JTAG Test Mode (JTAG/HOST = HIGH): When asserted LOW, all host registers and functional blocks will be set to their default conditions and the JTAG test sequence will be held in reset. When set HIGH, normal operation of the JTAG test sequence will resume. 64 GENLOCK Non Synchronous Input CONTROL SIGNAL INPUT Signal levels are LVCMOS/LVTTL compatible. Selects Genlock mode or Free Run mode. When this pin is set LOW and the device has successfully genlocked the output to the input reference, the device will enter Genlock mode. The video clock and timing outputs will be frequency and phase locked to the detected reference signal. When this pin is set HIGH, the video clock and the reference-timing generator will free-run. By default, the GS4911B GS4911B's audio clocks will be genlocked to the output video clock regardless of the setting of this pin. NOTE: The user must apply a reference to the input of the device prior to setting GENLOCK = LOW. If the GENLOCK pin is set LOW and no reference signal is present, the generated clock and timing outputs of the device may correspond to the internal default settings of the chip until a reference is applied. ­ Ground Pad ­ 36655 - 4 ­ April 2007 Ground pad on bottom of package must be soldered to main ground plane of PCB. 18 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet External Crystal Connection External Clock Source Connection 38pF 6 X1 6 X1 external clock 1M 7 X2 7 X2 NC 24pF Notes: 1. Capacitor values listed represent the total capacitance, including discrete capacitance and parasitic board capacitance. 2. X1 serves as an input, which may alternatively accept a 27MHz clock source. To accomodate this, mismatched capacitor values are recommended. Figure 1-1: XTAL1 and XTAL2 Reference Circuits 36655 - 4 April 2007 19 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet 1.4 Pre-Programmed Recognized Video and Graphics Standards Table 1-2 describes the video and graphics standards automatically recognized by the GS4911B/GS4910B GS4911B/GS4910B. Any one of the 36 different video formats and 16 different graphic display formats listed below can be applied to the GS4911B/GS4910B GS4911B/GS4910B and automatically detected by the reference format detector. Moreover, each format, with the exception of VID_STD[5:0] = 2, 52, 53, or 54, is available for output on the timing output pins by setting the VID_STD[5:0] pins. In addition to the pre-programmed video standards listed in Table 1-2, custom output timing signals may be generated by the GS4911B/GS4910B GS4911B/GS4910B. The custom timing parameters are programmed in the host interface when VID_STD[5:0] is set to 62 (see Section 3.10 on page 75). Setting VID_STD[5:0] to 63 will cause the device to produce an output format with identical timing to the detected input reference. If desired, the external VID_STD[5:0] pins may be ignored by setting bit 1 of the Video_Control register, and the video standard may instead be selected via the VID_STD[5:0] register of the host interface (see Section 3.12.3 on page 80). Although the external VID_STD[5:0] pins will be ignored in this case, they should not be left floating. 36655 - 4 April 2007 20 of 113 PCLK1&2 =LOW. PCLK3/PCLK3 = High Impedance 4fsc 525 / 2:1 interlace Composite PAL 625 / 2:1 interlace / 25 601 525 / 2:1 interlace 601 625 / 2:1 interlace 601 ­ 18MHz 525 / 2:1 interlace 601 ­ 18 MHz 625 / 2:1 interlace 720x486/59.94/2:1 interlace 720x576/50/2:1 interlace 720x483/59.94/1:1 progressive 720x576/50/1:1 progressive 1280x720/60/1:1 progressive 1280x720/59.94/1:1 progressive 1280/720/50/1:1 progressive 1 2* 3 4 5 6 7 8 9 10 11 12 13 System Nomenclature 0 VID_STD [5:0] PCLKS / Total Line 36655 - 4 74.25 74.175 74.25 54 54 54 54 36 36 27 27 ­ April 2007 1980 1650 1650 1728 1716 3456 3432 2304 2288 1728 1716 ­ 910 ­ 14.32 ­ Video PCLK Frequency (MHz) Table 1-2: Recognized Video and Graphics Standards 750 750 750 625 525 625 525 625 525 625 525 625 525 ­ Total Lines / Frame 1280 1280 1280 1440 1440 2880 2880 1920 1920 1440 1440 ­ 768 ­ PCLKS / Active Line 80 80 80 127 127 252 252 169 169 127 127 ­ 67 ­ H Sync Width (Clocks) tri tri tri negative negative negative negative negative negative negative negative negative negative ­ H Sync Polarity 5 5 5 5 6 2.5 3 2.5 3 2.5 3 2.5 3 ­ V Sync Width (Lines) negative negative negative negative negative negative negative negative negative negative negative negative negative ­ V Sync Polarity 720 720 720 576 483 576 486 576 486 576 486 576 486 ­ Active Lines / Frame 21 of 113 SMPTE 296M SMPTE 296M SMPTE 296M ITU-R BT.1358 / SMPTE 347M SMPTE 293M / SMPTE 347M ITU-R BT.799 / SMPTE 347M SMPTE RP174 RP174 / SMPTE 347M ITU-R BT.601-5 SMPTE 267M ITU-R BT.601-5 SMPTE 125M/267M 125M/267M ­ SMPTE 244M ­ Scan Format Standard GS4911B/GS4910B GS4911B/GS4910B Data Sheet 1280x720/30/1:1 progressive 1280x720/29.97/1:1 progressive 1280x720/25/1:1 progressive 1280x720/24/1:1 progressive 1280x720/23.98/1:1 progressive 1920x1035/60/2:1 interlace 1920x1035/59.94/2:1 interlace 1920x1080/60/1:1 progressive 1920x1080/59.94/1:1 progressive 1920x1080/50/1:1 progressive Reserved 1920x1080/60/2:1 interlace 1920x1080/59.94/2:1 interlace 1920x1080/50/2:1 interlace Reserved 15 16 17 18 19 20 21 22 23 24 25 26 27 28 System Nomenclature 14 VID_STD [5:0] ­ April 2007 36655 - 4 2640 2200 2200 ­ 2640 2200 2200 2200 2200 4125 4125 3960 3300 3300 PCLKS / Total Line ­ 74.25 74.175 74.25 ­ 148.5 148.35 148.5 74.175 74.25 74.175 74.25 74.25 74.175 74.25 Video PCLK Frequency (MHz) Table 1-2: Recognized Video and Graphics Standards (Continued) ­ 1125 1125 1125 ­ 1125 1125 1125 1125 1125 750 750 750 750 750 Total Lines / Frame ­ 1920 1920 1920 ­ 1920 1920 1920 1920 1920 1280 1280 1280 1280 1280 PCLKS / Active Line ­ 80 80 80 ­ 80 80 80 80 80 80 80 80 80 80 H Sync Width (Clocks) ­ tri tri tri ­ tri tri tri tri tri tri tri tri tri tri H Sync Polarity ­ 5 5 5 ­ 5 5 5 5 5 5 5 5 5 5 V Sync Width (Lines) ­ negative negative negative ­ negative negative negative negative negative negative negative negative negative negative V Sync Polarity ­ 1080 1080 1080 ­ 1080 1080 1080 1035 1035 720 720 720 720 720 Active Lines / Frame ­ 22 of 113 SMPTE 274M SMPTE 274M SMPTE 274M ­ SMPTE 274M SMPTE 274M SMPTE 274M SMPTE 260M SMPTE 260M SMPTE 296M SMPTE 296M SMPTE 296M SMPTE 296M SMPTE 296M Scan Format Standard GS4911B/GS4910B GS4911B/GS4910B Data Sheet 1920x1080/30/1:1 progressive 1920x1080/30/PsF 1920x1080/29.97/1:1 progressive 1920x1080/29.97/PsF 1920x1080/25/1:1 progressive 1920x1080/25/PsF 1920x1080/24/1:1 progressive 1920x1080/24/PsF 1920x1080/23.98/1:1 progressive 1920x1080/23.98/PsF 640 x 480 VGA @ 60 Hz 640 x 480 VGA @ 75 Hz 640 x 480 VGA @ 85 Hz 800 x 600 SVGA @ 60 Hz 800 x 600 SVGA @ 75 Hz 800 x 600 SVGA @ 85 Hz 1024 x 768 XGA @ 60 Hz 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 System Nomenclature 29 VID_STD [5:0] 36655 - 4 65 56.25 49.5 40.00 36 31.5 25.2 74.175 74.175 74.25 74.25 74.25 74.25 74.175 74.175 74.25 74.25 1344 1048 1056 1056 832 840 800 2750 2750 2750 2750 2640 2640 2200 2200 2200 2200 PCLKS / Total Line April 2007 Video PCLK Frequency (MHz) Table 1-2: Recognized Video and Graphics Standards (Continued) 806 631 625 628 509 500 525 1125 1125 1125 1125 1125 1125 1125 1125 1125 1125 Total Lines / Frame 1024 800 800 800 640 640 640 1920 1920 1920 1920 1920 1920 1920 1920 1920 1920 PCLKS / Active Line 136 64 80 128 56 64 96 80 80 80 80 80 80 80 80 80 80 H Sync Width (Clocks) negative positive positive positive negative negative negative tri tri tri tri tri tri tri tri tri tri H Sync Polarity 6 3 3 4 3 3 2 5 5 5 5 5 5 5 5 5 5 V Sync Width (Lines) negative positive positive positive negative negative negative negative negative negative negative negative negative negative negative negative negative V Sync Polarity 768 600 600 600 480 480 480 1080 1080 1080 1080 1080 1080 1080 1080 1080 1080 Active Lines / Frame 23 of 113 VESA VG901101A VG901101A VESA VDMTPROP VESA VDMT75HZ VDMT75HZ VESA VG900602 VG900602 VESA VDMTPROP VESA VDMT75HZ VDMT75HZ IBM Standard SMPTE RP 211 SMPTE 274M SMPTE RP 211 SMPTE 274M SMPTE RP 211 SMPTE 274M SMPTE RP 211 SMPTE 274M SMPTE RP 211 SMPTE 274M Scan Format Standard GS4911B/GS4910B GS4911B/GS4910B Data Sheet 1024 x 768 XGA @ 85 Hz 1280 x 1024 SXGA @ 60 Hz 1280 x 1024 SXGA @ 75 Hz 1280 x 1024 SXGA @ 85 Hz 1600 x 1200 UXGA @ 60 Hz 1600 x 1200 UXGA @ 75 Hz 1600 x 1200 UXGA @ 85 Hz 2048 x 1536 QXGA @ 60 Hz 47 48 49 50 51 52* 53* 54* Automatic Output Standard follows Input Standard 63 ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ ­ 2160 1728 157.5 162 1688 1688 1376 1312 PCLKS / Total Line 135.00 108.00 94.5 78.75 Video PCLK Frequency (MHz) ­ ­ ­ 1589 1250 1250 1250 1072 1066 1066 808 800 Total Lines / Frame ­ ­ ­ ­ ­ ­ 1600 1280 1280 1280 1024 1024 PCLKS / Active Line ­ ­ ­ ­ ­ ­ 192 160 144 112 96 96 H Sync Width (Clocks) ­ ­ ­ negative negative negative negative negative negative positive negative positive H Sync Polarity ­ ­ ­ 3 3 3 3 3 3 3 3 3 V Sync Width (Lines) ­ ­ ­ positive positive positive positive positive positive positive positive positive V Sync Polarity ­ ­ ­ 1536 1200 1200 1200 1024 1024 1024 768 768 Active Lines / Frame ­ ­ ­ ­ ­ ­ VESA VDMTPROP VESA VDMTPROP VESA VDMT75HZ VDMT75HZ VESA VDMTREV VESA VDMTPROP VESA VDMT75HZ VDMT75HZ Scan Format Standard 36655 - 4 April 2007 24 of 113 When VID_STD = 4, 6, or 8, the Vblanking output pulse width is 2 lines too long for field 1 and 1 line too short for field 2 when compared to the digital timing defined in ITU-R BT.656 and ITU-R BT.799. The LOCK_LOST output signal will be unstable when attempting to genlock to an input reference corresponding to VID_STD[5:0] = 51, although the device does achieve lock. To correct this, the user can program register address 27h = 38d. * VID_STD[5:0] = 2, 52, 53, and 54 are recognized as input references only. To generate clock and timing signals for these standards use the device's custom format capability. Custom format only (Section 3.10 on page 75) 62 Reserved 1024 x 768 XGA @ 75 Hz 46 55 - 61 System Nomenclature VID_STD [5:0] Table 1-2: Recognized Video and Graphics Standards (Continued) GS4911B/GS4910B GS4911B/GS4910B Data Sheet GS4911B/GS4910B GS4911B/GS4910B Data Sheet 1.5 Output Timing Signals Table 1-3 describes the output timing signals available to the user via pins TIMING_OUT_1 to TIMING_OUT_8. The user may output any of the signals listed below on each pin by programming the Output_Select registers beginning at address 43h of the host interface. s Table 1-3: Output Timing Signals Signal Name Description Default Output Pin H Sync The H Sync signal has a leading edge at the start of the horizontal sync pulse. Its length is determined by the selected video standard (see Table 1-2), or according to custom timing parameters programmed in the host interface (see Section 3.10 on page 75). TIMING_OUT_1 The width of the H Sync output pulse is determined by the selected video standard. Table 1-2 lists the H Sync width (in clocks) of each pre-programmed video and graphics standard recognized by the GS4911B/GS4910B GS4911B/GS4910B. Custom video timing parameters may also be programmed in the host interface to define a unique H Sync width (see Section 3.10 on page 75). In Genlock mode the leading edge of the output H Sync signal is nominally simultaneous with the half amplitude point of the reference HSYNC input. This timing may be offset using the Genlock Offset registers beginning at address 1Bh of the host interface (see Section 3.2.1.1 on page 38). By default, after system reset, the polarity of the H Sync signal output will be active LOW. The polarity may be selected as active HIGH by programming the Polarity register at address 56h of the host interface (see Section 3.12.3 on page 80). H Blanking The H Blanking signal is used to indicate the portion of the video line not containing active video data. TIMING_OUT_2 The H Blanking signal will be LOW (default polarity) for the portion of the video line containing valid video samples. The signal will be LOW at the first valid pixel of the line, and HIGH after the last valid pixel of the line. The H Blanking signal remains HIGH throughout the horizontal blanking period. The width of this signal will be determined by the selected video standard (see Table 1-2), or according to custom timing parameters programmed in the host interface (see Section 3.10 on page 75). When in Genlock mode, the output H Blanking signal will be phase locked to the reference HSYNC input. This timing may be offset using the Genlock Offset registers beginning at address 1Bh of the host interface (see Section 3.2.1.1 on page 38). The default polarity of this signal may be inverted by programming the Polarity register at address 56h of the host interface (see Section 3.12.3 on page 80). 36655 - 4 April 2007 25 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet Table 1-3: Output Timing Signals (Continued) Signal Name Description Default Output Pin V Sync The V Sync timing signal has a leading edge at the start of the vertical sync pulse. Its length is determined by the selected video standard (see Table 1-2), or according to custom timing parameters programmed in the host interface (see Section 3.10 on page 75). TIMING_OUT_3 The leading edge of V Sync is nominally simultaneous with the leading edge of the first broad pulse. When in Genlock mode, the output V Sync signal will be phase locked to the reference VSYNC input. This timing may be offset using the Genlock Offset registers beginning at address 1Bh of the host interface (see Section 3.2.1.1 on page 38). By default, after system reset, the polarity of the V Sync signal output will be active LOW. The polarity may be selected as active HIGH by programming the Polarity register at address 56h of the host interface (see Section 3.12.3 on page 80). V Blanking The V Blanking signal is used to indicate the portion of the video field/frame not containing active video lines. TIMING_OUT_4 The V Blanking signal will be LOW (default polarity) for the portion of the field/frame containing valid video data, and will be HIGH throughout the vertical blanking period. The width of this signal will be determined by the selected video standard (see Table 1-2), or according to custom timing parameters programmed in the host interface (see Section 3.10 on page 75). When in Genlock mode, the output V Blanking signal will be phase locked to the reference VSYNC input. This timing may be offset using the Genlock Offset registers beginning at address 1Bh of the host interface (see Section 3.2.1.1 on page 38). The default polarity of this signal may be inverted by programming the Polarity register at address 56h of the host interface (see Section 3.12.3 on page 80). NOTE: When VID_STD = 4, 6, or 8, the Vblank output pulse width is 2 lines too long for field 1 and 1 line too short for field 2 when compared to the digital timing defined in ITU-R BT.656 and ITU-R BT.799. F Sync The F Sync signal is used to indicate field 1 and field 2 for interlaced video formats. TIMING_OUT_5 The F Sync signal will be HIGH (default polarity) for the entire period of field 1. It will be LOW for all lines in field 2 and for all lines in progressive scan systems. The width and timing of this signal will be determined by the V Sync parameters of the selected video standard (see Table 1-2), or according to custom V Sync timing parameters programmed in the host interface (see Section 3.10 on page 75). The F Sync signal always changes state on the leading edge of V Sync. When in Genlock mode, the output F Sync signal will be phase locked to the reference FSYNC input. This timing may be offset using the Genlock Offset registers beginning at address 1Bh of the host interface (see Section 3.2.1.1 on page 38). The default polarity of this signal may be inverted by programming the Polarity register at address 56h of the host interface (see Section 3.12.3 on page 80). 36655 - 4 April 2007 26 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet Table 1-3: Output Timing Signals (Continued) Signal Name Description Default Output Pin F Digital F Digital is used in digital interlaced standards to indicate field 1 and field 2. TIMING_OUT_6 The F Digital changes state at the leading edge of every V Blanking pulse. It will be LOW (default polarity) for the entire period of field 1 and for all lines in progressive scan systems. It will be HIGH for all lines in field 2 . The width and timing of this signal will be determined by the timing parameters of the selected video standard (see Table 1-2), or according to custom parameters programmed in the host interface (see Section 3.10 on page 75). When in Genlock mode, the output F Digital signal will be phase locked to the reference FSYNC input. This timing may be offset using the Genlock Offset registers beginning at address 1Bh of the host interface (see Section 3.2.1.1 on page 38). The default polarity of this signal may be inverted by programming the Polarity register at address 56h of the host interface (see Section 3.12.3 on page 80). 10 Field Identification The 10 Field Identification (10FID 10FID) signal is used to indicate the 10-field sequence for 29.97Hz, 30Hz, 59.94Hz and 60Hz video standards. It will be LOW for output standards with other frame rates. TIMING_OUT_7 The sequence defines the phase relationship between film frames and video frames, so that cadence may be maintained in mixed format environments. The 10FID 10FID signal will be HIGH (default polarity) for one line at the start of the 10-field sequence. It will be LOW for all other lines. The signal's rising and falling edges will be simultaneous with the leading edge of the H Sync output signal. Alternatively, by setting bit 4 of the Video_Control register (see Section 3.12.3 on page 80), the 10FID 10FID output signal may be configured to go HIGH (default polarity) on the leading edge of the H Sync output on line 1 of the first field in the 10 field sequence, and be reset LOW on the leading edge of the H Sync pulse of the first line of the second field in the 10 field sequence. When in Genlock mode, the output 10FID 10FID signal will be phase locked to the 10FID 10FID reference input. If a 10FID 10FID input is not provided to the device, the user must configure the 10FID 10FID output using register 1Ah of the host interface (see Section 3.8.1 on page 68). For applications involving audio, this signal may be used in place of the AFS signal if the format selected is appropriate for a 10 field AFS repetition rate, and the desired phase relationship of audio to video clock phasing coincides with the desired film frame cadence. The default polarity of this signal may be inverted by programming the Polarity register at address 56h of the host interface (see Section 3.12.3 on page 80). Please see Section 3.8.1 on page 68 for more detail on the 10FID 10FID output signal. Display Enable The Display Enable (DE) signal is used to indicate the display enable for graphic display interfaces. TIMING_OUT_8 This signal will be HIGH (default polarity) whenever pixel information is to be displayed on the display device (i.e. whenever both H Blanking and V Blanking are in the active video state) The width and timing of this signal will be determined by the timing parameters of the selected video standard (see Table 1-2), or according to custom timing parameters programmed in the host interface (see Section 3.10 on page 75). The default polarity of this signal may be inverted by programming the Polarity register at address 56h of the host interface (see Section 3.12.3 on page 80). 36655 - 4 April 2007 27 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet Table 1-3: Output Timing Signals (Continued) Signal Name Description Default Output Pin Audio Frame Sync The Audio Frame Sync (AFS) signal is HIGH (default polarity) for the duration of the first line of the n'th video frame to indicate that the ACLK dividers are reset at the start of line 1 of that frame. It is defined according to the frame rate of the video format and the selected audio sample rate programmed via the VID_STD[5:0] and ASR_SEL[2:0] pins or the host interface. ­ (GS4911B GS4911B only) For example, if the video format is based on a 59.94Hz frame rate and the audio sample rate clock is 48kHz, then n=5, and the AFS signal will be identical to the 10FID 10FID signal. By default, the AFS signal is reset by the 10 Field Identification (10FID 10FID) reference input. This feature may be disabled using the Audio_Control register at address 31h of the host interface (see Section 3.12.3 on page 80). The AFS signal may also be reset using register 1Ah of the host interface. With no reference, the frame divide by "n" controlling the AFS signal will free-run at an arbitrary phase. The default polarity of this signal may be inverted by programming the Polarity register at address 56h of the host interface (see Section 3.12.3). Please see Section 3.8.2 on page 69 for more detail on the AFS output signal. USER_1~4 The GS4911B/GS4910B GS4911B/GS4910B offers four user programmable output signals. Each USER signal is controlled by four timing registers and a polarity select bit. The timing registers define the start and stop times in H pixels and V lines and begin at address 57h of the host interface (see Section 3.12.3 on page 80). ­ Each user signal is individually programmable and the polarity, position, and width of each output may be defined with respect to the H, V, and F output timings of the device. Each output signal may be programmed in both the horizontal and vertical dimensions relative to the leading edges of H and V Sync. If desired, the pulses produced may then be combined with a logical AND, OR, or XOR function to produce a composite signal (for example, a horizontal back porch pulse during active lines only, or the active part of lines 15 through 20 for vertical information retrieval). Each output has selectable polarity. Please see Section 3.8.3 on page 70 for more detail on the USER_1~4 output signals. 36655 - 4 April 2007 28 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Conditions Value/Units Supply Voltage Core and Analog ­ -0.3V to +2.1V ­ -0.3V to +3.6V IO_VDD = +3.3V -0.3V to +5.5V IO_VDD = +1.8V -0.3V to +3.6V Operating Temperature ­ -20°C < TA < 85°C Storage Temperature ­ -50°C < TSTG < 125°C Soldering Temperature ­ 260°C ESD protection on all pins ­ 1 kV (CORE_VDD, VID_PLL_VDD, AUD_PLL_VDD, PhS_VDD, ANALOG_VDD) Supply Voltage I/O (IO_VDD, XTAL_VDD) Input Voltage Range (any input) 2.2 DC Electrical Characteristics Table 2-1: DC Electrical Characteristics VDD = 1.8V, TA = 0°C to 70°C, unless otherwise specified. Parameter Symbol Condition Min Typ Max Units Notes Operating Temperature Range TA ­ 0 25 70 °C 1 Core power supply voltage CORE_VDD ­ 1.71 1.8 1.89 V ­ Digital I/O Buffer Power Supply Voltage IO_VDD 1.8V Operation 1.71 1.8 1.89 V ­ IO_VDD 3.3V Operation 3.135 3.3 3.465 V ­ Video PLL Power Supply Voltage VID_PLL_VDD ­ 1.71 1.8 1.89 V ­ Audio PLL Power Supply Voltage (GS4911B GS4911B only) AUD_PLL_VDD ­ 1.71 1.8 1.89 V ­ Analog Power Supply Voltage ANALOG_VDD ­ 1.71 1.8 1.89 V ­ Crystal Buffer Power Supply Voltage XTAL_VDD 1.8V Operation 1.71 1.8 1.89 V ­ XTAL_VDD 3.3V Operation 3.135 3.3 3.465 V ­ PhS_VDD ­ 1.71 1.8 1.89 V ­ 36655 - 4 April 2007 System Video Clock Phase Shift Supply Voltage 29 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet Table 2-1: DC Electrical Characteristics (Continued) VDD = 1.8V, TA = 0°C to 70°C, unless otherwise specified. Parameter Symbol Condition System Power PD GS4911B GS4911B CORE_VDD = Max IO_VDD = Max Min Typ Max Units Notes ­ ­ 450 mW ­ ­ 300 ­ mW ­ ­ ­ 400 mW ­ ­ 250 ­ mW ­ T = 70oC unloaded, max PCLK frequency PD GS4911B GS4911B CORE_VDD = 1.8V IO_VDD = 3.3V T = 25oC unloaded, PCLK = 74.25MHz PD GS4910B GS4910B CORE_VDD = Max IO_VDD = Max T = 70oC unloaded, max PCLK frequency PD GS4910B GS4910B CORE_VDD = 1.8V IO_VDD = 3.3V T = 25oC unloaded, PCLK = 74.25MHz Digital I/O Input Voltage, Logic LOW VIL 1.8V Operation ­ ­ 0.35 x VDD V ­ VIL 3.3V Operation ­ ­ 0.8 V ­ VIH 1.8V Operation 0.65 x IO_VDD ­ 3.6 V ­ VIH 3.3V Operation 2.145 ­ 5.25 V ­ Output Voltage, Logic LOW VOL current drive = HIGH or LOW as selected ­ ­ 0.4 V 2 Output Voltage, Logic HIGH VOH current drive = HIGH or LOW as selected 0.65 x IO_VDD ­ ­ V 2 ­ IO_VDD = 1.8V current drive = LOW ­ 5 ­ mA ­ ­ IO_VDD = 3.3V current drive = LOW ­ 10 ­ mA ­ ­ IO_VDD = 1.8V current drive = HIGH ­ 7 ­ mA ­ ­ IO_VDD = 3.3V current drive = HIGH ­ 14 ­ mA ­ Input Voltage, Logic HIGH Digital Output Currents Timing Output Drive Current 36655 - 4 April 2007 30 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet Table 2-1: DC Electrical Characteristics (Continued) VDD = 1.8V, TA = 0°C to 70°C, unless otherwise specified. Parameter Symbol Condition Min Typ Max Units Notes Clock Output Drive Current ­ IO_VDD = 1.8V current drive = LOW ­ 5 ­ mA ­ ­ IO_VDD = 3.3V current drive = LOW ­ 7 ­ mA ­ ­ IO_VDD = 1.8V current drive = HIGH ­ 7 ­ mA ­ ­ IO_VDD = 3.3V current drive = HIGH ­ 14 ­ mA ­ Output Voltage LVDS, Common Mode VOCM ­ 1.125 1.25 1.375 V 3 Output Voltage LVDS, Differential VODIFF ­ ­ 350 ­ mV 3 LVDS High-impedance Leakage Current ­ To 1.8V or GND ­ ­ 1.4 uA ­ NOTES 1. All DC and AC electrical parameters within specification. 2. Assuming that the current being sourced or sinked is less than the Timing Output Drive Current specified. 3. Into a 100 termination connected between PCLK3 and PCLK3. 2.3 AC Electrical Characteristics Table 2-2: AC Electrical Characteristics VDD = 1.8V, TA = 0°C to 70°C, unless otherwise specified. Parameter Symbol Condition ­ from when the reference input is first present PCLK Output Frequency ­ ­ PCLK Jitter ­ SD video standards Min Typ Max Units Notes ­ 2 4 frames ­ 3.375 ­ 165 MHz ­ ­ 350 ­ ps 1, 2 ­ 250 ­ ps 1, 3 40 ­ 60 % ­ System Reference Detection Time Digital I/O XTAL_VDD = 3.3V ­ HD & Graphics video standards XTAL_VDD = 3.3V PCLK Duty Cycle ­ ­ 36655 - 4 April 2007 31 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet Table 2-2: AC Electrical Characteristics (Continued) VDD = 1.8V, TA = 0°C to 70°C, unless otherwise specified. Parameter Symbol Condition PCLK1 & PCLK2 Rise/Fall Times 15pF load 20% - 80% ­ Typ Max Units Notes IO_VDD = 1.8V current drive = LOW ­ ­ 1.7 ns ­ ­ IO_VDD = 3.3V current drive = LOW ­ ­ 1.5 ns ­ ­ IO_VDD = 1.8V current drive = HIGH ­ ­ 1.1 ns ­ ­ PCLK3 Rise/Fall Time 20% - 80% Min IO_VDD = 3.3V current drive = HIGH ­ ­ 0.9 ns ­ ­ 100 differential load ­ ­ 850 ps ­ -3 ­ 3 ns 4 10pF to ground per pin PCLK Outputs Relative Timing Skew ­ default PCLK phase delay of zero ACLK Frequency (GS4911B GS4911B only) ­ ­ 0.0097 ­ 49.152 MHz ­ ACLK Duty Cycle (GS4911B GS4911B only) ­ ­ 40 ­ 60 % 5 ACLK1-3 Rise/Fall Times 15pF load 20% - 80% (GS4911B GS4911B only) ­ IO_VDD = 1.8V current drive = LOW ­ ­ 3.0 ns ­ ­ IO_VDD = 3.3V current drive = LOW ­ ­ 1.5 ns ­ ­ IO_VDD = 1.8V current drive = HIGH ­ ­ 2.5 ns ­ ­ IO_VDD = 3.3V current drive = HIGH ­ ­ 1.4 ns ­ ACLK Outputs Relative Timing Skew (GS4911B GS4911B only) ­ ­ -3 ­ 3 ns 4 Digital Timing Output Delay Time tOD ­ ­ ­ 4.3 ns 6 Digital Timing Output Hold Time tOH ­ 1 ­ ­ ns 6 36655 - 4 April 2007 32 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet Table 2-2: AC Electrical Characteristics (Continued) VDD = 1.8V, TA = 0°C to 70°C, unless otherwise specified. Parameter Symbol Condition Min Typ Max Units Notes Digital Timing Output Rise/Fall Times 15pF load 20% - 80% ­ IO_VDD = 1.8V current drive = LOW ­ ­ 3.0 ns ­ ­ IO_VDD = 3.3V current drive = LOW ­ ­ 1.5 ns ­ ­ IO_VDD = 1.8V current drive = HIGH ­ ­ 2.5 ns ­ ­ IO_VDD = 3.3V current drive = HIGH ­ ­ 1.4 ns ­ GSPI Input Clock Frequency fGSPI ­ ­ ­ 10.0 MHz 7 GSPI Clock Duty Cycle DCGSPI ­ 40 ­ 60 % 7 GSPI Input Setup Time t3 in Figure 3-18 ­ 1.5 ­ ­ ns 7 GSPI Input Hold Time t8 in Figure 3-18 ­ 1.5 ­ ­ ns 7 GSPI NOTES 1. The video output clock may be directly connected to Gennum's GS1532 GS1532 or GS1531 GS1531 serializer for a SMPTE-compliant SDI or HD-SDI output with output jitter below 0.2UI, when the serializer is configured for a loop bandwidth of 100KHz. 2. All SD standards EXCEPT VID_STD[5:0] = 1 (450ps typ.) and VID_STD[5:0] = 5 or 6 (500ps typ.) 3. All HD and Graphics standards EXCEPT VID_STD[5:0] = 22 (300ps typ.) and VID_STD[5:0] = 41-43 (400ps typ.) 4. Timings from any CLK output to any other CLK output. 5. If fs=96kHz and ACLK is configured to output a clock signal at 192fs or 384fs, a 512fs clock will typically have a 33% duty cycle distortion. See Section 3.7.2 on page 64. 6. With PCLK phasing delay set to nominal (zero offset), each increment of the clock phasing adjustment decreases output hold time and delay time by a nominal 700ps. The times tOD and tOH are defined in Figure 2-1. 7. For detailed GSPI timing parameters, please refer to Table 3-12. 36655 - 4 April 2007 33 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet tOH tOD 50% PCLK VOH VOH VOL VOL TIMING_OUT Figure 2-1: PCLK to TIMING_OUT Signal Output Timing Table 2-3: Suggested External Crystal Specification 27.000000 MHz AT Cut Nominal Dissipation = 50 uW Frequency accuracy at 25°C = +/- 10ppm Frequency variation 0-70°C = +/- 10ppm ASR = 50 +/- 20 NOTE: The user may select an appropriate crystal accuracy for their application. If the device is operating in Free Run mode, the output clock and timing signals will have the same accuracy as the crystal. However, if operating in Genlock mode, all output signals are based on the input reference, and therefore a less accurate crystal may be sufficient. See Section 3.2 on page 37. 36655 - 4 April 2007 34 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet 2.4 Solder Reflow Profiles The device is manufactured with Matte-Sn terminations and is compatible with both standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed using the maximum Pb-free reflow profile shown in Figure 2-2. The recommended standard Pb reflow profile is shown in Figure 2-3. Temperature 60-150 sec. 20-40 sec. 260°C 250°C 3°C/sec max 217°C 6°C/sec max 200°C 150°C 25°C Time 60-180 sec. max 8 min. max Figure 2-2: Maximum Pb-free Solder Reflow Profile (preferred) 60-150 sec. Temperature 10-20 sec. 230°C 220°C 3°C/sec max 183°C 6°C/sec max 150°C 100°C 25°C Time 120 sec. max 6 min. max Figure 2-3: Standard Pb Solder Reflow Profile 36655 - 4 April 2007 35 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet 3. Detailed Description 3.1 Functional Overview The GS4911B/GS4910B GS4911B/GS4910B is a highly flexible, digitally controlled clock synthesis circuit and timing generator with genlock capability. The device has two main modes of operation: Genlock mode and Free Run mode. In Genlock mode, the video clock and timing outputs, will be frequency and phase locked to the detected reference input signal. In Free Run mode, the occurrence of all frequencies is based on a 27MHz external crystal reference. The GS4911B/GS4910B GS4911B/GS4910B will recognize input reference signals conforming to 36 different video standards and 16 different graphic formats. It supports cross-locking, allowing the output to be genlocked to an incoming reference that is different from the output video standard selected. When the device is in Genlock mode and the input reference is removed, the GS4911B/GS4910B GS4911B/GS4910B will enter Freeze mode. In this mode, the output clock and timing signals will maintain their previously genlocked phase and frequency to within +/- 2ppm. The user may select to output one of 8 different video sample clock rates or 13 different graphic display clock rates, or may program any clock frequency between 13.5MHz and 165MHz. The chosen clock frequency may be further internally divided, and is available on two video clock outputs and one LVDS video clock output pair. The video clocks may also be individually phase delayed with respect to the timing outputs for clock skew control. Eight user-selectable timing outputs are provided that can automatically produce the following timing signals for 35 different video formats and 13 different graphics formats: HSync, Hblanking, VSync, Vblanking, F sync, F digital, AFS (GS4911B GS4911B only), DE, and 10FID 10FID. Alternatively, custom output timing signals may be programmed in the host interface. In addition, the GS4911B GS4911B provides three audio sample clock outputs that can produce audio clocks up to 512fs with fs ranging from 9.7kHz to 96kHz. Audio to video phasing is accomplished by either an external 10FID 10FID input reference, a 10FID 10FID signal specified via internal registers, or a user-programmed audio frame sequence. 3.2 Modes of Operation The GS4911B/GS4910B GS4911B/GS4910B will operate in either Genlock mode or Free Run mode depending on the setting of the GENLOCK pin. These two modes are described in Section 3.2.1 on page 38 and Section 3.2.2 on page 41 respectively. If desired, the external GENLOCK pin may be ignored by setting bit 5 of the Genlock_Control register (address 16h) so that genlock can instead be controlled via the host interface (see Section 3.12.3 on page 80). Although the external GENLOCK pin will be ignored in this case, it should not be left floating. 36655 - 4 April 2007 36 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet 3.2.1 Genlock Mode When the application layer sets the GENLOCK pin LOW and the device has successfully genlocked the outputs to the input reference, the GS4911B/GS4910B GS4911B/GS4910B will enter Genlock mode. In this mode, all clock and timing generator outputs will be frequency and phase locked to the detected input reference signal. The PCLK outputs will be locked to the H reference. When in Genlock mode, the output clock and timing signals are generated using the applied reference signal. The 27MHz crystal reference is necessary for operation; however, neither crystal accuracy nor changes in crystal frequency (due to a shift in operating temperature) will affect the output signals. For example, the output signals will be generated with the same accuracy whether the 27MHz reference crystal has an accuracy of 10ppm or 100ppm. The GS4911B/GS4910B GS4911B/GS4910B supports cross-locking, allowing the outputs to be genlocked to an incoming reference that is different from the output video standard selected (see Section 3.6 on page 51). NOTE: The user must apply a reference to the input of the device prior to setting GENLOCK = LOW. If the GENLOCK pin is set LOW and no reference signal is present, the generated clock and timing outputs of the device may correspond to the internal default settings of the chip until a reference is applied. 3.2.1.1 Genlock Timing Offset By default, the phase of the clock and timing out signals is genlocked to the input reference signal. These output signals may be phase adjusted with respect to the input reference by programming the host interface (see Section 3.12.3 on page 80). Offsets are separately programmable in terms of clock phase, horizontal phase, and vertical phase (i.e. fractions of a pixel, pixels, and lines). Genlock timing offsets can be used to co-time the output of a piece of equipment containing the GS4911B/GS4910B GS4911B/GS4910B with the outputs of other equipment at different locations. The signal leaving the piece of equipment containing the GS4911B/GS4910B GS4911B/GS4910B may pass through processing equipment with significant fixed delays before arriving at the switcher. These delays may include video line delays or even field delays. To compensate for these delays, genlock timing offsets allow the user to back-time the output of the equipment relative to the input reference. Using the host interface, the following registers may be programmed once the device is stably locked: · Clock_Phase_Offset (1Dh) - with a range of zero to one clock pulse in increments of between 1/64 and 1/512 of a clock period (depending on the PCLK frequency). The increments will be between 100ps and 200ps. All clock and timing output signals will be delayed by the clock phase offset programmed in this register. · H_Offset (1Bh) - the difference between the reference HSYNC signal and the output H Sync and/or H Blanking signal in clock pulses, with a control range of zero to +1 line. All timing output signals will be delayed by the horizontal offset programmed in this register. 36655 - 4 April 2007 37 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet · V_Offset (1Ch) - the difference between the reference VSYNC signal and the output V Sync and/or V Blanking in lines, with a control range of zero to +1 frame. All line-based timing output signals will be delayed by the vertical offset programmed in this register. The encoding scheme for the Clock_Phase_Offset register (1Dh) is shown in Table 3-1. The offset programmed will be in the positive direction. Note that the step size will depend on the frequency of the output video clock. NOTE: If VID_STD[5:0] = 63 and the reference format is changed, care must be taken to ensure that the Clock_Phase_Offset register is correctly programmed for the new output format before the reference is applied. Table 3-1: Clock_Phase_Offset[15:0] Encoding Scheme VID_STD[5:0] Setting Output Video Clock Frequency Step Size (Fraction of a PCLK) Maximum Number of Steps Bits Required to Set the Number of Steps Clock_Phase_Offset [15:0] Settings 1 fPCLK < 20MHz 1-512 511 b 8b 7b6b5 b4b3b2 b1b0 b8000001b8b7b6b5b4b3b2b1b0 3-6, 39-42 20MHz < fPCLK < 40MHz 1-256 255 b 7b6 b5b4b3 b2b1b0 b7000010b7b6b5b40b3b2b1b0 7-20, 25-38, 43-46 40MHz < fPCLK < 80MHz 1-128 127 b 6b5b4 b3b2b1 b0 b6000100b6b5b400b3b2b1b0 21-23, 47-51 fPCLK > 80MHz 1-64 63 b5 b4b3b2 b1b0 b5001000b5b4000b3b2b1b0 Note: Program Clock_Phase_Offset = 0000 0000 0000 0000b to achieve a zero clock phase offset. The value programmed in the H_Offset register (1Bh) must not exceed the maximum number of clock periods per line of the outgoing video standard. Similarly, the value programmed in the V_Offset register (1Ch) must not exceed the maximum number of lines per frame of the outgoing standard. Both horizontal and vertical offsets will be in the positive direction. Negative offsets (advances) are achieved by programming a value in the appropriate register equal to the maximum allowable offset minus the desired advance. NOTES: 1. The device will delay all output timing signals by 2 PCLKs relative to the input HSYNC reference. This will occur even when the H_Offset register is not programmed. The user may compensate for this delay by subtracting 2 PCLK cycles from the desired horizontal offset before loading the value into the host interface. 36655 - 4 April 2007 38 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet 2. For both sync and blanking-based input references, the device will advance all line-based output timing signals by 1 line relative to the input VSYNC reference for all output standards except VID_STD[5:0] = 4, 6, and 8. This will occur even when the V_Offset register is not programmed. The user may compensate for this advance by adding 1 line to the desired vertical offset before loading this value into the register. 3. When locking the "f/1.001" HD output standards to the 525-line SD input reference standards, or vice versa, the device will delay all line-based output timing signals by VSync lines relative to the input VSYNC reference. This will occur even when the V_Offset register is not programmed. The user may compensate for this delay by subtracting VSync lines from the desired vertical offset before loading this value into the register. The value VSync is given by the equation: VSync = HSYNC_IN_Period + VSYNC _HSYNC ­ ( 2 × HSYNC_OUT_Period ) where: HSYNC_IN_Period = the period of the H reference pulse VSYNC_HSYNC = the time difference between the leading edges of the applied V and H reference pulses Hsync_OUT_Period = the period of the generated H Sync output See Figure 3-1. H_Feedback_Divide represents the numerator of the ratio of the output clock frequency to the frequency of the H reference pulse. It is calculated as described in Section 3.6.2.1 on page 55. HSYNC_IN_Period HSYNC VSYNC_HSYNC VSYNC HSync_OUT_Period H Sync V Sync VSync Figure 3-1: HD-SD Calculation 36655 - 4 April 2007 39 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet 4. For sync-based input references, the device will advance all line-based output timing signals by 1 line if the value programmed in the H_Offset register is greater than 20. The user may compensate for this advance by adding 1 line to the desired vertical offset before loading this value into the register. In addition, the internal V_lock and F_lock signals reported in bits 3 and 4 of register 16h will be LOW when H_Offset = 20 only, although the device will remained genlocked. The user may choose to mask these lock signals such that the device will continue to report genlock under this condition. 5. For blanking-based input references, the device will advance all line-based output timing signals by 1 line if the value programmed in the H_Offset register is greater than the number of output video clock cycles from the start of H Sync to the end of active video (Hsync_to_EAV) + 20. The value of Hsync_to_EAV is reported in register 51h and changes according to the output VID_STD selected. The user may compensate for this advance by adding 1 line to the desired vertical offset before loading this value into the register. In addition, the internal V_lock and F_lock signals reported in bits 3 and 4 of register 16h will be LOW when H_Offset = Hsync_to_EAV + 20 only, although the device will remained genlocked. The user may choose to mask these lock signals such that the device will continue to report genlock under this condition. 6. The offsets that occur as described in notes 1-5 are independent of one another and must be accounted for as such. 3.2.1.2 Freeze Mode When the device is in Genlock mode and the input reference is removed, the GS4911B/GS4910B GS4911B/GS4910B will enter Freeze mode. The behaviour of the device during loss and re-acquisition of an input reference signal is described in Section 3.5.3 on page 48. In Freeze mode, the frequency of the output clock and timing signals will be maintained to within +/- 2ppm. This assumes a loop bandwidth of 10Hz. Also, if the frequency of the 27MHz reference crystal shifts while in Freeze mode, the frequency of the output clock and timing signals will shift as well. 3.2.2 Free Run Mode The GS4911B/GS4910B GS4911B/GS4910B will enter Free Run mode when the GENLOCK pin is set HIGH by the application layer. In this mode, the occurrence of all frequencies is based on the external 27MHz reference input. Therefore, the frequency of the output clock and timing signals will have the same accuracy as the crystal reference. If operating in Free Run mode, using a more accurate crystal (e.g. 10ppm) ensures more accurate clock and timing signals are generated. NOTE: In Free Run mode, the audio clocks of the GS4911B GS4911B will remain genlocked to the video clock. 36655 - 4 April 2007 40 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet Figure 3-2 summarizes the differences in output accuracy in each mode of operation. Assuming a crystal reference of +/-100ppm, in Free Run mode the frequency of the output clock and timing signals will be as accurate as the crystal. In Genlock mode the frequency will be as accurate as the input reference regardless of the crystal accuracy. In Freeze mode, the frequency of the output clock and timing signals will be maintained to within +/- 2ppm. Assumption: Reference XTAL is 27MHz+/-100ppm + t t +100ppm + t +2ppm -2ppm 74.25 MHz - t -100ppm - t Free Run Genlock Freeze No Input Reference Reference Applied Reference Lost Time NOTES: 1. t represents the temperature variability of the crystal 2. Diagram not to scale. Figure 3-2: Output Accuracy and Modes of Operation 36655 - 4 April 2007 41 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet 3.3 Output Timing Format Selection At device power-up (described in Section 3.14 on page 107), the application layer should immediately set the external VID_STD[5:0] and ASR_SEL[2:0] pins. The VID_STD[5:0] pins are used to select a pre-programmed output video format, or to indicate that custom timing parameters will be programmed in the host interface. The ASR_SEL[2:0] pins are only available on the GS4911B GS4911B, and are used to select the fundamental audio frequency or to turn off audio clock generation. The output timing formats selectable by the user via the VID_STD[5:0] pins are listed in Section 1.4 on page 20. Table 3-7 in Section 3.7.2 on page 64 lists the audio sample rates available via the ASR_SEL[2:0] pins. If the user sets VID_STD[5:0] =1-51 on power-up, the device will first check the status of the GENLOCK pin. If GENLOCK is set LOW and a valid reference has been applied to the inputs, the device will output the selected video standard while attempting to genlock. However, if a reference signal has not been applied and GENLOCK=LOW, the initial clock and timing outputs may be determined by the internal default settings of the chip. If GENLOCK is set HIGH, the device will immediately enter Free Run mode and will correctly output the selected video standard. If the user sets VID_STD[5:0] = 62 on power-up, the device will be configured to generate custom output timing signals. The initial output timing signals will be equal to the internal default timing of the chip until the user programs registers 4Eh to 55h of the host interface (see Section 3.10 on page 75). Additionally, the output video clock will run at a frequency determined by the internal default settings of the chip until the user modifies it via registers 20h to 23h (see Section 3.9.1 on page 73). If the user sets VID_STD[5:0] = 63 on power-up, the device will wait until a valid reference has been applied, at which time it will output the same video format as the input reference and enter Genlock mode if GENLOCK = LOW. When operating in Free Run or Genlock mode, the GS4911B/GS4910B GS4911B/GS4910B will continuously monitor the settings of the VID_STD[5:0] and ASR_SEL[2:0] pins. If the user wishes to change the format of the output clocks and timing signals, these pins may be reconfigured at any time, although it is recommended that the device be reset when changing output video standards. 36655 - 4 April 2007 42 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet 3.4 Input Reference Signals The HSYNC, VSYNC, FSYNC, and 10FID 10FID reference signals are applied to the GS4911B/GS4910B GS4911B/GS4910B via the designated input pins. To operate in Genlock mode, the input reference signals must be valid and must conform to a recognized video or graphics standard (see Section 3.5 on page 46). Alternatively, if VID_STD[5:0] = 62, the signal applied to the HSYNC input must be stable and have a period of less than 2.4ms. In Free Run mode, no input reference is required. Section 3.4.1 on page 44 describes the HSYNC, VSYNC and FSYNC input timing. The 10FID 10FID input signal is discussed in Section 3.4.2 on page 45. 3.4.1 HSYNC, VSYNC, and FSYNC Timing for Video Formats The HSYNC, VSYNC, and FSYNC input reference signals may have analog timing, such as from Gennum's GS4981/82 GS4981/82 sync separators (Figure 3-3), or may have digital timing, such as from Gennum's GS1559/60A/61 GS1559/60A/61 deserializers (Figure 3-4). Section 1.4 on page 20 lists the 36 pre-programmed video timing formats recognized by the GS4911B/GS4910B GS4911B/GS4910B. If the input reference format does not include an F sync signal, the FSYNC pin should be held LOW. HSYNC VSYNC FSYNC Figure 3-3: Example HSYNC, VSYNC, and FSYNC Analog Input Timing from a Sync Separator PCLK LUMA DATA OUT 3FF 000 000 XYZ (eav) 3FF 000 000 XYZ (sav) CHROMA DATA OUT 3FF 000 000 XYZ (eav) 3FF 000 000 XYZ (sav) H V F H:V:F TIMING - HD 20-BIT 20-BIT OUTPUT MODE H Signal Timing Typical H Timing Alternative H Timing Figure 3-4: Example H Blanking, V Blanking, and F Digital Input Timing from an SDI Deserializer 36655 - 4 April 2007 43 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet Timing for Graphics Formats The GS4911B/GS4910B GS4911B/GS4910B is pre-programmed to recognize the timing for 16 different graphics formats presented to the input reference pins. These graphic formats are described in Section 1.4 on page 20. The supported graphics standards are all progressive, and do not use the FSYNC signal. Therefore, FSYNC should be held LOW by the application layer. The VESA formats supported have a 0.5% frequency tolerance. VSYNC transitions are typically co-timed with the leading edge of HSYNC. The duration and polarity of these signals for each format is listed in Table 1-2. NOTE: The user must ensure that the input HSYNC polarity for VID_STD [5:0] = 47 and 49 ­ 54 be active LOW. 3.4.2 10FID 10FID The 10FID 10FID input is a reset pin, which can be used to reset the divider for the 10FID 10FID output signal. In the GS4911B GS4911B, the 10FID 10FID input pin will also reset the divider for the AFS output signal. This default setting may be modified using the Audio_Control register of the host interface (see Section 3.12.3 on page 80). The GS4911B GS4911B will reset the phase of the audio clocks to the leading edge of the H Sync output on line 1 of every output frame in which the 10FID 10FID input is HIGH. This enables the user to reset the phase of the dividers when generating custom signals via the host interface (see Section 3.7.2.1 on page 66). If the input reference format does not include a 10 Field ID signal, the external 10FID 10FID input pin should be held LOW. The timing of the 10FID 10FID input signal is shown in Figure 3-5. Total Line 10FID 10FID Input Line 1, Frame 1 every 'n' frames Horizontal Sync Input Line 1 every n frames where: n = 5 @ 29.97 fps, 30 fps n = 10 @ 59.94 fps, 60 fps Figure 3-5: 10FID 10FID Input Timing 36655 - 4 April 2007 44 of 113 GS4911B/GS4910B GS4911B/GS4910B Data Sheet 3.4.3 Automatic Polarity Recognition To accommodate any standards that employ the polarity of the H and V sync signals to indicate the format of the display, the GS4911B/GS4910B GS4911B/GS4910B will recognize H and V sync polarity and automatically synchronize to the leading edge. The polarities of the HSYNC and VSYNC signals are reported in bits 3 and 4 of the Video_Status register. Additionally, bit 2 of this register reports the detection of either analog or digital input timing. See Section 3.12.3 on page 80 for detailed register descriptions. 3.5 Reference Format Detector The reference format detector checks the validity and analyzes the format of the input reference signal. It is designed to accurately differentiate between 59.94 and 60Hz frame rates. 3.5.1 Horizontal and Vertical Timing Characteristic Measurements When a reference signal is applied to the designated input pins, the GS4911B/GS4910B GS4911B/GS4910B will analyse the signal and report the following in registers 0Ah to 0Eh of the host interface: · the number of 27MHz clock pulses between leading edges of the H input reference signal (H_Period register) · the number of 27MHz clock pulses in 16 horizontal periods (H_16_Period register) · the number of H reference pulses between leading edges of the V input reference signal (V_Lines register) · the number of H reference pulses in two vertical periods (V_2_Lines register) · the number of H reference pulses in one F period (F_Lines register) These parameters may be read via the host interface and are used by the device to determine reference signal validity. 3.5.2 Input Reference Validity Before the device attempts to operate in Genlock mode, the input signals applied to HSYNC and VSYNC must be valid and must conform to one of the 36 recognized video standards or 16 recognized graphics standards described in Section 1.4 on page 20. Alternatively, if VID_STD[5:0] = 62, the device may be manually programmed to genlock to a reference that is neither valid nor recognized (see Section 3.10.1 on page 75)