GPTC6603A1 SEG21 SEG20 T32KHZ T128S1 T128S0 T128HZ GPTC6603A SEG23 104J/250V - Datasheet Archive

 

CALLER ID CONTROLLER/LCD DRIVER 1. GENERAL DESCRIPTION The GPTC6603A1, a newly invented micro-controller for caller ID One 8-bit

 

GPTC6603A1 GPTC6603A1 CALLER ID CONTROLLER/LCD DRIVER 1. GENERAL DESCRIPTION The GPTC6603A1 GPTC6603A1, a newly invented micro-controller for caller ID One 8-bit timer and vocal dialer products, carries GENERALPLUS newest 16-bit Power management for system reliability µ'nSPTM CPU technology. Low-Voltage-Reset function The µ'nSPTM high processing speed Power-On-Reset function assures that the GPTC6603A1 GPTC6603A1 is able to facilitate the sophisticated digital signal processing. Watchdog reset (derived from 32768Hz crystal) In addition to the advanced µ'nSPTM technology, other primary functions include 10 Interrupt / Wakeup Sources (INT / WP) RAM, ROM, IO, interrupt controller, two timer/counters, LCD IOC[1:0] edge-triggered controller/driver, IOA[7:0] edge-triggered 8-bit Analog-to-Digital Converter (ADC), Dual-Tone- Multi-Frequency (DTMF) generator, and melody Timer A / Timer B overflow Digital-to-Analog Converter (DAC) output. T32KHz,T2KHz,T128Hz,T8Hz (derived from 32768Hz) For power savings, a software controllable standby mode and adjustable CPU clock Line Signal Detector can be used to achieve the best power management. LCD Driver Typical 8 COM x 24 SEG SEG[23:20] shared with IOD[1:0], IOB5 and IOA5 The GPTC6603A1 GPTC6603A1 is able to drive LCD directly, and to perform complex function and arithmetic. 1/4 bias, 1/8 duty An external 32768Hz crystal oscillator produces a steady time base for clock function. 17 I/Os, up to 21 I/Os max. With IOA[5:0]:programmable pull-high, wakeup / interrupt the built-in DTMF generator, the telephone dialer function can be implemented. IOA[7:6]:programmable pull-high / pull-low, wakeup / Plus, the flexible LCD controller and regulator interrupt make the LCD driver achieving the best display quality. IOB[5:0]:COMS output, IOB[7:6] NMOS open drain IOC[2:0]:COMS output, IOC0 shared with DAC2 The GPTC6603A1 GPTC6603A1 can be widely used in telecom products such IOD[1:0] : CMOS I/O, shared with SEG[23:22] as multifunction telephone dialer with/without Caller Identification and general-purpose controller. Analog Front End The GPTC6603A1 GPTC6603A1 provides not Op amp for the twisted pair telephone line only the latest telecom technology, but also the full service and 5-stage programmable PGA support of GENERALPLUS. 8-bit A/D, with sample-rate up to 8KHz DTMF and FSK demodulation Object code of DTMF and FSK decoders provided 2. FEATURES Compatible with Bell 202, and ITU V.23 FSK specifications GENERALPLUS 16-bit µ'nSPTM CPU FSK/DTMF decoder auto-select function SRAM 0.5K x 16 bits Built-in line signal detector ROM 12K x 16 bits Miscellaneous Clock Built-in DTMF generator An external 32768Hz crystal for dialing and demodulation 2 DAC output pins for melody and speech An external resistor to drive RC-oscillator for CPU clock Multiplication with cumulative addition for user's digital filters Programmable RC-oscillator frequency : 1MHz or 10MHz /1,/2,/4,/8 of selected RC-oscillator for CPU clock 3. APPLICATION FIELD Operating voltage CPU operation voltage : 2.0V - 3.6V Telephones, fax machines, answering machines, and modems DTMF receiver / FSK decoder : 2.2V - 3.6V that support caller-ID services Adjunct boxes for caller-ID information services Operation Modes Operating mode, Standby mode, and Halt mode Timer/Counter One 16-bit timer/counter © Generalplus Technology Inc. Proprietary & Confidential 1 MAY 11, 2006 Version: 1.0 GPTC6603A1 GPTC6603A1 4. BLOCK DIAGRAM ROSC IOA[7:0] X32I X32O IOA[7:0] IOB[7:0] IOC[2:0] IOD[1:0] 32768Hz XTAL OSC & Dual RC-OSC System Clock Gen. Signal Channel 8-bit DAC Output Sleep / INT Control ROM 12k x 16 8-bit SAR ADC u'nSP 16-bit Processor RAM 0.5k x 16 PGA & Pre-Amp Hardware STM & Reset / POR / LVRST / WDOG Max. 8 x 24 LCD Driver IOB[7:0] IOC[2:0] IOD[1:0] DTMFO IOC0_DAC2 PGAIN GS TIPIN RINGIN RESET 31768Hz TimeBase Gen. 8-bit timer x1 16-bit timer x1 COM[7:0] SEG[23:0] *SEG[23:20] share pad with IOs* © Generalplus Technology Inc. Proprietary & Confidential 2 MAY 11, 2006 Version: 1.0 GPTC6603A1 GPTC6603A1 5. SIGNAL DESCRIPTIONS P: Port Mnemonic PIN No. Type SEG[19:3] 17 - 1 O LCD segment outputs. (SEG[19:0] are dedicated for LCD application.) SEG[2:0] 62 - 60 IOD[1:0]_SEG[23:22] 21 ­ 20 I/O Each pin of SEG[23:20] is shared with the corresponding pin of IOs individually via IOB5_SEG21 SEG21 19 IOA5_SEG20 SEG20 Description 18 mask option. COM[7:0] 59 - 52 O LCD common outputs. IOA[7:6] 38 ­ 39 I/O 1). 8-bit I/O port, each pin could be set as an input or output individually. IOA[4:0] 40 - 44 2). Input mode: Each one of IOA[5:0] is a CMOS input with programmable internal pull-high resistor, Moreover, each one of IOA[7:6] is a COMS inputs capable of both programmable pull-high and pull-low resistors. 3). Output mode: CMOS output. 4). All pins are capable of wake-up and interrupt functions. IOB[7:6] 31 ­ 32 IOB[4:0] 33 - 37 I/O 1). 8-bit I/O port, each pin can be set as an input or output individually. 2). Input mode: Each one of IOB[7:0] is a CMOS input pin without internal pull resistor. 3). Output mode: IOB[5:0] CMOS outputs, whereas IOB[7:6] are NMOS open drain outputs. IOC[2:1] IOC0_DAC2 28 - 29 I/O 30 1). 8-bit I/O port. Each pin can be set as an input or output individually. 2). Input mode: CMOS inputs without internal pull resistors, Moreover, IOC[1:0] provide wake-up and interrupt functions enabled by software. 3). Output mode: CMOS outputs. 4). IOC0 might be configured as DAC second output pin via mask option. IOD[1:0]_SEG[23:22] 21 ­ 20 I/O Mask optional I/Os 1). Behave as CMOS I/O when configured as I/O. 2). IOD[1:0] are shared with SEG[23:22] via individual mask option. ROSC 23 I RC-oscillator resistor interconnection pin, Connect a resistor between this pin and X32O 26 O 32768Hz crystal oscillator output. X32I 25 I 32768Hz crystal oscillator input. RESET 24 I VDD. System reset input. It is low-active and internal pulled high. All of the internal registers are reset to the default state when this pin is set to Low level. Connect a 0.1µF capacitor between this pin and VSS to achieve power-on reset. TIPIN 47 I Positive input of pre-amplifier. Connect this pin to the TIP side of the twisted-pair telephone line through a 150K resistor and a DC-decoupling capacitor. Besides, connect a 1000-pF capacitor between this pin and AVSS to improve noise immunity. RINGIN 48 I Negative input of pre-amplifier. Connect this pin to the RING side of the twisted-pair telephone line through a 150K resistor and DC-decoupling capacitor. Besides, connect a 1000-pF capacitor between this pin and GS pin to improve noise immunity. GS 49 O Output of pre-amplifier. Connect a 0.1µF capacitor between this pin and PGAIN pin to block DC bias between the pre-amplifier and PGA. Besides, connect a 1000-pF capacitor between this pin and RINGIN. © Generalplus Technology Inc. Proprietary & Confidential 3 MAY 11, 2006 Version: 1.0 GPTC6603A1 GPTC6603A1 Mnemonic PIN No. Type Description PGAIN 50 I PGA input. DTMFO 46 O DTMF tone output. AVDD 51 I Analog circuit power input. AVSS 45 I Analog circuit ground input. VDD 22 I Digital circuit power input. VSS 27 I Digital circuit ground input. © Generalplus Technology Inc. Proprietary & Confidential 4 MAY 11, 2006 Version: 1.0 GPTC6603A1 GPTC6603A1 6. FUNCTIONAL DESCRIPTIONS 6.1. CPU 6.3. Clock and Operation Mode The GPTC6603A1 GPTC6603A1 is equipped with a 16-bit µ'nSPTM, the newest 6.3.1. Clock 16-bit CPU developed by SUNPLUS, pronounced as micro-n-SP. 6.3.1.1. System clock µ'nSPTM: R4 Only one external resistor is required; the unique designed (General-purpose registers), PC (Program Counter), SP (Stack RC-oscillator supports dual operating speed (10MHz / 1MHz) for Pointer), Base Pointer (BP) and, SR (Segment Register). various applications. Eight registers are involved in R1 ~ The For each RC-oscillator, the user can concatenation of R3 and R4 forms a 32-bit register, MR, which is program CPU clock to /1, /2, /4, /8 of oscillator clock output. used The default CPU clock is 250KHz (1MHz / 4) after reset or as the inner-production. destination register for multiplication and Moreover, Two types of interrupts are FIQ wakeup from sleep mode. (Fast Interrupt Request) and eight IRQs (Interrupt Request), plus one software interrupt, BREAK. VDD The µ'nSPTM is a 16-bit microprocessor with 16-bit data and 22-bit address buses. R ROSC The address bus is capable of addressing 4M bytes of 16-bit data. Not only does the µ'nSPTM perform general operations such as addition, subtraction and other logical operations, but it also supports multiplication and inner-product operations for digital signal processing. For more 6.3.1.2. 32768 RTC information about the µ'nSPTM, please contact GENERALPLUS The 32768Hz X'TAL supplies precise and steady timing for the to obtain the latest documents. time-base sources, LCD driver, ADC sampling rate and DTMF generator. 6.2. Memory The time-base can be utilized for interrupt, wake-up source, timer / counter clock and watchdog timer. The GPTC6603A1 GPTC6603A1 contains 12K words ROM and 0.5K words RAM. 32768 X'TAL 6.2.1. Memory mapping 20PF 0000 0.5K SRAM 01FF 20PF Reserved 7000 A brief summary of time-base selection is listed in the following Control Register 702F table: Reserved 7100 LCD RAM Buffer 7117 T32kS1 T32kS0 T2kS1 T2kS0 11: T32KHz = 32KHz Test Program 01: T2KHZ = 512Hz 00: T32KHZ T32KHZ = 4KHz(Default) 0.5K 11.5K 10: T2KHZ = 1KHz 01: T32KHZ T32KHZ = 8KHz D000 D200 11: T2KHZ = 2KHz 10: T32KHZ T32KHZ = 16KHz Reserved 00: T2KHZ = 256Hz(Default) Program ROM FFE0 FFFF T128S1 T128S1 T128S0 T128S0 T8S1 T8S0 IRQ/FIQ/Reset Vector 11: T128HZ T128HZ = 128Hz 10: T128HZ T128HZ = 64Hz for Generalplus internal test program. © Generalplus Technology Inc. Proprietary & Confidential 5 01: T8HZ = 2Hz 00: T128HZ T128HZ = 16Hz(Default) The available ROM is from $D200 to $FFDF. 10: T8Hz = 4Hz 01: T128HZ T128HZ = 32Hz Note: The ROM area of $D000 to $D1FF and $FFE0 to $FFEF is reserved 11: T8Hz = 8Hz 00: T8HZ = 1Hz(Default) MAY 11, 2006 Version: 1.0 GPTC6603A1 GPTC6603A1 6.4. Operation Mode Three Operation modes are available: Operating, Halt and service sub-routine if related interrupt flag is enabled. Be sure that Standby. all interrupts must be disabled before entering sleep mode. The following summary depicts the major differences between three modes. Interrupt vectors in GPTC6603A1 GPTC6603A1 are summarized in the following table: Operating Halt Standby CPU & ROSC ON OFF OFF 32768Hz OSC. ON ON LCD Driver ON ON Vector Address OFF FIQ OFF IRQ0 IRQ1 Priority FFF6 IOC1INT Higher FFF8 IOCOINT / Line Detector FFF9 IOAKEY IRQ2 T32Khz FFFD T2kHz FFFE T128Hz IRQ7 u or up FFFC IRQ6 , ter gi s N re P or O EE llat SL sci to zo rite H W 768 et 32 es rr se eak W TMBOC IRQ5 Wake-up or user reset TMAOC FFFB IRQ4 STANDBY FFFA IRQ3 Write to SLEEP register, 32768Hz oscillator OFF OPERATING Interrupt Source FFFF T8Hz Lower Note: If more than one IRQ occurs simultaneously, the first priority is IRQ0; the 2nd priority is IOR1 and.etc. priority. The IRQ7 holds the lowest However, a higher priority IRQ cannot dominate a lower priority IRQ if the lower one occurs before the higher IRQ. HALT The priority applies only when two IRQs occur concurrently. 6.6. Wakeup Similar to interrupt function, three are five wake-up sources: IOA 6.4.1. Operating mode In operating state, functions including CPU, [7:0] key change wake-up, IOC[1:0] input change wake-up, Line R-oscillator, Detect, timer/counter, and LCD controllers are all activated. TimerA/B T32kHz/T2kHz/T128Hz/T8Hz. attention. CPU clock control SCK2 - SCK0 (in Register $7015) to "111" to The CPU can awake only when an overflow signal occurs. After the device awakes from halt or standby state, it will In halt mode, the 32768Hz oscillator must be execute instruction from the beginning of the program. Memory, enabled if the time-base wakeup is selected. control registers and I/O status will all remain in previous states. 6.4.3. Standby mode 6.7. RESET To enter standby mode, set CKS2 - CKS0 = "111" and disable 6.7.1. RESET pin In standby mode, all functions are The control registers and CPU are initialized when reset pin shut down, but RAM and I/O continue to remain in the previous states. and source, the Timer/Counter can work individually without extra The user has to enable wakeup sources ($7012) before setting 32768Hz crystal oscillator. wake-up For instance, suppose TimerA control registers are enabled and 32768Hz is selected as the clock 6.4.2. Halt mode enter halt mode. overflow receives a low signal, but the data in SRAM will not be changed. The power consumption is minimized in standby mode. A 0.1µF capacitor is required crossing on RESET pin and GND. For any wakeup event occurs during the halt or standby mode, the device will execute instruction from the beginning of the 6.7.2. PORN and LVR program (warm start). A Power-On-Reset (POR) and a Low Voltage Reset (LVR) are available in the GPTC6603A1 GPTC6603A1. Once POR or LVR activates, the 6.5. Interrupt GPTC6603A1 GPTC6603A1 will be reset and the CPU will start executing from Setting or clearing the Interrupt Control Register ($7010) can the beginning of the program (cold start). enable or disable the service of the corresponding interrupt function. Once an interrupt event occurs, the CPU will enter its interrupt © Generalplus Technology Inc. Proprietary & Confidential 6 MAY 11, 2006 Version: 1.0 GPTC6603A1 GPTC6603A1 6.7.3. Watchdog timer (WDT) 6.10.2. ADC The external Watchdog Timer (WDT) is designed for recovering The external 8-bit Analog-to-Digit Converter (ADC) is software system from abnormal operation. controllable. If the system is halted for Plus, the ADC sampling rate can be determined by more than one second, WDT generates a system reset to restart the overflow signal of Timer A. system. rate is 8192Hz. If WDT is enabled, the WDT must be cleared within every 2 seconds to avoid accidental reset. The default of ADC sampling Note that the WDT only works when 32768Hz clock is activated. Note: In any mode, the sampling rate must be equal or less than 8192Hz. 6.8. I/O 6.11. DTMF Generator There is a total of 26-bit programmable bi-directional I/O ports The GPTC6603A1 GPTC6603A1 provides two current DACs that serve as the (IOA [7:0], IOB[7:0], IOC[7:0] and IOD[1:0]) in GPTC6603A1 GPTC6603A1. Dual-Tone-Multi-Frequency (DTMF) generators, and speech or Each pin can be programmed individually to pure output buffer, melody generators. ODP (open drain PMOS), ODN (open drain NMOS), pure input following DTMF signals by software programming. buffer, input with pull-low or input with pull-high. have alternative functions. The IOs also C0 The IOA and IOC[1:0] can be used as wakeup / interrupt sources. The generator is capable of producing the R0 Furthermore, IOD1 can be C1 C2 C3 1 2 3 A - 697Hz R1 4 5 6 B - 770Hz R2 7 8 9 C - 852Hz R3 programmed as tone output. * 0 # D - 941Hz Please refer to the GPTC6603A GPTC6603A programming guide - I/O 1209 Configuration for more information. 1336 1477 1633 Hz Note: Be sure to disable DACs to save power when the DTMF generator is Finally, make sure that all I/Os are set as input mode without pull not needed. high / pull low after RESET. 6.12. Line Signal Detector 6.9. LCD Driver A Line Signal Detector, controlled by Register $702E, is built-in GPTC6603A1 GPTC6603A1 offers a LCD controller and driver for a maximum the GPTC6603A1 GPTC6603A1. of 192 dots LCD display (1/4 bias, 1/8 duty). circuit related to pin TIPIN and RINGIN must be added. LCD display is off in default mode. In power-on state, The user can activate LCD If the detector is required, the application The detector dissipates only transition current and can be always display and define the LCD configuration (bias, duty, display turned on. mode) transitions on pins TIPIN and RINGIN can be programmed as through software programming. Once the LCD configuration is initialized, the desired pattern can be displayed To satisfy various applications, both rising and falling interrupt or wake-up source. by filling the LCD RAM buffer with appropriated data. The LCD driver can operate automatically even the system is in halt mode 6.13. Timer A / B and Tone Output (if 32768Hz oscillator keep running). 6.13.1. Timer A / B Furthermore, the programmer can turn off the LCD display through LCD Control The GPTC6603A1 GPTC6603A1 provides a 16-bit TimerA and an 8-bit Timer B. Register to save power. The overflow signal of TimerA or TimerB can be used as interrupt / wakeup sources, and be used to determine ADC sampling rate 6.10. PGA and ADC (only timer A) and the tone output frequency. A variety of signals 6.10.1. PGA can be chosen for clock sources of Timer A and TimerB. The Register, $7026, controls the digital gain of the built-in OP refer to GPTC6603A GPTC6603A Programming Guide for more information. AMP. Please The available gains are x1/3, x2, x8 and x32 and the PGA 6.13.2. Tone output output is sent into an 8-bit ADC. Normally, the pin IOD1 behaves as a normal I/O. While $700E bit 5 is set to "1", IOD1 behaves as a tone output pin, in which frequency is determined by Timer A or TimerB overflow signal. © Generalplus Technology Inc. Proprietary & Confidential 7 MAY 11, 2006 Version: 1.0 GPTC6603A1 GPTC6603A1 7. ELECTRICAL SPECIFICATIONS 7.1. Absolute Maximum Ratings Characteristics Symbol Ratings DC Supply Voltage V+ < 3.6V Input Voltage Range VIN -0.5V to V+ + 0.5V Operating Temperature TA 0 to +60 TSTO -50 to +150 Storage Temperature Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device. For normal operational conditions, see AC/DC Electrical Characteristics. 7.2. DC Characteristics (VDD = 3.0V, TA = 25) Characteristics Limit Symbol Unit Min. Typ. Condition Max. Operating Voltage 1 VDD 2.0 - 3.6 V For Pulse/Tone dialer operation Operating Voltage 2 VDD 2.2 - 3.6 V For CID signal receiving Operating Current 1 IOP1 - 200 - µA Operating Current 2 IOP2 - 400 - µA Operating Current 3 IOP3 - 2250 - µA Halt Mode Current IHALT - 20 - µA IOH -5.0 - - mA Output High Current (IOC[2:0], IOD1) Output Sink Current FCPU = 250KHz @ 3.0V, no load, For Pulse dial FCPU = 250KHz @ 3.0V, no load, For Tone dial FCPU = 10MHz @ 3.0V, no load, For CID signal receiving Active 32768Hz OSC, LCD display on without panel loading, ROSC off VDD = 3.0V VOH = 2.4V VDD = 3.0V IOL 5.0 - - mA IOH -1.0 - - mA IOL 2.0 - - mA RHIGH - 200 - k VDD = 3.0V Pull Low Resistor (IOA[7:6]) RLOW - 200 - k VDD = 3.0V ROSC Frequency (Fast) FOSCH - 10 - MHz VDD = 3.0V, ROSC = 100K ROSC Frequency (Slow) FOSCL - 1.0 - MHz VDD = 3.0V, ROSC = 100K (IOB[7:6], IOD1) Output High Current (IOA[7:0], IOB[5:0], IOD0) Output Sink Current (IOA[7:0], IOB[5:0], IOD0) Pull High Resistor (IOA[7:0]) © Generalplus Technology Inc. Proprietary & Confidential 8 VOL = 0.4V VDD = 3.0V VOH = 2.4V VDD = 3.0V VOL = 0.4V MAY 11, 2006 Version: 1.0 GPTC6603A1 GPTC6603A1 7.3. The Relationships between the ROSC and the FOSC 7.4. The Relationships between the FOSC and VDD 7.3.1. Fast mode, VDD = 3.0V, TA = 25 7.4.1. Fast mode, ROSC = 100K, TA = 25 Fosc v.s. VDD at ROSC=100K(Fast Mode) Fosc v.s. ROSC at VDD=3V(Fast Mode) 11.0 MHz MHz 30 15 10.5 10.0 0 0 200 400 2.4 600 2.6 ROSC(Kohm) 3 7.4.2. Slow mode, ROSC = 100K, TA = 25 7.3.2. Slow mode, VDD = 3.0V, TA = 25 Fosc v.s. VDD at ROSC=100K(Slow Mode) Fosc v.s. Rosc at VDD=3V(Slow Mode) 1.3 MHz 4 MHz 2.8 VDD(V) 2 0 0 100 200 300 400 500 1.1 600 2 ROSC(Kohm) © Generalplus Technology Inc. Proprietary & Confidential 1.2 2.5 3 3.5 ROSC(Kohm) 9 MAY 11, 2006 Version: 1.0 GPTC6603A1 GPTC6603A1 8. APPLICATION CIRCUIT 1 2 103/250 V A92 30K 150K RJ11 (on-hook) Hook 103/250 V F 2.2K 4.7K 103 100K 9014 1K 12V 2.2K 100 3.9V 4148 4148 100K 1M 4.7K 200K Caller-ID Decoder 100K 10 AVDD 3.3V 100u 200u 220u NPN 470K Speech Network VDD A42 104 104 4148 102 50K 48 49 5M 30 32 46 31 38 29 GS GPTC6603A1 GPTC6603A1 AGCIN IOC0 SEG23 SEG23 RICTRL 22 VDD 28 100u RESET X32I 25 24 ROSC X32O 26 OPTION 39 23 41 40 42 COL0 COL1 COL2 COL3 COL4 43 37 44 36 51 RINGER 35 VSS ROW4 ROW3 ROW2 ROW1 ROW0 SEG0 27 AVSS 104 34 4148 COM0 103 Ringing Sound Generator 50 21 60 COM7 104 RINGIN 59 102 52 VDD MUTE 4148 DTMFO 100K AVDD 3.3M DP 0K 104J/250V 104J/250V HKI HFO 33K 45 2.2K 4148 104 50K 33 104J/250V 104J/250V 100K 47 3.3M TIPIN 103/ 250V 103/250V 103/250V 100u F 104 speaker 0.2V 5.1 62K 104 50P VDD 12P * 12P * 32768Hz 5.1 Power LCD Panel Maximum 8 Com x 24 Seg Note*: These capacitor values are for design guidance only. Different capacitor values may be required for different crystal/resonator used. © Generalplus Technology Inc. Proprietary & Confidential 10 MAY 11, 2006 Version: 1.0 GPTC6603A1 GPTC6603A1 9. PACKAGE/PAD LOCATIONS GS AVDD COM0 COM1 COM2 49 COM3 60 59 58 57 56 55 54 53 52 51 50 COM4 61 COM5 62 COM6 PGAIN SEG4 SEG0 1 SEG1 SEG3 COM7 SEG2 9.1. PAD Assignment 48 RINGIN 2 47 TIPIN SEG5 3 46 DTMFO SEG6 4 45 AVSS SEG7 5 44 IOA0 SEG8 6 43 IOA1 SEG9 7 42 IOA2 41 IOA3 40 IOA4 SEG10 SEG10 8 SEG11 SEG11 Y 9 X (0,0) IOA6 38 IOA7 SEG14 SEG14 12 37 IOB0 SEG15 SEG15 13 36 IOB1 SEG16 SEG16 14 35 IOB2 SEG17 SEG17 15 34 IOB3 SEG18 SEG18 16 33 IOB4 SEG19 SEG19 17 32 IOB6 IOC0_DAC2 IOC1 IOC2 VSS X32O X32I ROSC 31 RESET 20 21 22 23 24 25 26 27 28 29 30 VDD 19 IOD1_SEG23 SEG23 IOA5_SEG20 SEG20 18 IOB7 39 11 IOD0_SEG22 SEG22 10 SEG13 SEG13 IOB5_SEG21 SEG21 SEG12 SEG12 This IC substrate should be connected to VSS Note1: To ensure that the IC functions properly, please bond all of VDD and VSS pins. Note2: The 0.1µF capacitor between VDD and VSS should be placed to IC as close as possible. 9.2. Ordering Information Product Number Package Type GPTC6603A1-NnnV-C Chip form Note1: Code number is assigned for customer. Note2: Code number (N = A - Z or 0 - 9, nn = 00 - 99); version (V = A - Z). © Generalplus Technology Inc. Proprietary & Confidential 11 MAY 11, 2006 Version: 1.0 GPTC6603A1 GPTC6603A1 10. DISCLAIMER The information appearing in this publication is believed to be accurate. Integrated circuits sold by Generalplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. GENERALPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or regarding the freedom of the described chip(s) from patent infringement. OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. specifications and prices at any time without notice. Accordingly, the reader is cautioned to verify that the data sheets and other information in this publication are current before placing orders. applications. FURTHERMORE, GENERALPLUS MAKES NO WARRANTY GENERALPLUS reserves the right to halt production or alter the Products described herein are intended for use in normal commercial Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by GENERALPLUS for such applications. Please note that application circuits illustrated in this document are for reference purposes only. © Generalplus Technology Inc. Proprietary & Confidential 12 MAY 11, 2006 Version: 1.0 GPTC6603A1 GPTC6603A1 11. REVISION HISTORY Date Revision # MAY 11, 2006 1.0 © Generalplus Technology Inc. Proprietary & Confidential Description Original Page 13 13 MAY 11, 2006 Version: 1.0