AN0075 GPL16925X GPL169251A GPL169256UA

GPL16925X Oct. 13, 2009 Reset Flag Register Mistakenly Clearance Issue Introduction Reset flag register 0x7006 will be mistakenly

AN0075 AN0075 GPL16925X GPL16925X Oct. 13, 2009 Reset Flag Register Mistakenly Clearance Issue Introduction Reset flag register 0x7006 will be mistakenly cleared when writing to system clock control register, 0x7007. Analysis When program writes data to system clock control register 0x7007, this data will also be written to reset flag register 0x7006 and cause corresponding reset flag to be mistakenly cleared (write 1 to clear flag). Conclusion To avoid program mistakenly clearing reset flag, programmers should read reset flag first before changing system clock control register setting. © Generalplus Technology Inc. PAGE 1 Oct. 13, 2009 AN0075 AN0075 GPL16925X GPL16925X Oct. 13, 2009 Watchdog Reset Issue Introduction Watchdog timeout will have no function after watchdog timer is cleared (write 0xAxx5 to watchdog clear register 0x700B). Analysis When 0xAxx5 is written into watchdog clear register 0x700B, the watchdog will keep in clear status and cause watchdog timer stop operating. Conclusion Programmer should generate a dummy clock for watchdog control logic to release watchdog from clear status via reading any of the watchdog registers (watchdog reset control register 0x700A or watch clear register 0x700B). Ex: R1 = 0xA005 [P_Watchdog_Clear] = r1 R1 = [P_Watchdog_Ctrl] © Generalplus Technology Inc. PAGE 2 Oct. 13, 2009 AN0075 AN0075 GPL16925X GPL16925X Oct. 13, 2009 TimeBase Reset Issue Introduction TimeBase interrupt will have no function when TimeBase is reset via TimeBase Reset control register (write 0x5555 to register P_TimeBase_Reset 0x70B8). Analysis When 0x5555 is written into TimeBase Reset control register 0x70B8, the TimeBase interrupt will have no function. Conclusion Programmer should generate a dummy clock for TimeBase control logic to release TimeBase from reset status via reading TimeBaseX control registers. Ex: R1 = 0x5555 [P_TimeBase_Reset] = r1 R1 = [P_TimeBaseA_Ctrl] © Generalplus Technology Inc. PAGE 3 Oct. 13, 2009 AN0075 AN0075 GPL16925X GPL16925X Oct. 13, 2009 UART/IrDA Reset Issue Introduction UART/IrDA control logic will keep in reset status when UART/IrDA is reset via UART/IrDA Reset control bit (write 1 to register P_UARTIrDA_Ctrl 0x7102, bit11). Analysis When 1 is written into UART/IrDA Reset control bit (P_UARTIrDA_Ctrl 0x7102, bit11), the UART/IrDA control logic will keep in reset status. Conclusion Programmer should generate a dummy clock for UART/IrDA control logic to release UART/IrDA from reset status via read UART/IrDA control registers. Ex: R1 = [P_UARTIrDA_Ctrl] R1 |= 0x0800 [P_UARTIrDA_Ctrl] = R1 R1 = [P_UARTIrDA_Ctrl] © Generalplus Technology Inc. PAGE 4 Oct. 13, 2009 AN0075 AN0075 GPL16925X GPL16925X Oct. 13, 2009 SPI Reset Issue Introduction SPI control logic will keep in reset status when SPI is reset via SPI Reset control bit (write 1 to register P_ SPI _Ctrl 0x7102, bit11). Analysis When 1 is written into SPI Reset control bit (P_ SPI _Ctrl 0x7102, bit11), the SPI control logic will keep in reset status. Conclusion Programmer should generate a dummy clock for SPI control logic to release SPI from reset status via read SPI control registers. Ex: R1 = [P_ SPI _Ctrl] R1 |= 0x0800 [P_ SPI _Ctrl] = R1 R1 = [P_ SPI _Ctrl] © Generalplus Technology Inc. PAGE 5 Oct. 13, 2009 AN0075 AN0075 GPL16925X GPL16925X Oct. 13, 2009 The Differences between GPL169251A GPL169251A & GPL169256UA GPL169256UA (A) Power System Introduction GPL169251A GPL169251A IC power is supplied from external power, but GPL169256UA GPL169256UA (A) IC power can be supplied from external power or embedded regulator. Analysis GPL169251A GPL169251A and GPL169256UA GPL169256UA(A) are both embedded internal regulators. GPL169251A GPL169251A embedded regulator (Input pin: VDDC_33 / Output pin: VDDO_25) can generate 2.5V output voltage which can only supply for IC core power; other IO power pins (VDDANA_33, VDDAUD_33, VDDIO_33, VDDADC_33 and VDDUSB_33) should be supplied from external power. GPL169256UA GPL169256UA(A) embedded regulator (Input pin: VDDREG_55 / Output pin: VDDO_33) output voltage can be opted as 2.5V, 2.7V, 2.9V, 3.1V, 3.3V or disabled (Mask option). This output voltage can supply power to entire IC (IC core power & IO power), except peripheral components e.g. amplifier and .etc. GPL169256UA GPL169256UA(A) embedded regulator output VDDO_33 pin is also the IC core power input pin; thus, programmers should provide an external power to VDDO_33 pin when embedded regulator is disabled. Conclusion 1. Generalplus suggests circuit designers reserving optional power path from VDDO_33 to entire IC in schematic for GPL169256UA GPL169256UA(A). 2. Programmers should provide an external power to VDDO_33 pin if embedded regulator is disabled. © Generalplus Technology Inc. PAGE 6 Oct. 13, 2009 AN0075 AN0075 GPL16925X GPL16925X Oct. 13, 2009 Power Leakage Issue for GPL169256UA GPL169256UA (A) Introduction The power leakage issue will occur when the IO power (VDDANA_33, VDDAUD_33, VDDIO_33, VDDADC_33 and VDDUSB_33) and IC core power (VDDO_33) voltage is different. Analysis GPL169256UA GPL169256UA(A) embedded regulator (Input pin: VDDREG_55 / Output pin: VDDO_33) output voltage can provide entire IC power. For GPL169256UA GPL169256UA(A) IC design, the IC core power and IO power voltage should be the same to prevent power leakage. Conclusion GENERALPLUS suggests the IO power (VDDANA_33, VDDAUD_33, VDDIO_33, VDDADC_33 and VDDUSB_33) and IC core power (VDDO_33) should be the same to prevent power leakage. © Generalplus Technology Inc. PAGE 7 Oct. 13, 2009 AN0075 AN0075 GPL16925X GPL16925X Oct. 13, 2009 LCD Control Register Setting Issue Introduction Any modification for P_LCD_Setup register is valid only when ROSC is enabled and frame end flag is set. Analysis For GPL16925X GPL16925X, LCD controller source clock is ROSC; thus, when programmers do any modification to P_LCD_Setup register, ROSC should be enabled even LCD selects low power mode (P_LCD_Setup bit7=1, 32768Hz source clock). When LCD turn-off procedure is executing, the ROSC should be enabled first and programmers should delay at least one LCD frame period to ensure LCD driver is disabled properly. Conclusion Any modification for P_LCD_Setup register is valid only when ROSC is enabled and frame end flag is set. © Generalplus Technology Inc. PAGE 8 Oct. 13, 2009 AN0075 AN0075 GPL16925X GPL16925X Oct. 13, 2009 DAC Driver Enable/Disable Power Consumption Issue in Sleep Mode Introduction Programmers should delay at least 245ms to assure that DAC driver is Enabled/Disabled successfully. Analysis For GPL16925X GPL16925X, DAC driver needs about 245ms to execute driver enable/disable process. Thus, programmers should delay at least 245ms to assure that DAC driver is Enabled/Disabled correctly. The DAC driver enable/disable process timer source clock is 32768Hz; thus, programmers should delay at least 245ms to assure DAC driver is disabled properly before system enter sleep mode (32768Hz crystal will be disabled when system enters sleep mode). If DAC driver is enabled, the IC will increase about 3mA power consumption. Conclusion Programmers should delay at least 245ms to assure that DAC driver is disabled properly before system enters sleep mode (32768Hz crystal will be disabled when entering sleep mode). If DAC driver is enabled, the IC will increase about 3mA power consumption. -This concludes the engineering note- © Generalplus Technology Inc. PAGE 9 Oct. 13, 2009