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GLC 3-29

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ic hfc 4094

Abstract: LN 358 n CONOUIT THREAO AOARTER HG I 3.5 CONOUIT THREAO M20 X I.5 CONOUIT THREAO HF I X2 CONDUIT THREAO - GLC X
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A54 ZENER

Abstract: A3PE600L the GLB and GLC global outputs to drive the global networks. A PLL macro can also drive the YB and YC regular core outputs. The GLB (or GLC) global outputs cannot be reused if the YB (or YC) outputs are used , /LVPECL Macro Clock Conditioning PLL Macro CLKA GLA LOCK GLB YB GLC YC Output GLA or GLA and (GLB or YB) or GLA and (GLC or YC) or GLA and (GLB or YB) and (GLC or YC) PADN PADP Y , ] XDLYSEL VCOSEL[2:0] CLKDLY Macro CLK GL GLA or GLB DLYGL[4:0] or GLC CLKBUF_LVDS/LVPECL
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hall sensor u18 024

Abstract: Johnson motor 2 607 022 013 reference clock. It uses the GLA and optionally the GLB and GLC global outputs to drive the global networks. A PLL macro can also drive the YB and YC regular core outputs. The GLB (or GLC) global output cannot , Conditioning PLL Macro CLKA GLA LOCK GLB YB GLC YC Output GLA or GLA and (GLB or YB) or GLA and (GLC or YC) or GLA and (GLB or YB) and (GLC or YC) PADN PADP Y POWERDOWN INBUF* Macro PAD Y , CLK GL GLA or GLB DLYGL[4:0] or GLC CLKBUF_LVDS/LVPECL Macro PADN PADP Y CLKBUF Macro
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cortex-m1

Abstract: dflipflop the GLB and GLC global outputs to drive the global networks. A PLL macro can also drive the YB and YC regular core outputs. The GLB (or GLC) global outputs cannot be reused if the YB (or YC) outputs are used , /LVPECL Macro Clock Conditioning PLL Macro CLKA EXTFB POWERDOWN GLA LOCK GLB YB GLC YC Output GLA or GLA and (GLB or YB) or GLA and (GLC or YC) or GLA and (GLB or YB) and (GLC or YC) PADN PADP , ] XDLYSEL VCOSEL[2:0] CLKDLY Macro CLK GL GLA or GLB DLYGL[4:0] or GLC CLKBUF_LVDS/LVPECL
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Abstract: the GLB and GLC global outputs to drive the global networks. A PLL macro can also drive the YB and YC regular core outputs. The GLB (or GLC) global outputs cannot be reused if the YB (or YC) outputs are used , /LVPECL Macro Clock Conditioning PLL Macro CLKA GLA LOCK GLB YB GLC YC Output GLA or GLA and (GLB or YB) or GLA and (GLC or YC) or GLA and (GLB or YB) and (GLC or YC) PADN PADP Y , ] XDLYSEL VCOSEL[2:0] CLKDLY Macro CLK GL GLA or GLB DLYGL[4:0] or GLC CLKBUF_LVDS/LVPECL Actel
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application note 979

Abstract: optionally the GLB and GLC global outputs to drive the global networks. A PLL macro can also drive the YB and YC regular core outputs. The GLB (or GLC) global outputs cannot be reused if the YB (or YC) outputs , Conditioning PLL Macro CLKA EXTFB POWERDOWN GLA LOCK GLB YB GLC YC Output GLA or GLA and (GLB or YB) or GLA and (GLC or YC) or GLA and (GLB or YB) and (GLC or YC) PADN PADP Y INBUF* Macro PAD Y , CLK GL GLA or GLB DLYGL[4:0] or GLC CLKBUF_LVDS/LVPECL Macro PADN PADP Y CLKBUF Macro
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9AB TRANSISTOR

Abstract: Clocking Options 2 -1 8 Advanced v0.6 PLL / CCC GLA GLC To Core NGMUX CLKOUT Fusion , and GLC global outputs to drive the global networks. A PLL macro can also drive the YB and YC regular core outputs. The GLB (or GLC) global output cannot be reused if the YB (or YC) output is used , more information. Output GLA LOCK GLB YB GLC YC PADP PAD â'¢ Clock , [6:0] FBDLY[4:0] FBSEL[1:0] XDLYSEL VCOSEL[2:0] GLA or GLA and (GLB or YB) or GLA and (GLC
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High voltage Diode GLC 3-29

Abstract: transistor 1548 b PLL / CCC GLA GLC Figure 2-16 · Fusion Clocking Options 2 -1 8 Advanced v0.7 Fusion , , optionally, the GLB and GLC global outputs to drive the global networks. A PLL macro can also drive the YB and YC regular core outputs. The GLB (or GLC) global output cannot be reused if the YB (or YC) output , LVDS/LVPECL Macro PADN PADP Y GLB YB GLC YC OADIVHALF OADIV[4:0] OAMUX[2:0] DLYGLA[4:0] OBDIV , YB) or GLA and (GLC or YC) or GLA and (GLB or YB) and (GLC or YC) Notes: 1. Visit the Actel
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fr diode 205

Abstract: A3PE600 input to drive its reference clock. It uses the GLA and optionally the GLB and GLC global outputs to , GLC) global output cannot be reused if the YB (or YC) output is used (Figure 2-13 on page 2-14). Refer , GLA LOCK GLB YB GLC YC Output GLA or GLA and (GLB or YB) or GLA and (GLC or YC) or GLA and (GLB or YB) and (GLC or YC) PADN PADP Y POWERDOWN INBUF* Macro PAD Y OADIV[4:0] OAMUX[2:0 , DLYGL[4:0] or GLC CLKBUF_LVDS/LVPECL Macro PADN PADP Notes: CLKBUF Macro PAD Y CLKINT Macro
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A3PE600

Abstract: reference clock. It uses the GLA and optionally the GLB and GLC global outputs to drive the global networks. A PLL macro can also drive the YB and YC regular core outputs. The GLB (or GLC) global output cannot , Conditioning PLL Macro CLKA GLA LOCK GLB YB GLC YC Output GLA or GLA and (GLB or YB) or GLA and (GLC or YC) or GLA and (GLB or YB) and (GLC or YC) PADN PADP Y POWERDOWN INBUF* Macro PAD Y , CLK GL GLA or GLB DLYGL[4:0] or GLC CLKBUF_LVDS/LVPECL Macro PADN PADP Y CLKBUF Macro
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dunlop s 708

Abstract: A3PE600 input to drive its reference clock. It uses the GLA and optionally the GLB and GLC global outputs to , GLC) global output cannot be reused if the YB (or YC) output is used (Figure 2-13 on page 2-14). Refer , GLA LOCK GLB YB GLC YC Output GLA or GLA and (GLB or YB) or GLA and (GLC or YC) or GLA and (GLB or YB) and (GLC or YC) PADN PADP Y POWERDOWN INBUF* Macro PAD Y OADIV[4:0] OAMUX[2:0 , DLYGL[4:0] or GLC CLKBUF_LVDS/LVPECL Macro PADN PADP Notes: CLKBUF Macro PAD Y CLKINT Macro
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fr diode 205

Abstract: A3PE600 the GLB and GLC global outputs to drive the global networks. A PLL macro can also drive the YB and YC regular core outputs. The GLB (or GLC) global output cannot be reused if the YB (or YC) output is used
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