GAL22LV10 22V10 GAL22LV10C 132X44 GAL22LV10D 1-800-LATTICE GAL22LV10D-4LJ

Tolew 5V Inp rant 22Luts on V10 D Features GAL22LV10 Low Voltage E2CMOS PLD Generic Array LogicTM Functional Block Diagram

Ne Tolew 5V Inp rant 22Luts on V10 D Features GAL22LV10 GAL22LV10 Low Voltage E2CMOS PLD Generic Array LogicTM Functional Block Diagram · HIGH PERFORMANCE E2CMOS® TECHNOLOGY - 4 ns Maximum Propagation Delay - Fmax = 250 MHz - 3 ns Maximum from Clock Input to Data Output - UltraMOS® Advanced CMOS Technology RESET I/CLK 8 OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q OLMC I/O/Q I · 3.3V LOW VOLTAGE 22V10 22V10 ARCHITECTURE - JEDEC-Compatible 3.3V Interface Standard - 5V Compatible Inputs - I/O Interfaces with Standard 5V TTL Devices (GAL22LV10C GAL22LV10C) 10 I 12 I · E2 CELL TECHNOLOGY - Reconfigurable Logic - Reprogrammable Cells - 100% Tested/100% Yields - High Speed Electrical Erasure (