FW323 FW322 06/FW323 PCI32 FW323/FW322 66MHZ - Datasheet Archive

 

April 2005 TM FW323 06 1394A PCI PHY/Link Open Host Controller Interface Features 1394a-2000 OHCI link and PHY core function in a

 

Data Sheet April 2005 TM FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Features 1394a-2000 OHCI link and PHY core function in a single device: - Single-chip link and PHY enable smaller, simpler, more efficient motherboard and add-in card designs - Enables lower system costs - Leverages proven 1394a-2000 PHY core design - Demonstrated compatibility with current Microsoft Windows ® drivers and common applications - Demonstrated interoperability with existing, as well as older, 1394 TM consumer electronics and peripherals products - Feature-rich implementation for high performance in common applications - Supports low-power system designs (CMOS implementation, power management features) - Provides LPS, LKON, and CNA outputs to support legacy power management implementations OHCI: - Complies with the 1394 OHCI 1.1 Specification - OHCI 1.0 backwards compatible-configurable via EEPROM to operate in either OHCI 1.0 or OHCI 1.1 mode - Complies with Microsoft Windows logo program system and device requirements - Listed on Windows hardware compatibility list http://www.microsoft.com/hcl/results.asp - Compatible with Microsoft Windows and MacOS ® operating systems - 4 Kbyte isochronous transmit FIFO - 2 Kbyte asynchronous transmit FIFO - 4 Kbyte isochronous receive FIFO - 2 Kbyte asynchronous receive FIFO - Dedicated asynchronous and isochronous descriptor-based DMA engines - Eight isochronous transmit contexts - Eight isochronous receive contexts - Prefetches isochronous transmit data - Supports posted write transactions - Supports parallel processing of incoming physical read and write requests - Supports notification (via interrupt) of a failed register access 1394a-2000 PHY core: - Compliant with IEEE ® 1394a-2000, Standard for a High Performance Serial Bus (Supplement) - Provides three fully compliant cable ports, each supporting 400 Mbits/s, 200 Mbits/s, and 100 Mbits/s traffic - Supports extended BIAS_HANDSHAKE time for enhanced interoperability with camcorders - While unpowered and connected to the bus, will not drive TPBIAS on a connected port even if receiving incoming bias voltage on that port - Does not require external filter capacitor for PLL - Supports link-on as a part of the internal PHY core-link interface - 25 MHz crystal oscillator and internal PLL provide a 50 MHz internal link-layer controller clock as well as transmit/receive data at 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s - Interoperable across 1394 cable with 1394 physical layers (PHY core) using 5 V supplies - Provides node power-class information signaling for system power management - Supports ack-accelerated arbitration and fly-by concatenation - Supports arbitrated short bus reset to improve utilization of the bus - Fully supports suspend/resume - Supports connection debounce - Supports multispeed packet concatenation - Supports PHY pinging and remote PHY access packets - Reports cable power fail interrupt when voltage at CPS pin falls below 7.5 V - Provides separate cable bias and driver termination voltage supply for each port Link: - Cycle master and isochronous resource manager capable - Supports 1394a-2000 acceleration features PCI: - Revision 2.2 compliant - 33 MHz/32-bit operation - Programmable burst size thresholds for PCI data transfer - Supports optimized memory read line, memory read multiple, and memory write invalidate burst commands - Supports PCI Bus Power Management Interface Specification v.1.1, including D3cold wakeups - Supports CLKRUN# protocol per PCI Mobile Design Guide - Supports Mini PCI Specification v1.0, including Mini PCI power requirements - Global byte swap function - CardBus support per PC Card Standard Release 8.0, including 128 bytes of on-chip tuple memory. FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Data Sheet April 2005 Table of Contents Contents Page Features . 1 Other Features . 6 FW323 FW323 Functional Overview . 6 FW323 FW323 Functional Description . 6 PCI Core . 7 OHCI Data Transfer . 8 OHCI Isochronous Data Transfer . 8 Isochronous Register Access . 9 OHCI Asynchronous Data Transfer . 9 Asynchronous Register Access . 9 Link Core . 11 PHY Core . 13 Pin Information . 15 Internal Registers . 22 PCI Configuration Registers . 22 Vendor ID Register . 24 Device ID Register . 24 PCI Command Register . 25 PCI Status Register . 26 Class Code and Revision ID Registers . 27 Latency Timer and Cache Line Size Register . 28 Header Type and BIST Register . 28 OHCI Base Address Register . 29 CardBus Base Address Register . 30 CIS Pointer . 30 PCI Subsystem Identification Register . 31 PCI Power Management Capabilities Pointer Register . 31 Interrupt Line and Pin Register . 32 MIN_GNT and MAX_LAT Register . 32 PCI OHCI Control Register . 33 Capability ID and Next Item Pointer Register . 33 Power Management Capabilities Register . 34 Power Management Control and Status Register . 35 Power Management CSR PCI-to-PCI Bridge Support Extensions . 36 Power Management Data . 36 CardBus Function Registers (CardBusN = 0) . 36 OHCI Registers . 37 OHCI Version Register . 40 GUID ROM Register . 41 Asynchronous Transmit Retries Register . 41 CSR Data Register . 42 CSR Compare Register . 42 CSR Control Register . 42 Configuration ROM Header Register . 43 Bus Identification Register . 44 Bus Options Register . 44 GUID High Register . 45 GUID Low Register . 45 Configuration ROM Mapping Register . 46 Posted Write Address Low Register . 47 Posted Write Address High Register . 47 2 Agere Systems Inc. Data Sheet April 2005 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Table of Contents (continued) Contents Page Vendor ID Register . Host Controller Control Register . SelfID Buffer Pointer Register . SelfID Count Register . Isochronous Receive Multiple Channel Mask High (IRMultiChanMaskHi) Register . Isochronous Receive Multiple Channel Mask Low (IRMultiChanMaskLo) Register . Interrupt Event (IntEvent) Register . Interrupt Mask (IntMask) Register . Isochronous Transmit Interrupt Event (isoXmitIntMask) Register . Isochronous Transmit Interrupt Mask (isoXmitIntMask) Register . Isochronous Receive Interrupt Event (isoRecvIntEvent) Register . Isochronous Receive Interrupt Mask (isoRecvIntMask) Register . Fairness Control Register . Link Control Register . Node Identification Register . PHY Core Layer Control Register . Isochronous Cycle Timer Register . Asynchronous Request Filter High Register . Asynchronous Request Filter Low Register . Physical Request Filter High Register . Physical Request Filter Low Register . Asynchronous Context Control Register . Asynchronous Context Command Pointer Register . Isochronous Transmit Context Control (IT DMA ContextControl) Register . Isochronous Transmit Context Command Pointer Register . Isochronous Receive Context Control (IR DMA ContextControl) Register . Isochronous Receive Context Command Pointer Register . Isochronous Receive Context Match (IR DMA ContextMatch) Register . FW323 FW323 Vendor-Specific Registers . Isochronous DMA Control . Asynchronous DMA Control . Link Options . Internal Register Configuration . PHY Core Register Map . PHY Core Register Fields . Crystal Selection Considerations . Load Capacitance . Adjustment to Crystal Loading . Crystal/Board Layout . Serial EEPROM Interface . ac Characteristics of Serial EEPROM Interface Signals . NAND Tree Testing . Solder Reflow and Handling . Absolute Maximum Voltage/Temperature Ratings . Electrical Characteristics . Timing Characteristics . Outline Diagrams . 128-Pin TQFP . Ordering Information . Agere Systems Inc. 47 48 50 50 51 51 52 54 56 57 58 59 59 60 61 62 62 63 63 64 64 65 66 67 68 69 70 71 72 72 73 74 75 75 76 81 81 81 81 82 82 85 87 87 88 90 91 91 91 3 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Data Sheet April 2005 Table of Contents (continued) Figure Page Figure 1. FW323 FW323 Conceptual Block Diagram . 6 Figure 2. PCI Core Block Diagram . 7 Figure 3. OHCI Core Block Diagram . 8 Figure 4. Link Core Block Diagram . 11 Figure 5. The PHY Core Block Diagram . 12 Figure 6. Pin Assignments for the FW323 FW323 06 . 15 Figure 7. Crystal Circuitry . 81 Figure 8. Bus Timing . 83 Figure 9. Write Cycle Timing . 83 Figure 10. Data Validity . 83 Figure 11. Start and Stop Definition . 84 Figure 12. Output Acknowledge . 84 Figure 13. Nand Tree Logic Structure . 86 Table Page Table 1. Pin Descriptions . 16 Table 2. Bit-Field Access Tag Description . 22 Table 3a. PCI Configuration Register Map, CardBusN = 1 . 22 Table 3b. PCI Configuration Register Map, CardBusN = 0 . 23 Table 4. PCI Command Register Description . 25 Table 5. PCI Status Register . 26 Table 6. Class Code and Revision ID Register Description . 27 Table 7. Latency Timer and Class Cache Line Size Register Description . 28 Table 8. Header Type and BIST Register Description . 28 Table 9. OHCI Base Address Register Description . 29 Table 10. CardBus Base Address Register Description . 30 Table 11. PCI Subsystem Identification Register Description . 31 Table 12. Interrupt Line and Pin Register Description . 32 Table 13. MIN_GNT and MAX_LAT Register Description . 32 Table 14. PCI OHCI Control Register Description . 33 Table 15. Capability ID and Next Item Pointer Register Description . 33 Table 16. Power Management Capabilities Register Description . 34 Table 17. Power Management Control and Status Register Description . 35 Table 18. Power Management Data Register Description . 36 Table 19. OHCI Register Map . 37 Table 20. OHCI Version Register Description . 40 Table 21. GUID ROM Register Description . 41 Table 22. Asynchronous Transmit Retries Register Description . 41 Table 23. CSR Data Register Description . 42 Table 24. CSR Compare Register Description . 42 Table 25. CSR Control Register Description . 42 Table 26. Configuration ROM Header Register Description . 43 Table 27. Bus Identification Register Description. 44 Table 28. Bus Options Register Description . 44 Table 29. GUID High Register Description . 45 Table 30. GUID Low Register Description . 45 Table 31. Configuration ROM Mapping Register Description . 46 Table 32. Posted Write Address Low Register Description . 47 Table 33. Posted Write Address High Register Description . 47 Table 34. Vendor ID Register Description . 47 4 Agere Systems Inc. Data Sheet April 2005 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Table of Contents (continued) Table Page Table 35. Host Controller Control Register Description . 48 Table 36. SelfID Buffer Pointer Register Description . 50 Table 37. SelfID Count Register Description . 50 Table 38. Isochronous Receive Channel Mask High Register Description . 51 Table 39. Isochronous Receive Channel Mask Low Register Description . 51 Table 40. Interrupt Event Register Description . 52 Table 41. Interrupt Mask Register Description . 54 Table 42. Isochronous Transmit Interrupt Event Register Description . 56 Table 43. Isochronous Transmit Interrupt Event Description . 57 Table 44. Isochronous Receive Interrupt Event Description . 58 Table 45. Fairness Control Register Description . 59 Table 46. Link Control Register Description . 60 Table 47. Node Identification Register Description . 61 Table 48. PHY Core Layer Control Register Description . 62 Table 49. Isochronous Cycle Timer Register Description . 62 Table 50. Asynchronous Request Filter High Register Description . 63 Table 51. Asynchronous Request Filter Low Register Description . 63 Table 52. Physical Request Filter High Register Description . 64 Table 53. Physical Request Filter Low Register Description . 64 Table 54. Asynchronous Context Control Register Description . 65 Table 55. Asynchronous Context Command Pointer Register Description . 66 Table 56. Isochronous Transmit Context Control Register Description . 67 Table 57. Isochronous Transmit Context Command Pointer Register Description . 68 Table 58. Isochronous Receive Context Control Register Description . 69 Table 59. Isochronous Receive Context Command Pointer Register Description . 70 Table 60. Isochronous Receive Context Match Register Description . 71 Table 61. FW323 FW323 Vendor-Specific Registers Description . 72 Table 62. Isochronous DMA Control Registers Description . 72 Table 63. Asynchronous DMA Control Registers Description . 73 Table 64. Link Options Register Description . 74 Table 65. PHY Core Register Map . 75 Table 66. PHY Core Register Fields . 76 Table 67. PHY Core Register Page 0: Port Status Page . 78 Table 68. PHY Core Register Port Status Page Fields . 79 Table 69. PHY Core Register Page 1: Vendor Identification Page . 80 Table 70. PHY Core Register Vendor Identification Page Fields . 80 Table 71. ac Characteristics of Serial EEPROM Interface Signals . 82 Table 72. NAND Tree Testing . 85 Table 73. Absolute Maximum Ratings . 87 Table 74. Analog Characteristics . 88 Table 75. Driver Characteristics . 89 Table 76. Device Characteristics . 89 Table 77. Switching Characteristics . 90 Table 78. Clock Characteristics . 90 Agere Systems Inc. 5 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Data Sheet April 2005 Features (continued) Other Features I2C serial ROM interface CMOS process 3.3 V operation, 5 V tolerant inputs 128-pin TQFP package NAND tree test mode FW323 FW323 Functional Overview The FW323 FW323 is a high-performance, PCI bus-based open host controller designed by Agere Systems Inc. for implementation of IEEE 1394a-2000 compliant systems and devices. Link-layer functions are handled by the FW323 FW323, utilizing the on-chip 1394a-2000 compliant link core and physical layer core. A high-performance and cost-effective solution for connecting and servicing multiple IEEE 1394 (both 1394-1995 and 1394a-2000) peripheral devices can be realized using this PHY/link OHCI device. OHCI ASYNCHRONOUS DATA TRANSFER PCI BUS PCI CORE OHCI ISOCHRONOUS DATA TRANSFER CABLE PORT 2 LINK CORE PHY CORE CABLE PORT 1 CABLE PORT 0 ROM I/F 5-6250 (F).f Figure 1. FW323 FW323 Conceptual Block Diagram FW323 FW323 Functional Description The FW323 FW323 is comprised of four major functional sections (see Figure 1): PCI core, OHCI isochronous and asynchronous data transfer, link core, and PHY core. The following is a general description of each of the major sections. 6 Agere Systems Inc. Data Sheet April 2005 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface FW323 FW323 Functional Description (continued) SLAVE CONTROL PCI SLAVE MASTER CONTROL PCI MASTER ADDRESS/DATA MUX PCI BUS PCI CONFIGURATION Figure 2. PCI Core Block Diagram PCI Core The PCI core (shown in Figure 2) serves as the interface to the PCI bus. It contains the state machines that allow the FW323 FW323 to respond properly when it is the target of the transaction. Also, during 1394 packet transmission or reception, the PCI core arbitrates for the PCI bus and enables the FW323 FW323 to become the bus master for reading the different buffer descriptors and management of the actual data transfers to/from host system memory. The PCI core also supports the PCI Bus Power Management Interface Specification v.1.1. Included in this support is a standard power management register interface accessible through the PCI configuration space. Through this register interface, software is able to transition the FW323 FW323 into four distinct power consumption states (D0, D1, D2, and D3hot). This permits software to selectively increase/decrease the power consumption of the FW323 FW323 for reasons such as periods of system inactivity or power conservation. In addition, the FW323 FW323 also includes support for waking up the system through the generation of a power management event (PME). The FW323 FW323 supports generation of a power management event (PME) while in the D0, D1, D2, D3hot, and D3cold power states. To facilitate PME generation from the D3cold power state, the FW323 FW323 supports the detection of an auxiliary power supply. If an auxiliary power supply is not present, PME generation from the D3cold power state is disabled. Refer to the FW322 FW322 06/FW323 06/FW323 06 D3cold Application Note for specific implementation details of enabling and supporting the generation of a PME wakeup event while the FW323 FW323 is in the D3cold power state. The PCI core will support CardBus applications, per the PC Card Standard v8.0, when the CARDBUSN pin is low. This support includes the CardBus I/O electrical requirements, the CIS (Card Information Structure) pointer, 128 bytes of memory in PCI configuration space for user-defined tuples, an additional Base Address register dedicated to CardBus registers, a serial EEPROM format to load the CIS into PCI configuration space, and the CardBus Function Event registers. The FW323 FW323 will also support the CardBus implementation of PCI power management, including support for the CSTSCHG (CardBus status change) signal. Refer to the Application Note, Using the FW322 FW322 06/FW323 06/FW323 06 in CardBus Applications, for more information. Agere Systems Inc. 7 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Data Sheet April 2005 FW323 FW323 Functional Description (continued) ASYNCHRONOUS DATA TRANSFER SELFID DMA ASYNC_RX DMA PCI32 PCI32 INTERFACE ASYNC REGISTER ACCESS PCI SLAVE REGISTER SELECT PHYSICAL REQUEST/ RESPONSE DMA ASYNC_TX DMA OHCI INTERRUPT HANDLER AR FIFO AT FIFO ASYNC TX ADMIN ISOCHRONOUS DATA TRANSFER ISOCH REGISTER ACCESS PCI MASTER ASYNC RX ADMIN ISOCH RECEIVE DMA IR FIFO ARBITER ISOCH TRANSMIT DMA IT FIFO Figure 3. OHCI Core Block Diagram OHCI Data Transfer The OHCI core consists of the three blocks shown in Figure 3: the PCI interface (PCI32 PCI32_interface), the isochronous data transfer, and the asynchronous data transfer blocks. The PCI interface provides an interface between the OHCI blocks and the PCI core. It contains an arbiter to select the appropriate OHCI data engine to gain access to the PCI core. In addition, the PCI interface includes a register select function to decode slave accesses to the OHCI core and select data from appropriate sources. The PCI interface also has an OHCI interrupt handler to service OHCI generated interrupts, which are ultimately translated into PCI interrupts. OHCI Isochronous Data Transfer The isochronous data transfer logic, which is incorporated into the OHCI core, handles the transfer of isochronous data between the link core and the PCI interface module. It consists of the Isochronous register access module, the isochronous transmit DMA module, the isochronous receive DMA module, the isochronous transmit (IT) FIFO, and the isochronous receive (IR) FIFO. 8 Agere Systems Inc. Data Sheet April 2005 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface FW323 FW323 Functional Description (continued) Isochronous Register Access The Isochronous register access module services PCI slave accesses to OHCI registers within the isochronous block. The module also maintains the status of interrupts generated within the isochronous block and sends the isochronous interrupt status to the OHCI interrupt handler block. Isochronous Transmit DMA (ITDMA) The isochronous transmit DMA (ITDMA) module moves data from host memory to the link core, which will then send the data via the PHY core to the 1394 bus. This module consists of eight isochronous transmit contexts, each of which is independently configurable by software, and is capable of sending data on a separate 1394 isochronous channel. During each 1394 isochronous cycle, the ITDMA module will service each of the contexts and attempt to process one 1394 packet for each active context. While processing an active context, ITDMA will request access to the PCI bus. When granted PCI access, a descriptor block is fetched from host memory. This data is decoded by ITDMA to determine how much data is required and where in host memory the data resides. ITDMA initiates another PCI access to fetch this data, which is placed into the isochronous transmit FIFO for processing by the link core. If the context is not active, it is skipped by ITDMA for the current cycle. After processing each context, ITDMA writes a cycle marker word in the transmit FIFO to indicate to the link core that there is no more data for this isochronous cycle. As a summary, the major steps for the FW323 FW323 ITDMA to transmit a packet are the following: 1. Fetch a descriptor block from host memory. 2. Fetch data specified by the descriptor block from host memory and place it into the isochronous transmit FIFO. 3. Data in FIFO is read by the link and sent to the PHY core device interface. 1394 isochronous channel. However, software can select one context to receive data on multiple channels. When IRDMA detects that the link core has placed data into the receive FIFO, it immediately reads out the first word in the FIFO, which makes up the header of the isochronous packet. IRDMA extracts the channel number for the packet and packet filtering controls from the header. This information is compared with the Control registers for each context to determine if any context is to process this packet. If a match is found, IRDMA will request access to the PCI bus. When granted PCI access, a descriptor block is fetched from host memory. The descriptor provides information about the host memory block allocated for the incoming packet. IRDMA then reads the packet from the receive FIFO and writes the data to host memory via the PCI bus. If no match is found, IRDMA will read the remainder of the packet from the receive FIFO, but not process the data in any way. OHCI Asynchronous Data Transfer The asynchronous data transfer block within the OHCI core is functionally partitioned into blocks responsible for processing incoming SelfID packet streams, transmitting and receiving asynchronous 1394 packets, processing incoming physical request packets and outgoing physical response packets, and servicing accesses to OHCI registers within the respective asynchronous blocks. Asynchronous Register Access The Asynchronous register access module operates on PCI slave accesses to OHCI registers within the asynchronous block. The module also maintains the status of interrupts generated within the asynchronous block and sends the asynchronous interrupt status to the OHCI interrupt handler block. Isochronous Receive DMA (IRDMA) The isochronous receive DMA (IRDMA) module moves data from the isochronous receive FIFO to host memory. It consists of eight isochronous contexts, each of which is independently controlled by software. Normally, each context can process data on a single Agere Systems Inc. 9 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Data Sheet April 2005 FW323 FW323 Functional Description (continued) The header of the received packet is processed to determine, among other things, the following: Asynchronous Transmit DMA (ASYNC_TX DMA, ASYNC_TX_ADMIN) 1. The type of packet received. 2. The source and destinations. 3. The data and size, if any. 4. Any required operation, for example, compare and swap operation. The ASYNC_TX DMA and ASYNC_TX_ADMIN blocks of the FW323 FW323 manage the asynchronous transmission of either request or response packets. The mechanism for asynchronous transmission of requests and responses is similar. The only difference is the system memory location of the buffer descriptor list when processing the two contexts. Therefore, the discussion below, which pertains to asynchronous transmit requests, parallels that of asynchronous transmit responses. The FW323 FW323 asynchronous transmission of packets involves the following steps: 1. Fetch complete buffer descriptor block from host memory. 2. Get data from system memory and store into asynchronous transmit (AT) FIFO. 3. Request transfer of data from FIFO to the link core. 4. Handle retries, if any. 5. Handle errors in steps 1 to 4. 6. End the transfer if there are no errors. Asynchronous Receive DMA (ASYNC_RX DMA, ASYNC_RX_ADMIN) The ASYNC_RX DMA and ASYNC_RX_ADMIN blocks of the FW323 FW323 manage the processing of received packets. Data packets are parsed and stored in a dedicated asynchronous receive (AR) FIFO. Command descriptors are read through the PCI interface to determine the disposition of the data arriving through the 1394 link. 10 The asynchronous data transfer block also handles DMA transfers of SelfID packets during the 1394 bus initialization phase and block transactions associated with physical requests. Physical Request/Response DMA The Physical DMA block within the FW323 FW323 is responsible for processing incoming physical requests and outgoing physical responses. When an incoming asynchronous packet is received, the FW323 FW323 will process the packet automatically without software intervention if the packet meets a set of criteria defined within the OHCI specification. When the criteria are met, the asynchronous packet is reclassified as a physical packet. Requests that do not meet the criteria remain asynchronous packets and are processed as described above in the Asynchronous Receive DMA section. Processing packets as physical requests/ responses allows the FW323 FW323 to either receive or transmit an asynchronous packet without the use of DMA descriptors. Instead, the FW323 FW323 directly writes or reads data to/from memory using the address defined within the packet header. Since physical packets can be processed independently of the system's software and CPU, processing a packet as physical results in a system performance optimization. SelfID DMA The SelfID DMA block within the FW323 FW323 is responsible for receiving SelfID packets during the bus initialization process. The received SelfID packets are written into a software-defined host memory buffer. Agere Systems Inc. Data Sheet April 2005 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface FW323 FW323 Functional Description (continued) ISOCH CONTROL TIMER AT FIFO TX IT FIFO PHYDATA CRC DATAMUX AR FIFO PHY - LINK INTERFACE PHYCTL RX IR FIFO ADDRESS DECODER PCI SLAVE LINK CONTROL STATE MACHINE PHYLREQ INTERFACE CONTROL Figure 4. Link Core Block Diagram Link Core The link core shown in Figure 4 consists of the following blocks: Link Control State Machine: main link state machine that controls all other link core modules. Transmit (TX): reads from the AT and IT FIFOs and forms 1394 packets for transmit. Receive (RX): pipes incoming 1394 packet data to appropriate FIFO (if any). Address Decoder: decodes the destination ID of an incoming 1394 packet to determine if an acknowledge is needed. CRC: calculates and checks CRC on outgoing and incoming packets. Isochronous Control Timer: contains the logic for the 1394 cycle timer. DataMUX: pipes 1394 data to and from various modules. Interface Control: contains interrupt and registers for the link core. Interfaces with the slave control block of the PCI core. PHY-Link Interface: interfaces with the 1394 physical layer. Agere Systems Inc. 11 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface FW323 FW323 Functional Description (continued) It is the responsibility of the link to ascertain if a received packet is to be forwarded to the OHCI for processing. If so, the packet is directed to a proper inbound FIFO for either the isochronous block or the asynchronous block to process. The link is also responsible for CRC generation on outgoing packets and CRC checking on received packets. To become aware of data to be sent outbound on the 1394 bus, the link must monitor the OHCI FIFOs looking for packets in need of transmission. Based on data received from the OHCI block, the link will form packet headers for the 1394 bus. The link will alert the PHY core regarding the availability of the outbound data. It is the link's function to generate CRC for the outbound data. The link also provides PHY core register access for the OHCI. RECEIVED DATA DECODER/ RETIMER CPS LPS SYSCLK Data Sheet April 2005 LREQ BIAS VOLTAGE AND CURRENT GENERATOR R0 R1 CTL0 CTL1 D0 D1 D2 D3 D4 D5 D6 D7 LKON PC0 PC1 PC2 LINK INTERFACE I/O TPA0+ TPA0­ ARBITRATION AND CONTROL STATE MACHINE LOGIC TPBIAS0 CABLE PORT 0 TPB0+ TPB0­ CONTENDER SE SM CABLE PORT 1 CABLE PORT 2 RESETN TRANSMIT DATA ENCODER TPA1+ TPA1­ TPBIAS1 TPB1+ TPB1­ TPA2+ TPA2­ TPBIAS2 TPB2+ TPB2­ CRYSTAL OSCILLATOR, PLL SYSTEM, AND CLOCK GENERATOR XI XO 5-5459.i(F) R.01 Figure 5. The PHY Core Block Diagram 12 Agere Systems Inc. Data Sheet April 2005 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface FW323 FW323 Functional Description (continued) PHY Core The PHY core in Figure 5 on the preceding page, provides the analog physical layer functions needed to implement a three-port node in a cable-based IEEE 1394-1995 and IEEE 1394a-2000 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The PHY core interfaces with the link core. The PHY core requires either an external 24.576 MHz crystal or crystal oscillator. The internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216 MHz reference signal. The 393.216 MHz reference signal is internally divided to provide the 49.152 MHz, 98.304 MHz, and 196.608 MHz clock signals that control transmission of the outbound encoded strobe and data information. The 49.152 MHz clock signal is also supplied to the associated link layer controller (LLC) for synchronization of the link with the PHY core and is used for resynchronization of the received data. The PHY/link interface is a direct connection and does not provide isolation. Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight data lines (D[0:7]), and are latched internally in the PHY in synchronization with the 49.152 MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304 Mbits/s, 196.608 Mbits/s, or 393.216 Mbits/s as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPA and TPB cable pair(s). During packet reception, the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA and TPB cable pair. The received data strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two (for S100), four (for S200), or eight (for S400) parallel streams, resynchronized to the local system clock, and sent to the associated LLC. The received data is also transmitted (repeated) out of the other active (connected) cable ports. Agere Systems Inc. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage for the presence of the remotely supplied twisted-pair bias voltage. This monitor is called bias-detect. The TPBIAS circuit monitors the value of incoming TPA pair common-mode voltage when local TPBIAS is inactive. Because this circuit has an internal current source and the connected node has a current sink, the monitored value indicates the cable connection status. The monitor is called connect-detect. Both the TPB bias-detect monitor and TPBIAS connect-detect monitor are used in suspend/resume signaling and cable connection detection. The PHY core provides a 1.86 V nominal bias voltage for driver load termination. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. The value of this bias voltage has been chosen to allow interoperability between transceiver chips operating from 5 V or 3 V nominal supplies. This bias voltage source should be stabilized by using an external filter capacitor of approximately 0.33 µF. The port transmitter circuitry and the receiver circuitry are disabled when the port is disabled, suspended, or disconnected. The line drivers in the PHY core operate in a highimpedance current mode and are designed to work with external 112 line-termination resistor networks. One network is provided at each end of each twistedpair cable. Each network is composed of a pair of series-connected 56 resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair A (TPA) signals is connected to the TPBIAS voltage signal. The midpoint of the pair of resistors that is directly connected to the twisted-pair B (TPB) signals is coupled to ground through a parallel RC network with recommended resistor and capacitor values of 5 k and 220 pF, respectively. The values of the external resistors are specified to meet the 1394a2000 Specification when connected in parallel with the internal receiver circuits. 13 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface FW323 FW323 Functional Description (continued) An external resistor sets the driver output current, along with other internal operating currents. This resistor is connected between the R0 and R1 signals and has a value of 2.49 k ± 1%. Four signals are used as inputs to set four configuration status bits in the self-identification (SelfID) packet. These signals are hardwired high or low as a function of the equipment design. PC[0:2] are the three signals that indicate either the need for power from the cable or the ability to supply power to the cable. The fourth signal (CONTENDER), as an input, indicates whether a node is a contender for bus manager. When the CONTENDER signal is asserted, it means the node is a contender for bus manager. When the signal is not asserted, it means that the node is not a contender. The contender bit corresponds to the c field (bit 20) in the SelfID packet. PC[0:2] corresponds to the pwr field of the SelfID packet in the following manner: PC0 corresponds to bit 21, PC1 corresponds to bit 22, and PC2 corresponds to bit 23 (see SelfID packets table in Section 4.3.4.1 of the IEEE 1394-1995 and 1394a-2000 standards for additional details). As an example, for a Power_Class value of 001, PC0 = 0, PC1 = 0, and PC2 = 1. When the power supply of the PHY core is removed while the twisted-pair cables are connected, the PHY core transmitter and receiver circuitry has been designed to present a high impedance to the cable in order to not load the TPBIAS signal voltage on the other end of the cable. Data Sheet April 2005 Note: All gap counts on all nodes of a 1394 bus must be identical. The software accomplishes this by issuing PHY core configuration packets (see Section 4.3.4.3 of IEEE 1394-1995 and 1394a2000 standards) or by issuing two bus resets, which resets the gap counts to the maximum level (3Fh). The internal link power status (LPS) signal works with the internal LKON signal to manage the LLC power usage of the node. The LPS signal indicates if the LLC of the node is powered up or down. If LPS is inactive for more than 1.2 µs and less than 25 µs, the internal PHY/link interface is reset. If LPS is inactive for greater than 25 µs, the PHY will disable the internal PHY/link interface to save power. The FW323 FW323 continues its repeater function even when the PHY/link interface is disabled. If the PHY then receives a link-on packet, the internal LKON signal is activated to output a 6.114 MHz signal, which can be used by the LLC to power itself up. Once the LLC is powered up, the internal LPS signal communicates this to the PHY and the internal PHY/link interface is enabled. The internal LKON signal is turned off when the LCtrl bit is set. (For more information on this bit, refer to the Table 66 on PHY Core Register Fields in this data sheet.) Three of the FW323 FW323 pins are used to set up various test conditions used only during the device manufacturing process. These pins are SE, SM, and PTEST. Whenever the TPA±/TPB± signals are wired to a connector, they must be terminated using the normal termination network. This is required for reliable operation. For those applications when one or more of the FW323 FW323 ports are not wired to a connector, those unused ports may be left unconnected without normal termination. When a port does not have a cable connected, internal connect-detect circuitry will keep the port in a disconnected state. 14 Agere Systems Inc. Data Sheet April 2005 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 VSSA TPBIAS2 TPA2+ TPA2­ TPB2+ TPB2­ VDDA VSSA CPS VDD MPCIACTN LPS LKON PC0 PC1 PC2 CONTENDER PCI_VIOS PCI_AD[0] PCI_AD[1] VDD VSS PCI_AD[2] PCI_AD[3] PCI_AD[4] VSS PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_CBEN[0] VDD VSS PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] VSS PCI_AD[12] PCI_AD[21] PCI_AD[20] PCI_AD[19] PCI_AD[18] VDD VSS PCI_AD[17] PCI_AD[16] PCI_CBEN[2] PCI_FRAMEN VDD VSS PCI_IRDYN PCI_TRDYN PCI_DEVSELN PCI_STOPN VDD VSS PCI_PERRN PCI_SERRN PCI_PAR PCI_CBEN[1] VSS PCI_AD[15] PCI_AD[14] PCI_AD[13] 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 VDD VSS CARDBUSN NU CNA NANDTREE TEST1 ROM_CLK ROM_AD TEST0 VDD VSS CLKRUNN PCI_INTAN PCI_RSTN PCI_GNTN PCI_REQN PCI_PMEN/CSTSCHG VDD PCI_CLK VSS PCI_AD[31] PCI_AD[30] PCI_AD[29] PCI_AD[28] VDD VSS PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] VSS PCI_CBEN[3] PCI_IDSEL PCI_AD[23] PCI_AD[22] VDD VSS 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 VAUX_PRESENT NU SE SM PTEST RESETN XO XI PLLVSS PLLVDD R1 R0 VDDA VSSA TPBIAS0 TPA0+ TPA0­ TPB0+ TPB0­ TPBIAS1 TPA1+ TPA1­ TPB1+ TPB1­ VDDA VSSA Pin Information 5-7838 (F)a R.03 Note: Active-low signals within this document are indicated by an N following the symbol names. Figure 6. Pin Assignments for the FW323 FW323 06 Agere Systems Inc. 15 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Data Sheet April 2005 Pin Information (continued) Table 1. Pin Descriptions Pin Symbol* Type Description 1 2 3 VDD VSS CARDBUSN - - I 4 5 NU CNA - O 6 NANDTREE O 7 TEST1 I 8 9 10 ROM_CLK ROM_AD TEST0 I/O I/O I 11 12 13 VDD VSS CLKRUNN - - I/O 14 15 16 17 18 PCI_INTAN PCI_RSTN PCI_GNTN PCI_REQN PCI_PMEN/CSTSCHG O I I O O 19 20 21 22 23 24 25 26 VDD PCI_CLK VSS PCI_AD[31] PCI_AD[30] PCI_AD[29] PCI_AD[28] VDD - I - I/O I/O I/O I/O - Digital Power. Digital Ground. CardBusN (Active-Low). Selects mode of operation for PCI output buffers. Connect this pin to ground for CardBus operation; connect to VDD for PCI operation. Not Usable. No external connections to this pin are allowed. Cable Not Active. CNA output is provided for use in legacy power management systems. CNA is asserted high when none of the PHY ports is receiving an incoming bias voltage. This circuit remains active during the powerdown mode. The CNA pin is TTL-compatible. This pin can source and sink up to a 6 mA load. NAND Tree Test Output. When the chip is placed into the NAND tree test mode, the pin is the output of the NAND tree logic. This pin is not used during normal operation. Test. Used by Agere for device manufacturing testing. Tie to VSS for normal operation. ROM Clock. ROM Address/Data. Test. Used by Agere for device manufacturing testing. Tie to VSS for normal operation. Digital Power. Digital Ground. CLKRUNN (Active-Low). Optional signal for PCI mobile computing environment. If not used, CLKRUNN pin needs to be pulled down to VSS for correct operation. PCI Interrupt (Active-Low). PCI Reset (Active-Low). PCI Grant Signal (Active-Low). PCI Request Signal (Active-Low). PCI Power Management Event (Active-Low)/CardBus Status Changed (Active-High). When the CARDBUSN signal is high (i.e., when the FW323 FW323 is communicating directly with the PCI bus and not the CardBus), a PCI power management event will be indicated if this signal is low. When the CARDBUSN signal is low (indicating the FW323 FW323 is in CardBus mode), this pin signals that the CardBus status has changed when it is active-high. (See PC Card Standard, v. 8.0, Volume 2, Section 5.2.11 for more information regarding CSTSCHG.) Digital Power. PCI Clock Input. 33 MHz. Digital Ground. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. Digital Power. * Active-low signals within this document are indicated by an N following the symbol names. 16 Agere Systems Inc. Data Sheet April 2005 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Pin Information (continued) Table 1. Pin Descriptions (continued) Pin Symbol* Type 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 VSS PCI_AD[27] PCI_AD[26] PCI_AD[25] PCI_AD[24] VSS PCI_CBEN[3] PCI_IDSEL PCI_AD[23] PCI_AD[22] VDD VSS PCI_AD[21] PCI_AD[20] PCI_AD[19] PCI_AD[18] VDD VSS PCI_AD[17] PCI_AD[16] PCI_CBEN[2] PCI_FRAMEN VDD VSS PCI_IRDYN PCI_TRDYN PCI_DEVSELN PCI_STOPN VDD VSS PCI_PERRN PCI_SERRN PCI_PAR PCI_CBEN[1] VSS PCI_AD[15] PCI_AD[14] PCI_AD[13] PCI_AD[12] VSS PCI_AD[11] PCI_AD[10] PCI_AD[9] - I/O I/O I/O I/O - I/O I I/O I/O - - I/O I/O I/O I/O - - I/O I/O I/O I/O - - I/O I/O I/O I/O - - I/O I/O I/O I/O - I/O I/O I/O I/O - I/O I/O I/O Description Digital Ground. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. Digital Ground. PCI Command/Byte Enable (Active-Low). PCI ID Select. PCI Address/Data Bit. PCI Address/Data Bit. Digital Power. Digital Ground. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. Digital Power. Digital Ground. PCI Address/Data Bit. PCI Address/Data Bit. PCI Command/Byte Enable Signal (Active-Low). PCI Frame Signal (Active-Low). Digital Power. Digital Ground. PCI Initiator Ready Signal (Active-Low). PCI Target Ready Signal (Active-Low). PCI Device Select Signal (Active-Low). PCI Stop Signal (Active-Low). Digital Power. Digital Ground. PCI Parity Error Signal (Active-Low). PCI System Error Signal (Active-Low). PCI Parity Signal. PCI Command/Byte Enable Signal (Active-Low). Digital Ground. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. Digital Ground. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. * Active-low signals within this document are indicated by an N following the symbol names. Agere Systems Inc. 17 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Data Sheet April 2005 Pin Information (continued) Table 1. Pin Descriptions (continued) Pin Symbol* Type Description 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 PCI_AD[8] VSS VDD PCI_CBEN[0] PCI_AD[7] PCI_AD[6] PCI_AD[5] VSS PCI_AD[4] PCI_AD[3] PCI_AD[2] VSS VDD PCI_AD[1] PCI_AD[0] PCI_VIOS I/O - - I/O I/O I/O I/O - I/O I/O I/O - - I/O I/O - 86 CONTENDER I 87 88 89 PC2 PC1 PC0 I 90 LKON O 91 LPS O 92 MPCIACTN O 93 VDD - PCI Address/Data Bit. Digital Ground. Digital Power. PCI Command/Byte Enable Signal (Active-Low). PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. Digital Ground. PCI Address/Data Bit. PCI Address/Data Bit. PCI Address/Data Bit. Digital Ground. Digital Power. PCI Address/Data Bit. PCI Address/Data Bit. PCI Signaling Indicator. For PCI applications that use a universal expansion board (see PCI Local Bus Specification, Rev. 2.2, Section 4.1.1), connect this pin to the VI/O pin. For Cardbus applications, connect this pin to 3.3 V. For other cases, connect this pin to 3.3 V for PCI buses using 3.3 V signaling or to 5 V for PCI buses using 5 V signaling. Contender. On hardware reset (RESETN), this input sets the default value of the CONTENDER bit indicated during SelfID. This bit can be tied to VDD (high), so it will be considered for bus manager or to ground (low) to not be considered for bus manager. Power-Class Indicators. On hardware reset (RESETN), these inputs set the default value of the power class indicated during SelfID. These bits can be tied to VDD (high) or to ground (low) as required for particular power consumption and source characteristics. In SelfID packet (see Section 4.3.4.1 of the 1394a-2000 Specification), PC0, the most significant bit of this 3-bit field, corresponds to bit 21, PC1 corresponds to bit 22, and PC2 corresponds to bit 23. As an example, for a Power_Class value of 001, PC0 = 0, PC1 = 0, and PC2 = 1. Link On. Signal from the internal PHY core to the internal link core. This signal is provided as an output for use in legacy power management systems. Link Power Status. Signal from the internal link core to the internal PHY core. LPS is provided as an output for use in legacy power management systems. Mini PCI Function Active. An active-low output used only in Mini PCI applications. A low indicates that the FW323 FW323 requires full system performance. If MPCIACTN is low, the FW323 FW323 requires that the system not be in a low-power state. Digital Power. * Active-low signals within this document are indicated by an N following the symbol names. 18 Agere Systems Inc. Data Sheet April 2005 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Pin Information (continued) Table 1. Pin Descriptions (continued) Pin Symbol* Type Description 94 CPS I 95 VSSA - 96 VDDA - 97 TPB2­ Analog I/O 98 TPB2+ 99 TPA2­ 100 TPA2+ 101 TPBIAS2 Analog I/O 102 VSSA - 103 VSSA - 104 VDDA - 105 TPB1­ Analog I/O 106 TPB1+ Cable Power Status. CPS is normally connected to the cable power through a 400 k resistor. This circuit drives an internal comparator that detects the presence of cable power. This information is maintained in one internal register and is available to the LLC by way of a register read (see IEEE 1394a-2000, Standard for a High Performance Serial Bus, Sections 4.2.2.7 and 5B.1). Note: This pin can be left unconnected for applications that do not use 1394 bus power (VP). When this pin is grounded, the PWR_FAIL bit in PHY register 01012 will set. Analog Circuit Ground. All VSSA signals should be tied together to a low-impedance ground plane. Analog Circuit Power. VDDA supplies power to the analog portion of the device. Port 2, Port Cable Pair B. TPB2± is the port B connection to the twisted-pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. When the FW323 FW323's 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. Internal connect-detect circuitry will keep the port in a disconnected state. Port 2, Port Cable Pair A. TPA2± is the port A connection to the twisted-pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. When the FW323 FW323's 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. Internal connect-detect circuitry will keep the port in a disconnected state. Port 2, Twisted-Pair Bias. TPBIAS2 provides the 1.86 V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. When the FW323 FW323's 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. Internal connect-detect circuitry will keep the port in a disconnected state. Analog Circuit Ground. All VSSA signals should be tied together to a low-impedance ground plane. Analog Circuit Ground. All VSSA signals should be tied together to a low-impedance ground plane. Analog Circuit Power. VDDA supplies power to the analog portion of the device. Port 1, Port Cable Pair B. TPB1± is the port B connection to the twisted-pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. When the FW323 FW323's 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. Internal connect-detect circuitry will keep the port in a disconnected state. Analog I/O * Active-low signals within this document are indicated by an N following the symbol names. Agere Systems Inc. 19 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Data Sheet April 2005 Pin Information (continued) Table 1. Pin Descriptions (continued) Pin Symbol* Type Description 107 TPA1­ Analog I/O 108 TPA1+ 109 TPBIAS1 Analog I/O 110 TPB0­ Analog I/O 111 TPB0+ 112 TPA0­ 113 TPA0+ 114 TPBIAS0 Analog I/O 115 VSSA - 116 VDDA - 117 R0 I 118 R1 119 PLLVDD - 120 PLLVSS - Port 1, Port Cable Pair A. TPA1± is the port A connection to the twisted-pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. When the FW323 FW323's 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. Internal connect-detect circuitry will keep the port in a disconnected state. Port 1, Twisted-Pair Bias. TPBIAS1 provides the 1.86 V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. When the FW323 FW323's 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. Internal connect-detect circuitry will keep the port in a disconnected state. Port 0, Port Cable Pair B. TPB0± is the port B connection to the twisted-pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. When the FW323 FW323's 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. Internal connect-detect circuitry will keep the port in a disconnected state. Port 0, Port Cable Pair A. TPA0± is the port A connection to the twisted-pair cable. Board traces from each pair of positive and negative differential signal pins should be kept matched and as short as possible to the external load resistors and to the cable connector. When the FW323 FW323's 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. Internal connect-detect circuitry will keep the port in a disconnected state. Port 0, Twisted-Pair Bias. TPBIAS0 provides the 1.86 V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers and for sending a valid cable connection signal to the remote nodes. When the FW323 FW323's 1394 port pins are not wired to a connector, the unused port pins may be left unconnected. Internal connect-detect circuitry will keep the port in a disconnected state. Analog Circuit Ground. All VSSA signals should be tied together to a low-impedance ground plane. Analog Circuit Power. VDDA supplies power to the analog portion of the device. Current Setting Resistor. An internal reference voltage is applied to a resistor connected between R0 and R1 to set the operating current and the cable driver output current. A low temperature-coefficient resistor (TCR) with a value of 2.49 k ± 1% should be used to meet the IEEE 1394-1995 standard requirements for output voltage limits. Power for PLL Circuit. PLLVDD supplies power to the PLL circuitry portion of the device. Ground for PLL Circuit. PLLVSS is tied to a low-impedance ground plane. Analog I/O * Active-low signals within this document are indicated by an N following the symbol names. 20 Agere Systems Inc. Data Sheet April 2005 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Pin Information (continued) Table 1. Pin Descriptions (continued) Pin Symbol* Type Description 121 XI Analog I/O 122 XO 123 RESETN I 124 PTEST I 125 SM I 126 SE I 127 128 NU VAUX_PRESENT - I Crystal Oscillator. XI and XO connect to a 24.576 MHz parallel resonant fundamental mode crystal. Although when a 24.576 MHz clock source is used, it can be connected to XI with XO left unconnected. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used. It is necessary to add an external series resistor to the XO pin. The value of the resistor is nominally 400 . For more details, refer to the Crystal Selection Considerations section in this data sheet. Note that it is very important to place the crystal as close as possible to the XO and XI pins, i.e., within 0.5 in./1.27 cm. For more important details regarding the crystal, refer to the FW323/FW322 FW323/FW322 Hardware Implementation Design Guideline Application Note. Reset (Active-Low). When RESETN is asserted low (active), a 1394 bus reset condition is set on the active cable port and the FW323 FW323 is reset to the reset start state. To guarantee that the PHY will reset, this pin must be held low for at least 2 ms. An internal pull-up resistor, connected to VDD, is provided, so only an external delay capacitor (0.1 µF) and resistor (510 k), in parallel, are required to connect this pin to ground. This circuitry will ensure that the capacitor will be discharged when PHY power is removed. The input is a standard logic buffer and can also be driven by an open-drain logic output buffer. Do not leave this pin unconnected. This pin is also used with the EEPROM interface. It is the powerup reset pin. This pin is asserted low (active) to indicate a powerup reset. Refer to the FW322 FW322 06/FW323 06/FW323 06 EEPROM Interface and Start-up Behavior Application Note sections titled Initiation of EEPROM Load and Initial Powerup. Test. Used by Agere for device manufacturing testing. Tie to VSS for normal operation. Test Mode Control. SM is used during Agere's manufacturing test and should be tied to VSS for normal operation. Test Mode Control. SE is used during Agere's manufacturing test and should be tied to VSS for normal operation. Not Usable. No external connections to this pin are allowed. 3.3 Vaux Present. An active-high input indicating whether the FW323 FW323 is powered via an auxiliary power supply (e.g., PCI 3.3 Vaux). An internal pull-down resistor connected to VSS is provided, so an external pull-up is only required when the device is being powered by an auxiliary power supply. Note that VAUX_PRESENT is not an actual power supply pin to the device. Rather, this pin is an indicator of whether the FW323 FW323 is powered via an auxiliary power supply (VAUX_PRESENT = 1) or the regular PCI power supply (VAUX_PRESENT = 0). This input is used by the FW323 FW323 to properly support the D3cold power management functionality. * Active-low signals within this document are indicated by an N following the symbol names. Note: For those applications when one or more FW323 FW323 ports are not wired to a connector, those unused ports may be left unconnected without normal termination. When a port does not have a cable connected, internal connect-detect circuitry will keep the port in a disconnected state. Agere Systems Inc. 21 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Data Sheet April 2005 Internal Registers This section provides a summary of the internal registers within the FW323 FW323, including both PCI Configuration registers and OHCI registers. Register default values, registers, bits that have not been implemented in the FW323 FW323, and other information specific to the FW323 FW323 will be noted. Please refer to the PCI Local Bus Specification v.2.2, PCI Bus Power Management Interface Specification, v.1.1, 1394 OHCI specification v.1.1, and the IEEE standard 1394a-2000 Specification for further details concerning these registers. Table 2 describes the field access tags that are designated in the Type column of the register tables in this document. Table 2. Bit-Field Access Tag Description Access Tag Name R W S C U Read Write Set Clear Update Description Field may be read by software. Field may be written by software to any value. Field may be set by a write of 1. Writes of 0 have no effect. Field may be cleared by a write of 1. Writes of 0 have no effect. Field may be autonomously updated by the FW323 FW323. PCI Configuration Registers Table 3a and Table 3b illustrates the PCI configuration header that includes both the predefined portion of the configuration space and the user-definable registers. Note that there are two mutually exclusive versions of this header: one for PCI applications (CardBusN = 1) and one for CardBusN applications (CardBusN = 0). Table 3a. PCI Configuration Register Map, CardBusN = 1 Register Name [default] Offset Device ID [5811h] Vendor ID [11C1h] 00h Status [02901h] Command [0000h] 04h Revision ID [6xh]* Class Code [0C0010h] BIST [00h] Header Type [00h] Latency Timer [00h] 08h Cache Line Size [00h] 0Ch OHCI Base Address Register [0000 0000h] 10h Reserved 14h Reserved 18h Reserved 1Ch Reserved 20h Reserved 24h CardBus CIS Pointer [0000 0000h] 28h Subsystem ID [0000h] Subsystem Vendor ID [0000h] Reserved Reserved 30h PCI Power Management Capabilities Pointer [44h] Reserved Latency Maximum [18h] Grant Minimum [0Ch] Interrupt Pin [01h] 2Ch 34h 38h Interrupt Line [00h] 3Ch * x is a minor revision number of the FW323 FW323 06 and may be any value from 0 hex to F hex. Values for this register can be loaded from a serial EEPROM during the powerup sequence. 22 Agere Systems Inc. Data Sheet April 2005 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Table 3a. PCI Configuration Register Map, CardBusN = 1 (continued) Register Name [default] Offset Register [0000 PCI OHCI Control Power Management Capabilities , [FFC2h] Pm Data [00h] Pmcsr_bse [00h] 0000h] Next Item Pointer Capability ID [01h] [00h] Power Management CSR [0000h] Reserved 40h 44h 48h 4C-FCh Values for this register can be loaded from a serial EEPROM during the powerup sequence. Value for this register is affected by the state of the VAUX_PRESENT input pin. Table 3b. PCI Configuration Register Map, CardBusN = 0 Register Name [default] Offset Device ID [5811h] Vendor ID [11C1h] 00h Status [02901h] Command [0000h] 04h Revision ID [6xh] * Class Code [0C0010h] BIST [00h] Header Type [00h] Latency Timer [00h] 08h Cache Line Size [00h] 0Ch OHCI Base Address Register [0000 0000h] 10h CardBus Base Address Register [0000 0000h] 14h Reserved 18h Reserved 1Ch Reserved 20h Reserved 24h CardBus CIS Pointer [0000 0080h] 28h Subsystem ID [0000h] Subsystem Vendor ID [0000h] Reserved Reserved 30h PCI Power Management Capabilities Pointer [44h] Reserved Latency 2Ch Grant 34h 38h Minimum Interrupt Pin [01h] Interrupt Line [00h] [0Ch] PCI OHCI Control Register [0000 0000h] Power Management Capabilities , [FFC2h] Next Item Pointer Capability ID [01h] [00h] Pm Data [00h] Pmcsr_bse [00h] Power Management CSR [0000h] 3Ch Reserved CIS 4C-7Ch 80-FCh Maximum [18h] 40h 44h 48h * x is a minor revision number of the FW323 FW323 06 and may be any value from 0 hex to F hex. Values for this register can be loaded from a serial EEPROM during the powerup sequence. Value for this register is affected by the state of the VAUX_PRESENT input pin. Agere Systems Inc. 23 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Data Sheet April 2005 Internal Registers (continued) Vendor ID Register The Vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the device. The vendor ID assigned to Agere is 11C1h. Offset: Default: Type: Reference: 00h 11C1h Read only PCI Local Bus Specification, Rev. 2.2, Section 6.2.1 Device ID Register The Device ID register contains a value assigned to the FW323 FW323 by Agere. The device identification for the FW323 FW323 is 5811h. Offset: Default: Type: Reference: 24 02h 5811h Read only PCI Local Bus Specification, Rev. 2.2, Section 6.2.1 Agere Systems Inc. Data Sheet April 2005 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) PCI Command Register The Command register provides control over the FW323 FW323 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as in the following bit descriptions. Offset: Default: Type: Reference: 04h 0000h Read/write PCI Local Bus Specification, Rev. 2.2, Section 6.2.2 and 1394 Open Host Controller Interface Specification, Rev. 1.1, Section A.3.1 Table 4. PCI Command Register Description Bit Field Name Type Description 15:10 9 Reserved FBB_ENB R R 8 SERR_ENB RW 7 STEP_ENB R 6 PERR_ENB RW 5 VGA_ENB R 4 MWI_ENB RW 3 SPECIAL R 2 MASTER_ENB RW 1 MEMORY_ENB RW 0 IO_ENB R Reserved. Bits 15:10 return 0s when read. Fast Back-to-Back Enable. The FW323 FW323 does not generate fast backto-back transactions; thus, this bit returns 0 when read. SERR Enable. When this bit is set, the FW323 FW323 SERR driver is enabled. PCI_SERRN can be asserted after detecting an address parity error on the PCI bus. Address/Data Stepping Control. The FW323 FW323 does not support address/data stepping; thus, this bit is hardwired to 0. Parity Error Enable. When this bit is set, the FW323 FW323 is enabled to drive PERR response to parity errors through the PCI_PERRN signal. VGA Palette Snoop Enable. The FW323 FW323 does not feature VGA palette snooping. This bit returns 0 when read. Memory Write and Invalidate Enable. When this bit is set, the FW323 FW323 is enabled to generate MWI PCI bus commands. If this bit is reset, then the FW323 FW323 generates memory write commands instead. Special Cycle Enable. The FW323 FW323 function does not respond to special cycle transactions. This bit returns 0 when read. Bus Master Enable. When this bit is set, the FW323 FW323 is enabled to initiate cycles on the PCI bus. Memory Response Enable. Setting this bit enables the FW323 FW323 to respond to memory cycles on the PCI bus. This bit must be set to access OHCI registers. I/O Space Enable. The FW323 FW323 does not implement any I/O mapped functionality; thus, this bit returns 0 when read. Agere Systems Inc. 25 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Data Sheet April 2005 Internal Registers (continued) PCI Status Register The Status register provides status information for PCI bus related events. All bit functions adhere to the definitions in the PCI Local Bus Specification, v.2.2, Table 6.2. Offset: Default: Type: Reference: 06h 0290h Read/write PCI Local Bus Specification, Rev. 2.2, Section 6.2.3 and 1394 Open Host Controller Interface Specification, Rev. 1.1, Section A.3.2 Table 5. PCI Status Register Bit Field Name Type 15 PAR_ERR RCU 14 SYS_ERR RCU 13 MABORT RCU 12 TABORT_REC RCU 11 TABORT_SIG RCU 10:9 PCI_SPEED R 8 DATAPAR RCU 7 FBB_CAP R 6 5 Reserved 66MHZ 66MHZ R R 4 CAPLIST R 3:0 Reserved R 26 Description Detected Parity Error. This bit must be set by the device whenever it detects a parity error, even if parity error handling is disabled. Signaled System Error. This bit must be set whenever the device asserts SERR#. Received Master Abort. This bit must be set by a master device whenever its transaction (except for special cycle) is terminated with master-abort. Received Target Abort. This bit must be set by a master device whenever its transaction is terminated with target-abort. Signaled Target Abort. This bit must be set by a target device whenever it terminates a transaction with target-abort. DEVSEL Timing. Bits 9 and 10 encode the timing of DELSEL# (see Section 3.6.1 of the PCI Specification). These bits must indicate the slowest time that a device asserts DEVSEL# for any bus command except configuration read and configuration write. The default timing is 01 (medium). Master Data Parity Error. See Table 6-2 of the PCI Specification for more information. Fast Back-to-Back Capable. Indicates whether or not the target is capable of accepting fast back-to-back transactions when the transactions are not to the same agent. The FW323 FW323 does not support back-to-back transactions. Reserved. 66 MHz Capable. Indicates whether or not this device is capable of running at 66 MHz as defined in Chapter 7 of the PCI Specification. The FW323 FW323 reports a value of zero in this field indicating that 66 MHz functionality is not supported. Capabilities List. Indicates whether or not this device implements the pointer for a New Capabilities linked list at offset 34h. A value of zero indicates that no New Capabilities linked list is available. A value of one indicates that the value read at offset 34h is a point in Configuration Space to a linked list of new capabilities. (See Section 6.7 of the PCI Specification for more details.) Reserved. Agere Systems Inc. Data Sheet April 2005 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) Class Code and Revision ID Registers The Class Code register and Revision ID register categorize the FW323 FW323 as a serial bus controller (0Ch), controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the chip revision is indicated in the lower byte. Offset: Default: Type: Reference: 08h 0C00 106xh* Read only PCI Local Bus Specification, Rev. 2.2, Section 6.2.1 and 1394 Open Host Controller Interface Specification, Rev. 1.1, Section A.3.3 and A.3.4. Table 6. Class Code and Revision ID Register Description Bit Field Name Type Description 31:24 BASECLASS R 23:16 SUBCLASS R 15:8 PGMIF R 7:0 CHIPREV R Base Class. This field returns 0Ch when read, which classifies the function as a serial bus controller. Subclass. This field returns 00h when read, which specifically classifies the function as an IEEE 1394 serial bus controller. Programming Interface. This field returns 10h when read, indicating that the programming model is compliant with the 1394 Open Host Controller Interface Specification. Silicon Revision. This field returns 6xh* when read, indicating the silicon revision of the FW323 FW323. * x is a minor revision number of the FW323 FW323 06 and may be any value from 0 hex to F hex. Agere Systems Inc. 27 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Data Sheet April 2005 Internal Registers (continued) Latency Timer and Cache Line Size Register The Latency Timer and Class Cache Line Size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the FW323 FW323. If a serial EEPROM is detected, then the contents of this register are loaded from the serial EEPROM interface after a PCI reset. If no serial EEPROM is detected, then this register returns a default value of 0000h. Offset: Default: Type: Reference: 0Ch 0000h Read/write PCI Local Bus Specification, Rev. 2.2, Section 6.2.4 Table 7. Latency Timer and Class Cache Line Size Register Description Bit Field Name Type Description 15:8 LATENCY_TIMER RW 7:0 CACHELINE_SZ RW PCI Latency Timer. The value in this register specifies the latency timer, in units of PCI clock cycles, for the FW323 FW323. When the FW323 FW323 is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the FW323 FW323 transaction has terminated, then the FW323 FW323 terminates the transaction when its PCI_GNTN is deasserted. Cache Line Size. This value is used by the FW323 FW323 during memory write and invalidate, memory read line, and memory read multiple transactions. Header Type and BIST Register The Header Type and BIST register indicates the FW323 FW323 PCI header type. Offset: Default: Type: Reference: 0Eh 0000h Read only PCI Local Bus Specification, Rev. 2.2, Sections 6.2.1 and 6.2.4 Table 8. Header Type and BIST Register Description Bit Type Description 15:8 BIST R 7:0 28 Field Name HEADER_TYPE R Built-In Self-Test. The FW323 FW323 does not include a built-in self-test; thus, this field returns 00h when read. PCI Header Type. The FW323 FW323 includes the standard PCI header, and this is communicated by returning 00h when this field is read. Agere Systems Inc. Data Sheet April 2005 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) OHCI Base Address Register The OHCI Base Address register is programmed with a base address referencing the memory-mapped OHCI control. When BIOS writes all 1s to this register, the value read back is FFFF F000h, indicating that 4 Kbytes of memory address space are required for the OHCI registers. Offset: Default: Type: Reference: 10h 0000 0000h Read/write PCI Local Bus Specification, Rev. 2.2, Sections 6.2.5 and 1394 Open Host Controller Interface Specification, Rev. 1.1, Section A.3.5 Table 9. OHCI Base Address Register Description Bit Field Name Type Description 31:12 OHCIREG_PTR RW 11:4 OHCI_SZ R 3 OHCI_PF R 2:1 OHCI_MEMTYPE R 0 OHCI_MEM R OHCI Register Pointer. Specifies the upper 20 bits of the 32-bit OHCI base address. OHCI Register Size. This field returns 0s when read, indicating that the OHCI registers require a 4 Kbyte region of memory. OHCI Register Prefetch. This bit returns 0 when read, indicating that the OHCI registers are not prefetchable. OHCI Memory Type. This field returns 0s when read, indicating that the OHCI Base Address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. OHCI Memory Indicator. This bit returns 0 when read, indicating that the OHCI registers are mapped into system memory space. Agere Systems Inc. 29 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Data Sheet April 2005 Internal Registers (continued) CardBus Base Address Register The CardBus Base Address register is programmed with a base address referencing the memory-mapped Function Event registers. When BIOS writes all 1s to this register, the value read back is FFFF FF00h, indicating that 256 bytes of memory address space are required for the CardBus Function Event registers. Offset: Default: Type: Reference: 14h 0000 0000h Read/write PC Card Standard Rev 8, volume 2, Section 5.4.2.1.7 Table 10. CardBus Base Address Register Description Bit Field Name Type Description 31:8 CBREG_PTR RW 7:4 CB_SZ R 3 CB_PF R 2:1 CB_MEMTYPE R 0 CB_MEM R CardBus Register Pointer. Specifies the upper 24 bits of the 32-bit CardBus base address. CardBus Register Size. This field returns 0s when read, indicating that the CardBus registers require a 256 byte region of memory. CardBus Register Prefetch. This bit returns 0 when read, indicating that the CardBus Function Event registers do not have support for prefetchable memory. CardBus Memory Type. This field returns 0s when read, indicating that the CardBus Base Address register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space. CardBus Memory Indicator. This bit returns 0 when read, indicating that the CardBus registers are mapped into system memory space. CIS Pointer The CIS Pointer indicates the starting point of the card information structure (CIS). The CIS may begin in any one of the following spaces: Configuration space: must begin in device-dependent space at or after location 40h. Memory space: may be in any of the memory spaces. Expansion ROM space: may be in any of the images. The FW323 FW323 will only support the first, configuration space starting at location 80h. Offset: Default (CardBusN = 1): Default (CardBusN = 0): Type: Reference: 30 28h 0000 0000h 0000 0080h Read only PCI Card Standard, Rev. 8, volume 2, Section 5.4.2.1.8 Agere Systems Inc. Data Sheet April 2005 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) PCI Subsystem Identification Register The PCI Subsystem Identification register is used to uniquely identify the card or system in which the FW323 FW323 resides. If a serial EEPROM is present, these values are loaded from the EEPROM during the powerup sequence. Subsystem vendor IDs can be obtained from the PCI SIG. Values for the subsystem ID are vendor specific. By default, the PCI Subsystem ID and PCI Subsystem Vendor ID registers are read only. However, if a serial EEPROM is not interfaced to the FW323 FW323 06, bit 0 (SubSystemWriteEn) of the PCI Config register, offset 4Ch can be set to enable writes to the PCI Subsystem ID and PCI Subsystem Vendor ID so that these registers can be customized to the correct ID values. After the IDs have been written, the SubSystemWriteEn bit should be reset to protect the data from being overwritten. Offset: Default: Type: Reference: 2Ch 0000 0000h Read/write PCI Local Bus Specification, Rev. 2.2, Section 6.2.4 Table 11. PCI Subsystem Identification Register Description Bit Field Name Type Description 31:16 15:0 SSID SSVID RU RU Subsystem ID. This field indicates the subsystem ID. Subsystem Vendor ID. This field indicates the subsystem vendor ID. PCI Power Management Capabilities Pointer Register The PCI Power Management Capabilities Pointer register provides a pointer into the PCI configuration header where the PCI Power Management register block resides. The FW323 FW323 configuration words at offsets 44h and 48h provide the Power Management registers. This register is read only and returns 44h when read. Offset: Default: Type: Reference: 34h 44h Read only PCI Local Bus Specification, Rev. 2.2, Section 6.2.4 and 6.7 and 1394 Open Host Controller Interface Specification, Rev. 1.1, Section A.3.6. Agere Systems Inc. 31 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Data Sheet April 2005 Internal Registers (continued) Interrupt Line and Pin Register The Interrupt Line and Pin register is used to communicate interrupt line routing information. Offset: Default: Type: Reference: 3Ch 0100h Read only PCI Local Bus Specification, Rev. 2.2, Section 6.2.4 and 6.7 Table 12. Interrupt Line and Pin Register Description Bit Field Name Type Description 15:8 INTR_PIN R 7:0 INTR_LINE RW Interrupt Pin Register. This register returns 01h when read, indicating that the FW323 FW323 PCI function signals interrupts on the INTA pin. Interrupt Line Register. This register is programmed by the system and indicates to software to which interrupt line the FW323 FW323 INTA is connected. MIN_GNT and MAX_LAT Register The MIN_GNT and MAX_LAT register is used to communicate to the system the desired setting of the Latency Timer register. If a serial EEPROM is detected, then the contents of this register are loaded from the serial EEPROM interface after a PCI reset. If no serial EEPROM is detected, then this register returns a default value that corresponds to the MIN_GNT = 0Ch, MAX_LAT = 18h. Offset: Default: Type: Reference: 3Eh 180Ch Read only PCI Local Bus Specification, Rev. 2.2, Section 6.2.4 Table 13. MIN_GNT and MAX_LAT Register Description Bit Type Description 15:8 MAX_LAT RU 7:0 32 Field Name MIN_GNT RU Maximum Latency. The contents of this register may be used by host BIOS to assign an arbitration priority level to the FW323 FW323. The default for this register (18h) indicates that the FW323 FW323 may need to access the PCI bus as often as every 0.25 µs; thus, an extremely high-priority level is requested. The contents of this field may also be loaded from the serial ROM. Minimum Grant. The contents of this register may be used by host BIOS to assign a Latency Timer register value to the FW323 FW323. The default (0Ch) for this register indicates that the FW323 FW323 may need to sustain burst transfers for nearly 64 µs; thus, requesting a large value be programmed in the FW323 FW323 Latency Timer register. The contents of this field may also be loaded from the serial ROM. Agere Systems Inc. Data Sheet April 2005 FW323 FW323 06 1394A PCI PHY/Link Open Host Controller Interface Internal Registers (continued) PCI OHCI Control Register The PCI OHCI Control register is defined in Section A.3.7 o