FT245BM FT8U245AM DS245B FT232BM 93C46 93C56 93C66 CRC16 93LC46B LQFP-32 - Datasheet Archive

 

The FT245BM is the 2nd generation of FTDI's popular USB FIFO i.c. This device not only adds extra functionality to it's FT8U245AM

 

FT245BM FT245BM USB FIFO ( USB - Parallel ) I.C. The FT245BM FT245BM is the 2nd generation of FTDI's popular USB FIFO i.c. This device not only adds extra functionality to it's FT8U245AM FT8U245AM predecessor and reduces external component count, but also maintains a high degree of pin compatibility with the original, making it easy to upgrade or cost reduce existing designs as well as increasing the potential for using the device in new application areas. 1.0 Features HARDWARE FEATURES · 4.35V to 5.25V single supply operation Single Chip USB ó Parallel FIFO bi-directional · UHCI / OHCI / EHCI host controller compatible Data Transfer · USB 1.1 and USB 2.0 compatible · Transfer Data rate to 1M Byte / Sec - D2XX Drivers · USB VID, PID , Serial Number and Product · Transfer Data rate to 300 Kilobyte / Sec - VCP · Description strings in external EEPROM Drivers · EEPROM programmable on-board via USB Simple to interface to MCU/ PLD / FPGA logic with · Compact 32LD LQFP package a 4 wire handshake interface VIRTUAL COM PORT ( VCP ) DRIVERS for Entire USB protocol handled on-chip . no USB- - Windows 98 and Windows 98 SE specific firmware programming required - Windows 2000 / ME / XP FTDI's royalty-free VCP and D2XX drivers - Windows CE * eliminate the requirement for USB driver - MAC OS-8 and OS-9 development in most cases. - MAC OS-X 384 Byte FIFO Tx buffer / 128 Byte FIFO Rx Buffer - Linux 2.40 and greater for high data throughput. D2XX ( USB Direct Drivers + DLL S/W Interface ) New Send Immediate support via SI Pin for - Windows 98 and Windows 98 SE optimised data throughput. - Windows 2000 / ME / XP Support for USB Suspend / Resume through APPLICATION AREAS PWREN# and WAKEUP pins. - Easy MCU / PLD / FPGA interface to USB Support for high power USB Bus powered devices - Upgrading Legacy Peripheral Designs to USB through PWREN# pin - USB Instrumentation · Adjustable RX buffer timeout - USB Industrial Control · In-built support for event characters - USB Audio and Low Bandwidth Video data transfer · Integrated level converter on FIFO and control - PDA ó USB data transfer signals for interfacing to 5V and 3.3V logic - USB MP3 Player Interface · Integrated 3.3V regulator for USB IO - USB FLASH Card Reader / Writers · Integrated Power-On-Reset circuit - Set Top Box ( S.T.B. ) PC - USB interface · Integrated 6MHz ­ 48Mhz clock multiplier PLL - USB Digital Camera Interface · USB Bulk or Isochronous data transfer modes - USB Hardware Modems · New Bit-Bang Mode allows the data bus to be used - USB Wireless Modems as an 8 bit general purpose IO Port without the - need for MCU or other support logic. [ * = In planning or under development ] · · · · · · · DS245B DS245B Version 1.1 © Future Technology Devices Intl. Ltd. 2003 Page 1 of 22 FT245BM FT245BM USB FIFO ( USB - Parallel ) I.C. 1.1 General Description The FT245BM FT245BM provides an easy cost-effective method of transferring data to / from a peripheral and a host P.C. at up to 8 Million bits ( 1 Megabyte ) per second. Its simple, FIFO-like design makes it easy to interface to any microcontroller or microprocessor via IO ports. To send data from the peripheral to the host computer, simply write the byte-wide data into the module when TXE# is low. If the (384-byte) transmit buffer fills up or is busy storing the previously written byte, the device keeps TXE# high in order to stop further data from being written until some of the FIFO data has been transferred over USB to the host. TXE# goes high after every byte written. When the host sends data to the peripheral over USB, the device will take RXF# low to let the peripheral know that at least one byte of data is available. The peripheral can read a data byte every time RXF# goes low. RXF# goes high after every byte read. By using FTDI's virtual COM port drivers, the peripheral looks like a standard COM port to the application software. Commands to set the baud rate are ignored - the device always transfers data at its fastest rate regardless of the application's baud-rate setting. Alternatively, FTDI's D2XX drivers allow application software to access the device "directly" through a published DLL based API. Details of the current VCP and D2XX driver can be found on FTDI's web site ( http://www.ftdichip.com ) 2.0 Enhancements This section summarises the enhancements of the 2nd generation device compared to it's FT8U245AM FT8U245AM predecessor. For further details, consult the device pin-out description and functional descriptions. · Integrated Power-On-Reset ( POR ) Circuit · Integrated Level Converter on FIFO interface The device now incorporates an internal POR and control signals function. The existing RESET# pin is maintained The previous devices would drive the FIFO and in order to allow external logic to reset the device control signals at 5V CMOS logic levels. The where required, however for many applications new device has a separate VCCIO pin allowing this pin can now be either left N/C or hard wired the device to directly interface to 3.3V and other to VCC. In addition, a new reset output pin logic families without the need for external level (RSTOUT#) is provided in order to allow the new converter i.c.'s POR circuit to provide a stable reset to external · Power Management control for USB Bus MCU and other devices. RSTOUT# was the TEST pin on the previous generation of devices. · Powered, high current devices A new PWREN# signal is provided which can be Integrated RCCLK Circuit used to directly drive a transistor or P-Channel In the previous devices, an external RC circuit MOSFET in applications where power switching was required to ensure that the oscillator and of external circuitry is required. A new EEPROM clock multiplier PLL frequency was stable prior based option makes the device pull gently down to enabling the clock internal to the device. This it's FIFO interface lines when the power is shut off circuit is now embedded on-chip ­ the pin assigned ( PWREN# is High ). In this mode, any residual to this function is now designated as the TEST pin voltage on external circuitry is bled to GND when and should be tied to GND for normal operation. power is removed thus ensuring that external DS245B DS245B Version 1.1 © Future Technology Devices Intl. Ltd. 2003 Page 2 of 22 FT245BM FT245BM USB FIFO ( USB - Parallel ) I.C. circuitry controlled by PWREN# resets reliably · Relaxed VCC Decoupling when power is restored. PWREN# can also be used by external circuitry to determine when USB of on-chip VCC decoupling. Though this does is in suspend mode ( PWREN# goes high ). not eliminate the need for external decoupling Send Immediate / WakeUp ( SI / WU ) signal capacitors, it significantly improves the ease of The new Send Immediate / WakeUp signal PCB design requirements to meet FCC, CE and combines two functions on a single pin. If USB is · The 2nd generation devices now incorporate a level other EMI related specifications. in suspend mode ( and remote wakeup is enabled · Bit Bang Mode in the EEPROM ), strobing this pin low will cause the device to request a resume from suspend FIFO interface mode and an 8-bit Parallel IO operation, if this pin is strobed low any data in the port. Data packets can be sent to the device and device RX buffer will be sent out over USB on the they will be sequentially sent to the interface at a next Bulk-IN request from the drivers regardless of rate controlled by an internal timer ( equivalent to the packet size. This can be used to optimise USB the prescaler of the FT232BM FT232BM device ). As well transfer speed for some applications. as allowing the device to be used stand-alone Lower Suspend Current as a general purpose IO controller for example Integration of RCCLK within the device and internal controlling lights, relays and switches, some other design improvements reduce the suspend current interesting possibilities exist. For instance, it may of the FT245BM FT245BM to under 100uA typical ( excluding be possible to connect the device to an SRAM the 1.5k pull-up on USB DP ) in USB suspend configurable FPGA as supplied by vendors such as mode. This allows greater margin for peripherals to Altera and Xilinx. The FPGA device would normally meet the USB Suspend current limit of 500uA. be un-configured ( i.e. have no defined function ) Support for USB Isochronous Transfers at power-up. Application software on the PC could Whilst USB Bulk transfer is usually the best use Bit Bang Mode to download configuration choice for data transfer, the scheduling time of the data to the FPGA which would define it's hardware data is not guaranteed. For applications where function, then after the FPGA device is configured scheduling latency takes priority over data integrity the FT245BM FT245BM can switch back into FIFO interface such as transferring audio and low bandwidth mode to allow the programmed FPGA device video data, the new device now offers an option of to communicate with the PC over USB. This USB Isochronous transfer via an option bit in the approach allows a customer to create a "generic" EEPROM. · the eight FIFO data lines can be switched between be used to wake up the Host PC. During normal · referred to as "Bit Bang" mode. In Bit Bang mode, ( WakeUp ) on the USB Bus. Normally, this can · The 2nd generation device has a new option USB peripheral who's hardware function can be Programmable FIFO TX Buffer Timeout defined under control of the application software. In the previous device, the TX buffer timeout The FPGA based hardware can be easily upgraded used to flush remaining data from the TX buffer or totally changed simply by changing the FPGA was fixed at 16ms timeout. This timeout is now configuration data file. Application notes, software programmable over USB in 1ms increments and development modules for this application area from 1ms to 255ms, thus allowing the device to will be available from FTDI and other 3rd party be better optimised for protocols requiring faster developers. response times from short data packets. DS245B DS245B Version 1.1 © Future Technology Devices Intl. Ltd. 2003 Page 3 of 22 FT245BM FT245BM USB FIFO ( USB - Parallel ) I.C. · Less External Support Components As well as eliminating the RCCLK RC network, and re-plugs the device into a different USB port. · EEREQ# / EEGNT# for most applications the need for an external reset These ( FT8U245AM FT8U245AM ) pins are not supported on circuit, we have also eliminated the requirement for the FT245BM FT245BM device. They have been replaced a 100k pull-up on EECS to select 6MHz operation. with the new SI / WU and PWREN# signals When the FT245BM FT245BM is being used without the respectively. configuration EEPROM, EECS, EESK and EEDATA can now be left n/c. For circuits requiring a long reset time ( where the device is reset externally using a reset generator i.c., or reset is controlled by the IO port of a MCU, FPGA or ASIC device ) an external transistor circuit is no longer required as the 1k5 pull-up resistor on USBDP can be wired to the RSTOUT# pin instead of to 3.3V. Note : RSTOUT# drives out at 3.3V level, not at 5V VCC level. This is the preferred configuration for new designs. · Extended EEPROM Support The previous generation of devices only supported EEPROM of type 93C46 93C46 ( 64 x 16 bit ). The new devices will also work with EEPROM type 93C56 93C56 ( 128 x 16 bit ) and 93C66 93C66 ( 256 x 16 bit ). The extra space is not used by the device, however it is available for use by other external MCU / logic whilst the FT245BM FT245BM is being held in reset. · USB 2.0 ( full speed option ) A new EEPROM based option allows the FT245BM FT245BM to return a USB 2.0 device descriptor as opposed to USB 1.1. Note : The device would be a USB 2.0 Full Speed device ( 12Mb/s ) as opposed to a USB 2.0 High Speed device ( 480Mb/s ). · Multiple Device Support without EEPROM When no EEPROM ( or a blank or invalid EEPROM ) is attached to the device, the FT245BM FT245BM no longer gives a serial number as part of it's USB descriptor. This allows multiple devices to be simultaneously connected to the same PC. However, we still highly recommend that EEPROM is used, as without serial numbers a device can only be identified by which hub port in the USB tree it is connected to which can change if the end user DS245B DS245B Version 1.1 © Future Technology Devices Intl. Ltd. 2003 Page 4 of 22 FT245BM FT245BM USB FIFO ( USB - Parallel ) I.C. 3.0 Block Diagram ( simplified ) VCC 3V3OUT Send Immediate / WakeUP PWREN# 3.3 Volt LDO Regulator USBDP USBDM USB Transceiver FIFO Receive Buffer 128 Bytes Serial Interface Engine ( SIE ) FIFO Controller USB Protocol Engine D0 D1 D2 D3 D4 D5 D6 D7 RD# WR RXF# TXE# FIFO Transmit Buffer 384 Bytes USB DPLL XTOUT XTIN 6MHZ Oscillator x8 Clock Multiplier GND TEST 3.1 · · 3V3OUT 48MHz EEPROM Interface EECS EESK EEDATA 12MHz RESET GENERATOR RESET# RSTOUT# Functional Block Descriptions 3.3V LDO Regulator The 3.3V LDO Regulator generates the 3.3 volt reference voltage for driving the USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin. It also provides 3.3V power to the RSTOUT# pin. The main function of this block is to power the USB Transceiver and the Reset Generator Cells rather than to power external logic. However, external circuitry requiring 3.3V nominal at a current of not greater than 5mA could also draw it's power from the 3V3OUT pin if required. USB Transceiver The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface to the USB cable. The output drivers provide 3.3 volt level slew rate control signalling, whilst a differential receiver and two single ended receivers provide USB data in, SEO and USB Reset condition detection. DS245B DS245B Version 1.1 · · · · USB DPLL The USB DPLL cell locks on to the incoming NRZI USB data and provides separate recovered clock and data signals to the SIE block. 6MHz Oscillator The 6MHz Oscillator cell generates a 6MHz reference clock input to the x8 Clock multiplier from an external 6MHz crystal or ceramic resonator. x8 Clock Multiplier The x8 Clock Multiplier takes the 6MHz input from the Oscillator cell and generates a 12MHz reference clock for the SIE, USB Protocol Engine and FIFO controller blocks. It also generates a 48MHz reference clock for the USB DPLL. Serial Interface Engine ( SIE ) The Serial Interface Engine ( SIE ) block performs the Parallel to Serial and Serial to Parallel conversion of the USB data. In accordance to the USB 2.0 specification, it performs bit stuffing / un- © Future Technology Devices Intl. Ltd. 2003 Page 5 of 22 FT245BM FT245BM USB FIFO ( USB - Parallel ) I.C. · · · · · · stuffing and CRC5 / CRC16 CRC16 generation / checking on the USB data stream. USB Protocol Engine The USB Protocol Engine manages the data stream from the device USB control endpoint. It handles the low level USB protocol (Chapter 9) requests generated by the USB host controller and the commands for controlling the functional parameters of the FIFO. FIFO Receive Buffer ( 128 bytes ) Data sent from the USB Host to the FIFO via the USB data out endpoint is stored in the FIFO Receive Buffer and is removed from the buffer by reading the FIFO contents using RD#. FIFO Transmit Buffer ( 384 bytes ) Data written into the FIFO using WR# is stored in the FIFO Transmit Buffer. The Host removes Data from the FIFO Transmit Data by sending a USB request for data from the device data in endpoint. FIFO Controller The FIFO Controller handles the transfer of data between the external FIFO interface pins and the FIFO Transmit and Receive buffers. RESET Generator The Reset Generator Cell provides a reliable power-on reset to the device internal circuitry on power up. An additional RESET# input and RSTOUT# output are provided to allow other devices to reset the FT245BM FT245BM, or the FT245BM FT245BM to reset other devices respectively. During reset, RSTOUT# is driven low, otherwise it drives out at the 3.3V provided by the onboard regulator. RSTOUT# can be used to control the 1k5 pullup on USB DP directly where delayed USB enumeration is required. RSTOUT# will be low for approximately 5ms after VCC has risen above 3.5V AND the device oscillator is running AND RESET# is high. RESET# should be tied to VCC unless it is a requirement to reset the device from external logic or an external reset generator i.c. EEPROM Interface Though the FT245BM FT245BM will work without the optional EEPROM, an external 93C46 93C46 ( 93C56 93C56 or 93C66 93C66 ) DS245B DS245B Version 1.1 EEPROM can be used to customise the USB VID, PID, Serial Number, Product Description Strings and Power Descriptor value of the FT245BM FT245BM for OEM applications. Other parameters controlled by the EEPROM include Remote Wake Up, Isochronous Transfer Mode, Soft Pull Down on Power-Off and USB 2.0 descriptor modes. The EEPROM should be a 16 bit wide configuration such as a MicroChip 93LC46B 93LC46B or equivalent capable of a 1Mb/s clock rate at VCC = 4.35V to 5.25V. The EEPROM is programmableon board over USB using a utility available from FTDI's web site ( http://www.ftdichip.com ). This allows a blank part to be soldered onto the PCB and programmed as part of the manufacturing and test process. If no EEPROM is connected ( or the EEPROM is blank ), the FT245BM FT245BM will use it's built-in default VID, PID Product Description and Power Descriptor Value. In this case, the device will not have a serial number as part of the USB descriptor. © Future Technology Devices Intl. Ltd. 2003 Page 6 of 22 FT245BM FT245BM USB FIFO ( USB - Parallel ) I.C. 4.0 Device Pin-Out D0 VCC XTIN XTOUT AGND AVCC EECS XXYY USBDP 8 D4 RD# WR TXE# VCCIO RXF# SI / WU PWREN# GND D6 17 16 7 D5 D7 9 8 GND 5 4 27 28 32 1 2 31 USBDM D0 D1 D2 D3 USBDP D4 D5 RSTOUT# D6 RESET# D7 XTIN RD# WR XTOUT TXE# EECS RXF# EESK SI / WU EEDATA TEST A G N D G N D PWREN# 25 24 23 22 21 20 19 18 16 15 14 12 11 10 17 © Future Technology Devices Intl. Ltd. 2003 G N D 9 29 DS245B DS245B Version 1.1 V C C I O D3 FT245BM FT245BM RSTO# 3V3OUT USBDM D2 V C C 13 VCC D1 V C C 26 FTDI EEDATA 24 A V V 3V3OUT C 3 1 RESET# 6 25 32 EESK Figure 2 Pin-Out (Schematic Symbol ) 30 TEST Figure 1 Pin-Out (LQFP-32 LQFP-32 Package ) Page 7 of 22 FT245BM FT245BM USB FIFO ( USB - Parallel ) I.C. 4.1 Signal Descriptions Table 1 - FT245BM FT245BM - PINOUT DESCRIPTION FIFO DATA BUS GROUP ( * Note 1 ) Pin# Signal Type Description 25 DO I/O FIFO Data Bus Bit 0 24 D1 I/O FIFO Data Bus Bit 1 23 D2 I/O FIFO Data Bus Bit 2 22 D3 I/O FIFO Data Bus Bit 3 21 D4 I/O FIFO Data Bus Bit 4 20 D5 I/O FIFO Data Bus Bit 5 19 D6 I/O FIFO Data Bus Bit 6 18 D7 I/O FIFO Data Bus Bit 7 FIFO CONTROL INTERFACE GROUP Pin# Signal Type Description 16 RD# IN Enables Current FIFO Data Byte on D0.D7 when low. Fetches the next FIFO Data Byte ( if available ) from the Receive FIFO Buffer when RD# goes from low to high. ( * Note 1 ) 15 WR IN Writes the Data Byte on the D0.D7 into the Transmit FIFO Buffer when WR goes from high to low. ( * Note 1 ) 14 TXE# OUT When high, do not write data into the FIFO. When low, data can be written into the FIFO by strobing WR high then low. ( * Note 2 ) 12 RXF# OUT When high, do not read data from the FIFO. When low, there is data available in the FIFO which can be read by strobing RD# low then high again ( * Note 2 ) USB INTERFACE GROUP Pin# Signal Type Description 7 USBDP I/O USB Data Signal Plus ( Requires 1.5k pull-up to 3V3OUT or RSTOUT# ) 8 USBDM I/O USB Data Signal Minus EEPROM INTERFACE GROUP Pin# Signal Type Description 32 EECS I/O EEPROM ­ Chip Select. For 48MHz operation pull EECS to GND using a 10k resistor. For 6MHz operation no resistor is required. ( * Note 3 ) 1 EESK OUT Clock signal to EEPROM. ( * Note 3 ) 2 EEDATA I/O EEPROM ­ Data I/O Connect directly to Data-In of the EEPROM and to DataOut of the EEPROM via a 2k2 resistor. Also pull Data-Out of the EEPROM to VCC via a 10k resistor for correct operation. ( * Note 3 ) DS245B DS245B Version 1.1 © Future Technology Devices Intl. Ltd. 2003 Page 8 of 22 FT245BM FT245BM USB FIFO ( USB - Parallel ) I.C. POWER CONTROL GROUP Pin# Signal Type Description 10 PWREN# OUT Goes Low after the device is configured via USB, then high during USB suspend. Can be used to control power to external logic using a P-Channel Logic Level MOSFET switch. Enable the Interface Pull-Down Option in EEPROM when using the PWREN# pin in this way. 11 SI / WU IN The Send Immediate / WakeUp signal combines two functions on a single pin. If USB is in suspend mode ( PWREN# = 1 ) and remote wakeup is enabled in the EEPROM , strobing this pin low will cause the device to request a resume on the USB Bus. Normally, this can be used to wake up the Host PC. During normal operation ( PWREN# = 0 ), if this pin is strobed low any data in the device TX buffer will be sent out over USB on the next Bulk-IN request from the drivers regardless of the pending packet size. This can be used to optimise USB transfer speed for some applications. Tie this pin to VCCIO if not used. MISCELLANEOUS SIGNAL GROUP Pin# Signal Type Description 4 RESET# IN Can be used by an external device to reset the FT245BM FT245BM. If not required, tie to VCC. 5 RSTOUT# OUT Output of the internal Reset Generator. Stays high impedance for ~ 5ms after VCC > 3.5V and the internal clock starts up, then clamps it's output to the 3.3V output of the internal regulator. Taking RESET# low will also force RSTOUT# to drive low. RSTOUT# is NOT affected by a USB Bus Reset. 27 XTIN IN Input to 6MHz Crystal Oscillator Cell. This pin can also be driven by an external 6MHz clock if required. Note : Switching threshold of this pin is VCC/2, so if driving from an external source, the source must be driving at 5V CMOS level or a.c. coupled to centre around VCC/2. 28 XTOUT OUT Output from 6MHz Crystal Oscillator Cell. XTOUT stops oscillating during USB suspend, so take care if using this signal to clock external logic. 31 TEST IN Puts device in i.c. test mode ­ must be tied to GND for normal operation. POWER AND GND GROUP Pin# Signal Type Description 6 3V3OUT OUT 3.3 volt Output from the integrated L.D.O. regulator This pin should be decoupled to GND using a 33nF ceramic capacitor in close proximity to the device pin. It's prime purpose is to provide the internal 3.3V supply to the USB transceiver cell and the RSTOUT# pin. A small amount of current ( Vcc ) . 100mA 6.1 D.C. Characteristics DC Characteristics ( Ambient Temperature = 0 . 70oC ) Operating Voltage and Current Parameter Description Min Typ Max Units Conditions Vcc1 VCC Operating Supply Voltage 4.35 5.0 5.25 V Vcc2 VCCIO Operating Supply Voltage 3.0 - 5.25 V Icc1 Operating Supply Current - 25 - mA Normal Operation Icc2 Operating Supply Current - 100 200 uA USB Suspend * Note 1 Note 1 ­ Supply current excludes the 200uA nominal drawn by the external pull-up resistor on USB DP. FIFO Data / Control Bus IO Pin Characteristics ( VCCIO = 5.0V ) Parameter Description Min Typ Max Units Voh Output Voltage High 4.4 - 4.9 V I source = 2mA Vol Output Voltage Low 0.1 - 0.7 V I sink = 4 mA Vin Input Switching Threshold 1.1 1.5 1.9 V * Note 2 VHys Input Switching Hysteresis 200 Conditions mV FIFO Data / Control Bus IO Pin Characteristics ( VCCIO = 3.3V ) Parameter Description Min Typ Max Units Voh Output Voltage High 2.7 - 3.2 V I source = 2mA Vol Output Voltage Low 0.1 - 0.7 V I sink = 4 mA Vin Input Switching Threshold 1.0 1.4 1.8 V * Note 2 VHys Input Switching Hysteresis 200 Conditions mV Note 2 ­ Inputs or IO Pins in Input Mode have an internal 200k pull-up resistor to VCCIO. DS245B DS245B Version 1.1 © Future Technology Devices Intl. Ltd. 2003 Page 12 of 22 FT245BM FT245BM USB FIFO ( USB - Parallel ) I.C. XTIN / XTOUT Pin Characteristics Parameter Description Min Typ Max Units Conditions Voh Output Voltage High 4.0 - 5.0 V Fosc = 6MHz Vol Output Voltage Low 0.1 - 1.0 V Fosc = 6MHz Vin Input Switching Threshold 1.8 2.5 3.2 V RESET#, TEST, EECS, EESK, EEDATA, IO Pin Characteristics Parameter Description Min Typ Max Units Voh Output Voltage High 4.4 - 4.9 V I source = 2mA Vol Output Voltage Low 0.1 - 0.7 V I sink = 4 mA Vin Input Switching Threshold 1.1 1.5 1.9 V * Note 3 VHys Input Switching Hysteresis 200 Conditions mV Note 3 ­ EECS, EESK and EEDATA pins have an internal 200k pull-up resistor to VCC RSTOUT Pin Characteristics Parameter Description Min Typ Max Units Voh Output Voltage High 3.0 - 3.6 V Iol Leakage Current Tri-State - - 5 uA Typ Max Units Conditions I source = 2mA USB IO Pin Characteristics Parameter Description Min Conditions UVoh IO Pins Static Output ( High) 2.8 3.6 V RI = 1k5 to 3V3Out ( D+ ) RI = 15k to GND ( D- ) UVol IO Pins Static Output ( Low ) 0 0.3 V RI = 1k5 to 3V3Out ( D+ ) RI = 15k to GND ( D- ) UVse Single Ended Rx Threshold 0.8 2.0 V UCom Differential Common Mode 0.8 2.5 V UVDif Differential Input Sensitivity 0.2 UDrvZ Driver Output Impedance 29 V 44 Ohm * Note 4 Note 4 ­ Driver Output Impedance includes the external 27R series resistors on USBDP and USBDM pins. DS245B DS245B Version 1.1 © Future Technology Devices Intl. Ltd. 2003 Page 13 of 22 FT245BM FT245BM USB FIFO ( USB - Parallel ) I.C. 7.0 Device Configuration Examples 7.1 Oscillator Configurations Figure 4 3 Pin Ceramic Resonator Configuration Figure 5 Crystal or 2-Pin Ceramic Resonator FT245BM FT245BM FT245BM FT245BM 27pF 27 3-Pin Resonator 6MHz XTIN 28 XTOUT 2 - Pin Resonator or Crystal 6MHz 1M 28 27 XTIN 27pF XTOUT Configuration Figure 4 illustrates how to use the FT245BM FT245BM with a 3-Pin Ceramic Resonator. A suitable part would be a ceramic resonator from Murata's CERALOCK range. (Murata Part Number CSTCR6M00G15 CSTCR6M00G15), or equivalent. 3-Pin ceramic resonators have the load capacitors built into the resonator so no external loading capacitors are required. This makes for an economical configuration. The accuracy of this Murata ceramic resonator is +/- 0.1% and it is specifically designed for USB full speed applications. A 1 MOhm loading resistor across XTIN and XTOUT is recommended in order to guarantee this level of accuracy. Other ceramic resonators with a lesser degree of accuracy ( typically +/- 5% ) are technically out-with the USB specification, but it has been calculated that using such a device will work satisfactorily in practice with a FT245BM FT245BM design. Figure 5 illustrates how to use the FT245BM FT245BM with a 6MHz Crystal or 2-Pin Ceramic Resonator. In this case, these devices do not have in-built loading capacitors so these have to be added between XTIN, XTOUT and GND as shown. A value of 27pF is shown as the capacitor in the example ­ this will be good for many crystals and some resonators but do select the value based on the manufacturers recommendations wherever possible. If using a crystal, use a parallel cut type. If using a resonator, see the previous note on frequency accuracy. DS245B DS245B Version 1.1 © Future Technology Devices Intl. Ltd. 2003 Page 14 of 22 FT245BM FT245BM USB FIFO ( USB - Parallel ) I.C. 7.2 EEPROM Configuration Figure 6 FT245BM FT245BM EEPROM Configuration 32 EECS Figure 6 illustrates how to connect the FT245BM FT245BM to the 93C46 93C46 ( 93C56 93C56 or 93C66 93C66 ) EEPROM. EECS ( pin 32 ) EESK is directly connected to the chip select ( CS ) pin of the 2 EEDATA EEPROM. EESK ( pin 1 ) is directly connected to the clock ( SK ) pin of the EEPROM. EEDATA ( pin 2 ) is directly connected to the Data In ( Din ) pin of the EEPROM. There is a potential condition whereby both the Data Output ( Dout ) of the EEPROM can drive out at the same time as the EEDATA VCC pin of the FT245BM FT245BM. To prevent potential data clash in this EEPROM - 93C46 93C46 / 56 / 66 situation, the Dout of the EEPROM is connected to EEDATA 1 8 of the FT245BM FT245BM via a 2k2 resistor. CS VCC Following a power-on reset or a USB reset, the FT245BM FT245BM will 7 2 SK NC scan the EEPROM to find out a) if an EEPROM is attached 2k2 3 6 DIN NC to the Device and b) if the data in the device is valid. If both 4 5 of these are the case, then the FT245BM FT245BM will use the data in DOUT GND the EEPROM, otherwise it will use it's built-in default values. When a valid command is issued to the EEPROM from the VCC 10k FT245BM FT245BM, the EEPROM will acknowledge the command by pulling it's Dout pin low. In order to check for this condition, it is necessary to pull Dout high using a 10k resistor. If the command acknowledge doesn't happen then EEDATA will be pulled high by the 10k resistor during this part of the cycle and the device will detect an invalid command or no EEPROM present. There are two varieties of these EEPROM's on the market ­ one is configured as being 16 bits wide, the other is configured as being 8 bits wide. These are available from many sources such as Microchip, ST Micro, ISSI etc. The FT245BM FT245BM requires EEPROM's with a 16-bit wide configuration such as the Microchip 93LC46B 93LC46B device. The EEPROM must be capable of reading data at a 1Mb clock rate at a supply voltage of 4.35V to 5.25V. Most available parts are capable of this. Check the manufacturers data sheet to find out how to connect pins 6 and 7 of the EEPROM. Some devices specify these as no-connect, others use them for selecting 8 / 16 bit mode or for test functions. Some other parts have their pinout rotated by 90o so please select the required part and it's options carefully. It is possible to "share" the EEPROM between the FT245BM FT245BM and another external device such as an MCU. However, this can only be done when the FT245BM FT245BM is in it's reset condition as it tri-states it's EEPROM interface at that time. A typical configuration would use four bit's of an MCU IO Port. One bit would be used to hold the FT245BM FT245BM reset ( using RESET# ) on power-up, the other three would connect to the EECS, EESK and EEDATA pins of the FT245BM FT245BM in order to read / write data to the EEPROM at this time. Once the MCU has read / written the EEPROM, it would take RESET# high to allow the FT245BM FT245BM to configure itself and enumerate over USB. 1 DS245B DS245B Version 1.1 © Future Technology Devices Intl. Ltd. 2003 Page 15 of 22 FT245BM FT245BM USB FIFO ( USB - Parallel ) I.C. 7.3 USB Bus Powered and Self Powered Configuration Figure 7 USB Bus Powered Configuration USB "B" Connector Ferrite Bead 1 470R VCC 27R 2 3 3 FT245BM FT245BM 27R 4 6 10nF 33nF 8 7 26 V C C V C C 3v3OUT 30 13 V C C I O 0.1uF A V C C USB DM USB DP 1k5 5 RSTOUT# VCC VCC 4 RESET# + 0.1uF 0.1uF 10uF G N D A G N D G N D 9 17 29 Decoupling Capacitors Figure 7 illustrates a typical USB bus powered configuration. A USB Bus Powered device gets its power from the USB bus. Basic rules for USB Bus power devices are as follows ­ a) On plug-in, the device must draw no more than 100mA b) On USB Suspend the device must draw no more than 500uA. c) A Bus Powered High Power Device ( one that draws more than 100mA ) should use the PWREN# pin to keep the current below 100mA on plug-in and 500uA on USB suspend. d) A device that consumes more than 100mA can not be plugged into a USB Bus Powered Hub e) No device can draw more that 500mA from the USB Bus. The power descriptor in the EEPROM should be programmed to match the current draw of the device. A Ferrite Bead is connected in series with USB power to prevent noise from the device and associated circuitry ( EMI ) being radiated down the USB cable to the Host. The value of the Ferrite Bead depends on the total current required by the circuit ­ a suitable range of Ferrite Beads is available from Steward ( www.steward.com ) for example Steward Part # MI0805K400R-00 MI0805K400R-00 also available as DigiKey Part # 240-1035-1. DS245B DS245B Version 1.1 © Future Technology Devices Intl. Ltd. 2003 Page 16 of 22 FT245BM FT245BM USB FIFO ( USB - Parallel ) I.C. Figure 8 USB Self Powered Configuration USB "B" Connector 1 470R VCC 27R 2 3 3 FT245BM FT245BM 27R 4 6 33nF 26 V C C V C C 3v3OUT 30 13 V C C I O 0.1uF A V C C 4k7 8 7 10k USB DP 1k5 5 4 VCC + 0.1uF USB DM 0.1uF RSTOUT# RESET# G N D 10uF A G N D G N D 9 17 29 Decoupling Capacitors Figure 8 illustrates a typical USB self powered configuration. A USB Self Powered device gets its power from its own POWER SUPPLY and does not draw current from the USB bus. The basic rules for USB Self power devices are as follows ­ a) A Self-Powered device should not force current down the USB bus when the USB Host or Hub Controller is powered down. b) A Self Powered Device can take as much current as it likes during normal operation and USB suspend as it has its own POWER SUPPLY. c) A Self Powered Device can be used with any USB Host and both Bus and Self Powered USB Hubs The USB power descriptor option in the EEPROM should be programmed to a value of zero ( self powered ). To meet requirement a) the 1k5 pull-up resistor on USB DP is connected to RSTOUT# as per the bus-power circuit. However, the USB Bus Power is used to control the RESET# Pin of the FT245BM FT245BM device. When the USB Host or Hub is powered up RSTOUT# will pull the 1K5 resistor on USB DP to 3.3V, thus identifying the device as a full speed device to USB. When the USB Host or Hub power is off, RESET# will go low and the device will be held in reset. As RESET# is low, RSTOUT# will also be low, so no current will be forced down USB DP via the 1k5 pull-up resistor when the host or hub is powered down. Failure to do this may cause some USB host or hub controllers to power up erratically. Note : When the FT245B FT245B is in reset, the FIFO interface pins all go tri-state. These pins have internal 200k pull-up resistors to VCCIO so they will gently pull high unless driven by some external logic. DS245B DS245B Version 1.1 © Future Technology Devices Intl. Ltd. 2003 Page 17 of 22 FT245BM FT245BM USB FIFO ( USB - Parallel ) I.C. Figure 9 Bus Powered Circuit with 3.3V logic drive / supply voltage 3.3v LDO Regulator In USB "B" Connector Ferrite Bead 1 2 Gnd 10nF 0.1uF 470R 3 27R 4 Out VCC 27R 3 3.3v Power to External Logic 6 33nF 26 V C C 13 V C C V C C I O 3v3OUT 30 0.1uF A V C C FT245BM FT245BM 8 7 USB DM USB DP Figure 9 shows how to configure the FT245BM FT245BM to interface with a 3.3V logic device. In this example, a discrete 3.3V regulator is used to supply the 3.3V logic from the USB supply. VCCIO is connected to the output of the 3.3V regulator, which in turn will cause the FIFO interface IO pins to drive out at 3.3V level. For USB bus powered circuits some considerations have to be taken into account when selecting the regulator ­ a) The regulator must be capable of sustaining its output voltage with an input voltage of 4.35 volts. A Low Drop Out ( LDO ) regulator must be selected. b) The quiescent current of the regulator must be low in order to meet the USB suspend total current requirement of