FT232BM FT8U232AM RS232 RS422/RS485 RS422 RS485 32-LD DS232B 93C46 93C56 93C66

The FT232BM is the 2nd generation of FTDI's popular USB UART I.C. This device not only adds extra functionality to its FT8U232AM

FT232BM FT232BM USB UART ( USB - Serial) I.C. The FT232BM FT232BM is the 2nd generation of FTDI's popular USB UART I.C. This device not only adds extra functionality to its FT8U232AM FT8U232AM predecessor and reduces external component count, but also maintains a high degree of pin compatibility with the original, making it easy to upgrade or cost reduce existing designs as well as increasing the potential for using the device in new application areas. 1.0 Features HARDWARE FEATURES · Single Chip USB Asynchronous Serial Data VIRTUAL COM PORT (VCP) DRIVERS for Transfer - Windows 98 and Windows 98 SE · Full Handshaking & Modem Interface Signals - Windows 2000 / ME / XP · UART I/F Supports 7 / 8 Bit Data, 1 / 2 Stop Bits - Windows CE 4.2 and Odd/Even/Mark/Space/No Parity - MAC OS-8 and OS-9 · Data rate 300 => 3M Baud (TTL) - MAC OS-X · Data rate 300 => 1M Baud (RS232 RS232) - Linux 2.40 and greater · Data rate 300 => 3M Baud (RS422/RS485 RS422/RS485) D2XX (USB Direct Drivers + DLL S/W Interface) · 384 Byte Receive Buffer / 128 Byte Transmit Buffer - Windows 98 and Windows 98 SE for high data throughput - Windows 2000 / ME / XP · Adjustable RX buffer timeout - Windows CE 4.2 · Fully Assisted Hardware or X-On / X-Off - Linux 2.40 and greater Handshaking APPLICATION AREAS In-built support for event characters and line break - USB RS232 RS232 Converters condition - USB RS422 RS422 / RS485 RS485 Converters · Auto Transmit Buffer control for RS485 RS485 - Upgrading RS232 RS232 Legacy Peripherals to USB · Support for USB Suspend / Resume through - Cellular and Cordless Phone USB data transfer · SLEEP# and RI# pins cables and interfaces Support for high power USB Bus powered devices - Interfacing MCU based designs to USB through PWREN# pin - USB Audio and Low Bandwidth Video data transfer Integrated level converter on UART and control - PDA USB data transfer signals for interfacing to 5V and 3.3V logic - USB Smart Card Readers · Integrated 3.3V regulator for USB IO - Set Top Box (S.T.B.) PC - USB interface · Integrated Power-On-Reset circuit - USB Hardware Modems · Integrated 6MHz 48Mhz clock multiplier PLL - USB Wireless Modems · USB Bulk or Isochronous data transfer modes - USB Instrumentation · 4.35V to 5.25V single supply operation - USB Bar Code Readers · UHCI / OHCI / EHCI host controller compatible · USB 1.1 and USB 2.0 compatible · USB VID, PID, Serial Number and Product · · Description strings in external EEPROM · EEPROM programmable on-board via USB · Compact 32-LD 32-LD LQFP package DS232B DS232B Version 1.7 © Future Technology Devices Intl. Ltd. 2005 Page 1 of 25 FT232BM FT232BM USB UART ( USB - Serial) I.C. 2.0 Enhancements This section summarises the enhancements of the 2nd generation device compared to its FT8U232AM FT8U232AM predecessor. For further details, consult the device pin-out description and functional descriptions. Integrated Power-On-Reset (POR) Circuit This gating is now done on-chip - USBEN has The device now incorporates an internal POR now been replaced with the new PWREN# signal function. The existing RESET# pin is maintained which can be used to directly drive a transistor or in order to allow external logic to reset the device P-Channel MOSFET in applications where power where required, however for many applications switching of external circuitry is required. A new this pin can now simply be hard wired to VCC. In EEPROM based option makes the device pull addition, a new reset output pin (RSTOUT#) is gently down its UART interface lines when the provided in order to allow the new POR circuit to power is shut off (PWREN# is High). In this mode, provide a stable reset to external MCU and other any residual voltage on external circuitry is bled to devices. RSTOUT# was the TEST pin on the GND when power is removed thus ensuring that previous generation of devices. · external circuitry controlled by PWREN# resets reliably when power is restored. · Integrated RCCLK Circuit In the previous devices, an external RC circuit · Lower Suspend Current was required to ensure that the oscillator and clock multiplier PLL frequency was stable prior design improvements reduce the suspend current to enabling the clock internal to the device. This of the FT232BM FT232BM to under 200uA (excluding the circuit is now embedded on-chip the pin assigned 1.5k pull-up on USBDP) in USB suspend mode. to this function is now designated as the TEST pin This allows greater margin for peripherals to meet and should be tied to GND for normal operation. · Integration of RCCLK within the device and internal the USB Suspend current limit of 500uA. Integrated Level Converter on UART interface · Support for USB Isochronous Transfers and control signals Whilst USB Bulk transfer is usually the best The previous devices would drive the UART and choice for data transfer, the scheduling time of the control signals at 5V CMOS logic levels. The data is not guaranteed. For applications where new device has a separate VCC-IO pin allowing scheduling latency takes priority over data integrity the device to directly interface to 3.3V and other such as transferring audio and low bandwidth logic families without the need for external level video data, the new device now offers an option of converter I.C.'s USB Isochronous transfer via an option bit in the EEPROM. · Improved Power Management control for USB Bus Powered, high current devices The previous devices had a USBEN pin, which became active when the device was enumerated by USB. To provide power control, this signal had to be externally gated with SLEEP# and RESET#. DS232B DS232B Version 1.7 © Future Technology Devices Intl. Ltd. 2005 Page 2 of 25 FT232BM FT232BM USB UART ( USB - Serial) I.C. Programmable Receive Buffer Timeout to the device and they will be sequentially sent to In the previous device, the receive buffer timeout the interface at a rate controlled by the prescaler used to flush remaining data from the receive setting. As well as allowing the device to be used buffer was fixed at 16ms timeout. This timeout is stand-alone as a general purpose IO controller for now programmable over USB in 1ms increments example controlling lights, relays and switches, from 1ms to 255ms, thus allowing the device to some other interesting possibilities exist. For be better optimised for protocols requiring faster instance, it may be possible to connect the device response times from short data packets. · to an SRAM configurable FPGA as supplied by vendors such as Altera and Xilinx. The FPGA TXDEN Timing fix device would normally be un-configured (i.e. have TXDEN timing has now been fixed to remove the no defined function) at power-up. Application external delay that was previously required for software on the PC could use Bit Bang Mode to RS485 RS485 applications at high baud rates. TXDEN download configuration data to the FPGA which now works correctly during a transmit send-break would define its hardware function, then after the condition. · FPGA device is configured the FT232BM FT232BM can switch back into UART interface mode to allow Relaxed VCC Decoupling the programmed FPGA device to communicate The 2 generation devices now incorporate a level with the PC over USB. This approach allows a of on-chip VCC decoupling. Though this does customer to create a "generic" USB peripheral not eliminate the need for external decoupling who's hardware function can be defined under capacitors, it significantly improves the ease of control of the application software. The FPGA PCB design requirements to meet FCC, CE and based hardware can be easily upgraded or other EMI related specifications. · totally changed simply by changing the FPGA nd configuration data file. Application notes, software Improved PreScaler Granularity and development modules for this application area The previous version of the Prescaler supported · will be available from FTDI and other 3rd parties. division by (n + 0), (n + 0.125), (n + 0.25) and (n + 0.5) where n is an integer between 2 and 14 · PreScaler Divide By 1 Fix 16,384 (2 ). To this we have added (n + 0.375), The previous device had a problem when the (n + 0.625), (n + 0.75) and (n+ 0.875) which can integer part of the divisor was set to 1. In the 2nd be used to improve the accuracy of some baud generation device setting the prescaler value to 1 rates and generate new baud rates which were gives a baud rate of 2 million baud and setting it previously impossible (especially with higher baud to zero gives a baud rate of 3 million baud. Non- rates). integer division is not supported with divisor values of 0 and 1. · Bit Bang Mode The 2nd generation device has a new option referred to as "Bit Bang" mode. In Bit Bang mode, the eight UART interface control lines can be switched between UART interface mode and an 8-bit Parallel IO port. Data packets can be sent DS232B DS232B Version 1.7 © Future Technology Devices Intl. Ltd. 2005 Page 3 of 25 FT232BM FT232BM USB UART ( USB - Serial) I.C. · Less External Support Components · Multiple Device Support without EEPROM As well as eliminating the RCCLK RC network, and When no EEPROM (or a blank or invalid for most applications the need for an external reset EEPROM) is attached to the device, the FT232BM FT232BM circuit, we have also eliminated the requirement for no longer gives a serial number as part of its a 100K pull-up on EECS to select 6MHz operation. USB descriptor. This allows multiple devices to When the FT232BM FT232BM is being used without the be simultaneously connected to the same PC. configuration EEPROM, EECS, EESK and EEDATA However, we still highly recommend that EEPROM can now be left n/c. For circuits requiring a long is used, as without serial numbers a device can reset time (where the device is reset externally only be identified by which hub port in the USB tree using a reset generator I.C., or reset is controlled it is connected to which can change if the end user by the IO port of a MCU, FPGA or ASIC device) an re-plugs the device into a different port. external transistor circuit is no longer required as the 1.5k pull-up resistor on USBDP can be wired to the RSTOUT# pin instead of to 3.3V. Note : RSTOUT# drives out at 3.3V level, not at 5V VCC level. This is the preferred configuration for new designs. · Extended EEPROM Support The previous generation of devices only supported EEPROM of type 93C46 93C46 (64 x 16 bit). The new devices will also work with EEPROM type 93C56 93C56 (128 x 16 bit) and 93C66 93C66 (256 x 16 bit). The extra space is not used by the device, however it is available for use by other external MCU / logic whilst the FT232BM FT232BM is being held in reset. · USB 2.0 (full speed option) A new EEPROM based option allows the FT232BM FT232BM to return a USB 2.0 device descriptor as opposed to USB 1.1. Note : The device would be a USB 2.0 Full Speed device (12Mb/s) as opposed to a USB 2.0 High Speed device (480Mb/s). DS232B DS232B Version 1.7 © Future Technology Devices Intl. Ltd. 2005 Page 4 of 25 FT232BM FT232BM USB UART ( USB - Serial) I.C. 3.0 Block Diagram (Simplified) VCC PWRCTL 3V3OUT SLEEP# PWREN# 3.3 Volt LDO Regulator USBDP USB Transceiver USBDM 48MHz Baud Rate Generator Dual Port TX Buffer 128 bytes Serial Interface Engine ( SIE ) USB Protocol Engine UART FIFO Controller UART TXD RXD RTS# CTS# DTR# DSR# DCD# RI# TXDEN TXLED# RXLED# Dual Port RX Buffer 384 Bytes USB DPLL 3V3OUT XTOUT 48MHz 6MHZ Oscillator x8 Clock Multiplier XTIN 12MHz EECS EEPROM Interface EESK EEDATA RESET GENERATOR RESET# RSTOUT# TEST GND 3.1 · · Functional Block Descriptions 3.3V LDO Regulator The 3.3V LDO Regulator generates the 3.3 volt reference voltage for driving the USB transceiver cell output buffers. It requires an external decoupling capacitor to be attached to the 3V3OUT regulator output pin. It also provides 3.3V power to the RSTOUT# pin. The main function of this block is to power the USB Transceiver and the Reset Generator Cells rather than to power external logic. However, external circuitry requiring 3.3V nominal at a current of not greater than 5mA could also draw its power from the 3V3OUT pin if required. and two single ended receivers provide USB data in, SEO and USB Reset condition detection. · USB DPLL The USB DPLL cell locks on to the incoming NRZI USB data and provides separate recovered clock and data signals to the SIE block. · 6MHz Oscillator The 6MHz Oscillator cell generates a 6MHz reference clock input to the x8 Clock multiplier from an external 6MHz crystal or ceramic resonator. USB Transceiver The USB Transceiver Cell provides the USB 1.1 / USB 2.0 full-speed physical interface to the USB cable. The output drivers provide 3.3 volt level slew rate control signalling, whilst a differential receiver DS232B DS232B Version 1.7 © Future Technology Devices Intl. Ltd. 2005 Page 5 of 25 FT232BM FT232BM USB UART ( USB - Serial) I.C. · x8 Clock Multiplier The x8 Clock Multiplier takes the 6MHz input from the Oscillator cell and generates a 12MHz reference clock for the SIE, USB Protocol Engine and UART FIFO controller blocks. It also generates a 48MHz reference clock for the USB DPPL and the Baud Rate Generator blocks. · Serial Interface Engine (SIE) The Serial Interface Engine (SIE) block performs the Parallel to Serial and Serial to Parallel conversion of the USB data. In accordance to the USB 2.0 specification, it performs bit stuffing / unstuffing and CRC5 / CRC16 CRC16 generation / checking on the USB data stream. · USB Protocol Engine The USB Protocol Engine manages the data stream from the device USB control endpoint. It handles the low level USB protocol (Chapter 9) requests generated by the USB host controller and the commands for controlling the functional parameters of the UART. · Dual Port TX Buffer (128 bytes) Data from the USB data out endpoint is stored in the Dual Port TX buffer and removed from the buffer to the UART transmit register under control of the UART FIFO controller. · Dual Port RX Buffer (384 bytes) Data from the UART receive register is stored in the Dual Port RX buffer prior to being removed by the SIE on a USB request for data from the device data in endpoint. · UART FIFO Controller The UART FIFO controller handles the transfer of data between the Dual Port RX and TX buffers and the UART transmit and receive registers. · of the data on the RS232 RS232 (RS422 RS422 and RS485 RS485) interface. Control signals supported by the UART include RTS, CTS, DSR , DTR, DCD and RI. The UART provides a transmitter enable control signal (TXDEN) to assist with interfacing to RS485 RS485 transceivers. The UART supports RTS/ CTS, DSR/DTR and X-On/X-Off handshaking options. Handshaking, where required, is handled in hardware to ensure fast response times. The UART also supports the RS232 RS232 BREAK setting and detection conditions. · Baud Rate Generator The Baud Rate Generator provides a x16 clock input to the UART from the 48MHz reference clock and consists of a 14 bit prescaler and 3 register bits which provide fine tuning of the baud rate (used to divide by a number plus a fraction). This determines the Baud Rate of the UART which is programmable from 183 baud to 3 million baud. · RESET Generator The Reset Generator Cell provides a reliable power-on reset to the device internal circuitry on power up. An additional RESET# input and RSTOUT# output are provided to allow other devices to reset the FT232BM FT232BM or the FT232BM FT232BM to reset other devices respectively. During reset, RSTOUT# is driven low, otherwise it drives out at the 3.3V provided by the onboard regulator. RSTOUT# can be used to control the 1.5k pull-up on USBDP directly where delayed USB enumeration is required. It can also be used to reset other devices. RSTOUT# will stay highimpedance for approximately 5ms after VCC has risen above 3.5V AND the device oscillator is running AND RESET# is high. RESET# should be tied to VCC unless it is a requirement to reset the device from external logic or an external reset generator i.c. UART The UART performs asynchronous 7 / 8 bit Parallel to Serial and Serial to Parallel conversion DS232B DS232B Version 1.7 © Future Technology Devices Intl. Ltd. 2005 Page 6 of 25 FT232BM FT232BM USB UART ( USB - Serial) I.C. EEPROM Interface Though the FT232BM FT232BM will work without the optional EEPROM, an external 93C46 93C46 (93C56 93C56 or 93C66 93C66) EEPROM can be used to customise the USB VID, PID, Serial Number, Product Description Strings and Power Descriptor value of the FT232BM FT232BM for OEM applications. Other parameters controlled by the EEPROM include Remote Wake Up, Isochronous Transfer Mode, Soft Pull Down on Power-Off and USB 2.0 descriptor modes. The EEPROM should be a 16 bit wide configuration such as a MicroChip 93LC46B 93LC46B or · 4.0 equivalent capable of a 1Mb/s clock rate at VCC = 4.35V to 5.25V. The EEPROM is programmableon board over USB using a utility available from FTDI's web site (http://www.ftdichip.com). This allows a blank part to be soldered onto the PCB and programmed as part of the manufacturing and test process. If no EEPROM is connected (or the EEPROM is blank), the FT232BM FT232BM will use its built-in default VID, PID Product Description and Power Descriptor Value. In this case, the device will not have a serial number as part of the USB descriptor. Device Pin-Out V C C I O V C C TXD RXD TXD VCC XTIN AGND XTOUT AVCC TEST EECS 13 26 3V3OUT 3 30 6 V C C A V V C 8 USBDM RTS# CTS# 7 25 32 EESK FTDI EEDATA VCC 3V3OUT USBDP CTS# 4 27 DTR# 16 28 32 GND 1 2 TXDEN Figure 1 Pin-Out (LQFP-32 LQFP-32 Package ) RXLED# XTOUT 23 22 21 20 19 18 16 12 11 EECS EESK PWRCTL EEDATA PWREN# TEST TXDEN PWREN# PWRCTL VCCIO TXLED# XTIN 24 A G N D SLEEP# G N D 14 15 10 G N D 17 RXLED# RI# 9 SLEEP# RESET# 29 GND 31 DS232B DS232B Version 1.7 DCD# TXLED# DCD# 17 9 RSTOUT# DSR# RI# XXYY 8 5 RXD RTS# FT232BM FT232BM RSTOUT# USBDM DSR# 24 1 RESET# DTR# USBDP 25 Figure 2 Pin-Out (Schematic Symbol ) © Future Technology Devices Intl. Ltd. 2005 Page 7 of 25 FT232BM FT232BM USB UART ( USB - Serial) I.C. 4.1 Signal Descriptions Table 1 - FT232BM FT232BM - PINOUT DESCRIPTION UART INTERFACE GROUP Pin# Signal Type Description 25 TXD OUT Transmit Asynchronous Data Output 24 RXD IN Receive Asynchronous Data Input 23 RTS# OUT Request To Send Control Output / Handshake signal 22 CTS# IN Clear To Send Control Input / Handshake signal 21 DTR# OUT Data Terminal Ready Control Output / Handshake signal 20 DSR# IN Data Set Ready Control Input / Handshake signal 19 DCD# IN Data Carrier Detect Control Input 18 RI# IN Ring Indicator Control Input. When the Remote Wakeup option is enabled in the EEPROM, taking RI# low can be used to resume the PC USB Host controller from suspend. 16 TXDEN OUT Enable Transmit Data for RS485 RS485 USB INTERFACE GROUP Pin# Signal Type Description 7 USBDP I/O USB Data Signal Plus ( Requires 1.5k pull-up to 3V3OUT or RSTOUT# ) 8 USBDM I/O USB Data Signal Minus EEPROM INTERFACE GROUP Pin# Signal Type Description 32 EECS I/O EEPROM Chip Select. For 48MHz operation pull EECS to GND using a 10K resistor. For 6MHz operation no resistor is required. Tri-State during device reset. *Note 1 1 EESK OUT Clock signal to EEPROM. Tri-State during device reset, else drives out. Adding a 10K pull down resistor onto EESK will cause the FT232BM FT232BM to use USB Product ID 6004 (hex) instead of 6001 (hex). All of the other USB device descriptors are unchanged.*Note 1 2 EEDATA I/O EEPROM Data I/O Connect directly to Data-In of the EEPROM and to DataOut of the EEPROM via a 2.2K resistor. Also, pull Data-Out of the EEPROM to VCC via a 10K resistor for correct operation. Tri-State during device reset. *Note 1 DS232B DS232B Version 1.7 © Future Technology Devices Intl. Ltd. 2005 Page 8 of 25 FT232BM FT232BM USB UART ( USB - Serial) I.C. POWER CONTROL GROUP Pin# Signal Type Description 10 SLEEP# OUT Goes Low during USB Suspend Mode. Typically used to power-down an external TTL to RS232 RS232 level converter i.c. in USB RS232 RS232 converter designs. 15 PWREN# OUT Goes Low after the device is configured via USB, then high during USB suspend. Can be used to control power to external logic using a P-Channel Logic Level MOSFET switch. Enable the Interface Pull-Down Option in EEPROM when using the PWREN# pin in this way. 14 PWRCTL IN Bus Powered Tie Low / Self Powered Tie High (to VCCIO) MISCELLANEOUS SIGNAL GROUP Pin# Signal Type Description 4 RESET# IN Can be used by an external device to reset the FT232BM FT232BM. If not required, tie to VCC. 5 RSTOUT# OUT Output of the internal Reset Generator. Stays high impedance for ~ 5ms after VCC > 3.5V and the internal clock starts up, then clamps its output to the 3.3v output of the internal regulator. Taking RESET# low will also force RSTOUT# to drive low. RSTOUT# is NOT affected by a USB Bus Reset. 12 TXLED# O.C. LED Drive - Pulses Low when Transmitting Data via USB 11 RXLED# O.C. LED Drive - Pulses Low when Receiving Data via USB 27 XTIN IN Input to 6MHz Crystal Oscillator Cell. This pin can also be driven by an external 6MHz clock if required. Note : Switching threshold of this pin is VCC/2, so if driving from an external source, the source must be driving at 5V CMOS level or a.c. coupled to centre around VCC/2. 28 XTOUT OUT Output from 6MHz Crystal Oscillator Cell. XTOUT stops oscillating during USB suspend, so take care if using this signal to clock external logic. 31 TEST IN Puts device in I.C. test mode must be tied to GND for normal operation. POWER AND GND GROUP Pin# Signal Type Description 6 3V3OUT OUT 3.3 volt Output from the integrated L.D.O. regulator This pin should be decoupled to GND using a 33nF ceramic capacitor in close proximity to the device pin. Its prime purpose is to provide the internal 3.3V supply to the USB transceiver cell and the RSTOUT# pin. A small amount of current (