FSD210 FSD200 230VAC 85-265VAC FSDH565 FSDH0565 FSD200/210 H11A817 KA431 - Datasheet Archive

 

FSD210, FSD200 Green Mode Fairchild Power Switch (FPSTM) Features · Single Chip 700V Sense FET Power Switch ·

 

www.fairchildsemi.com FSD210 FSD210, FSD200 FSD200 Green Mode Fairchild Power Switch (FPSTM) Features · Single Chip 700V Sense FET Power Switch · Precision Fixed Operating Frequency (134kHz) · Advanced Burst-Mode operation Consumes under 0.1W at 265Vac and no load (FSD210 FSD210 only) · Internal Start-up Switch and Soft Start · Under Voltage Lock Out (UVLO) with Hysteresis · Pulse by Pulse Current Limit · Over Load Protection (OLP) · Internal Thermal Shutdown Function (TSD) · Auto-Restart Mode · Frequency Modulation for EMI · FSD200 FSD200 does not require an auxiliary bias winding Applications OUTPUT POWER TABLE 230VAC 230VAC ±15%(3) PRODUCT 85-265VAC 85-265VAC Open Open Adapter(1) Adapter(1) Frame(2) Frame(2) FSD210 FSD210 5W 7W 4W 5W FSD200 FSD200 5W 7W 4W 5W Table 1. Notes: 1. Typical continuous power in a non-ventilated enclosed adapter measured at 50°C ambient. 2. Maximum practical continuous power in an open frame design at 50°C ambient. 3. 230 VAC or 100/115 VAC with doubler. Typical Circuit · Charger & Adaptor for Mobile Phone, PDA & MP3 · Auxiliary Power for White Goods, PC, C-TV & Monitor Description The FSD200 FSD200 and FSD210 FSD210 are integrated Pulse Width Modulators (PWM) and Sense FETs specially designed for high performance off-line Switch Mode Power Supplies (SMPS) with minimal external components. Both devices are monolithic high voltage power switching regulators which combine an LDMOS Sense FET with a voltage mode PWM control block. The integrated PWM controller features include: a fixed oscillator with frequency modulation for reduced EMI, Under Voltage Lock Out (UVLO) protection, Leading Edge Blanking (LEB), optimized gate turn-on/turnoff driver, thermal shut down protection (TSD), temperature compensated precision current sources for loop compensation and fault protection circuitry. When compared to a discrete MOSFET and controller or RCC switching converter solution, the FSD200 FSD200 and FSD210 FSD210 reduce total component count, design size, weight and at the same time increase efficiency, productivity, and system reliability. The FSD200 FSD200 eliminates the need for an auxiliary bias winding at a small cost of increased supply power. Both devices are a basic platform well suited for cost effective designs of flyback converters. AC IN DC OUT Vstr Drain PWM Vfb Vcc Source Figure 1. Typical Flyback Application using FSD210 FSD210 AC IN DC OUT Vstr Drain PWM Vfb Vcc Source Figure 2. Typical Flyback Application using FSD200 FSD200 FPSTM is a trademark of Fairchild Semiconductor Corporation. ©2005 Fairchild Semiconductor Corporation Rev.1.0.4 FSD210 FSD210, FSD200 FSD200 Internal Block Diagram Vstr 8 L Vcc 5 Voltage Ref UVLO Internal Bias 7 Drain H 8.7/6.7V Frequency Modulation 5uA Vck OSC SFET DRIVER 250uA S Vfb 4 Q R BURST V BURST LEB OLP Reset Iover S V SD Rsense Vth Q R TSD S/S 3mS A/R GND 1, 2, 3 Figure 3. Functional Block Diagram of FSD210 FSD210 Vstr 8 Vcc 5 HV/REG UVLO 7V Frequency Modulation 5uA Voltage Ref. 7 Drain ON/OFF INTERNAL BIAS Vck OSC SFET DRIVER 250uA S Vfb 4 Q R BURST V BURST LEB Iover OLP Reset S V SD R TSD A/R Q Rsense Vth S/S 3mS 1, 2, 3 Figure 4. Functional Block Diagram of FSD200 FSD200 showing internal high voltage regulator 2 GND FSD210 FSD210, FSD200 FSD200 Pin Definitions Pin Number Pin Name 1, 2, 3 GND 4 5 7 8 Pin Function Description Sense FET source terminal on primary side and internal control ground. Vfb The feedback voltage pin is the inverting input to the PWM comparator with nominal input levels between 0.5Vand 2.5V. It has a 0.25mA current source connected internally while a capacitor and opto coupler are typically connected externally. A feedback voltage of 4V triggers overload protection (OLP). There is a time delay while charging between 3V and 4V using an internal 5uA current source, which prevents false triggering under transient conditions but still allows the protection mechanism to operate under true overload conditions. Vcc FSD210 FSD210 Positive supply voltage input. Although connected to an auxiliary transformer winding, current is supplied from pin 8 (Vstr) via an internal switch during startup (see Internal Block Diagram section). It is not until Vcc reaches the UVLO upper threshold (8.7V) that the internal start-up switch opens and device power is supplied via the auxiliary transformer winding. FSD200 FSD200 This pin is connected to a storage capacitor. A high voltage regulator connected between pin 8 (Vstr) and this pin, provides the supply voltage to the FSD200 FSD200 at startup and when switching during normal operation. The FSD200 FSD200 eliminates the need for auxiliary bias winding and associated external components. Drain The Drain pin is designed to connect directly to the primary lead of the transformer and is capable of switching a maximum of 700V. Minimizing the length of the trace connecting this pin to the transformer will decrease leakage inductance. Vstr The startup pin connects directly to the rectified AC line voltage source for both the FSD200 FSD200 and FSD210 FSD210. For the FSD210 FSD210, at start up the internal switch supplies internal bias and charges an external storage capacitor placed between the Vcc pin and ground. Once this reaches 8.7V, the internal current source is disabled. For the FSD200 FSD200, an internal high voltage regulator provides a constant supply voltage. Pin Configuration 7-DIP GND 1 8 Vstr GND 2 7 Drain GND 3 Vfb 4 5 Vcc Figure 5. Pin Configuration (Top View) 3 FSD210 FSD210, FSD200 FSD200 Absolute Maximum Ratings (Ta=25°C unless otherwise specified) Parameter Symbol Value Unit Maximum Supply Voltage (FSD200 FSD200) VCC,MAX 10 V Maximum Supply Voltage (FSD210 FSD210) VCC,MAX 20 V VFB -0.3 to VSTOP V Input Voltage Range Operating Junction Temperature. TJ +150 °C Operating Ambient Temperature TA -25 to +85 °C TSTG -55 to +150 °C Symbol Value Unit JA(1) JA(1) JC(2) 74.07(3) °C/W (4) °C/W Storage Temperature Range Thermal Impedance Parameter 7DIP Junction-to-Ambient Thermal Junction-to-Case Thermal Note: 1. Free standing without heat sink. 2. Measured on the GND pin close to plastic interface. 3. Soldered to 100mm2 copper clad. 4. Soldered to 300mm2 copper clad. 4 60.44 22.00 °C/W FSD210 FSD210, FSD200 FSD200 Electrical Characteristics (Ta=25°C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit 700 - - V Sense FET SECTION Drain-Source Breakdown Voltage BVDSS Startup Voltage (Vstr) Breakdown VCC = 0V, ID = 100µA BVSTR Off-State Current IDSS On-State Resistance RDS(ON) 700 - - V VDS = 560V - - 100 µA Tj = 25°C, ID = 25mA - 28 32 Tj = 100°C, ID = 25mA - 42 48 Rise Time TR VDS = 325V, ID = 50mA - 100 - ns Fall Time TF VDS = 325V, lD = 25mA - 50 - ns CONTROL SECTION Output Frequency FOSC Tj = 25°C 126 134 142 kHz Output Frequency Modulation FMOD Tj = 25°C - ±4 - kHz IFB Vfb = 0V 0.22 0.25 0.28 mA Feedback Source Current Maximum Duty Cycle DMAX Vfb = 3.5V 60 65 70 % Minimum Duty Cycle DMIN Vfb = 0V 0 0 0 % 6.3 7 7.7 V 5.3 6 6.7 V 8.0 8.7 9.4 V 6.0 6.7 7.4 V - 7 - V TS/S - 3 - ms VBURH 0.58 0.64 0.7 V VSTART UVLO Threshold Voltage (FSD200 FSD200) VSTOP After turn on VSTART UVLO Threshold Voltage (FSD210 FSD210) VSTOP Supply Shunt Regulator (FSD200 FSD200) After turn on - VCCREG Internal Soft Start Time BURST MODE SECTION 0.5 0.58 0.64 V Hysteresis VBURL Burst Mode Voltage Tj = 25°C - 60 - mV IOVER 0.275 0.320 0.365 A - 220 - ns 125 145 160 °C 3.5 4.0 4.5 V 3 5 7 µA 200 - - ns PROTECTION SECTION Drain to Source Peak Current Limit(1) Current Limit Delay (2) TCLD Thermal Shutdown Temperature (Tj) Shutdown Feedback Voltage Feedback Shutdown Delay Current (3) Leading Edge Blanking Time (2) Tj = 25°C TSD - VSD IDELAY Vfb = 4.0V TLEB TOTAL DEVICE SECTION Operating Supply Current (FSD200 FSD200) IOP Vcc = 7V - 600 - µA Operating Supply Current (FSD210 FSD210) IOP Vcc = 11V - 700 - µA Start Up Current (FSD200 FSD200) ISTART Vcc = 0V - 1 1.2 mA Start Up Current (FSD210 FSD210) ISTART Vcc = 0V - 700 900 µA Vcc = 0V 20 - - V Vstr Supply Voltage Note: 1. Test current slope : di/dt = 150mA/us 2. These parameters, although guaranteed, are not 100% tested in production 3. This parameter is derived from characterization 5 FSD210 FSD210, FSD200 FSD200 Comparison Between FSDH565 FSDH565 and FSD210 FSD210 Function FSDH0565 FSDH0565 FSD210 FSD210 FSD210 FSD210 Advantages Soft-Start not applicable 3mS · Gradually increasing current limit during soft-start further reduces peak current and voltage component stresses · Eliminates external components used for soft-start in most applications · Reduces or eliminates output overshoot Switching Frequency 100kHz 134kHz · Smaller transformer Frequency Modulation ±4kHz · Reduced conducted EMI not applicable Yes-built into controller · Improve light load efficiency · Reduces no-load consumption · Transformer audible noise reduction Drain Creepage at Package 6 not applicable Burst Mode Operation 1.02mm 3.56mm DIP · Greater immunity to acting as a result of build-up of dust, debris and other contaminants FSD210 FSD210, FSD200 FSD200 Typical Performance Characteristics (These characteristic graphs are normalized at Ta=25) 1.0 Operating Current (A) 1.2 1.0 Fosc (kHz) 1.2 0.8 0.6 0.4 0.2 0.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 125 -25 Junction Temperature () 50 75 100 125 Operating Current vs. Temp 1.2 Feedback SOurce Current (A) 1.2 Peak Current Limit (A) 25 Junction Temperature () Frequency vs. Temp 1.0 0.8 0.6 0.4 0.2 0.0 -25 0 25 50 75 100 1.0 0.8 0.6 0.4 0.2 0.0 125 -25 Junction Temperature () 0 25 50 75 100 125 Junction Temperature () Peak Current Limit vs. Temp Feedback Source Current vs. Temp 1.20 1.00 1.00 0.80 0.80 Vstop (V) 1.20 Vstart (V) 0 0.60 0.40 0.20 0.60 0.40 0.20 0.00 0.00 -25 0 25 50 75 100 Junction Temperature () Vstart Voltage vs. Temp 125 -25 0 25 50 75 100 125 Junction Temperature () Vstop Voltage vs. Temp 7 FSD210 FSD210, FSD200 FSD200 Typical Performance Characteristics (Continued) (These characteristic graphs are normalized at Ta=25) 1.2 1.6 1.4 1.0 1.2 0.8 BVdss (V) On State Resistance () 1.8 1.0 0.8 0.6 0.4 0.2 0.6 0.4 0.2 0.0 0.0 -25 0 25 50 75 100 125 -25 0 25 50 75 100 Junction Temperature () On State Resistance vs. Temp Breakdown Voltage vs. Temp 1.2 1.0 1.0 0.8 0.8 VSD (V) Vcc Regulation Voltage (V) 1.2 0.6 0.4 0.6 0.4 0.2 0.2 0.0 0.0 -25 0 25 50 75 100 -25 125 Vcc Regulation Voltage vs. Temp (for FSD200 FSD200) 25 50 75 100 125 Shutdown Feedback Voltage vs. Temp 1.4 1.2 1.2 1.0 Istart (A) 1.0 Istart (A) 0 Junction Temperature () Junction Temperature () 0.8 0.6 0.4 0.8 0.6 0.4 0.2 0.2 0.0 0.0 -25 0 25 50 75 100 Junction Temperature () Start Up Current vs. Temp (for FSD210 FSD210) 8 125 Junction Temperature () 125 -25 0 25 50 75 100 Junction Temperature () Start Up Current vs. Temp (for FSD200 FSD200) 125 FSD210 FSD210, FSD200 FSD200 Functional Description Vin,dc 1. Startup : At startup, the internal high voltage current source supplies the internal bias and charges the external Vcc capacitor as shown in figure 7. In the case of the FSD210 FSD210, when Vcc reaches 8.7V the device starts switching and the internal high voltage current source is disabled (see figure 1). The device continues to switch provided that Vcc does not drop below 6.7V. For FSD210 FSD210, after startup, the bias is supplied from the auxiliary transformer winding. In the case of FSD200 FSD200, Vcc is continuously supplied from the external high voltage source and Vcc is regulated to 7V by an internal high voltage regulator (HVReg), thus eliminating the need for an auxiliary winding (see figure 2). Vin,dc Istr Vref FSD2xx Vcc Vcc must not drop to UVLO stop Vstr Vcc H 8.7V/ 6.7V J-FET UVLO Istr Vstr L Vstr i = Istr-max 100uA i = Istr-max 100uA Vcc max 100uA UVLO start Vin,dc Vcc Istr FSD210 FSD210 UVLO stop Auxiliary winding voltage HV Reg. 7V t FSD200 FSD200 Figure 6. Internal startup circuit Figure 7. Charging the Vcc capacitor through Vstr Calculating the Vcc capacitor is an important step to designing in the FSD200/210 FSD200/210. At initial start-up in both the FSD200/210 FSD200/210, the stand-by maximum current is 100uA, supplying current to UVLO and Vref Block. The charging current (i) of the Vcc capacitor is equal to Istr - 100uA. After Vcc reaches the UVLO start voltage only the bias winding supplies Vcc current to device. When the bias winding voltage is not sufficient, the Vcc level decreases to the UVLO stop voltage. At this time Vcc oscillates. In order to prevent this ripple it is recommended that the Vcc capacitor be sized between 10uF and 47uF. 3. Leading edge blanking (LEB) : At the instant the internal Sense FET is turned on, there usually exists a high current spike through the Sense FET, caused by the primary side capacitance and secondary side rectifier diode reverse recovery. Exceeding the pulse-by-pulse current limit could cause premature termination of the switching pulse (see Protection Section). To counter this effect, the FPS employs a leading edge blanking (LEB) circuit. This circuit inhibits the over current comparator for a short time (TLEB) after the Sense FET is turned on. 2. Feedback Control : The FSD200/210 FSD200/210 are both voltage mode devices as shown in Figure 8. Usually, a H11A817 H11A817 optocoupler and KA431 KA431 voltage reference (or a FOD2741 FOD2741 integrated optocoupler and voltage reference) are used to implement the isolated secondary feedback network. The feedback voltage is compared with an internally generated sawtooth waveform, directly controlling the duty cycle. When the KA431 KA431 reference pin voltage exceeds the internal reference voltage of 2.5V, the optocoupler LED current increases pulling down the feedback voltage and reducing the duty cycle. This event will occur when either the input voltage increases or the output load decreases. Vcc 5uA Vfb Vo OSC Vref 0.25mA Gate driver FB 4 Cfb R KA431 KA431 VSD OLP Figure 8. PWM and feedback circuit 4. Protection Circuit : The FSD200/210 FSD200/210 has 2 self protection functions: over load protection (OLP) and thermal shutdown (TSD). Because these protection circuits are fully integrated into the IC with no external components, system 9 FSD210 FSD210, FSD200 FSD200 reliability is improved without a cost increase. If either of these thresholds are triggered, the FPS starts an auto-restart cycle. Once the fault condition occurs, switching is terminated and the Sense FET remains off. This causes Vcc to fall. When Vcc reaches the UVLO stop voltage (6.7V:FSD210 FSD210, 6V:FSD200 FSD200), the protection is reset and the internal high voltage current source charges the Vcc capacitor. When Vcc reaches the UVLO start voltage (8.7V:FSD210 FSD210,7V:FSD200 FSD200), the device attempts to resume normal operation. If the fault condition is no longer present start up will be successful. If it is still present the cycle is repeated (see figure 10). to detect the temperature of the Sense FET. When the temperature exceeds approximately 145°C, thermal shutdown is activated. Vfb under Vstop of UVLO OLP 4V 3V FPS Switching Area Idelay (5uA) charges Cfb OSC IC Reset t 5uA 250uA Vfb 4 R Cfb S + - GATE DRIVER Q R 3V RESET Vth 4V TSD R A/R Q FSD2xx OLP, TSD Protection Block Figure 9. Protection block 4.1 Over Load Protection (OLP) : Over load protection occurs when the load current exceeds a pre-set level due to an abnormal situation. If this occurs, the protection circuit should be triggered to protect the SMPS. It is possible that a short term load transient can occur under normal operation. In order to avoid false shutdowns, the over load protection circuit is designed to trigger after a delay. Therefore the device can differentiate between transient over loads and true fault conditions. The maximum input power is limited using the pulse-by-pulse current limit feature. If the load tries to draw more than this, the output voltage will drop below its set value. This reduces the optocoupler LED current which in turn reduces the photo-transistor current (see figure 9). Therefore, the 250uA current source will charge the feedback pin capacitor, Cfb, and the feedback voltage, Vfb, will increase. The input to the feedback comparator is clamped at 3V. Once Vfb reaches 3V, the device switches at maximum power, the 250uA current source is blocked and the 5uA source continues to charge Cfb. Once Vfb reaches 4V, switching stops.and overload protection is triggered. The resultant shutdown delay time is set by the time required to charge Cfb from 3Vto 4Vwith 5uA as shown in Fig. 10. 4.2 Thermal Shutdown (TSD) : The Sense FET and the control IC are integrated, making it easier for the control IC t2 t3 t1