FS6219 ISO9001 - Datasheet Archive

 

Dual-VCXO/Triple-PLL Programmable Clock Generator IC AMERICAN MICROSYSTEMS, INC. Preliminary Information April 2000 1.0 Features

 

FS6219 FS6219 Dual-VCXO/Triple-PLL Programmable Clock Generator IC AMERICAN MICROSYSTEMS, INC. Preliminary Information April 2000 1.0 Features 2.0 · Two voltage-controlled crystal oscillators (VCXO) · Three fully programmable phase-locked loops (PLL) · · Three system clock frequency outputs 2 I C-bus serial interface · 3.3 volt operation (contact factory for 5 volt versions) · Compact 16-pin SOIC (0.150") package Figure 1: Pin Configuration XAO 1 16 XBO 2 15 XBI 3 14 XTUNEB SCL 4 13 VSS 12 CLKC FS6219 FS6219 XAI XTUNEA SDA 5 VDD 6 11 VDD ADDR 7 10 CLKB VSS 8 9 Description The FS6219 FS6219 is a monolithic CMOS clock generator IC designed to minimize cost and component count in digital video / audio systems. Two fully independent VCXOs permit accurate and simulaneous phase locking of the generated clocks to independent sources, such as satellite or cable delivered video and terrestrial broadcasts. Three fully independent, fully programmable PLLs with flexible post-dividers permit the generation of desired clock frequencies precisely, with no added "synthesis" errors. The FS6219 FS6219 makes use of the latest AMI PLL technology for low clock period jitter and low cumulative jitter. The ADDR pin permits two FS6219 FS6219 to be uniquely con2 trolled by a single I C bus. The full read/write slave capability of the FS6219 FS6219 allows all device programming to be completely verified. Contact factory for custom requirements. CLKA Figure 2: Device Block Diagram XTUNEA XAI Crystal XAO Oscillator "A" XBI Crystal XBO Oscillator "B" XTUNEB PLL "A" FXA FXB Source Select PLL "B" Post-Divider "B" Source Select FPLLA FPLLB PLL "C" FPLLC SCL Post-Divider "C" Source Select CLKB CLKC FXA I2C SDA CLKA Post-Divider "A" Interface (Read / Write Slave) FXB FS6219 FS6219 This document contains information on a preproduction product. Specifications and information herein are subject to change without notice. ISO9001 ISO9001 4.28.00 FS6219 FS6219 Dual-VCXO/Triple-PLL Programmable Clock Generator IC AMERICAN MICROSYSTEMS, INC. Preliminary Information April 2000 Table 1: Pin Descriptions Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin PIN TYPE NAME DESCRIPTION 1 AO XAO Crystal Oscillator "A" Drive 2 AI XAI Crystal Oscillator "A" Feedback 3 AI XTUNEA 4 DIU SCL 5 DIUO SDA Serial Interface Data Input/Output 6 P VDD Power Supply (+3.3V nominal) 7 DIU ADDR 8 P VSS 9 DO CLKA Clock Output "A" 10 DO CLKB Clock Output "B" 11 P VDD Power Supply (+3.3V nominal) 12 DO CLKC Clock Output "C" 13 P VSS 14 AI XTUNEB 15 AI XBI Crystal Oscillator "B" Feedback 16 AO XBO Crystal Oscillator "B" Drive Crystal Oscillator "A" Voltage Tuning Input Serial Interface Clock Input Serial Interface Address Select Ground Ground Crystal Oscillator "B" Voltage Tuning Input Note: When applying an external reference clock to the FS6219 FS6219, it should be capacitively coupled to the XAO or XBO pins. The XAI and/or XBI pins should be floating (no connection). FS6219 FS6219 VCXO Typical Characteristic 250 200 Deviation - ppm 150 100 50 0 0 0.5 1 1.5 2 2.5 3 -50 -100 -150 -200 V(XTUNE) - volts ISO9001 ISO9001 2 4.28.00 FS6219 FS6219 Dual-VCXO/Triple-PLL Programmable Clock Generator IC AMERICAN MICROSYSTEMS, INC. Preliminary Information April 2000 3.0 Programming Information Table 2: Register Map (Note: All Register Bits are cleared to zero on power-up.) ADDRESS BIT 7 BIT 6 BIT 5 BIT 4 BYTE 15 * * * * BYTE 14 * * * * BYTE 13 * * * * BYTE 12 * * * BIT 3 * BIT 2 BIT 1 BIT 0 * * * * TSCLK_C STOPCLK_C SRCCLK_C[2:0] TSCLK_B STOPCLK_B SRCCLK_B[2:0] TSCLK_A STOPCLK_A SRCCLK_A[2:0] BYTE 11 MODPOST_C[3:0] SRCPOST_C[2:0] BYTE 10 MODPOST_B[3:0] SRCPOST_B[2:0] BYTE 9 BYTE 8 MODPOST_A[3:0] SRCPLL_C[1:0] BYTE 7 PDPLL_C FBKDIV_C[2:0] A-Counter PDPLL_B LFTC_B CP_B FBKDIV_B[10:8] M-Counter FBKDIV_B[7:3] M-Counter FBKDIV_B[2:0] A-Counter BYTE 3 REFDIV_B[7:0] SRCPLL_A[1:0] BYTE 1 PDPLL_A LFTC_A CP_A FBKDIV_A[10:8] M-Counter FBKDIV_A[7:3] M-Counter FBKDIV_A[2:0] A-Counter BYTE 0 3.1 FBKDIV_C[10:8] M-Counter REFDIV_C[7:0] SRCPLL_B[1:0] BYTE 4 BYTE 2 CP_C FBKDIV_C[7:3] M-Counter BYTE 6 BYTE 5 SRCPOST_A[2:0] LFTC_C REFDIV_A[7:0] Control Bit Assignment Table 4: Divider Control Bits If any PLL control bit is altered during device operation, including those bits controlling the Reference and Feedback Dividers, the output frequency will slew smoothly (in a glitch-free manner) to the new frequency. The slew rate is related to the programmed charge pump current and loop filter time constant. However, any programming changes to any Mux or Post Divider control bits will cause a glitch on an operating clock output. NAME REFDIV_x[7:0] REFerence DIVider for PLL "x" (NR) FeedBacK DIVider for PLL "x" (NF) FBKDIV_x[10:0] FBKDIV_x[2:0] A-Counter Value FBKDIV_x[10:3] M-Counter Value Table 5: Post-Divider Control Bits NAME Table 3: PLL Power-Down Bits NAME DESCRIPTION DESCRIPTION MODPOST_x[3:0] DESCRIPTION Modulus for POST divider "x" (see Table 7: Post Divider Modulus) Power-Down PLL "x" PDPLL_x Bit = 0 Table 6: CLK Pin Stop Bit Power On Bit = 1 Power Off NAME DESCRIPTION CLK "x" Stop Bit STOPCLK_x ISO9001 ISO9001 Bit=0 Normal, CLK running Bit=1 CLK Stopped Low 3 4.28.00 FS6219 FS6219 Dual-VCXO/Triple-PLL Programmable Clock Generator IC AMERICAN MICROSYSTEMS, INC. Preliminary Information April 2000 Table 7: Post Divider Modulus Table 9: Post-Divider Source Select Bits BIT [3] BIT [2] BIT [1] BIT [0] DIVIDE BY 0 0 0 0 1 Post-Divider "x" Reference Source Select 0 0 0 1 2 Bit[2] Bit[1] Bit[0] 0 0 1 0 3 0 0 0 0 0 1 1 4 0 0 1 Reference Frequency B 0 1 0 0 5 0 1 0 PLL A Frequency 0 1 0 1 6 0 1 1 PLL B Frequency 0 1 1 0 8 1 0 0 PLL C Frequency 1 1 1 Shutdown Post-Divider 0 1 1 1 0 0 0 0 0 1 12 1 0 1 0 15 1 0 1 1 1 0 0 18 1 1 0 1 20 1 1 1 0 25 Reference Frequency A 16 1 DESCRIPTION 10 1 SRCPOST_x 9 1 NAME Table 10: CLK Pin Source Select Bits NAME DESCRIPTION CLK "x" Source Select 1 1 1 50 Table 8: PLL Reference Source Select Bits NAME PLL "A" Reference Source Select SRCPLL_A 0 0 1 0 1 TEST MODE DESCRIPTION 1 PLL C Frequency Bit[1] 0 Reference Frequency A 0 1 Reference Frequency B 1 0 PLL A Frequency 1 1 Normal, CLK enabled CLK Tri-Stated Table 12: PLL Tuning Bits Bit[0] 0 Bit=0 Bit=1 PLL B Frequency PLL "B" Reference Source Select PLL C Frequency NAME Bit[1] LFTC_x 0 1 0 PLL A Frequency 1 1 Time Constant = t.b.d. Reference Frequency B 1 Time Constant = t.b.d. Charge Pump Current for PLL"x" Reference Frequency A 0 Bit = 0 Bit = 1 Bit[0] 0 DESCRIPTION Loop Filter Time Constant for PLL "x" PLL "C" Reference Source Select ISO9001 ISO9001 Post-Divider "C" CLK "x" Source Select TSCLK_x Reference Frequency B 1 SRCPLL_C Post-Divider "B" 0 NAME Reference Frequency A 1 SRCPLL_B Post-Divider "A" 1 Bit[0] 0 0 0 Table 11: CLK Pin Tri-State Bit DESCRIPTION Bit[1] 0 1 SRCCLK_x Bit[0] 1 1 Bit[1] PLL B Frequency CP_x Bit = 0 Current = t.b.d. Bit = 1 Current = t.b.d. 4 4.28.00 FS6219 FS6219 Dual-VCXO/Triple-PLL Programmable Clock Generator IC AMERICAN MICROSYSTEMS, INC. Preliminary Information April 2000 4.0 Electrical Specifications Table 13: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER SYMBOL Supply Voltage (VSS = ground) MIN. MAX. UNITS VDD VSS-0.5 7 V Input Voltage, dc VI VSS-0.5 VDD+0.5 V Output Voltage, dc VO VSS-0.5 VDD+0.5 V Input Clamp Current, dc (VI < 0 or VI > VDD) IIK -50 50 mA Output Clamp Current, dc (VI < 0 or VI > VDD) IOK -50 50 mA Storage Temperature Range (non-condensing) TS -65 150 °C Ambient Temperature Range, Under Bias TA -55 125 °C Junction Temperature TJ 125 °C Lead Temperature (soldering, 10s) 260 °C 2 Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) kV CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 14: Operating Conditions PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS 3.3 3.6 V 70 °C 18 MHz Supply Voltage (3.3 volt system) VDD 3.0 Ambient Operating Temperature Range TA 0 Crystal Resonator Frequency ISO9001 ISO9001 fXTAL Fundamental Mode 5 13.5 5 4.28.00 FS6219 FS6219 Dual-VCXO/Triple-PLL Programmable Clock Generator IC AMERICAN MICROSYSTEMS, INC. Preliminary Information April 2000 Table 15: DC Electrical Specifications Unless otherwise stated, VDD = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3 f rom typical. Negative currents indicate current flows out of the device. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Overall Supply Current, Dynamic, with Loaded Outputs IDD mA Voltage Controlled Crystal Oscillator Crystal Loading Capacitance CL(xtal) Crystal Resonator Motional Capacitance As seen by a crystal connected to XIN and XOUT (@ VXTUNE = 1.5V) PURCHASE CRYSTAL TO THIS VALUE of CLOAD C1(xtal) VCXO Tuning Range 20 25 fF 0 Active tuning range fXTAL = 13.5MHz; CL(xtal) = 20pF; C1(xtal) = 25fF Crystal Frequency Change pF 3 V 300 VXTUNE = 0 to 3 V ppm VCXO Tuning Characteristic Note: positive delta F for positive delta V 100 ppm/V Crystal Drive Level RXTAL=20; CL = 20pF 200 uW Clock Outputs (CLKA, CLKB, CLKC) High-Level Output Source Current* IOH VO = 2.0V -40 mA Low-Level Output Sink Current * IOL VO = 0.4V 17 mA zOH VO = 0.1VDD; output driving high 25 zOL VO = 0.1VDD; output driving low 25 Short Circuit Source Current * IOSH VO = 0V; shorted for 30s, max. -55 mA Short Circuit Sink Current * IOSL VO = 3.3V; shorted for 30s, max. 55 mA Output Impedance * Table 16: AC Timing Specifications Unless otherwise stated, VDD = 3.3V ± 5%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not production tested to any specific limits. Where given, MIN and MAX characterization data are ± 3 f rom typical. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS 55 % Clock Outputs (CLKA, CLKB, CLKC) Ratio of high pulse width (as measured from rising edge to next falling edge at 1.4V) to one clock period Duty Cycle * 45 Rise Time * tr VDD = 3.3V; VO = 0.3V to 3.0V; CL = 15pF 1.7 ns Fall Time * tf VDD = 3.3V; VO = 3.0V to 0.3V; CL = 15pF 1.7 ns ISO9001 ISO9001 6 4.28.00 FS6219 FS6219 Dual-VCXO/Triple-PLL Programmable Clock Generator IC AMERICAN MICROSYSTEMS, INC. Preliminary Information April 2000 5.0 Package Information Table 17: 16-pin SOIC (0.150") Package Dimensions DIMENSIONS INCHES 16 MILLIMETERS MIN. MAX. MIN. MAX. A 0.061 0.068 1.55 1.73 A1 0.004 0.0098 0.102 0.249 A2 0.055 0.061 1.40 1.55 R B 0.013 0.019 0.33 0.0075 0.0098 0.191 0.249 D 0.386 0.393 9.80 9.98 E 0.150 0.157 3.81 3.99 H 0.49 C E AMERICAN MICROSYSTEMS, INC. e 0.050 BSC 1 ALL RADII: 0.005" TO 0.01" B 1.27 BSC H 0.230 0.244 5.84 0.010 0.016 0.25 0.41 L 0.016 0.035 0.41 0° 8° 0° 8° 7° typ. A C 0.89 A2 6.20 h h x 45° e D A1 BASE PLANE L SEATING PLANE Table 18: 16-pin SOIC (0.150") Package Characteristics PARAMETER SYMBOL CONDITIONS/DESCRIPTION TYP. UNITS Air flow = 0 m/s 110 °C/W Corner lead 4.0 Center lead 3.0 Thermal Impedance, Junction to Free-Air 16-pin 0.150" SOIC JA Lead Inductance, Self L11 Lead Inductance, Mutual L12 Any lead to any adjacent lead 0.4 nH Lead Capacitance, Bulk C11 Any lead to VSS 0.5 pF ISO9001 ISO9001 nH 7 4.28.00 FS6219 FS6219 Dual-VCXO/Triple-PLL Programmable Clock Generator IC AMERICAN MICROSYSTEMS, INC. Preliminary Information 6.0 April 2000 Ordering Information Table 19: Device Ordering Codes DEVICE NUMBER ORDERING CODE PACKAGE TYPE OPERATING TEMPERATURE RANGE SHIPPING CONFIGURATION FS6219 FS6219 12025-801 16-pin (0.150") SOIC (Small Outline Package) 0° C to 70° C (Commercial) Tape and Reel 7.0 Revision Information DATE PAGE 4/27/00 5-8 DESCRIPTION Fixed formatting errors 2 Purchase of I C components of American Microsystems, Inc., or one of its sublicensed Associated Compa2 2 nies conveys a license under Philips I C Patent Rights to use these components in an I C system, provided 2 that the system conforms to the I C Standard Specification as defined by Philips. Copyright © 2000 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com ISO9001 ISO9001 8 4.28.00