NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: XilinxFPGAADI www.analog.com/power 2 | XilinxFPGAADI Xilinx FPGA Virtex-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 (LDO) Virtex-5 Virtex-5Q . . . . . . . , . . . 15 LDO FPGA(3 Virtex®-61.0 V)I/O LDO ADIsimPo werTM BO M I / O ADIsimPowerI/OBOMwww. analog.com/ADIsimPower www.analog.com/power Virtex-6 1.0 V (0.9 V ... | Original |
16 pages, |
FPGA Virtex 6 ADP1613 ADP1710 ADP1711 ADP1712 ADP1713 ADP1714 ADP1715 ADP1716 ADP2108 ADP130 datasheet abstract |
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| Abstract: Virtex-6 FPGA Configuration User Guide UG360 UG360 (v3.2) November 1, 2010 Xilinx is disclosing , Virtex-6 FPGA Configuration User Guide www.xilinx.com UG360 UG360 (v3.2) November 1, 2010 Revision , TAPs; and in the new Step 6, changed 12 to 2000 times. Virtex-6 FPGA Configuration User Guide , www.xilinx.com Virtex-6 FPGA Configuration User Guide Date Version Revision 07/30/10 3.1 , Virtex-6 FPGA Configuration User Guide www.xilinx.com UG360 UG360 (v3.2) November 1, 2010 Date ... | Original |
180 pages, |
XCF128X flash J3F fpga radiation frame_ecc icap datasheet and pin diagram of IC 7491 spi flash parallel port spi flash programmer schematic XAPP951 XAPP899 virtex GTH VIRTEX-6 UG373 M25P128 UG360 UG360 abstract |
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| Abstract: Virtex-6 FPGA Configuration User Guide UG360 UG360 (v3.0) January 18, 2010 Xilinx is disclosing , Virtex-6 FPGA Configuration User Guide www.xilinx.com UG360 UG360 (v3.0) January 18, 2010 Revision , TAPs; and in the new Step 6, changed 12 to 2000 times. Virtex-6 FPGA Configuration User Guide , www.xilinx.com Virtex-6 FPGA Configuration User Guide Virtex-6 FPGA Configuration User Guide , . . . . . . . . . . . . Virtex-6 FPGA Configuration User Guide UG360 UG360 (v3.0) January 18, 2010 ... | Original |
174 pages, |
BGA LX760 fpga radiation spi flash programmer schematic UG360 XAPP951 XC6VLX760 XC6VSX475T UG628 FPGA Virtex 6 xcf128x UG360 abstract |
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| Abstract: Virtex-6 FPGA Configuration User Guide [optional] UG360 UG360 (v1.0) June 24, 2009 [optional , Revision Initial Xilinx release. Virtex-6 FPGA Configuration User Guide www.xilinx.com UG360 UG360 , . . . . . . . . . . . . Virtex-6 FPGA Configuration User Guide UG360 UG360 (v1.0) June 24, 2009 , Virtex-6 FPGA Configuration User Guide UG360 UG360 (v1.0) June 24, 2009 Bitstream Overview . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Virtex-6 FPGA Configuration User ... | Original |
166 pages, |
XILINX/FPGA Virtex 6 fpga radiation spi flash parallel port UG360 UG438 UG628 virtex 6 XCF128X XC6VLX760 XAPP973 VIRTEX-6 UG360 DSP48E1 XAPP974 UG360 abstract |
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| Abstract: Platform Flash PROM (1) FPGA Virtex-6 FPGAs XC6VLX75T XC6VLX75T XCF32P XCF32P XC6VLX130T XC6VLX130T XCF128X XCF128X(2) or , XC6VLX365T XC6VLX365T XCF128X XCF128X(2) or XCF32P XCF32P+XCF32P XCF32P+XCF32P XCF32P XC6VLX550T XC6VLX550T See UG360 UG360, Virtex-6 FPGA Configuration User Guide for BPI flash. XC6VLX760 XC6VLX760 See UG360 UG360, Virtex-6 FPGA Configuration User Guide for BPI flash. , XC6VHX380T XC6VHX380T XCF128X XCF128X(2) XC6VHX565T XC6VHX565T See UG360 UG360, Virtex-6 FPGA Configuration User Guide for BPI flash. XC6VSX315T XC6VSX315T XCF128X XCF128X(2) XC6VSX475T XC6VSX475T See UG360 UG360, Virtex-6 FPGA Configuration User Guide for BPI flash. ... | Original |
102 pages, |
XC6VLX130T stapl for xcf128x XC6VSX475T XCF01S XCF02S XCF02S pcb XCF04S XCF08P spartan6 jtag instruction XCF16P UG161 virtex 6 XC6VSX475T xc6slx75 XCF32P UG161 abstract |
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| Abstract: XC2VP100 XC2VP100 Note: For Virtex®-6 FPGA EasyPath offerings contact you local Xilinx Sales Representative. , R e -sp in R isk N o ne M ed ium H igh U n it P rice Note: For Virtex-6 FPGA EasyPath , to volume production with the flexibility to revert back to the standard Virtex® FPGA if system , , timing, as their standard FPGA counterparts. Virtex-5 Virtex-4 Virtex-II Pro LX LXT SXT , production now. Customers can also begin their Virtex-5 SXT, FXT and TXT FPGA designs and migrate to ... | Original |
3 pages, |
xilinx silicon device XC4VLX40 XC4VSX35 XC5VLX220 XC5VLX330 XC5VLX85T XC5VTX150T EasyPath XC5VLX220T XC4VSX55 XC4VFX40 FPGA Virtex 6 LXT XC5VTX240T datasheet abstract |
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| Abstract: OptiPHYF10G(M29730 M29730) SPI-4 Phase 2 SONET Virtex®-II FPGA PL4 SPI-4 Phase 2 Xilinx FPGA SONET Xilinx Virtex®-II FPGA OC-192 OC-192 OC-48 OC-48 OC-192/4xOC-48 SONET/SDH (M29730 M29730) OIF SPI-4 Phase 2 Packet-over-SONET Ail Mesri Xilinx Virtex®-II FPGA, SPI-4 Phase 2 OC-192 OC-192 iScaleTM IC Xilinx Virtex®-II FPGA PL4 terabit Xilinx IP Mark Aaldering Xilinx PL4 OC-192 OC-192 Xilinx PL4 Virtex-II FPGA System IO SystemIO (I/O ... | Original |
3 pages, |
xilinx STM-64 M29730 OC-192 OC-48 OC-192/ OC-48/STM-16 OC-192 abstract |
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| Abstract: Virtex-5 FPGA Stratix III Xilinx CCINT V V CCAUX CCO V Xilinx FPGA I/O ICCINTMIN AUXMIN ICCOMIN I LM1771 LM1771 PWM3 / LM3880 LM3880 FPGA FPGAXilinx Virtex-5Altera Stratix III 2 , FPGA I/O DCAC 30% TSOP-6FET SO-8 FETI/O TSOP-6 FET SO-8 FET -1AB LM388030ms , : Virtex-5 FPGA Figure 5: ; VIN = 5.0V � National Semiconductor Corporation, 2008. National , ANALOG edge FPGA Application Note AN-1677 AN-1677 Tim Hegarty, Applications Engineer FPGA ... | Original |
3 pages, |
Si3867DV Si3460DV LM3880 LM1771 lm17 Xilinx analog comparator AN-1677 M1771M AN-1677 abstract |
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| Abstract: New Products - Virtex Development Board Stackable Virtex FPGA For General Use Board A new , single unit. Virtex FPGA XCV800-HQ240 XCV800-HQ240 Header Connector 2x50pol. 2 Quarz Oscillators with , the FPGA Board Module Key Features The heart of the board is a Virtex FPGA in an HQ-240 HQ-240 package , functional diagram detailing the building blocks of the Virtex FPGA board is shown in figure 1. The board is very well suited to: · Evaluate the larger members of the Virtex FPGA family. · Implement ... | Original |
2 pages, |
XCV800 quarz crystal Quarz FPGA Virtex 6 FPGA boards dipswitch 8 datasheet abstract |
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| Abstract: Avnet Product Brief Xilinx® Virtex-4TM LX Evaluation Kit Features: FPGA - Xilinx XC4VLX25-FF668 XC4VLX25-FF668 or XC4VLX60-FF668 XC4VLX60-FF668 Virtex-4 FPGA I/O Peripherals - 128x64 OSRAM graphical display - AvBus , platform to develop and test designs targeted to the revolutionary Xilinx Virtex-4 Platform FPGA family. , - Micron 32 MB DDR SDRAM - 8 MB FLASH - Xilinx platform FLASH Communication Xilinx Virtex-4 LX Evaluation Kit - RS-232 RS-232 serial port The Xilinx Virtex-4 LX Evaluation Kit provides a ... | Original |
2 pages, |
,national semiconductor Linear ADS-XLX-V4LX-EVL25 CY7C68013 xilinx jtag cable DP83847 LM2704 LP2995M PT5401A ethernet xilinx vhdl vhdl code for lcd display VHDL code of lcd display Xilinx lcd display controller design XC4VLX60-FF668 XC4VLX25-FF668 XC4VLX60-FF668 XC4VLX25-FF668 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
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| Xilinx Answer #6236 : FPGA Express 3.1: Virtex: May not always infer the MUXF5 / MUXF6 : FPGA Express 3.1: Virtex: May not always infer the MUXF5 / MUXF6 Problem Description !!! -> Answers Database FPGA Express 3.1: Virtex: May not always infer the MUXF5 / MUXF6 Record #6236 Product Family: Software ) has the ability to infer the MUXF5, but not the MUXF6. FPGA Express 3.2 (Foundation Express 2.1i www.datasheetarchive.com/files/xilinx/docs/rp0001a/rp01a42.htm |
Xilinx | 29/02/2000 | 4.62 Kb | HTM | rp01a42.htm |
| JDF G // Created by Project Navigator ver 1.0 PROJECT vidag DESIGN vidag DEVFAM virtex2p DEVFAMTIME 0 DEVICE xc2vp20 DEVICETIME 1091041853 DEVPKG ff1152 DEVPKGTIME 1091041853 DEVSPEED -6 DEVSPEEDTIME GENERATEDSIMULATIONMODELTIME 0 SOURCE ./code/fpga_top.v SOURCE ./code/trxfull.v SOURCE ./code/loopback5.v SOURCE ./code /tx_sdr_16d_4to1_left.v DEPASSOC fpga_top ./ml10g_tester.ucf [Normal] p_ngdbuild_otherCmdLineOptions=xstvlg, virtex2p, Verilog.t_ngdbuild, 1091044744, -aul p_xstBusDelimiter=xstvlg, virtex2p, Verilog www.datasheetarchive.com/download/38645452-995988ZC/xapp543.zip (vidag.npl) |
Xilinx | 21/09/2004 | 1785.68 Kb | ZIP | xapp543.zip |
| Xilinx Answer #8572 : 2.1i Virtex-E Map - Map outputs incorrect message when processing invalid Virtex LOC constraints. Answers Database 2.1i Virtex-E Map - Map outputs incorrect message when processing invalid Virtex LOC constraints. Record #8572 Product Family: Software Product Line: FPGA Implementation Product Part: map Product www.datasheetarchive.com/files/xilinx/docs/rp0001e/rp01e6d.htm |
Xilinx | 29/02/2000 | 4.78 Kb | HTM | rp01e6d.htm |
| library "VIRTEX-parts" { fpga_library_version : "v1.0.0"; fpga_default_part : "V300PQ240 V300PQ240 V300PQ240 V300PQ240 ; fpga_valid_speed_grades : ["-4" "-5" "-6"]; fpga_num_rows : 16 ; fpga_num_cols : 24 _valid_speed_grades : ["-4" "-5" "-6"]; fpga_num_rows : 16 ; fpga_num_cols : 24 ; fpga_num_ffs : 1824 ; } design "V100PQ240 V100PQ240 V100PQ240 V100PQ240" { read_only : 1; fpga_valid_speed_grades : ["-4" "-5" "-6 BG256 BG256 BG256 BG256" { read_only : 1; fpga_valid_speed_grades : ["-4" "-5" "-6"]; fpga www.datasheetarchive.com/download/87862986-986968ZC/wcd02dc7.zip (VIRTEX.pts) |
Xilinx | 12/02/1999 | 4.99 Kb | ZIP | wcd02dc7.zip |
| Description: When an SRL16 SRL16 SRL16 SRL16 or SRL16E SRL16E SRL16E SRL16E component is instantiated in a Virtex design in FPGA Express, the Xilinx Answer #7812 : FPGA Express 3.x: Address lines unconnected when SRL16 SRL16 SRL16 SRL16 components are instantiated (FPGA-CHECK-7) Answers Database FPGA Express 3.x: Address lines unconnected when SRL16 SRL16 SRL16 SRL16 components are instantiated (FPGA-CHECK-7) Record #7812 www.datasheetarchive.com/files/xilinx/docs/rp0001d/rp01d6a.htm |
Xilinx | 29/02/2000 | 5.11 Kb | HTM | rp01d6a.htm |
| = PCI32/64 PCI32/64 PCI32/64 PCI32/64 Virtex FPGA Compiler 1998.08/VHDL 08/VHDL 08/VHDL 08/VHDL M2.1i VSS 1998.08 PCI32/64 PCI32/64 PCI32/64 PCI32/64 Virtex FPGA Compiler 1998.08/Verilog M2.1i Verilog-XL 2.6.10 - PCI32/64 PCI32/64 PCI32/64 PCI32/64 Virtex FPGA Express 3.1/VHDL M2.1i MTI PE/Plus 5.2e PCI32/64 PCI32/64 PCI32/64 PCI32/64 Virtex FPGA - PCI32/64 PCI32/64 PCI32/64 PCI32/64 Virtex FPGA Express 3.1/VHDL M2.1i Aldec ACTIVE-HDL PCI32/64 PCI32/64 PCI32/64 PCI32/64 Virtex FPGA XL FPGA Compiler 1998.08/Verilog M2.1i Verilog-XL 2.6 www.datasheetarchive.com/files/xilinx/docs/rp00008/rp00808.htm |
Xilinx | 29/02/2000 | 7.44 Kb | HTM | rp00808.htm |
| # Xilinx CORE Generator 6.1.02i; Cores Update # 2 # User = stevet Initializing default project. Loading plug-ins. All runtime messages will be recorded in # busformat=BusFormatAngleBracketNotRipped # designflow=VHDL # > # flowvendor=Foundation_iSE # formalverification=None # simulationoutputproducts=VHDL # xilinxfamily=Virtex2 # outputoption=DesignFlow # overwritefiles=Default # simvendor=ModelSim # > www.datasheetarchive.com/download/34963024-996029ZC/xapp685.zip (coregen.log) |
Xilinx | 09/01/2004 | 376.3 Kb | ZIP | xapp685.zip |
| # Xilinx CORE Generator 6.1.02i; Cores Update # 2 # User = stevet Initializing default project. Loading plug-ins. All runtime messages will be recorded in # busformat=BusFormatAngleBracketNotRipped # designflow=VHDL # > # flowvendor=Foundation_iSE # formalverification=None # simulationoutputproducts=VHDL # xilinxfamily=Virtex2 # outputoption=DesignFlow # overwritefiles=Default # simvendor=ModelSim # > www.datasheetarchive.com/download/34963024-996029ZC/xapp685.zip (coregen.log) |
Xilinx | 09/01/2004 | 376.3 Kb | ZIP | xapp685.zip |
| transmitter on a single Virtex-E FPGA suitable for point-to-point data transmission the SelectI/O in Virtex FPGAs to interface with external DDR SDRAMs at 100MHz (1.6 A synthesizable, auto-place-and-route 200 MHz ZBT SRAM interface in the Virtex FPGA -placed-and-routed synchronous DRAM controller in the Virtex FPGA family. A 32-bit wide data interace version can run up to 125 MHz when automatically placed and routed in a Virtex -6 speed grade. Hand www.datasheetarchive.com/files/xilinx/docs/rp00003/rp003b9.htm |
Xilinx | 06/03/2000 | 20.26 Kb | HTM | rp003b9.htm |
| , -6 -4, -5, -6 -4, -5, -6 -4, -5, -6 Return to Virtex-Redefining the FPGA | Product Overview Cover | Corporate Overview | Virtex-Redefining the FPGA | | CPLDs - A New Xilinx: Virtex-Redefining the FPGA Virtex Family ,700 3,888 5,292 6,912 10,800 15,552 21,168 27,648 Block RAM www.datasheetarchive.com/files/xilinx/docs/wcd0004a/wcd04ae6.htm |
Xilinx | 16/02/1999 | 18.02 Kb | HTM | wcd04ae6.htm |