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HFA1100IB Intersil Corporation VIDEO AMPLIFIER, PDSO8 visit Intersil
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FPGA "video wall"

Catalog Datasheet MFG & Type PDF Document Tags

40 pins led screen LVDS

Abstract: FPGA "video wall" Maxim > App Notes > Display Drivers Keywords: video display board, low cost FPGA, LED driver , LED-based video-display board that is used with a low-cost, medium-size FPGA chip. Introduction Roughly , design's new architecture uses a combination of one inexpensive FPGA chip for the digital video bit , each other on different PCBs inside each video brick. Also included on the LED-driver PCB are an FPGA , LED video-display board can be constructed with the help of a lowcost, medium-size FPGA chip. The
Maxim Integrated Products
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lcmxo2-1200

Abstract: LCMXO2-4000 2 W O LD NE hXALL P acO-IT MTHE D Product Selector Guide November 2010 FPGA · CPLD · , . 4 FPGA Products. 6 CPLD , , development kits and evaluation boards. FPGA, PLD and Mixed Signal Products Lattice FPGA (Field Programmable Gate Array) solutions deliver unique features, low power, and excellent value for FPGA designs , download a logic configuration to our FPGA devices, while PAC-Designer software is used in the design of
Lattice Semiconductor
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matlab code for radix-4 fft

Abstract: matlab code for half adder . Accordingly, FPGA vendors are beginning to include hard multipliers and DSP blocks within their core silicon , functions that are optimized for the FPGA architecture. Altera's Total 28-nm DSP Portfolio The biggest challenge faced by FPGA vendors is in providing a complete DSP solution portfolio-one that not only , a radar design jointly developed by Altera and The MathWorks to be implemented in an Stratix V FPGA , code and a bitstream were generated for the Stratix V FPGA. The timing constraints (in this case, fMAX
Altera
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UG130

Abstract: written Spartan-3 FPGA Starter Kit Board User Guide UG130 (v1.2) June 20, 2008 R R Xilinx is , portions reproduced by permission from Digilent, Inc. Spartan-3 FPGA Starter Kit Board User Guide UG130 , . 06/20/08 1.2 Corrected A1 pins in Table 2-2. Updated links. Spartan-3 FPGA Starter Kit Board , : FPGA Configuration Modes and Functions FPGA Configuration Mode Settings . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Spartan-3 FPGA Starter Kit Board
Xilinx
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XCF02SVO20C written XC3S200FT256 SPARTAN 3E STARTER BOARD DB15-VGA DB15 connector pin outs XILINX/SPARTAN 3E STARTER BOARD XC3S200-4FT256C IS61LV25616AL-10T MAX3232 ICL3232
Abstract: . . . . . . . . . 31 Chapter 7: RS-232 Port Chapter 8: Clock Sources Chapter 9: FPGA Configuration Modes and Functions FPGA Configuration Mode Settings . . . . . . . . . . . . . . . . . . . . . . , low-cost, easy-to-use development and evaluation platform for Spartan-3 FPGA designs. Key Components , components and features: â'¢ 200,000-gate Xilinx Spartan-3 XC3S200 FPGA in a 256-ball thin Ball Grid , available after FPGA configuration Jumper options allow FPGA application to read PROM data or FPGA Xilinx
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XC2064 XC3090 XC4005 XC5210

LC4256

Abstract: camera-link to HDMI converter PRODUCT SELECTOR GUIDE OCTOBER 2012 FPGA â'¢ CPLD â'¢ MIXED SIGNAL â'¢ INTELLECTUAL PROPERTY â , .4 â  FPGA â , â  FPGA and CPLD Design Software , affordably. Lattice FPGA solutions offer unique features, low power, and excellent value for FPGA designs , power iCE40â"¢ and MachXO2â"¢ FPGA families are ideal for applications ranging from glue logic and
Lattice Semiconductor
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LC4256 camera-link to HDMI converter I0211K

FTN256

Abstract: camera-link to SDI converter referred to as LatticeECP2/M, redefine the low-cost FPGA category. By integrating features and , expand the range of applications that can take advantage of low-cost FPGA products. Features that the LatticeECP2 family brings to the low cost FPGA category include high performance DSP blocks, up to 70 K LUT , LatticeECP2 also provides enhanced FPGA configuration options with features such as dual boot, bitstream , property of their respective owners. 2 FPGA Fabric Features and Capabilities · Low Cost FPGAs ·
Avnet Memec
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MICO32 FTN256 camera-link to SDI converter BP5867 camera-link to 3G-SDI converter Lattice ECP3 8 pin dip switch N-0680 PL-41-800 P-4400-335

schematic isp Cable lattice hw-dln-3c

Abstract: PRODUCT SELECTOR GUIDE APRIL 2012 FPGA â'¢ CPLD â'¢ MIXED SIGNAL â'¢ INTELLECTUAL PROPERTY â , .4 â  FPGA â , .14 â  Programming â  FPGA and , excellent service in order to succeed. FPGA, PLD and Mixed Signal Products Lattice FPGA (Field Programmable Gate Array) solutions offer unique features, low power, and excellent value for FPGA designs. We
Lattice Semiconductor
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schematic isp Cable lattice hw-dln-3c I0211F

TMS320C6713 DSK image processing

Abstract: motion ultrasound DOPPLER ), field-programmable gate array (FPGA), DSP or PC. 2.3 Front-End Processing Ultrasound image formation begins , systems have used a combination of ASIC, FPGA, DSP and PC for capturing and processing beamformed , Demod EDMA3 DDR2 ARM9 297 MHz VICP SCR EDMA3 Display SPI Beamformer FPGA , SDRC FPGA SCR Beamformer 32-Bit 162 MHz LPDDR DDR2 ADC McASP DAC AFE
Texas Instruments
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TMS320C6713 DSK image processing motion ultrasound DOPPLER SPRAB12 ultrasound transducer analog front end TMS320DM648 dsp application ultrasound doppler circuit SPRAB18A

VHDL code for dac

Abstract: 7-segment LED display 1 to 99 vhdl productbrief Xilinx SpartanTM-3 400 Evaluation Kit Enhance your engineering productivity and accelerate time to market with the Xilinx Spartan-3 Evaluation Kit from Avnet Design Services. The kit delivers a stable platform to develop and test designs targeted to the world's lowest cost per gate and lowest cost per I/O FPGA. The installed XC3S400 device offers a prototyping environment to effectively , Spartan-3 FPGA Xilinx platform FLASH configuration PROM 2 Oscillators (66 MHz installed & socket for use
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XC3S1500-FG456 ADS-XLX-SP3-EVL400 ADS-XLX-SP3-EVL1500 VHDL code for dac 7-segment LED display 1 to 99 vhdl SPARTAN-3 XC3S400 pin XC3S400 SPARTAN-3 BOARD xilinx vhdl rs232 code 50-pin lvds XC3S400-FG456 ADS-SP3-MB-EVL400 ADS-SP3-MB-EVL1500

DAC3283

Abstract: ADS62PXX the included FMC adapter boards, the EVMs are ideally suited for mating with a FPGA development board , standard FMC interconnect header. The FMC interconnect header is a typical input on the latest Xilinx FPGA , Figure 1 shows the configurations of the TSW4200-DAC and TSW4200-ADC EVM with the FPGA development board. Section 3 covers the setup information of the EVMs. FPGA Development Board LVDS Data OUT 6V Power , TCXO FPGA CLK Modulator Reference CLK CDCE62005 Ext. CLK J11 OSTR_CLK DAC_CLK TRF3720
Texas Instruments
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DAC3283 ADS62PXX FMC-ADC-ADAPTER TRF3704 Xilinx usb cable Schematic HSMC-ADC-BRIDGE SLWU071B TSW4200 ADS62P49

active noise cancellation for FPGA

Abstract: FPGA "video wall" with programmable logic, such as a focal-plane grid array (FPGA). This paper discusses how to use the , ADS1672 and an FPGA. ADS1672 FPGA MOD1[4:0] (ECL + AAF) MOD2[4:0] Figure 1. Flexible Data , MOD1[4:0] I/O MOD2[4:0] I/O FPGA/ Procesor ADS1672 Figure 4. Hardware Connections The processor (or FPGA) that captures the data must process the data through the error cancellation
Texas Instruments
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active noise cancellation for FPGA FPGA "video wall" SBAA159

FPGA "video wall"

Abstract: CS4954 WRRDA/D7:0 FPGA CTL Addr Data RESET- SDRAM PROGRAMMING ENABLE JUMPER Flash RESET , . 4 2.2.1 Changing a CS4954/5 or FPGA Register , . 9 Figure 6. FPGA , board's control FPGA, and display NTSC images stored in FLASH. When the CDB4954A/55A (Microsoft , ability to access some features of the on-board FPGA. A comprehensive online Help is included. 2.2.1
Cirrus Logic
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CS4954 CDB4954A CDB4955A CS4954-55 led full color screen fpga IBM PC AT schematics CS4954/55 RS232 10VDC

DB3 C531

Abstract: DB3 C502 LatticeECP2M LFE2M35-FF672 FPGA device. The stand-alone evaluation PCB provides a functional platform for , and DVB-ASI encoders and decoders into an FPGA. The evaluation board includes provisioning to , based on the FPGA array included on the board. The board has several debugging and analyzing features , in conjunction with evaluation design tutorials to demonstrate the LatticeECP2M FPGA. Figure 1 , Flash SMAs 75-ohm CH3 GS4911 CH1 VCO GS4915 FPGA I/O 27M Osc CH2 CFG
Lattice Semiconductor
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DB3 C531 DB3 C502 db3 c535 db3 c605 AE171 CS10-27.000MABJ-UT SMPTE292M SMPTE259M 1000PF-0402SMT

SMPTE checkfield pattern

Abstract: WFM700M Interface SD-SDI or HD-SDI Data GS1528 Cable Driver FPGA Figure 2. Pictorial Test Setup to , Data Control Interface Onboard FPGA Generating Color Bar Data Figure 9. Pictorial Test , Generated by GS1528 Cable Driver when Interfaced to HOTLink II Outputs while using an FPGA to Generate , using an FPGA to Generate SD-SDI Checkfield Data Jitter measured at GS1528 output (UI) SMPTE SPEC , GS1528 Cable Driver when Interfaced to HOTLink II Outputs while using an FPGA to Generate HD-SDI Color
Cypress Semiconductor
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SMPTE checkfield pattern WFM700M SDI pattern generator HOTLink WFM700 smpte rp 198 AN5004 8B/10B

544-1775-ND

Abstract: CYCLONE III EP3C25F324 FPGA Cyclone® II FPGA Starter Development Kit The low-cost Cyclone II FPGA Starter Development Kit is ideal , daughtercards) Cyclone II FPGA Starter Development kit CD-ROM: · Reference designs and demonstrations targets for the Cyclone II FPGA Starter Development Board · User manual · Reference guide · Quartus® II Web , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $150.00 Arria GX FPGA Development Kit The Arria GX FPGA Development Kit delivers a complete environment for the development and
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544-1775-ND CYCLONE III EP3C25F324 FPGA CYCLONE 3 ep3c25f324* FPGA excalibur APEX development board nios EP2C35F672 EP2C20F484C7N 7000S 7000B 544-2444-ND DK-DEV-3C120N

Digital Displays

Abstract: circuit on how to make a simple projector application. Figure 4 - FPGA utility in component integration Figure 3 illustrates how an FPGA-based , FPGA (illustrated in red) and associated logic between the A/D converter and existing system controller. In this design the FPGA serves as the I/O arbiter, accepting input from all three sources. In , of USB 2.0 and 802.11 however, the FPGA serves to manage these new interfaces completely, as well as , in the FPGA or with the assistance of an ASIC or ASSP as appropriate (illustrated by the combined
Xilinx
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Digital Displays circuit on how to make a simple projector plasma displays Display theory 802.11 USB FPGA-based LCD driver circuit

CLOCK RADIO schematic diagram

Abstract: . Notes on Interfacing with Xilinx 7-Series FPGA , for mating with a FPGA development board to evaluate the DAC and the ADC as a basic transmitter and , header. The FMC interconnect header is a typical input on the latest Xilinx FPGA EVMs. The TSW4200-DAC , configurations of the TSW4200-DAC and TSW4200-ADC EVM with the FPGA development board. Section 3 covers the setup information of the EVMs. FPGA Development Board LVDS Data OUT IN Wall Outlet 6V
Texas Instruments
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CLOCK RADIO schematic diagram SLWU071C ISO/TS16949

rca 2000h

Abstract: CS4954 and V sync). See Appendix A for a description. Note: Programming the FPGA to decode the SAV and EAV , Master EVB Control Registers (FPGA) User Flash EEPROM CSMON54 Table 1. Memory Map 2 Address 6000H , (Read/Write) Reserved 4K Parallel-Serial Fifo Data Register (Teletext Data) (Write-only) FPGA Version , interface for I/O1: Selects parallel interface for I/0 mode Enable 656-to-601 in FPGA (0 = 656, 1= 601 , (CS4954/53 only) CS4954/5 supply Video Clock source External video clock source Global Reset uP Clock FPGA
Cirrus Logic
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rca 2000h RCA RS-232 protocol CDB4954/5 SAB-C161 CDB4954 CDB4955 CS4952/3 CS4952

touch screen monitor

Abstract: FPT-1015 Instruments CVS-1454 compact vision system combines a high-performance processor with an onboard FPGA
National Instruments
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FPT-1015 touch screen monitor FPT 500 140 779572-01 BY307 vision builder to labview 2000/NT/XP NEMA4/IP65- CVS-145
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