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Part Manufacturer Description PDF & SAMPLES
CS2000P-DZZ Cirrus Logic Phase Locked Loop, Hybrid, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10
CS2000CP-DZZ Cirrus Logic PHASE LOCKED LOOP, 30MHz, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10
CS2000CP-CZZ Cirrus Logic PHASE LOCKED LOOP, 30MHz, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10
CS2000P-CZZ Cirrus Logic PHASE LOCKED LOOP, 30MHz, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10
CS2000P-CZZR Cirrus Logic PHASE LOCKED LOOP, 30MHz, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10
CS2000CP-CZZR Cirrus Logic Phase Locked Loop, Hybrid, PDSO10, 3 MM, LEAD FREE, MO-187, MSOP-10

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FOUR INPUT AND GATE

Catalog Datasheet MFG & Type PDF Document Tags
Abstract: 56 32 40 56 32 48 64 32 48 64 56 40 128 128 176 Three Input AND Gate l=A, B, C 0=AND Four Input AND Gate l=A, B, C, D 0=AND Two Input NAND/AND Gate l=A, B 0=NAND, AND Three Input NAND/AND Gate l=A, B, C 0=NAND, AND Four Input NAND/AND Gate l=A, B, C, D 0=NAND, AND Two Input OR Gate I=A, B 0=0R Three Input OR Gate l=A, B, C 0=0R Four Input OR Gate l=A, B, C, D 0=0R Two Input NOR/OR Gate l=A, B 0 =N 0R , Shifter 0 = 0U T l=A Two Input Decode Gate l=A,B O=N0R of A and NB Two Input AND Gate 0=AND l=A, B -
OCR Scan
SC3000 0NPA ua 8560
Abstract: main blocks of logic besides the AND gate, OR gate and INVERTER functions. The four blocks are "3 BIT , (discussed previously) a 3 input AND gate and a 4 input AND gate. There are three instantiations of this , counter (i.e. an increment for each frame) and is input to the shift register function. The four input , a part of figure 1. It contains one AND gate and one 2:1 MUX. In LOP operation, its functionality , with STS1 #2, the third instantiation decodes indications associated with STS1 #3. The three input AND PMC-Sierra
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PM5344 9508 PMC-950822
Abstract: opened or disconnected. The commutation truth table is shown in Figure 20. A four input AND gate is used , to stop before latching the enable input and the top drive AND gate low. To enabling the motor, the , Forward/Reverse and Brake Inputs (Pins 3, 23) High State Input Current (V|h = 5.0 V) Low State Input , phase motors and operate with two of the four most common conventions of sensor phasing. The MC33034P60 , shorted sensor line. When an invalid input condition exists, the Fault output is activated and the drive -
OCR Scan
MC33034 MC33034P120 commutation techniques of scr mps 724 mps 444 mps 1010 MC33034/D
Abstract: forward drop. 6. Input leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate inputs and the latch input. Dallas Semiconductor devices are built to the highest , controlled by the gate inputs and latch pin status. When the latch pin is logic 0, the gate input levels are , tained. When the latch input is returned to logic 0, the gate inputs again are inverted and passed to , Gate Inputs Latch Control LATCH VCc DESCRIPTION The DS1640 contains four P channel power MOS -
OCR Scan
DS1640/DS1640C 1640/D S1640C DS1640C
Abstract: capable of carrying 300 mA maximum at 200 mV forward drop. 6. Input leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate inputs and the latch input. Dallas , controlled by the latch input. The logic levels passed to the FET gates are controlled by the gate inputs and latch pin status. When the latch pin is logic 0, the gate input levels are inverted and passed di rectly , input is returned to logic 0, the gate inputs again are inverted and passed to the FET control gates -
OCR Scan
Abstract: . Input leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate , gate inputs and latch pin status. When the latch pin is logic 0, the gate input levels are inverted and , latch input is returned to logic 0, the gate inputs again are inverted and passed to the FET control , No Connection Gate Inputs Latch Control DESCRIPTION The DS1640 contains four P channel power MOS , logic and to operate a gate bias generator. 022698 1/4 DS1640/DS1640C OPERATION With +3 u +5 volts -
OCR Scan
Abstract: drop. 6. Input leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate inputs and the latch input. Dallas Semiconductor devices are built to the highest , input which is used to power internal logic and to operate a gate bias generator. 1 of 4 111999 , control gate (see Figure 1). A set of four internal latches is controlled by the latch input. The logic , pin is logic 0, the gate input levels are inverted and passed directly to the control gates, enabling Dallas Semiconductor
Original
Abstract: . Input leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate , +3 Û +5 volt power supply input which is used to power internal logic and to operate a gate bias , bias applied to the control gate (see Figure 1). A set of four internal latches is controlled by the latch input. The logic levels passed to the FET gates are controlled by the gate inputs and latch pin status. When the latch pin is logic 0, the gate input levels are inverted and passed directly to the Dallas Semiconductor
Original
Abstract: carrying 300 mA maximum at 200 mV forward drop. 6. Input leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate inputs and the latch input. Dallas , controlled by the gate inputs and latch pin status. When the latch pin is logic 0, the gate input levels are , tained. When the latch input is returned to logic 0, the gate inputs again are inverted and passed to , GATE1-GATE4 NC LATCH +3 to +5 Volt Input Ground FET Sources FET Drains FET Control Gates No Connection Gate -
OCR Scan
S1540C 1540/D 640/DS1 DS1G40C
Abstract: four gate inputs and the latch input only. 7. Applies to each of four gate inputs and the latch input , input which is used to power internal logic and to oper­ ate a gate bias generator. 021492 1/4 , input. The logic levels passed to the F ET gates are controlled by the gate inputs and latch pin status. When the latch pin is logic 0, the gate input levels are inverted and passed di­ rectly to the , input is returned to logic 0, the DS1640 BLOCK DIAGRAM gate inputs again are inverted and passed -
OCR Scan
Abstract: capable of carrying 300 mA maximum at 200 mV forward drop. 6. Input leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate Inputs and the latch input. Dallas , , the gate input levels are inverted and passed di­ rectly to the control gates, enabling the switches , the latch pin, the input levels present on the gate inputs are locked by the four internal latches , +3 to +5 Volt Input Ground FET Sources FET Drains FET Control Gates No Connection Gate Inputs -
OCR Scan
DS1640/D 1640C
Abstract: maximum at 200 mV forward drop. 6. Input leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate inputs and the latch input. Dallas Semiconductor devices are built , internal logic and to oper­ ate a gate bias generator. The DS1640 contains four P channel power MOS F , , the gate input levels are inverted and passed di­ rectly to the control gates, enabling the switches , the latch pin, the input levels present on the gate inputs are locked by the four internal latches -
OCR Scan
1640/DS
Abstract: four gate inputs and the latch input only. 7. Applies to each of four gate inputs and the latch input , -*- +5 volt power supply input which is used to power internal logic and to operate a gate bias , latch input. The logic levels passed to the FET gates are controlled by the gate Inputs and latch pin status. When the latch pin is logic 0, the gate input levels are inverted and passed directly to the , Input Ground FET Sources FET Drains FET Control Gates No Connection Gate Inputs Latch Control -
OCR Scan
D012 0Q12T71
Abstract: . Input leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate , gate (see Figure 1). A set of four internal latches is controlled by the latch input. The logic levels , logic 0, the gate input levels are inverted and passed directly to the control gates, enabling the , the latch pin, the input levels present on the gate inputs are locked by the four internal latches , Control Gates - No Connection - Gate Inputs Latch Control DESCRIPTION The DS1640 contains four P Dallas Semiconductor
Original
Abstract: forward drop. 6. Input leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate inputs and the latch input. Dallas Semiconductor devices are built to the highest , by the latch input. The logic levels passed to the FET gates are controlled by the gate inputs and latch pin status. When the latch pin is logic 0, the gate input levels are inverted and passed di rectly , input is returned to logic 0, the gate inputs again are inverted and passed to the FET control gates -
OCR Scan
power one 15 volt power supply
Abstract: carrying 300 mA maximum at 200 mV forward drop. 6. Input leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate inputs and the latch input. Dallas Semiconductor , , the gate input levels are inverted and passed directly to the control gates, enabling the switches to , latch pin, the input levels present on the gate inputs are locked by the four internal latches , Gate Inputs Latch Control DESCRIPTION The DS1640 contains four P channel power MOS FET's designed Dallas Semiconductor
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Low Input Capacitance MOS FET POWER FET DATA BOOK ttl logic gates 3 input or gate
Abstract: leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate inputs , gate (see Figure 1). A set of four internal latches is controlled by the latch input. The logic levels , logic 0, the gate input levels are inverted and passed directly to the control gates, enabling the , the latch pin, the input levels present on the gate inputs are locked by the four internal latches , Control Gates - No Connection - Gate Inputs Latch Control DESCRIPTION The DS1640 contains four P Dallas Semiconductor
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56-G5005-002A P16-2 56-G4009-001B DS1640S DS1640SN W16-3
Abstract: defined as a two input NAND or, in Atmel's library, a NAN2. A NAN2 uses four transistors. For each gate , , each gate array routing site contains four transistors, two NMOS and two PMOS. Transistors are , required for the design. A site is four transistors. Loads: Lists the number of unit loads the input , Timechk "D+CLK" denotes the Setup/ Hold requirement between inputs D and CLK. Gate Count Estimation , by having the upper gates tied off. For the INV2, all gates are used for the input, both upper and Atmel
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ATL35 nand gate layout ATL60
Abstract: below. · Enables arbitrary turn-on and turn-off sequencing of up to four power supplies (0.7V - 5V) The four channel ISL6123 (ENABLE input), ISL6124 (ENABLE# input) and ISL6125 ICs offer the designer 4 rail control when it is required that all four rails are in minimal compliance prior to turn on and , immediate and unconditional latch-off of all GATE outputs when driven low. This input can also be used to , cause RESET# to latch low and all four GATE outputs to follow the programmed turn off sequence similar Intersil
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ISL6126 ISL6127 ISL6128 ISL6123IR ISL6124IR ISL6125IR FN9005 TB389 ISO9000
Abstract: below. · Enables arbitrary turn-on and turn-off sequencing of up to four power supplies (0.7V - 5V) The four channel ISL6123 (ENABLE input), ISL6124 (ENABLE# input) and ISL6125 ICs offer the designer 4 , for each rail GATE C In contrast to the ISL6123 and ISL6124, with the ISL6126, each of the four , reference, and ENABLE# input is also satisfied the GATE for the associated UVLO input will turn-on. In turn , signaling ENABLE# high, this will cause RESET# to latch low and all four GATE outputs to follow the Intersil
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capacitor 47k 63v MO-220
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