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FOUR INPUT AND GATE

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Abstract: forward drop. 6. Input leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate inputs and the latch input. Dallas Semiconductor devices are built to the highest , controlled by the gate inputs and latch pin status. When the latch pin is logic 0, the gate input levels are , tained. When the latch input is returned to logic 0, the gate inputs again are inverted and passed to , Gate Inputs Latch Control LATCH VCc DESCRIPTION The DS1640 DS1640 contains four P channel power MOS ... OCR Scan
datasheet

4 pages,
116.37 Kb

DS1640/DS1640C TEXT
datasheet frame
Abstract: capable of carrying 300 mA maximum at 200 mV forward drop. 6. Input leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate inputs and the latch input. Dallas , controlled by the latch input. The logic levels passed to the FET gates are controlled by the gate inputs and latch pin status. When the latch pin is logic 0, the gate input levels are inverted and passed di rectly , input is returned to logic 0, the gate inputs again are inverted and passed to the FET control gates ... OCR Scan
datasheet

4 pages,
111.5 Kb

DS1640/DS1640C TEXT
datasheet frame
Abstract: . Input leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate , gate inputs and latch pin status. When the latch pin is logic 0, the gate input levels are inverted and , latch input is returned to logic 0, the gate inputs again are inverted and passed to the FET control , No Connection Gate Inputs Latch Control DESCRIPTION The DS1640 DS1640 contains four P channel power MOS , logic and to operate a gate bias generator. 022698 1/4 DS1640/DS1640C DS1640/DS1640C OPERATION With +3 u +5 volts ... OCR Scan
datasheet

4 pages,
160.03 Kb

DS1640C DS1640 DS1640/DS1640C TEXT
datasheet frame
Abstract: . Input leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate , +3 Û +5 volt power supply input which is used to power internal logic and to operate a gate bias , bias applied to the control gate (see Figure 1). A set of four internal latches is controlled by the latch input. The logic levels passed to the FET gates are controlled by the gate inputs and latch pin status. When the latch pin is logic 0, the gate input levels are inverted and passed directly to the ... Dallas Semiconductor
Original
datasheet

4 pages,
35.36 Kb

DS1640C DS1640 DS1640/DS1640C TEXT
datasheet frame
Abstract: drop. 6. Input leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate inputs and the latch input. Dallas Semiconductor devices are built to the highest , input which is used to power internal logic and to operate a gate bias generator. 1 of 4 111999 , control gate (see Figure 1). A set of four internal latches is controlled by the latch input. The logic , pin is logic 0, the gate input levels are inverted and passed directly to the control gates, enabling ... Dallas Semiconductor
Original
datasheet

4 pages,
72.75 Kb

DS1640C DS1640 DS1640/DS1640C TEXT
datasheet frame
Abstract: carrying 300 mA maximum at 200 mV forward drop. 6. Input leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate inputs and the latch input. Dallas , controlled by the gate inputs and latch pin status. When the latch pin is logic 0, the gate input levels are , tained. When the latch input is returned to logic 0, the gate inputs again are inverted and passed to , GATE1-GATE4 NC LATCH +3 to +5 Volt Input Ground FET Sources FET Drains FET Control Gates No Connection Gate ... OCR Scan
datasheet

4 pages,
70.1 Kb

S1540C 1540/D TEXT
datasheet frame
Abstract: four gate inputs and the latch input only. 7. Applies to each of four gate inputs and the latch input , input which is used to power internal logic and to oper­ ate a gate bias generator. 021492 1/4 , input. The logic levels passed to the F ET gates are controlled by the gate inputs and latch pin status. When the latch pin is logic 0, the gate input levels are inverted and passed di­ rectly to the , input is returned to logic 0, the DS1640 DS1640 BLOCK DIAGRAM gate inputs again are inverted and passed ... OCR Scan
datasheet

4 pages,
80.13 Kb

DS1640/DS1640C TEXT
datasheet frame
Abstract: capable of carrying 300 mA maximum at 200 mV forward drop. 6. Input leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate Inputs and the latch input. Dallas , , the gate input levels are inverted and passed di­ rectly to the control gates, enabling the switches , the latch pin, the input levels present on the gate inputs are locked by the four internal latches , +3 to +5 Volt Input Ground FET Sources FET Drains FET Control Gates No Connection Gate Inputs ... OCR Scan
datasheet

4 pages,
74.73 Kb

DS1640/DS1640C DS1640/D 1640C TEXT
datasheet frame
Abstract: maximum at 200 mV forward drop. 6. Input leakage applies to the four gate inputs and the latch input only. 7. Applies to each of four gate inputs and the latch input. Dallas Semiconductor devices are built , internal logic and to oper­ ate a gate bias generator. The DS1640 DS1640 contains four P channel power MOS F , , the gate input levels are inverted and passed di­ rectly to the control gates, enabling the switches , the latch pin, the input levels present on the gate inputs are locked by the four internal latches ... OCR Scan
datasheet

4 pages,
72.92 Kb

DS1640/DS1640C TEXT
datasheet frame
Abstract: four gate inputs and the latch input only. 7. Applies to each of four gate inputs and the latch input , -*- +5 volt power supply input which is used to power internal logic and to operate a gate bias , latch input. The logic levels passed to the FET gates are controlled by the gate Inputs and latch pin status. When the latch pin is logic 0, the gate input levels are inverted and passed directly to the , Input Ground FET Sources FET Drains FET Control Gates No Connection Gate Inputs Latch Control ... OCR Scan
datasheet

4 pages,
212.15 Kb

DS1640C DS1640 D012 DS1640/DS1640C TEXT
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Archived Files

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,DC,ON/OFF, 2, 1, 2,DC and Transient analyses value of the Source,dc/tran,Volts, 3, 0, 1,AC small signal input,ac,AC,ON/OFF, 4,-4, 2,AC magnitude,acmag, 5,-4, 2,AC phase,acphase, 6 , 1, 1, 2,DC and Transient analyses value of the Source,dc/tran,Volts, *I,Independent Current values,dc,DC,ON/OFF, 2, 1, 2,DC and Transient analysis value of the Source,dc/tran,Amperes, 3, 0, 1,AC small signal input,ac,AC,ON/OFF, 4,-4, 2,AC magnitude,acmag, 5,-4, 2,AC phase,acphase
/datasheets/files/kaleidoscope/cad/visionics_edwinxp140/edwinxp/sys/elements.spc
Kaleidoscope 15/09/2004 444.15 Kb SPC elements.spc
input. The clear function for the 161 is asynchronous; and a low level at the clear input sets all four function for the 163 is synchronous; and a low level at the clear input sets all four of the flip-flop designs. The 161 and 163 are 4-bit binary counters. The carry output is decoded by means of a NOR gate buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input presetting is synchronous, setting up a low level at the load input disables the counter and causes the
/datasheets/files/national/htm/nsc01600-v5.htm
National 01/11/2002 14.17 Kb HTM nsc01600-v5.htm
function for the 161 is asynchronous; and a low level at the clear input sets all four of the flip-flop synchronous; and a low level at the clear input sets all four of the flip-flop outputs low after the next triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. These synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree NAND gate. The gate output is connected to the clear input to synchronously clear the counter to all
/datasheets/files/national/pf/dm54161.html
National 17/02/2005 6.31 Kb HTML dm54161.html
LS161A LS161A is asynchronous; and a low level at the clear input sets all four of the flip-flop outputs low normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four low level at the load input disables the counter and causes the outputs to agree with the setup data ; and a low level at the clear inputs sets all four of the flip-flop outputs low after the next clock gate. The gate output is connected to the clear input to synchronously clear the counter to all low
/datasheets/files/national/docs/wcd00049/wcd0494f.htm
National 03/04/1998 7.27 Kb HTM wcd0494f.htm
four channel ISL6123 ISL6123 (ENABLE input), ISL6124 ISL6124 (ENABLE# input) and ISL6125 ISL6125 ICs offer the designer 4 rail control when it is required that all four rails are in minimal compliance prior to turn on and that In contrast to the ISL6123 ISL6123 and ISL6124 ISL6124, with the ISL6126 ISL6126, each of the four channels operates in compliance and ENABLE is asserted the sequencing starts and each subsequent GATE will turn-on independent I/O and is ideal for voltage sequencing into redundant capability loads as all four inputs need to
/datasheets/files/intersil/device_pages/device_isl6127.html
Intersil 07/09/2006 25.5 Kb HTML device_isl6127.html
LS161A LS161A and LS163A LS163A are 4-bit binary counters. The carry output is decoded by means of a NOR gate, thus input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. is synchronous, setting up a low level at the load input disables the counter and causes the outputs input. The clear function for the LS161A LS161A is asynchronous; and a low level at the clear input sets all function for the LS163A LS163A is synchronous; and a low level at the clear inputs sets all four of the flip-flop
/datasheets/files/national/htm/nsc02135-v4.htm
National 16/09/1998 8.55 Kb HTM nsc02135-v4.htm
clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the levels of the enable input. The clear function for the LS161A LS161A is asynchronous; and a low level at the clear input sets all four of the flip-flop outputs low, regardless of the levels of clock count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry high-speed counting designs. The LS161A LS161A and LS163A LS163A are 4-bit binary counters. The carry output is decoded by
/datasheets/files/national/pf/54ls161a.html
National 17/02/2005 6.38 Kb HTML 54ls161a.html
clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the levels of the enable input. The clear function for the LS161A LS161A is asynchronous; and a low level at the clear input sets all four of the flip-flop outputs low, regardless of the levels of clock count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry high-speed counting designs. The LS161A LS161A and LS163A LS163A are 4-bit binary counters. The carry output is decoded by
/datasheets/files/national/pf/54ls163a.html
National 17/02/2005 6.38 Kb HTML 54ls163a.html
four channel ISL6123 ISL6123 (ENABLE input), ISL6124 ISL6124 (ENABLE# input) and ISL6125 ISL6125 ICs offer the designer 4 rail control when it is required that all four rails are in minimal compliance prior to turn on and that In contrast to the ISL6123 ISL6123 and ISL6124 ISL6124, with the ISL6126 ISL6126, each of the four channels operates in compliance and ENABLE is asserted the sequencing starts and each subsequent GATE will turn-on independent I/O and is ideal for voltage sequencing into redundant capability loads as all four inputs need to
/datasheets/files/intersil/device_pages/device_isl6128.html
Intersil 07/09/2006 25.44 Kb HTML device_isl6128.html
four channel ISL6123 ISL6123 (ENABLE input), ISL6124 ISL6124 (ENABLE# input) and ISL6125 ISL6125 ICs offer the designer 4 rail control when it is required that all four rails are in minimal compliance prior to turn on and that In contrast to the ISL6123 ISL6123 and ISL6124 ISL6124, with the ISL6126 ISL6126, each of the four channels operates in compliance and ENABLE is asserted the sequencing starts and each subsequent GATE will turn-on independent I/O and is ideal for voltage sequencing into redundant capability loads as all four inputs need to
/datasheets/files/intersil/device_pages/device_isl6124.html
Intersil 07/09/2006 25.5 Kb HTML device_isl6124.html