FIN3385 FIN3386 FIN3383 FIN3384 FIN3365 FIN3366 FIN3363 FIN3364 - Datasheet Archive

 

FIN3385 · FIN3386, FIN3383 · FIN3384, FIN3365 · FIN3366, FIN3363 · FIN3364 Low Voltage 24/18 Bit Flat

 

Revised June 2003 FIN3385 FIN3385 · FIN3386 FIN3386, FIN3383 FIN3383 · FIN3384 FIN3384, FIN3365 FIN3365 · FIN3366 FIN3366, FIN3363 FIN3363 · FIN3364 FIN3364 Low Voltage 24/18 Bit Flat Panel Display Link Serializers/De-Serializers General Description Features The FIN3385/FIN3383/FIN3365/FIN3363 FIN3385/FIN3383/FIN3365/FIN3363 transforms 28/21 bit wide parallel LVTTL (Low Voltage TTL) data into 4/3 serial LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data steam over a separate LVDS link. Every cycle of transmit clock 28/21 bits of input LVTTL data are sampled and transmitted. s Low power consumption The FIN3386/FIN3384/FIN3366/FIN3364 FIN3386/FIN3384/FIN3366/FIN3364 receives and converts the 4/3 serial LVDS data streams back into 28/21 bits of LVTTL data. Refer to Table 1 for a matrix summary of the Serializers and De-serializers available. For the FIN3385 FIN3385, at a transmit clock frequency of 85 MHz, 28 bits of LVTTL data are transmitted at a rate of 595 Mbps per LVDS channel. s Internal PLL with no external component s 20 MHz to 85 MHz shift clock support s 50% duty cycle on the clock output of receiver s ±1V common-mode range around 1.2V s Narrow bus reduces cable size and cost s High throughput (up to 2.38 Gbps throughput) s Compatible with TIA/EIA-644 TIA/EIA-644 specification s Devices are offered in 48- and 56-lead TSSOP packages These chipsets are an ideal solution to solve EMI and cable size problems associated with wide and high-speed TTL interfaces. Ordering Code: Package Number Package Description FIN3363MTD FIN3363MTD (Preliminary) Order Number MTD48 MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153 MO-153, 6.1mm Wide FIN3364MTD FIN3364MTD (Preliminary) MTD48 MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153 MO-153, 6.1mm Wide FIN3365MTD FIN3365MTD (Preliminary) MTD48 MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153 MO-153, 6.1mm Wide FIN3366MTD FIN3366MTD (Preliminary) MTD48 MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153 MO-153, 6.1mm Wide FIN3383MTD FIN3383MTD MTD56 MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153 MO-153, 6.1mm Wide FIN3384MTD FIN3384MTD (Preliminary) MTD56 MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153 MO-153, 6.1mm Wide FIN3385MTD FIN3385MTD MTD56 MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153 MO-153, 6.1mm Wide FIN3386MTD FIN3386MTD (Preliminary) MTD56 MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153 MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. © 2003 Fairchild Semiconductor Corporation DS500864 DS500864 www.fairchildsemi.com FIN3385 FIN3385 · FIN3386 FIN3386, FIN3383 FIN3383 · FIN3384 FIN3384, FIN3365 FIN3365 · FIN3366 FIN3366, FIN3363 FIN3363 · FIN3364 FIN3364 Low Voltage 24/18 Bit Flat Panel Display Link Serializers/De-Serializers June 2003 FIN3385 FIN3385 · FIN3386 FIN3386, FIN3383 FIN3383 · FIN3384 FIN3384, FIN3365 FIN3365 · FIN3366 FIN3366, FIN3363 FIN3363 · FIN3364 FIN3364 TABLE 1. Display Panel Link Serializers/De-Serializers Chip Matrix Part CLK Frequency LVTTL IN LVDS OUT FIN3385 FIN3385 85 28 4 FIN3386 FIN3386 85 FIN3383 FIN3383 66 28 4 FIN3384 FIN3384 66 FIN3365 FIN3365 85 FIN3366 FIN3366 85 FIN3363 FIN3363 66 FIN3364 FIN3364 66 LVDS IN LVTTL OUT 4 56 TSSOP 4 28 56 TSSOP 3 21 48 TSSOP 3 21 28 21 48 TSSOP 56 TSSOP 3 21 48 TSSOP 3 48 TSSOP Block Diagrams Transmitter Functional Diagram for FIN3385 FIN3385 and FIN3383 FIN3383 Transmitter Functional Diagram for FIN3365 FIN3365 and FIN3363 FIN3363 www.fairchildsemi.com Package 56 TSSOP 2 FIN3385 FIN3385 · FIN3386 FIN3386, FIN3383 FIN3383 · FIN3384 FIN3384, FIN3365 FIN3365 · FIN3366 FIN3366, FIN3363 FIN3363 · FIN3364 FIN3364 Block Diagrams (Continued) Receiver Functional Diagram for FIN3386 FIN3386 and FIN3384 FIN3384 Receiver Functional Diagram for FIN3366 FIN3366 and FIN3364 FIN3364 3 www.fairchildsemi.com FIN3385 FIN3385 · FIN3386 FIN3386, FIN3383 FIN3383 · FIN3384 FIN3384, FIN3365 FIN3365 · FIN3366 FIN3366, FIN3363 FIN3363 · FIN3364 FIN3364 Transmitters Pin Descriptions Pin Names I/O Type Number of Pins Description of Signals TxIn I 28/21 LVTTL Level Inputs TxCLKIn I 1 TxOut+ O 4/3 Positive LVDS Differential Data Output TxOut- O 4/3 Negative LVDS Differential Data Output TxCLKOut+ O 1 Positive LVDS Differential Clock Output TxCLKOut- O 1 Negative LVDS Differential Clock Output R_FB I 1 Rising Edge Clock (HIGH), Falling Edge Clock (LOW) PwrDn I 1 LVTTL Level Power-Down Input Assertion (LOW) puts the outputs in high-impedance state. LVTTL Level Clock Input The rising edge is for data strobe. PLL VCC I 1 Power Supply Pin for PLL PLL GND I 2 Ground Pins for PLL LVDS VCC I 1 Power Supply Pin for LVDS Outputs LVDS GND I 3 Ground Pins for LVDS Outputs VCC I 3 Power Supply Pins for LVTTL Inputs GND I 5 Ground pins for LVTTL Inputs NC No Connect Connection Diagrams FIN3385 FIN3385 and FIN3383 FIN3383 (28:4 Transmitter) Pin Assignment for TSSOP www.fairchildsemi.com FIN3365 FIN3365 and FIN3363 FIN3363 (21:3 Transmitter) Pin Assignment for TSSOP 4 Pin Descriptions Pin Names I/O Type Number of Pins Description of Signals RxIn I 4/3 Negative LVDS Differential Data Inputs RxIn+ I 4/3 Positive LVDS Differential Data Inputs RxCLKIn- I 1 Negative LVDS Differential Clock Input RxCLKIn+ I 1 Positive LVDS Differential Clock Input RxOut O 28/21 RxCLKOut O 1 LVTTL Clock Output PwrDn I 1 LVTTL Level Input Refer to Transmitter and Receiver Power-Up and Power-Down Operation Truth Table Power Supply Pin for PLL LVTTL Level Data Outputs Goes HIGH for PwrDn LOW PLL VCC I 1 PLL GND I 2 Ground Pins for PLL LVDS VCC I 1 Power Supply Pin for LVDS Inputs LVDS GND I 3 Ground Pins for LVDS Inputs VCC I 4 Power Supply for LVTTL Outputs GND I 5 NC Ground Pins for LVTTL Outputs No Connect Connection Diagrams FIN3386 FIN3386 and FIN3384 FIN3384 (4:28 Receiver) Pin Assignment for TSSOP FIN3366 FIN3366 and FIN3364 FIN3364 (3:21 Receiver) Pin Assignment for TSSOP 5 www.fairchildsemi.com FIN3385 FIN3385 · FIN3386 FIN3386, FIN3383 FIN3383 · FIN3384 FIN3384, FIN3365 FIN3365 · FIN3366 FIN3366, FIN3363 FIN3363 · FIN3364 FIN3364 Receivers FIN3385 FIN3385 · FIN3386 FIN3386, FIN3383 FIN3383 · FIN3384 FIN3384, FIN3365 FIN3365 · FIN3366 FIN3366, FIN3363 FIN3363 · FIN3364 FIN3364 Transmitter and Receiver Power-Up/Power-Down Operation Truth Table The outputs of the transmitter remain in the High-Impedance state until the power supply reaches 2V. The following Transmitter table shows the operation of the transmitter during power-up and power-down and operation of the PwrDn pin. PwrDn Normal VCC 2V >2V >2V TxIn X X Active Active >2V >2V TxOut± Z Z Active X TxCLKIn X X Active H/L/Z TxCLKOut± Z Z Active (Note 1) PwrDn L L H H H H (Note 2) Receiver PwrDn RxIn± X X Active Active (Note 2) RxOut Z L L/H P H P RxCLKIn± X X Active (Note 2) Active (Note 2) RxCLKOut Z (Note 3) Active (Note 3) (Note 3) (Note 3) PwrDn L L H H H H VCC 2V >2V >2V >2V >2V H = HIGH Logic Level L = LOW Logic Level P = Last Valid State X = Don't Care Z = High-Impedance Note 1: If the transmitter is powered up and PwrDn is inactive HIGH and the clock input goes to any state LOW, HIGH or Z then the internal PLL will go to a known low frequency and stay until the clock starts normal operation again. Note 2: If the input is terminated and un-driven (Z) or shorted or open. (fail safe condition) Note 3: For PwrDn or fail safe condition the RxCLKOut pin will go LOW for Panel Link devices and HIGH for Channel Link devices. Note 4: Shorted here means (± inputs are shorted to each other, or ± inputs are shorted to each other and Ground or VCC, or either ± inputs are shorted to Ground or VCC) with no other Current/Voltage sources (noise) applied. If the VID is still in the valid range (greater than 100mV) and VCM is in the valid range (0V to 2.4V) then the input signal is still recognized and the part will respond normally. www.fairchildsemi.com 6 Recommended Operating Conditions Power Supply Voltage (VCC) -0.3V to +4.6V TTL/CMOS Input/Output Voltage -0.5V to +4.6V Supply Voltage (VCC) LVDS Input/Output Voltage -0.3V to +4.6V Operating Temperature (TA)(Note 5) LVDS Output Short Circuit Current (IOSD) Storage Temperature Range (TSTG) Continuous Maximum Supply Noise Voltage -65°C to +150°C Maximum Junction Temperature (TJ) (VCCNPP) 150°C Lead Temperature (TL) ESD Rating (HBM, 1.5 k, 100 pF) >10.0 kV I/O to GND >6.5 kV All Pins ESD Rating (MM, 0, 200 pF) 100 mVP-P (Note 6) Note 5: Absolute maximum ratings are DC values beyond which the device may be damaged or have its useful life impaired. The datasheet specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation outside datasheet specifications. 260°C (Soldering, 4 seconds) 3.0V to 3.6V -10°C to +70°C Note 6: 100mV VCC noise should be tested for frequency at least up to 2 MHz. All the specification below should be met under such a noise. >400V Transmitter DC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 7) Symbol Parameter Test Conditions Min Typ Max Units V Transmitter LVTTL Input Characteristics VIH Input High Voltage 2.0 VCC VIL Input Low Voltage GND 0.8 V VIK Input Clamp Voltage -0.79 -1.5 V IIN Input Current 1.8 10.0 IIK = -18 mA VIN = 0.4V to 4.6V VIN = GND -10.0 0 250 TBD µA Transmitter LVDS Output Characteristics (Note 8) VOD Output Differential Voltage VOD VOD Magnitude Change from Differential LOW-to-HIGH VOS Offset Voltage VOS Offset Magnitude Change from Differential LOW-to-HIGH IOS Short Circuit Output Current VOUT = 0V -3.5 -5.0 mA IOZ Disabled Output Leakage Current DO = 0V to 4.6V, PwrDn = 0V ±1.0 ±10.0 µA RL = 100 , See Figure 1 1.125 1.25 450 mV 35.0 mV 1.375 V mV Transmitter Supply Current 31.0 49.5 RL = 100 , 40.0 MHz 32.0 55.0 (Note 9) See Figures 3, 4 66.0 MHz 37.0 60.5 85.0 MHz ICCWT 32.5 MHz for Worst Case Pattern (With Load) ICCWT 28:4 Transmitter Power Supply Current 42.0 66.0 21:3 Transmitter Power Supply Current 32.5 MHz 28.0 46.2 for Worst Case Pattern (With Load) RL = 100 , 40.0 MHz 29.0 51.7 (Note 9) See Figures 3, 4 66.0 MHz 34.0 57.2 85.0 MHz 39.0 62.7 10.0 55.0 32.5 MHz 29.0 41.8 ICCPDT Powered Down Supply Current ICCGT PwrDn = 0.8V 28:4 Transmitter Supply Current for 16 Grayscale (Note 9) See Figure 22 40.0 MHz 30.0 44.0 (Note 10) 65.0 MHz 35.0 49.5 85.0 MHz ICCGT mA 39.0 µA 55.0 38.5 21:3 Transmitter Supply Current 32.5 MHz 26.0 See Figure 22 40.0 MHz 27.0 40.7 (Note 10) 65.0 MHz 32.0 46.2 85.0 MHz for 16 Grayscale (Note 9) mA 36.0 mA 51.7 mA Note 7: All Typical values are at TA = 25°C and with VCC = 3.3V. Note 8: Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltage are referenced to ground unless otherwise specified (except VOD and VOD). Note 9: The power supply current for both transmitter and receiver can be different with the number of active I/O channels. Note 10: The 16-grayscale test pattern tests device power consumption for a "typical" LCD display pattern. The test pattern approximates signal switching needed to produce groups of 16 vertical strips across the display. 7 www.fairchildsemi.com FIN3385 FIN3385 · FIN3386 FIN3386, FIN3383 FIN3383 · FIN3384 FIN3384, FIN3365 FIN3365 · FIN3366 FIN3366, FIN3363 FIN3363 · FIN3364 FIN3364 Absolute Maximum Ratings(Note 5) FIN3385 FIN3385 · FIN3386 FIN3386, FIN3383 FIN3383 · FIN3384 FIN3384, FIN3365 FIN3365 · FIN3366 FIN3366, FIN3363 FIN3363 · FIN3364 FIN3364 Transmitter AC Electrical Characteristics Over supply voltage and operating temperature ranges, unless otherwise specified. Symbol Parameter Test Conditions tTCH Transmit Clock (TxCLKIn) HIGH Time tTCL Transmit Clock Low Time tCLKT TxCLKIn Transition Time (Rising and Failing) (10% to 90%) tJIT TxCLKIn Cycle-to-Cycle Jitter TxIn Transition Time Max Units T 50.0 ns 0.35 0.5 0.65 T 0.5 0.65 T See Figure 12 tXIT Typ 0.35 Transmit Clock Period Min 11.76 tTCP See Figure 4 1.0 6.0 ns 6.0 1.5 ns 3.0 ns LVDS Transmitter Timing Characteristics tTLH Differential Output Rise Time (20% to 80%) tTHL Differential Output Fall Time (80% to 20%) 0.75 1.5 ns 0.75 See Figure 3 1.5 ns tSTC TxIn Setup to TxCLNIn tHTC TxIn Holds to TCLKIn tTPDD Transmitter Power-Down Delay See Figure 8, (Note 11) 100 tTCCD Transmitter Clock Input to Clock Output Delay See Figure 5 5.5 Transmitter Clock Input to Clock Output Delay (TA = 25°C and with VCC = 3.3V) See Figure 4 (f = 85 MHz) 2.5 ns 0 ns 2.8 6.8 ns ns Transmitter Output Data Jitter (f = 40 MHz) (Note 12) -0.25 0 0.25 ns a-0.25 a a+0.25 ns 1 2a-0.25 2a 2a+0.25 ns fx7 3a-0.25 3a 3a+0.25 ns Transmitter Output Pulse Position of Bit 4 4a-0.25 4a 4a+0.25 ns tTPPB5 Transmitter Output Pulse Position of Bit 5 5a-0.25 5a 5a+0.25 ns tTPPB6 Transmitter Output Pulse Position of Bit 6 6a-0.25 6a 6a+0.25 ns tTPPB0 Transmitter Output Pulse Position of Bit 0 tTPPB1 Transmitter Output Pulse Position of Bit 1 tTPPB2 Transmitter Output Pulse Position of Bit 2 tTPPB3 Transmitter Output Pulse Position of Bit 3 tTPPB4 See Figure 10 a= Transmitter Output Data Jitter (f = 65 MHz) (Note 12) -0.2 0 0.2 ns a-0.2 a a+0.2 ns 1 2a-0.2 2a 2a+0.2 ns fx7 3a-0.2 3a 3a+0.2 ns Transmitter Output Pulse Position of Bit 4 4a-0.2 4a 4a+0.2 ns tTPPB5 Transmitter Output Pulse Position of Bit 5 5a-0.2 5a 5a+0.2 ns tTPPB6 Transmitter Output Pulse Position of Bit 6 6a-0.2 6a 6a+0.2 ns tTPPB0 Transmitter Output Pulse Position of Bit 0 tTPPB1 Transmitter Output Pulse Position of Bit 1 tTPPB2 Transmitter Output Pulse Position of Bit 2 tTPPB3 Transmitter Output Pulse Position of Bit 3 tTPPB4 See Figure 10 a= Transmitter Output Data Jitter (f = 85 MHz) (Note 12) -0.2 0 0.2 ns a-0.2 a a+0.2 ns 1 2a-0.2 2a 2a+0.2 ns fx7 3a-0.2 3a 3a+0.2 ns Transmitter Output Pulse Position of Bit 4 4a-0.2 4a 4a+0.2 ns tTPPB5 Transmitter Output Pulse Position of Bit 5 5a-0.2 5a 5a+0.2 ns tTPPB6 Transmitter Output Pulse Position of Bit 6 6a-0.2 6a 6a+0.2 ns tJCC FIN3385/3365 FIN3385/3365 Transmitter Clock Out Jitter f = 40 MHz 350 370 (Cycle-to-Cycle) f = 65 MHz 210 230 See Figure 12 f = 85 MHz 110 150 Transmitter Phase Lock Loop Set Time (Note 13) See Figure 6, (Note 12) tTPPB0 Transmitter Output Pulse Position of Bit 0 tTPPB1 Transmitter Output Pulse Position of Bit 1 tTPPB2 Transmitter Output Pulse Position of Bit 2 tTPPB3 Transmitter Output Pulse Position of Bit 3 tTPPB4 tTPLLS See Figure 10 a= 10.0 ps ms Note 11: Outputs of all transmitters stay in 3-STATE until power reaches 2V. Both clock and data output begins to toggle 10ms after VCC reaches 3V and Power-Down pin is above 1.5V. Note 12: This output data pulse position works for both transmitter with 28 or 21 TTL inputs except the LVDS output bit mapping difference (see Figures 15, 16). Figure 17 shows the skew between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter. Note 13: This jitter specification is based on the assumption that PLL has a ref clock with cycle-to-cycle input jitter less than 2ns. www.fairchildsemi.com 8 Over supply voltage and operating temperature ranges, unless otherwise specified. (Note 14) Symbol Parameter Test Conditions Min Typ Max Units LVTTL/CMOS DC Characteristics VIH Input High Voltage 2.0 VCC V VIL Input Low Voltage GND 0.8 V VOH Output High Voltage IOH = -0.4 mA VOL Output Low Voltage IOL = 2 mA 0.06 0.3 V VIK Input Clamp Voltage IIK = -18 mA -0.79 -1.5 V IIN Input Current VIN = 0V to 4.6V 10.0 µA IOFF Input/Output Power Off Leakage Current 2.7 3.3 -10.0 VCC = 0V, ±10.0 All LVTTL Inputs/Outputs 0V to 4.6V IOS Output Short Circuit Current V VOUT = 0V -60.0 µA -120 mA Receiver LVDS Input Characteristics VTH Differential Input Threshold HIGH Figure 2, Table 2 VTL Differential Input Threshold LOW Figure 2, Table 2 -100 100 mV VICM Input Common Mode Range Figure 2, Table 2 0.05 2.35 V IIN Input Current VIN = 2.4V, VCC = 3.6V or 0V ±10.0 µA VIN = 0V, VCC = 3.6V or 0V ±10.0 µA mV Receiver Supply Current ICCWR 4:28 Receiver Power Supply Current 32.5 MHz 70.0 for Worst Case Pattern (With Load) CL = 8 pF, 40.0 MHz 75.0 (Note 15) See Figures 2, 3 66.0 MHz 114 85.0 MHz ICCWR 3:21 Receiver Power Supply Current mA 135 32.5 MHz 49.0 60.0 for Worst Case Pattern (With Load) CL = 8 pF, 40.0 MHz 53.0 65.0 (Note 15) See Figures 2, 3 66.0 MHz 78.0 100 85.0 MHz 90.0 115 ICCPDR Powered Down Supply Current PwrDn = 0.8V (RxOut stays LOW) NA 55.0 tRCOP Receiver Clock Output (RxCLKOut) Period T 50.0 tRCOL RxCLKOut LOW Time See Figure 9 4.0 5.0 6.0 ns tRCOH RxCLKOut HIGH Time (f = 85 MHz) 4.5 5.0 6.5 ns tRSRC RxOut Valid Prior to RxCLKOut (Rising Edge Strobe) 3.5 tRHRC RxOut Valid After RxCLKOut tROLH Output Rise Time (20% to 80%) CL = 8 pF, 2.0 3.5 ns tROHL Output Fall Time (80% to 20%) See Figure 5 1.8 3.5 ns tRCCD Receiver Clock Input to Clock Output Delay See Figure 11, (Note 16) 3.5 5.0 7.5 ns 1.0 µs 11.76 µA ns 3.5 TA = 25°C and VCC = 3.3V mA ns tRPDD Receiver Power-Down Delay tRSPB0 Receiver Input Strobe Position of Bit 0 See Figure 14 0.49 0.84 1.19 ns tRSPB1 Receiver Input Strobe Position of Bit 1 2.17 2.52 2.87 ns tRSPB2 Receiver Input Strobe Position of Bit 2 3.85 4.20 4.55 ns tRSPB3 Receiver Input Strobe Position of Bit 3 5.53 5.88 6.23 ns tRSPB4 Receiver Input Strobe Position of Bit 4 7.21 7.56 7.91 ns tRSPB5 Receiver Input Strobe Position of Bit 5 8.89 9.24 9.59 ns tRSPB6 Receiver Input Strobe Position of Bit 6 10.57 10.92 11.27 ns tRSKM RxIN Skew Margin See Figure 9, (Note 17) tRPLLS Receiver Phase Lock Loop Set Time See Figure 12 10.0 ms See Figure 8 (f = 85 MHz) 290 ps Note 14: All Typical Values are at TA = 25°C and with VCC = 3.3V. Positive current values refer to the current flowing into device and negative values means current flowing out of pins. Voltage are referenced to ground unless otherwise specified (except VOD and VOD). Note 15: The power supply current for the receiver can be different with the number of active I/O channels. Note 16: Total channel latency from Sewrializer to deserializer is (T + tTCCD) + (2*T + tRCCD). T here is the clock period. Note 17: Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position. 9 www.fairchildsemi.com FIN3385 FIN3385 · FIN3386 FIN3386, FIN3383 FIN3383 · FIN3384 FIN3384, FIN3365 FIN3365 · FIN3366 FIN3366, FIN3363 FIN3363 · FIN3364 FIN3364 Receiver DC Electrical Characteristics FIN3385 FIN3385 · FIN3386 FIN3386, FIN3383 FIN3383 · FIN3384 FIN3384, FIN3365 FIN3365 · FIN3366 FIN3366, FIN3363 FIN3363 · FIN3364 FIN3364 Receiver AC Electrical Characteristics (66 MHz) Symbol Parameter Test Conditions Min Typ Max Units See Figure 9 15.0 T 50.0 ns 10.0 11.0 ns 10.0 12.2 ns tRCOP Receiver Clock Output (RxCLKOut) Period tRCOL RxCLKOut LOW Time tRCOH RxCLKOut HIGH Time See Figure 9 tRSRC RxOut Valid Prior to RxCLKOut (Rising Edge Strobe) 6.5 11.6 ns tRHRC RxOut Valid After RxCLKOut (f = 40 MHz) 6.0 11.6 ns tRCOL RxCLKOut LOW Time 5.0 6.3 9.0 ns tRCOH RxCLKOut HIGH Time See Figure 9, (Note 18) 5.0 7.6 9.0 ns tRSRC RxOut Valid Prior to RxCLKOut (Rising Edge Strobe) 4.5 7.3 ns tRHRC RxOut Valid After RxCLKOut (f = 66 MHz) 4.0 6.3 ns tROLH Output Rise Time (20% to 80%) CL = 8 pF, (Note 17) 2.0 5.0 ns tROHL Output Fall Time (80% to 20%) See Figure 5 1.8 5.0 ns tRCCD Receiver Clock Input to Clock Output Delay 3.5 5.0 7.5 ns See Figure 11, (Note 19) TA = 25°C and VCC = 3.3V tRPDD Receiver Power-Down Delay 1.0 µs tRSPB0 Receiver Input Strobe Position of Bit 0 1.0 1.4 2.15 ns tRSPB1 Receiver Input Strobe Position of Bit 1 4.5 5.0 5.8 ns tRSPB2 Receiver Input Strobe Position of Bit 2 See Figure 17 8.1 8.5 9.15 ns (f = 40 MHz) See Figure 14 tRSPB3 Receiver Input Strobe Position of Bit 3 11.6 11.9 12.6 ns tRSPB4 Receiver Input Strobe Position of Bit 4 15.1 15.6 16.3 ns tRSPB5 Receiver Input Strobe Position of Bit 5 18.8 19.2 19.9 ns tRSPB6 Receiver Input Strobe Position of Bit 6 22.5 22.9 23.6 ns tRSPB0 Receiver Input Strobe Position of Bit 0 0.7 1.1 1.4 ns tRSPB1 Receiver Input Strobe Position of Bit 1 2.9 3.3 3.6 ns tRSPB2 Receiver Input Strobe Position of Bit 2 See Figure 17 5.1 5.5 5.8 ns (f = 65 MHz) ns tRSPB3 Receiver Input Strobe Position of Bit 3 7.3 7.7 8.0 tRSPB4 Receiver Input Strobe Position of Bit 4 9.5 9.9 10.2 ns tRSPB5 Receiver Input Strobe Position of Bit 5 11.7 12.1 12.4 ns tRSPB6 Receiver Input Strobe Position of Bit 6 13.9 14.3 14.6 ns tRSKM RxIn Skew Margin f = 40 MHz 490 See Figure 19, (Note 20) f = 66 MHz 400 Receiver Phase Lock Loop Set Time See Figure 17 tRPLLS ps 10.0 ms Note 18: For the receiver with falling-edge strobe, the definition of setup/hold time will be slightly different from the one with rising-edge strobe. The clock reference point is the time when the clock falling edge passes through 2V. For hold time tRHRC, the clock reference point is the time when falling edge passes through +0.8V. Note 19: Total channel latency from Sewrializer to deserializer is (T + tTCCD) + (2*T + tRCCD). There is the clock period. Note 20: Receiver skew margin is defined as the valid sampling window after considering potential setup/hold time and minimum/maximum bit position. FIGURE 1. Differential LVDS Output DC Test Circuit www.fairchildsemi.com 10 FIGURE 2. Differential Receiver Voltage Definitions and Propagation Delay and Transition Time Test Circuit TABLE 2. Receiver Minimum and Maximum Input Threshold Test Voltages Applied Voltages (V) VIA Resulting Differential Input Voltage Resulting Common Mode Input Voltage (mV) VIB (V) VID VIC 1.25 1.15 100 1.2 1.15 1.25 -100 1.2 2.4 2.3 100 2.35 2.3 2.4 -100 2.35 0.1 0 100 0.05 0 0.1 -100 0.05 1.5 0.9 600 1.2 0.9 1.5 -600 1.2 2.4 1.8 600 2.1 1.8 2.4 -600 2.1 0.6 0 600 0.3 0 0.6 -600 0.3 Note: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVTTL/CMOS I/O. Depending on the valid strobe edge of transmitter, the TxCLKIn can be either rising or falling edge data strobe. FIGURE 3. "Worst Case" Test Pattern FIGURE 4. Transmitter LVDS Output Load and Transition Times 11 www.fairchildsemi.com FIN3385 FIN3385 · FIN3386 FIN3386, FIN3383 FIN3383 · FIN3384 FIN3384, FIN3365 FIN3365 · FIN3366 FIN3366, FIN3363 FIN3363 · FIN3364 FIN3364 Note A: For all input pulses, tR or tF < = 1 ns. Note B: CL includes all probe and jig capacitance. FIN3385 FIN3385 · FIN3386 FIN3386, FIN3383 FIN3383 · FIN3384 FIN3384, FIN3365 FIN3365 · FIN3366 FIN3366, FIN3363 FIN3363 · FIN3364 FIN3364 FIGURE 5. Receiver LVTTL/CMOS Output Load and Transition Times FIGURE 6. Transmitter Setup/Hold and HIGH/LOW Times (Rising Edge Strobe) FIGURE 7. Transmitter Input Clock Transition Time FIGURE 8. Transmitter Outputs Channel-to-Channel Skew Note: For the receiver with falling-edge strobe, the definition of setup/hold time will be slightly different from the one with rising-edge strobe. The clock reference point is the time when the clock falling edge passes through 2V. For hold time tRHRC, the clock reference point is the time when falling edge passes through +0.8V. FIGURE 9. (Receiver) Setup/Hold and HIGH/LOW Times www.fairchildsemi.com 12 FIN3385 FIN3385 · FIN3386 FIN3386, FIN3383 FIN3383 · FIN3384 FIN3384, FIN3365 FIN3365 · FIN3366 FIN3366, FIN3363 FIN3363 · FIN3364 FIN3364 FIGURE 10. Transmitter Clock In to Clock Out Delay (Rising Edge Strobe) FIGURE 11. Receiver Clock In to Clock Out Delay (Falling Edge Strobe) FIGURE 12. Receiver Phase Lock Loop Set Time FIGURE 13. Transmitter Power-Down Delay 13 www.fairchildsemi.com FIN3385 FIN3385 · FIN3386 FIN3386, FIN3383 FIN3383 · FIN3384 FIN3384, FIN3365 FIN3365 · FIN3366 FIN3366, FIN3363 FIN3363 · FIN3364 FIN3364 FIGURE 14. Receiver Power-Down Delay Note: This output data pulse position works for both transmitter with 28 or 21 TTL inputs except the LVDS output bit mapping difference. All the information in this diagram tells that the skew between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter. FIGURE 15. 28 Parallel LVTTL Inputs Mapped to 4 Serial LVDS Outputs Note: This output data pulse position works for both transmitter with 28 or 21 TTL inputs except the LVDS output bit mapping difference. All the information in this diagram tells that the skew between the first data bit and clock output. Also 2-bit cycle delay is guaranteed when the MSB is output from transmitter. FIGURE 16. 21 Parallel LVTTL Inputs Mapped to 3 Serial LVDS Outputs www.fairchildsemi.com 14 15 FIGURE 18. FIGURE 17. www.fairchildsemi.com FIN3385 FIN3385 · FIN3386 FIN3386, FIN3383 FIN3383 · FIN3384 FIN3384, FIN3365 FIN3365 · FIN3366 FIN3366, FIN3363 FIN3363 · FIN3364 FIN3364 FIN3385 FIN3385 · FIN3386 FIN3386, FIN3383 FIN3383 · FIN3384 FIN3384, FIN3365 FIN3365 · FIN3366 FIN3366, FIN3363 FIN3363 · FIN3364 FIN3364 Note: tRSKM is the budget for the cable skew and source clock skew plus ISI (Inter-Symbol Interference). Note: The minimum and maximum pulse position values are based on the bit position of each of the 7 bits within the LVDS data stream across PVT (Process, Voltage Supply, and Temperature). FIGURE 19. Receiver LVDS Input Skew Margin Note: Test setup used considers no requirement for separation of RMS and deterministic jitter. Other hardware setup such as Wavecrest boxes can be used if no M1 software is available, but the test methodology in Figure 21 should be followed. FIGURE 20. Transmitter Clock Out Jitter Measurement Setup Note: This jitter pattern is used to test the jitter response (Clock Out) of the device over the power supply range with worst jitter ±3ns (cycle-to-cycle) clock input. The specific test methodology is as follows: · Switching input data TxIn0 to TxIn20 at 0.5 MHz, and the input clock is shifted to left -3ns and to the right +3ns when data is HIGH (by switching between CLK1 and CLK2 in Figure 20). · The ±3 ns cycle-to-cycle input jitter is the static phase error between the two clock sources. Jumping between two clock sources to simulate the worst case of clock edge jump (3 ns) from graphical controllers. Cycle-to-cycle jitter at TxCLK out pin should be measured cross VCC range with 100mV noise (VCC noise frequency