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Part Manufacturer Description Datasheet BUY
LTC3444EDD#TRPBF Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3444EDD#PBF Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3444EDD#TR Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
LTC3444EDD Linear Technology LTC3444 - Micropower Synchronous Buck-Boost DC/DC Converter for WCDMA Applications; Package: DFN; Pins: 8; Temperature Range: -40°C to 85°C visit Linear Technology - Now Part of Analog Devices Buy
CYCLONE-3-MERCURYCODE-REF Texas Instruments Cyclone III-based MercuryCode visit Texas Instruments
STELLARIS-3P-CODER-DPROBE430-DEVBD Texas Instruments Red Suite 2 visit Texas Instruments

FET MARKING CODE

Catalog Datasheet MFG & Type PDF Document Tags

FMC141401-02

Abstract: fujitsu gaas marking code the FET in a circuit, the circuit gate and drain connections should be shorted to ground. 3) When soldering the FET leads, an iron with a grounded tip is required. B. CIRCUIT INSTALLATION 1) Screw , . Prior to soldering, the FET and the amplifier case should be cleaned using acetone followed by an , . During reflow, pressure on the FET is recommended to minimize solder thickness. The gate terminal and , source flange, contamination and long term degradation of thermal resistance between the FET package and
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MARKING code VO SMD fet

Abstract: marking cdm , packages, availability and ordering Ordering code (12NC) Marking/Packing IC packing info Download PDF File , INTEGRATED CIRCUITS CBT3125 Quadruple FET bus switch Product data File under Integrated , Quadruple FET bus switch CBT3125 DESCRIPTION The CBT3125 quadruple FET bus switch features , +85 °C ORDER CODE CBT3125D CBT3125DB CBT3125DS CBT3125PW DRAWING NUMBER SOT108-1 SOT337-1 SOT519 , /packaging. 2001 Dec 12 2 853-2309 27452 Philips Semiconductors Product data Quadruple FET
Philips Semiconductors
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MARKING code VO SMD fet marking cdm smd 2a 3 PIN fet ICL03 JESD78 SA00562 SSOP14 TSSOP14 JESD22-A114
Abstract: /appnotes/an-1152.pdf PQFN 5x6 Outline "C" Part Marking INTERNATIONAL RECTIFIER LOGO DATE CODE , digits") MARKING CODE (Per Marking Spec) LOT CODE (Eng Mode - Min last 4 digits of EATI#) (Prod , and synchronous FET in one package Low charge control MOSFET (8.3 nC typical) Low RDSon synchronous , FET TOP VGS 10V 5.0V 4.5V 3.5V 3.0V 2.7V 2.5V 2.3V Q2 - Synchronous FET TOP VGS 10V 5.0V 4.5V , Q1 - Control FET 10000 VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + International Rectifier
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IRFH7911P IRFH7911TRPBF IRFH7911TR2PBF D-020D

FET marking code g5d

Abstract: PG2179TB ). 53 6. MARKING/PART NUMBER , . 54 6.2 Discrete rank, marking and specification list (Target devices: Minimold, S01, 75, 79A, 84C , Circuits 5 (2) GaAs Device products HJ-FETs (Hetero Junction FET) Discretes FETs MES , PRODUCTS OPERATED AT 3 TO 10 V 20.0 NE55xxxxxx : Si LDMOS FET NESG2xxxx : SiGe HBT 10.0 NE5511279A , (NE68939) 2SC5289 (NE69039) NE5500134 Mobile Comm., PDC, GSM, Power Amp., Power MOS FET
Renesas Electronics
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FET marking code g5d PG2179TB marking code C3E SOT-89 marking code C1E mmic marking code C1G mmic 2SC3357/NE85634 R09CL0001EJ0100 PX10727EJ02V0PF

IRFH7911

Abstract: IRFH7911TRPBF PART NUMBER ("4 or 5 digits") MARKING CODE (Per Marking Spec) LOT CODE (Eng Mode - Min last 4 , and Benefits Benefits Features Increased power density Control and synchronous FET in one , Characteristics Q1 - Control FET ID, Drain-to-Source Current (A) TOP 100 BOTTOM 10 Q2 - Synchronous FET 1000 VGS 10V 5.0V 4.5V 3.5V 3.0V 2.7V 2.5V 2.3V TOP ID, Drain-to-Source , Typical Characteristics Q1 - Control FET 10000 Q2 - Synchronous FET 100000 VGS = 0V, f = 1 MHZ
International Rectifier
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IRFH7911 W5337 AN1152 marking JE FET FET MARKING CODE FET MARKING QG

nec mosfet marked v75

Abstract: NEC Ga FET marking code T79 ). 55 6. MARKING/PART NUMBER , . 56 Selection Guide PX10727EJ02V0PF 5 6.2 Discrete rank, marking and specification list , ) GaAs Device products HJ-FETs (Hetero Junction FET) Discretes FETs MES FETs Power FETs , AT 3 TO 10 V 20.0 NE55xxxxxx : Si LDMOS FET NESG2xxxx : SiGe HBT 10.0 NE5511279A (@7.5 V
NEC
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nec mosfet marked v75 NEC Ga FET marking code T79 LGA 1155 PIN diagram marking code C1H mmic MMIC SOT 363 marking CODE R33 MMIC SOT 363 marking CODE 77 G0706

IRFH7911TRPBF

Abstract: PART NUMBER ("4 or 5 digits") MARKING CODE (Per Marking Spec) LOT CODE (Eng Mode - Min last 4 , and Benefits Benefits Features Increased power density Control and synchronous FET in one , Characteristics Q1 - Control FET ID, Drain-to-Source Current (A) TOP 100 BOTTOM 10 Q2 - Synchronous FET 1000 VGS 10V 5.0V 4.5V 3.5V 3.0V 2.7V 2.5V 2.3V TOP ID, Drain-to-Source , Typical Characteristics Q1 - Control FET 10000 Q2 - Synchronous FET 100000 VGS = 0V, f = 1 MHZ
International Rectifier
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97427B

PMV45EN

Abstract: surface-mounted package; 3 leads SOT23 4. Marking Table 4. Marking codes Type number Marking code[1] PMV45EN %4N [1] % = placeholder for manufacturing site code 5. Limiting values , Product specification PMV45EN N-channel TrenchMOS logic level FET Rev. 2 â'" 7 November 2011 , Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product is designed and , specification PMV45EN N-channel TrenchMOS logic level FET 3. Ordering information Table 3. Ordering
TY Semiconductor
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Abstract: surface-mounted package; 3 leads SOT23 4. Marking Table 4. Marking codes Type number Marking code[1] PMV31XN %M4 [1] % = placeholder for manufacturing site code 5. Limiting values , Product specification PMV31XN N-channel TrenchMOS FET Rev. 2 â'" 30 November 2011 Product , Transistor (FET) in a SOT23 (TO-236AB) small Surface-Mounted Device (SMD) plastic package using Trench , TrenchMOS FET 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 TY Semiconductor
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SLG55021

Abstract: SLG55021-xxyyzzV Source Voltage Package Top Marking System Definition 8 7 6 5 Part ID Assembly Code , Input Shut Down# - Low True Signal which immediately turns FET off GND 4 GND Ground D 5 Input FET Drain Connection S 6 Input Source Connection G 7 Output FET Gate Drive Output Output CMOS Open Drain - Power Good, indicates external FET fully on PG 8 CMOS Logic Level. High True Overview The SLG55021 N-Channel FET Gate Driver is used
Silego Technology
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SLG55020 SLG55021-xxyyzzV SLG55021-xxyyzzVTR high voltage gate driver Silego Technology

SLG55321

Abstract: datecode G1 FET Drain Connection (Connect to FET with highest VD voltage) S/DIS1 6 Input/Output CMOS , /G2/G3 7 Output FET Gate Drive for FET1, FET2, FET3. A minimum of a 1k resistor must be , exceed 5V. Overview The SLG55321/320 N-Channel FET Gate Drivers are used for controlling and ramping slew rate of the source voltage on N-Channel FET switches from a CMOS logic level input. Intended as a , `Low Drive' version of the device, SLG55320 is available to support applications where FET Vgs cannot
Silego Technology
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SLG55321 datecode G1

SLG55221

Abstract: fet n-channel pin configuration GND 4 GND Ground D 5 Input FET Drain Connection (Connect to FET with highest VD , 7 Output FET Gate Drive for FET1, FET2 PG 8 Output CMOS Power Good Signal CMOS Logic Level Discharge Connection for Load2 Overview The SLG55221/220 N-Channel FET Gate Drivers are used for controlling and ramping slew rate of the source voltage on N-Channel FET switches from a CMOS , Drive' version of the device, SLG55220 is available to support applications where FET Vgs cannot exceed
Silego Technology
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SLG55221 fet n-channel pin configuration FET MARKING 600 V logic level fet fet MARKING g2

slg55221

Abstract: SILEGO #. Discharge Connection for Load2 GND 4 GND Ground D 5 Input FET Drain Connection (Connect to FET with highest VD voltage) S/DIS1 6 Input/Output G1/G2 7 Output FET Gate , Connection for Load1 Overview The SLG55251 N-Channel FET Gate Drivers are used for controlling and ramping slew rate of the source voltage on N-Channel FET switches from a CMOS logic level input. Intended , VG not ramping FET = OFF - 0.1 - 1 A VG ramping FET = OFF to ON - 600
Silego Technology
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SILEGO

SLG55221

Abstract: fet n-channel pin configuration GND 4 GND Ground D 5 Input FET Drain Connection (Connect to FET with highest VD voltage) S/DIS1 6 Input/Output G1/G2 7 Output FET Gate Drive for FET1, FET2 PG , Overview The SLG55221/220 N-Channel FET Gate Drivers are used for controlling and ramping slew rate of the source voltage on N-Channel FET switches from a CMOS logic level input. Intended as a supporting control , available to support applications where FET Vgs cannot exceed 8V. Ordering Information Part Number
Silego Technology
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FET marking code

Abstract: fet junction transistor protective cover UL/Cul, TUV approval and CE marking Specifications Type FET version Current 10 A , GN single-phase GND DC output FET transistor versions 10, 15 and 30 A Bipolar , protective cover Code 84 137 850 84 137 860 84 137 870 84 134 850 84 134 860 84 134 870 84 137 750 , (rms) Input/output capacitance (pF) Material housing Material baseplate Weight FET 10A : 1 - 200 FET 15A : 1 - 100 FET 30A : 1 - 50 Bipolar 10A : 3 - 60 FET 10A : 14 FET 15A : 1 FET 30A : 1
Crouzet
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fet junction transistor

200 Amp mosfet

Abstract: mosfet tetrode . Manufacturer 2005, June Date code (Year/Month) Pin 1 marking Laser marking BCR108S Type code , =D* 5=S Marking 6=D* K2s * For amp. A; * for amp. B 180° rotated tape loading orientation , VG1S 5 VGG Drain current ID = (VGG ), amp. B Drain current of FET A and FET B VDS = 5V, VG2S = 4V as function of Gate 1 FET B (connected to VGG, VGG =gate1 supply voltage) 28 mA 22 56K mA FET A 24 68K 18 82K 16 ID 20 18 ID 22 100K 16 14
Infineon Technologies
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BG5412K 200 Amp mosfet mosfet tetrode BG5421K

BCR108S

Abstract: BG5412K ) Pin 1 marking Laser marking BCR108S Type code Standard Packing Reel ø180 mm = 3.000 Pieces , =S Marking 6=D* K2s * For amp. A; * for amp. B 180° rotated tape loading orientation available 1 , Drain current of FET A and FET B VDS = 5V, VG2S = 4V as function of Gate 1 FET B (connected to VGG, VGG =gate1 supply voltage) 28 mA 22 56K mA FET A 24 68K 18 82K 16 , 8 8 FET B 6 6 4 4 2 2 0 0 1 2 3 4 V 0 0 6 0.2
Infineon Technologies
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Abstract: 10.0 10 3.2 × 1.6 × 1.6 (EIA code: 1206) CH8 Description CH8 uses an external FET. It is , 20 1.6 × 0.8 × 0.8 (EIA code: 0603) Table 29. Recommended Parts for FET (CH8) VENDOR TYPE , -channel switching dc/dc converter, and seven channels have integrated power FET. CH2/4 are configured for H bridge , TPS65530ARSLR TOP-SIDE MARKING TPS65530A Package drawings, thermal data, and symbolization are available , FET 3 SW4I I Boost-side terminal of coil for CH4 4 VOUT4 O Output of CH4 5 Texas Instruments
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SLVS835C ISO/TS16949

DEVICE MARKING CODE 41

Abstract: Code sot-23 on semiconductor -23 package has a device marking and a date code etched on the device. The generic example below depicts both the device marking and a representation of the date code that appears on the SOT-23 package. ABCD , ANY FET product. Precautions include, but are not limited to, the implementation of static safe workstations and proper han dling techniques. Additionally, it is very important to keep FET devices in their , Fold Box Add an "RLR" suffix and the appropriate Style code* to the device title to order the Fan Fold
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DEVICE MARKING CODE 41 Code sot-23 on semiconductor sot23 markings marking CODE box SOT23 sot markings marking 41 sot23 318D-04 SC-59 318E-04 318G-02 SC-70/SOT-323
Abstract: × 1.15 (EIA code: 1206) Table 25. Recommended Parts for FET (CH8) VENDOR TYPE NO. ID (DC , -channel switching dc/dc converter, and seven channels have integrated power FET. CH2/4 are configured for H bridge , TPS65530RSLR TOP-SIDE MARKING TPS65530 Package drawings, thermal data, and symbolization are available , FET 3 SW4I I Boost-side terminal of coil for CH4 4 VOUT4 O Output of CH4 5 , . 12 VCC2 P Power supply at CH2 buck-side FET from battery 13 SW2S O Buck-side Texas Instruments
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SLVS744C
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