FDC37N3869 82077AA NS16C550 FDC37N3869-MD 16C550 FDC37N869 CLK33 CLK14 A0-A15 - Datasheet Archive

 

3.3V Super I/O Controller with Infrared Support for Portable Applications FEATURES PC 99 Compliant 3.3 Volt Operation (5V

 

FDC37N3869 FDC37N3869 3.3V Super I/O Controller with Infrared Support for Portable Applications FEATURES PC 99 Compliant 3.3 Volt Operation (5V Tolerant ) Intelligent Auto Power Management 16 Bit Address Qualification 2.88MB Super I/O Floppy Disk Controller - Licensed CMOS 765B Floppy Disk Controller - Software and Register Compatible with SMSC's Proprietary 82077AA 82077AA Compatible Core - Supports One Floppy Drive Directly - Configurable Open Drain/Push-Pull Output Drivers - Supports Vertical Recording Format - 16 Byte Data FIFO - 100% IBM Compatibility - Detects All Overrun and Underrun Conditions - Sophisticated Power Control Circuitry (PCC) Including Multiple Power-Down Modes for Reduced Power Consumption - DMA Enable Logic - Data Rate and Drive Control Registers - Swap Drives A and B - Non-Burst Mode DMA Option - 48 Base I/O Address, 15 IRQ and 4 DMA Options - Forceable Write Protect and Disk Change Controls Floppy Disk Available on Parallel Port Pins ACPI Compliant Enhanced Digital Data Separator - 2Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates - Programmable Precompensation Modes Serial Ports - Two High Speed NS16C550 NS16C550 Compatible UARTs with Send/Receive 16 Byte FIFOs - Supports 230k and 460k Baud - Programmable Baud Rate Generator - Modem Control Circuitry Infrared Communications Controller - IrDA v1.1 (4Mbps), HPSIR, ASKIR, Consumer IR Support - 2 IR Ports - 96 Base I/O Address, 15 IRQ Options and 4 DMA Options Multi-Mode Parallel Port with ChiProtect - Standard Mode - IBM PC/XT, PC/AT, and PS/2 Compatible Bidirectional Parallel Port - Enhanced Parallel Port (EPP) Compatible - EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) - Enhanced Capabilities Port (ECP) Compatible (IEEE 1284 Compliant) - Incorporates ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On - 192 Base I/O Address, 15 IRQ and 4 DMA Options Game Port Select Logic - 48 Base I/O Addresses General Purpose Address Decoder - 16-Byte Block Decode ORDERING INFORMATION Order Number: FDC37N3869-MD FDC37N3869-MD for 100 Pin TQFP Package SMSC DS ­ FDC37N3869 FDC37N3869 Rev, 10/25/2000 © STANDARD MICROSYSTEMS CORPORATION (SMSC) 2000 80 Arkay Drive Hauppauge, NY 11788 (631) 435-6000 FAX (631) 273-3123 Standard Microsystems is a registered trademark of Standard Microsystems Corporation, and SMSC is a trademark of Standard Microsystems Corporation. Product names and company names are the trademarks of their respective holders. Circuit diagrams utilizing SMSC products are included as a means of illustrating typical applications; consequently complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the semiconductor devices described any licenses under the patent rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES, OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT, TORT, NEGLIGENCE OF SMSC OR OTHERS, STRICT LIABILITY, BREACH OF WARRANTY, OR OTHERWISE; WHETHER OR NOT ANY REMEDY IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE; AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. SMSC DS ­ FDC37N3869 FDC37N3869 Page 2 Rev. 10/25/2000 GENERAL DESCRIPTION The SMSC FDC37N3869 FDC37N3869 is a 3.3v PC 99-compliant Super I/O Controller with Infrared support. The FDC37N3869 FDC37N3869 utilizes SMSC's proven SuperCell technology and is optimized for motherboard applications. The FDC37N3869 FDC37N3869 incorporates SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, 16-byte data FIFO, two 16C550 16C550 compatible UARTs, one Multi-Mode parallel port with ChiProtect circuitry plus EPP and ECP support, game port chip select logic and one floppy direct drive support. The FDC37N3869 FDC37N3869 does not require any external filter components, is easy to use and offers lower system cost and reduced board area. The FDC37N3869 FDC37N3869 is software and register compatible with SMSC's proprietary 82077AA 82077AA core. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and provides data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC's patented data separator technology allowing for ease of testing and use. The FDC37N3869 FDC37N3869 supports both 1Mbps and 2Mbps data rates and vertical recording operation at 1Mbps Data Rate. The FDC37N3869 FDC37N3869 also features a full 16-bit internally decoded address bus, a Serial IRQinterface with PCI nCLKRUN support, relocatable configuration ports and four DMA channel options. Both on-chip UARTs are compatible with the NS16C550 NS16C550. One UART includes additional support for a Serial Infrared Interface that complies with IrDA v1.2 (Fast IR), HPSIR, and ASKIR formats (used by Sharp, Apple Newton, and other PDAs), as well as Consumer IR. The parallel port and the game port select logic are compatible with IBM PC/AT architectures. The parallel port ChiProtect circuitry prevents damage caused by an attached powered printer when the FDC37N3869 FDC37N3869 is not powered. The FDC37N3869 FDC37N3869 incorporates sophisticated power control circuitry (PCC). The PCC supports multiple low power down modes. The FDC37N3869 FDC37N3869 also features Software Configurable Logic (SCL) for ease of use. SCL allows programmable system configuration of key functions such as the FDC, parallel port, and UARTs. SMSC DS ­ FDC37N3869 FDC37N3869 Page 3 Rev. 10/25/2000 TABLE OF CONTENTS FEATURES .1 GENERAL DESCRIPTION.3 PIN CONFIGURATION .8 PIN DESCRIPTION .9 BUFFER TYPE PER PIN .9 BUFFER TYPE SUMMARY .15 OUTPUT DRIVERS .16 FUNCTIONAL DESCRIPTION.17 HOST PROCESSOR INTERFACE .17 FLOPPY DISK CONTROLLER.17 MODES OF OPERATION .17 Floppy Modes.17 Interface Modes .18 FLOPPY DISK CONTROLLER INTERNAL REGISTERS .18 STATUS REGISTER A (SRA) .18 STATUS REGISTER B (SRB) .21 DIGITAL OUTPUT REGISTER (DOR) .23 TAPE DRIVE REGISTER (TDR).24 MAIN STATUS REGISTER (MSR).25 DATA RATE SELECT REGISTER (DSR) .26 DATA REGISTER (FIFO) .28 DIGITAL INPUT REGISTER (DIR).28 CONFIGURATION CONTROL REGISTER (CCR) .29 STATUS REGISTER ENCODING .31 RESET .32 RESET Pin (Hardware Reset) .32 DOR Reset vs. DSR Reset (Software Reset) .33 DMA TRANSFERS .33 CONTROLLER PHASES .33 Command Phase .33 Execution Phase .33 Result Phase .34 COMMAND SET/DESCRIPTIONS .35 INSTRUCTION SET.37 DATA TRANSFER COMMANDS .43 Read Data.43 Read Deleted Data .45 Read A Track .45 Write Data .46 Write Deleted Data.47 Verify .47 Format A Track.48 CONTROL COMMANDS .49 Read ID.49 Recalibrate .49 Seek .50 Sense Interrupt Status .50 Sense Drive Status .51 Specify .51 SMSC DS ­ FDC37N3869 FDC37N3869 Page 4 Rev. 10/25/2000 Configure .51 Version.52 Relative Seek .52 Perpendicular Mode .52 LOCK .53 ENHANCED DUMPREG.54 COMPATIBILITY.54 PARALLEL PORT FLOPPY DISK CONTROLLER .54 SERIAL PORT (UART) .56 REGISTER DESCRIPTION .56 RECEIVE BUFFER REGISTER (RB) .56 TRANSMIT BUFFER REGISTER (TB).56 INTERRUPT ENABLE REGISTER (IER).56 INTERRUPT IDENTIFICATION REGISTER (IIR) .57 FIFO CONTROL REGISTER (FCR) .58 LINE CONTROL REGISTER (LCR) .59 MODEM CONTROL REGISTER (MCR) .60 LINE STATUS REGISTER (LSR) .61 MODEM STATUS REGISTER (MSR) .62 SCRATCHPAD REGISTER (SCR).62 PROGRAMMABLE BAUD RATE GENERATOR DIVISOR LATCHES .63 The Affects of RESET on the UART Registers .63 FIFO INTERRUPT MODE OPERATION .64 FIFO POLLED MODE OPERATION .64 NOTES ON SERIAL PORT FIFO MODE OPERATION .66 GENERAL.66 TX AND RX FIFO OPERATION .66 INFRARED INTERFACE .67 IRDA SIR/FIR AND ASKIR .67 CONSUMER IR .67 HARDWARE INTERFACE .68 IR HALF DUPLEX TURNAROUND DELAY TIME .69 PARALLEL PORT.70 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES .71 DATA PORT.71 STATUS PORT.71 CONTROL PORT .72 EPP ADDRESS PORT .72 EPP DATA PORT 0 .72 EPP DATA PORT 1 .73 EPP DATA PORT 2 .73 EPP DATA PORT 3 .73 EPP 1.9 OPERATION .73 Software Constraints .73 EPP 1.9 Write .73 EPP 1.9 Read.74 EPP 1.7 OPERATION .75 Software Constraints .75 EPP 1.7 Write .75 EPP 1.7 Read.75 EXTENDED CAPABILITIES PARALLEL PORT .77 Vocabulary .77 ISA IMPLEMENTATION STANDARD .78 Description.78 Register Definitions.78 SMSC DS ­ FDC37N3869 FDC37N3869 Page 5 Rev. 10/25/2000 OPERATION .84 AUTO POWER MANAGEMENT .87 FDC POWER MANAGEMENT .88 DSR From Powerdown .88 Wake Up From Auto Powerdown .88 Register Behavior.88 Pin Behavior.89 UART POWER MANAGEMENT .91 PARALLEL PORT .91 SERIAL IRQ .91 Introduction .91 IRQSER Cycle Modes .92 IRQSER IRQ/Data Frames.93 Stop Cycle Control .94 Latency .94 EOI/ISR Read Latency .94 AC/DC Specification Issue .94 Reset and Initialization.94 ADD PCI NCLKRUN SUPPORT .94 Overview .94 Using nCLKRUN .95 CONFIGURATION .96 CONFIGURATION ACCESS PORTS .96 CONFIGURATION STATE .96 Entering the Configuration State .96 Configuration Register Programming .97 Exiting the Configuration State.97 Programming Example .97 Configuration Select Register (CSR).97 CONFIGURATION REGISTERS DESCRIPTION .98 CR00 .99 CR01 .99 CR02 .100 CR03 .100 CR04 .101 CR05 .102 CR06 .102 CR07 .103 CR08 .103 CR09 .103 CR0A .104 CR0B .104 CR0C .105 CR0D .105 CR0E .105 CR0F .105 CR10 .106 CR11 .106 CR12 - CR13 .106 CR14 .107 CR15 .107 CR16 .107 CR17 .107 CR18 - CR1D .108 CR1E .108 CR1F .108 SMSC DS ­ FDC37N3869 FDC37N3869 Page 6 Rev. 10/25/2000 CR20 .109 CR21 .109 CR23 .109 CR24 .110 CR25 .110 CR26 .110 CR27 .111 CR28 .111 CR29 .112 CR2A .112 CR2B .112 CR2C .112 CR2D .112 CR2E .113 CR2F .113 OPERATIONAL DESCRIPTION .114 MAXIMUM GUARANTEED RATINGS .114 DC ELECTRICAL CHARACTERISTICS .114 AC TIMING .117 HOST TIMING .117 FDD TIMING .121 SERIAL PORT TIMING.122 PARALLEL PORT TIMING .127 Parallel Port EPP Timing .128 Parallel Port ECP Timing .133 PACKAGE OUTLINES.136 SMSC DS ­ FDC37N3869 FDC37N3869 Page 7 Rev. 10/25/2000 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nSTROBE nAUTOFD nERROR nINIT nSLCT VCC PD0 PD1 PD2 PD3 VSS PD4 PD5 PD6 PD7 nACK BUSY PE SLCT PWRGD RESET_DRV D7 D6 D5 D4 PIN CONFIGURATION 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 FDC37N869 FDC37N869 FDC37N3869 FDC37N3869 100 PIN TQFP 100 PIN TQFP 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 DRQ_B D3 D2 D1 D0 VSS AEN nIOW nIOR A9 A8 A7 CLK33 CLK33 SIRQ A12 A11 nDACK_B TC A6 A5 A4 A3 A2 A1 A0 A13 nDS0 A14 VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT VCC nRDATA nDSKCHG DRVDEN1 DRQ_D CLK14 CLK14 DRQ_A nDACK_A IRMODE/IRRX3 nDACK_D IRRX2 IRTX2 A15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 RXD1 TXD1 nDSR1 nRTS1 nCTS1 nDTR1 nRI1 nDCD1 nRI2 nDCD2 RXD2 TXD2 nDSR2 nRTS2 nCTS2 nDTR2 nADRX/nCLKRUN VSS nDACK_C A10 IRQIN DRQ_C IOCHRDY DRVDEN0 nMTR0 FIGURE 1 - FDC37N3869 FDC37N3869 PIN CONFIGURATION SMSC DS ­ FDC37N3869 FDC37N3869 Page 8 Rev. 10/25/2000 PIN DESCRIPTION Buffer Type Per Pin TQFP PIN # 46-49 51-54 NAME Table 1 - Description Of Pin Functions BUFFER 6 MODE SYMBOL DESCRIPTION Data Bus 0-7 D0-D7 42 nI/O Read nIOR 43 nI/O Write nIOW 44 Address Enable AEN 26-32 39-41, 95,35, 36,1, 3,25 19,50, 97,17 Address Bus A0-A15 A0-A15 DMA Request A, B, C, D DRQ_A DRQ_B DRQ_C DRQ_D 20,34, 94,22 nDMA Acknowledge A, B, C, D 33 Terminal Count nDACK_A nDACK_B nDACK_C nDACK_D TC 37 Serial IRQ SIRQ 38 PCI Clock CLK33 CLK33 55 Reset RESET_ DRV 98 I/O Channel Ready 4 (Note ) IOCHRDY 14 nRead Disk Data nRDATA SMSC DS ­ FDC37N3869 FDC37N3869 HOST PROCESSOR INTERFACE IO12 The data bus connection used by the host microprocessor to transmit data to and from the chip. These pins are in a high-impedance state when not in the output mode. IS This active low signal is issued by the host microprocessor to indicate an I/O read operation. IS This active low signal is issued by the host microprocessor to indicate an I/O write operation. IS Active high Address Enable indicates DMA operations on the host data bus. Used internally to qualify appropriate address decodes. I These host address bits determine the I/O address to be accessed during nIOR and nIOW cycles. These bits are latched internally by the leading edge of nIOR and nIOW. All internal address decodes use the full A0 to A15 address bits. O12 IS These active high outputs are the DMA request for byte transfers of data between the host and the chip. These signals are cleared on the last byte of the data transfer by the nDACK signal going low (or by nIOR going low if nDACK was already low as in demand mode). These are active low inputs acknowledging the request for a DMA transfer of data between the host and the chip. These inputs enable the DMA read or write internally. IS This signal indicates that DMA data transfer is complete. TC is only accepted when nDACK_x is low. In AT and PS/2 model 30 modes, TC is active high and in PS/2 mode, TC is active low. IO12 Serial IRQ pin used with the CLK33 CLK33 pin to transfer FDC37N3869 FDC37N3869 interrupts to the host. ICLK 33MHz PCI clock input, used with the SIRQ and the nCLKRUN pins to serially transfer FDC37N3869 FDC37N3869 interrupts to the host. IS This active high signal resets the chip and must be valid for 500ns minimum. The effect on the internal registers is described in the appropriate section. The configuration registers are not affected by this reset. OD12 This pin is pulled low to extend the read/write command. IOCHRDY can used by the IRCC and by the Parallel Port in EPP mode. FLOPPY DISK INTERFACE IS Raw serial bit stream from the disk drive, low active. Each falling edge represents a flux transition of the encoded data. Page 9 Rev. 10/25/2000 TQFP PIN # 8 BUFFER 6 MODE NAME nWrite Gate SYMBOL nWGATE (O12/ OD12) 7 nWrite Data nWDATA (O12/ OD12) 9 nHead Select nHDSEL (O12/ OD12) 5 Direction Control nDIR (O12/ OD12) 6 nStep Pulse nSTEP (O12/ OD12) 15 Disk Change nDSKCHG 2 nDrive Select 0 nMotor On 0 Drive Density 0 nWrite Protected 100 99 12 11 wTrack 00 10 nIndex 16 Drive Density 1 86 Receive Data 2 Transmit Data 2 5 (Note ) Receive Data 1 Transmit Data 1 87 76 77 SMSC DS ­ FDC37N3869 FDC37N3869 nDS0 IS (O12/ OD12) DESCRIPTION This active low high current driver allows current to flow through the write head. It becomes active just prior to writing to the diskette. This active low high current driver provides the encoded data to the disk drive. Each falling edge causes a flux transition on the media. This high current output selects the floppy disk side for reading or writing. A logic "1" on this pin means side 0 will be accessed, while a logic "0" means side 1 will be accessed. This high current low active output determines the direction of the head movement. A logic "1" on this pin means outward motion, while a logic "0" means inward motion. This active low high current driver issues a low pulse for each track-to-track movement of the head. This input senses that the drive door is open or that the diskette has possibly been changed since the last drive selection. This input is inverted and read via bit 7 of I/O address 3F7H. The nDSKCHG bit also depends upon the state of the Force Disk Change bits in the Force FDD Status Change configuration register (see section CR17 on page 107). Active low output selects drive 0. nMTR0 DRVDEN0 (O12/ OD12) These active low output selects motor drive 0. (O12/ OD12) Indicates the drive and media selected. Refer to configuration registers CR03, CR0B, CR1F. nWRTPRT IS This active low Schmitt Trigger input senses from the disk drive that a disk is write protected. Any write command is ignored. The nWRPRT bit also depends upon the state of the Force Write Protect bit in the Force FDD Status Change configuration register (see section CR17 on page 107). nTRK0 IS This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the outermost track. nINDEX IS This active low Schmitt Trigger input senses from the disk drive that the head is positioned over the beginning of a track, as marked by an index hole. DRVDEN 1 (O12/ OD12) Indicates the drive and media selected. Refer to configuration registers CR03, CR0B, CR1F. SERIAL PORTS INTERFACE RXD2 IS Receiver serial data input for port 2. IR Receive Data TXD2 O12PD O12PD Transmit serial data output for port 2. IR transmit data. RXD1 I Receiver serial data input for port 1. TXD1 O12 Transmit serial data output for port 1. Page 10 Rev. 10/25/2000 TQFP PIN # 79,89 NAME nRequest to Send (System Option) 81,91 80,90 SYMBOL nRTS1 BUFFER 6 MODE O6 nRTS2 (SYSOPT) nData Terminal Ready nDTR1 nClear to Send nCTS1 O6 nDTR2 I nCTS2 78,88 nData Set Ready nDSR1 I nDSR2 83,85 nData Carrier Detect SMSC DS ­ FDC37N3869 FDC37N3869 nDCD1 nDCD2 I DESCRIPTION Active low Request to Send outputs for the Serial Port. Handshake output signal notifies modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of the Modem Control Register (MCR). The hardware reset will reset the nRTS signal to inactive mode (high). nRTS is forced inactive during loop mode operation. At the trailing edge of hardware reset the nRTS2 inputs is latched to determine the configuration base address: 0 = INDEX Base I/O Address 3F0 Hex; 1 = INDEX Base I/O Address 370 Hex. Active low Data Terminal Ready outputs for the serial port. Handshake output signal notifies modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will reset the nDTR signal to inactive mode (high). nDTR is forced inactive during loop mode operation. Active low Clear to Send inputs for the serial port. Handshake signal which notifies the UART that the modem is ready to receive data. The CPU can monitor the status of nCTS signal by reading bit 4 of Modem Status Register (MSR). A nCTS signal state change from low to high after the last MSR read will set MSR bit 0 to a 1. If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when nCTS changes state. The nCTS signal has no effect on the transmitter. Note: Bit 4 of MSR is the complement of nCTS. Active low Data Set Ready inputs for the serial port. Handshake signal which notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of nDSR signal by reading bit 5 of Modem Status Register (MSR). A nDSR signal state change from low to high after the last MSR read will set MSR bit 1 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDSR changes state. Note: Bit 5 of MSR is the complement of nDSR. Active low Data Carrier Detect inputs for the serial port. Handshake signal which notifies the UART that carrier signal is detected by the modem. The CPU can monitor the status of nDCD signal by reading bit 7 of Modem Status Register (MSR). A nDCD signal state change from low to high after the last MSR read will set MSR bit 3 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nDCD changes state. Note: Bit 7 of MSR is the complement of nDCD. Page 11 Rev. 10/25/2000 TQFP PIN # 82,84 NAME nRing Indicator SYMBOL nRI1 BUFFER 6 MODE I 1 (Note ) nRI2 TQFP PIN # NAME 71 nPrinter Select Input/FDC nStep Pulse 3 (Note ) 72 nInitiate Output/ FDC nDirection Control 3 (Note ) 74 nAutofeed Output/ FDC nDensity Select 3 (Note ) SYMBOL DESCRIPTION Active low Ring Indicator inputs for the serial port. Handshake signal which notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the status of nRI signal by reading bit 6 of Modem Status Register (MSR). A nRI signal state change from low to high after the last MSR read will set MSR bit 2 to a 1. If bit 3 of Interrupt Enable Register is set, the interrupt is generated when nRI changes state. Note: Bit 6 of MSR is the complement of nRI. BUFFER 6 MODE nDIR nAUTOFD nDENSEL 75 nSTROBE nStrobe Output/ FDC nDrive Select 0 3 (Note ) 59 Busy/ FDC nMotor On 1 nDS0 BUSY See FDC Pin definition. (OD14/OP14 OD14/OP14)/OD12 /OD12 This output goes low to cause the printer to automatically feed one line after each line is printed. The nAUTOFD output is the complement of bit 1 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. See FDC Pin definition. (OD14/OP14 OD14/OP14)/OD12 /OD12 An active low pulse on this output is used to strobe the printer data into the printer. The nSTROBE output is the complement of bit 0 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. See FDC Pin definition. I/OD12 I/OD12 nMTR1 SMSC DS ­ FDC37N3869 FDC37N3869 DESCRIPTION PARALLEL PORT INTERFACE (NOTE 2) nSLCT (OD14/OP14 OD14/OP14)/OD12 /OD12 This active low output selects the printer. This is the complement of bit 3 of the Printer Control Register. Refer to Parallel Port description for use of this pin in ECP and EPP mode. See FDC Pin definition. nSTEP nINIT (OD14/OP14 OD14/OP14)/OD12 /OD12 This output is bit 2 of the printer control register. This is used to initiate the printer when low. Refer to Parallel Port description for use of this pin in ECP and EPP mode. Page 12 This is a status output from the printer, a high indicating that the printer is not ready to receive new data. Bit 7 of the Printer Status Register is the complement of the BUSY input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. See FDC Pin definition. Rev. 10/25/2000 TQFP PIN # 60 NAME nAcknowledge/FDC nDrive Select 1 SYMBOL nACK BUFFER 6 MODE I/OD12 I/OD12 nDS1 58 Paper End/ PE FDC nWrite Data I/OD12 I/OD12 nWRDATA 57 73 SLCT Printer Selected Status/ FDC nWrite Gate nWGATE nError/FDC nERROR nHead Select I/OD12 I/OD12 I/OD12 I/OD12 PD0 IOP14/IS IOP14/IS A low on this input from the printer indicates that there is a error condition at the printer. Bit 3 of the Printer Status register reads the nERR input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. See FDC Pin definition. Port Data 0 nINDEX PD1 IOP14/IS IOP14/IS See FDC Pin definition. Port Data 1 nTRK0 PD2 IOP14/IS IOP14/IS See FDC Pin definition. Port Data 2 nHDSEL 69 Port Data 0/FDC nIndex 68 Port Data 1/FDC nTrack 0 67 Port Data 2/FDC nWrite Protected Port Data 3/FDC nRead Disk Data Port Data 4/FDC nDisk Change Port Data 5 Port Data 6/FDC nMotor On 0 Port Data 7 66 64 63 62 61 SMSC DS ­ FDC37N3869 FDC37N3869 DESCRIPTION A low active output from the printer indicating that it has received the data and is ready to accept new data. Bit 6 of the Printer Status Register reads the nACK input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. See FDC Pin definition. Another status output from the printer, a high indicating that the printer is out of paper. Bit 5 of the Printer Status Register reads the PE input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. See FDC Pin definition. This high active output from the printer indicates that it has power on. Bit 4 of the Printer Status Register reads the SLCT input. Refer to Parallel Port description for use of this pin in ECP and EPP mode. See FDC Pin definition. nWRTPRT PD3 See FDC Pin definition. IOP14/IS IOP14/IS nRDATA PD4 See FDC Pin definition. IOP14/IS IOP14/IS nDSKCHG PD5 PD6 Port Data 4 See FDC Pin definition. IOP14 IOP14 IOP14/ IOP14/ OD12 nMTR0 PD7 Port Data 3 Port Data 5 Port Data 6 See FDC Pin definition. IOP14 IOP14 Page 13 Port Data 7 Rev. 10/25/2000 TQFP PIN # 18 23 24 92 21 NAME 14.318 MHz Input Clock IR Receive 2 SYMBOL CLK14 CLK14 IRRX2 BUFFER 6 MODE DESCRIPTION ALTERNATE IR PINS/MISC ICLK The external connection to a single source 14.318 MHz clock. IS IR Receive input IR Transmit 2 5 (Note ) Address X/ PCI Clock Controller IRTX2 O12PD O12PD IR transmit output nADRX/ nCLKRUN OD12/ OD12/ IOD12 IOD12 IR Mode/ IR Receive 3 IRMODE/ IRRX3 O6/IS The active-low address decoder output nADRX can be asserted on 1, 8, or 16-byte address boundaries (an external pull-up is required). Refer to configuration registers CR03, CR08, and CR09 for more information. nCLKRUN is used to indicate the PCI clock status and to request that a stopped clock be started. IR mode IR Receive 3 56 Power Good/ nGame Port Chip Select PWRGD nGAMECS 96 13,70 4,45, 65,93 Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: External IRQIN Interrupt Input Power Ground VCC VSS I/O4 This active high input indicates that the power (VCC) is valid. For device operation PWRGD must be active. When PWRGD is inactive, all inputs are disconnected and put into a low power mode; all outputs are put into high impedance. The contents of all registers are preserved as long as VCC is valid. The output driver current drain when PWRGD is inactive mode drops to ISTBY - standby current. This is the Game Port Chip Select output - active low. It will go active when the I/O address, qualified by AEN, matches that selected in Configuration register CR1E. IS This pin is used to steer an interrupt signal from an external device onto one of 15 IRQs. POWER INTERFACE Positive Supply Voltage. (3.3V) Ground Supply. nRI and the UART interrupts are active when PWRGD is active and the UARTS are either fully powered or in AUTOPOWER DOWN mode. The FDD output pins multiplexed in the PARALLEL PORT INTERFACE are OD drivers only and are not affected by the FDD Output Driver Controls (see section CR05 on page 102). Active (push-pull) output drivers are required on these pins in the enhanced parallel port modes. An external pull-up must be provided for IOCHRDY. The pull-down on this pin is always active including when the output driver is tristated and regardless of the state of PWRGD. Buffer Modes describe the pad driver properties per function. Buffer Modes on multiplexed pins are separated by a slash "/". For example, the Buffer Modes for a multiplexed pin with two functions where the primary function is an input and the secondary function is an 8mA bidirectional driver is "I/IO8". Buffer Modes in parenthesis represent multiple Buffer Modes for a single pin function. SMSC DS ­ FDC37N3869 FDC37N3869 Page 14 Rev. 10/25/2000 Buffer Type Summary Table 2 below describes the buffer types shown in Table 1. All values are specified at Vcc = +3.3v, ±10% Table 2 - FDC37N3869 FDC37N3869 Buffer Type Summary (See Note) BUFFER TYPE DESCRIPTION IO12 Input/Output. 12mA sink; 6mA source O12 Output. 12mA sink; 6mA source O12PD O12PD Output. 12mA sink; 6mA source with 30µa pull-down OD12 Open Drain. 12mA sink O6 Output. 6mA sink; 3mA source OD14 Open Drain. 14mA sink OP14 Output. 14mA sink; 14mA source. Backdrive Protected IOP14 IOP14 Input/Output. 14mA sink; 14mA source. Backdrive Protected O4 Output. 4mA sink; 2mA source ICLK Input to Crystal Oscillator Circuit (TTL levels) I Input TTL Compatible IS Input with Schmitt Trigger IOD12 IOD12 Input/Open Drain Output. 12mA sink Note: These are minimum ratings guaranteed at 3.3V. SMSC DS ­ FDC37N3869 FDC37N3869 Page 15 Rev. 10/25/2000 Output Drivers Active output drivers in the FDC37N3869 FDC37N3869 will always achieve the minimum specified DC Electrical Characteristics shown in Table 120. Note: If there is a pull-up on an external node driven by an active output driver the FDC37N3869 FDC37N3869 may sink current from the pull-up through the low impedance source. Vcc (2) Vss (4) PWRGD/nGAMECS POWER MANAGEMENT MULTI-MODE PARALLEL PORT/FDC MUX DATA BUS nCS ADDRESS BUS nIOR nSLCTIN/nSTEP,nINI T/nDIR, nAUTOFD/ nDENSEL, nSTROBE/nDS0, BUSY/nMTR1, nACK/nDS1, PE/nWRDATA,nERR OR/nHDSEL, PD0/nINDEX, PD1/nTRK0, PD2/nWRTPRT, PD3/nRDATA, PD4/nDSKCHG, PD5/ PD6/nMTR, PD7 nIOW CONFIGURATION AEN 16C550 16C550 COMPATIBLE SERIAL PORT 1 REGISTERS A0-A15 A0-A15 nDSR1, nDCD1, nRI, nDTR1 CONTROL BUS D0-D7 DRQ_A-D HOST CPU INTERFACE WDATA nDACK_A-D WCLOCK SMSC PROPRIETARY 82077 COMPATIBLE TC SIRQ DIGITAL 16C550 16C550 COMPATIBLE SERIAL PORT 2 WITH INFRARED IR Mode/IRR3 TXD2/IRTX,nCTS2, nRTS2 RXD2/IRRX nDSR2,nDCD2, nRI2,nDTR2 DATA SEPARATOR WITH WRITE VERTICAL FLOPPYDISK CONTROLLER CORE CLK33 CLK33 TXD1, nCTS1, nRTS1, RXD1 PRECOMPENSATION RCLOCK nADRX/nCLKRUN RESET RDATA IRQIN IR IRRX2, IRTX2 CLOCK IOCHRDY GEN nINDEX 14.318 CLOCK nDIR nTRK0 nSTEP nDSKCHG DRVDEN0 nDS0 nMTR0 nHDSEL nWRPRT DRVDEN1 nRDATA nWDATA GAME PORT DECODER See Power Mgt nWGATE FIGURE 2 - FDC37N3869 FDC37N3869 BLOCK DIAGRAM SMSC DS ­ FDC37N3869 FDC37N3869 Page 16 Rev. 10/25/2000 FUNCTIONAL DESCRIPTION Super I/O Registers Table 3 shows the addresses of the various device blocks of the Super I/O immediately after power up. The base addresses must be set in the configuration registers before accessing these devices. The base addresses of the FDC, Serial and Parallel Ports can be moved via the configuration registers. Host Processor Interface The host processor communicates with the FDC37N3869 FDC37N3869 using the Super I/O registers. Register access is accomplished through programmed I/O or DMA transfers. All registers are 8 bits wide. All host interface output buffers are capable of sinking a minimum of 12 mA. ADDRESS 3F0, 3F1 or 370, 371 Base +[0:7] Base +[0:7] Base1 +[0:7] Base2 +[0:7] Base +[0:3] all modes Base +[4:7] for EPP Base +[400:403] for ECP Table 3 - FDC37N3869 FDC37N3869 Block Addresses BLOCK NAME NOTES Configuration Write only; Note 1 Floppy Disk Disabled at power up; Note 2 Serial Port Com 1 Disabled at power up; Note 2 Serial Port Com 2 Disabled at power up; Note 2 Parallel Port Disabled at power up; Note 2 Note 1: Configuration registers can only be modified in the configuration state, refer to section CONFIGURATION on page 96 for more information. All logical blocks in the FDC37N3869 FDC37N3869 can operate normally in the Configuration State. Note 2: The base addresses must be set in the configuration registers before accessing device blocks. FLOPPY DISK CONTROLLER The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection. The FDC37N3869 FDC37N3869 is compatible with the 82077AA 82077AA using SMSC's proprietary floppy disk controller core. For information about the floppy disk on the Parallel Port pins refer to section Parallel Port Floppy Disk Controller on page 54. Modes Of Operation The FDC37N3869 FDC37N3869 Floppy Disk Controller has two Floppy modes and three Interface modes. Each of the three Interface modes are available in each of the two Floppy modes. FLOPPY MODES The Floppy modes are used to select alternate configurations for the Tape Drive register. The active Floppy mode is determined by the Enhanced Floppy Mode 2 bit in Configuration Register 3 (see section CR03 on page 100). When the Enhanced Floppy Mode 2 bit is 0 Normal Floppy mode is selected, otherwise Enhanced Floppy Mode 2 (OS/2 mode) is selected. See section TAPE DRIVE REGISTER (TDR) on page 24 for the affects of the Enhanced Floppy Mode 2 bit on the Tape Drive register. SMSC DS ­ FDC37N3869 FDC37N3869 Page 17 Rev. 10/25/2000 INTERFACE MODES The Interface modes are determined by the MFM and IDENT configuration bits in Configuration Register 3 (see section CR03 on page 100). PC/AT Interface Mode When both IDENT and MFM are high the PC/AT register set is enabled, the DMA enable bit of the Digital Output Register becomes valid, FINTR and DRQ can be hi-Z, and TC and DENSEL become active high. PS/2 Interface Mode When IDENT is low and MFM is high PS/2 Interface mode is selected. This mode supports the PS/2 models 50/60/80 configuration and register set. The DMA bit of the Digital Output Register becomes a "don't care," FINTR and DRQ are always valid, TC and DENSEL become active low. Model 30 Interface Mode When both IDENT and MFM are low Model 30 Interface Mode is selected. This mode supports PS/2 Model 30 configuration and register set. The DMA enable bit of the Digital Output Register becomes valid, FINTR and DRQ can be hi-Z, TC is active high and DENSEL is active low. Floppy Disk Controller Internal Registers The Floppy Disk Controller contains eight internal registers that provide the interface between the host microprocessor and the floppy disk drives. Table 4 shows the addresses required to access these registers. Registers other than the ones shown are not supported. Table 4 - Status, Data and Control Registers BASE I/O ADDRESS +0 +1 +2 +3 +4 +4 +5 +6 +7 +7 R R R/W R/W R W R/W R W REGISTER Status Register A Status Register B Digital Output Register Tape Drive Register Main Status Register Data Rate Select Register Data (FIFO) Reserved Digital Input Register Configuration Control Register SRA SRB DOR TDR MSR DSR FIFO DIR CCR STATUS REGISTER A (SRA) Status Register A (Base Address + 0) monitors the state of the FINTR pin and several disk interface pins in PS/2 interface mode (Table 5) and Model 30 interface mode (Table 6). SRA is read-only and can be accessed at any time when in these modes. During a read in the PC/AT interface mode the data bus pins D0 - D7 are held in a high impedance state. SMSC DS ­ FDC37N3869 FDC37N3869 Page 18 Rev. 10/25/2000 PS/2 Interface Mode RESET CONDITION 7 INT PENDING 0 6 nDRV2 Table 5 - SRA PS/2 Mode 5 4 3 STEP nTRK0 HDSEL 1 0 N/A 0 2 nINDX 1 nWP 0 DIR N/A N/A 0 Direction, Bit 0 Active high status indicating the direction of head movement. A logic "1" indicating inward direction, a logic "0" outward. nWRITE PROTECT, Bit 1 Active low status of the WRITE PROTECT disk interface input. A logic "0" indicating that the disk is write protected. The nWRITE PROTECT bit also depends upon the state of the Force Write Protect bits in the Force FDD Status Change configuration register (see section CR17). nINDEX, Bit 2 Active low status of the INDEX disk interface input. Head Select, Bit 3 Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0. nTRACK 0, Bit 4 Active low status of the TRK0 disk interface input. Step, Bit 5 Active high status of the STEP output disk interface output pin. nDRV2, Bit 6 The nDRV2 bit is always "1". Interrupt Pending, Bit 7 Active high bit indicating the state of the Floppy Disk Interrupt output. SMSC DS ­ FDC37N3869 FDC37N3869 Page 19 Rev. 10/25/2000 PS/2 Model 30 Interface Mode RESET CONDITION 7 INT PENDING 0 Table 6 - SRA PS/2 Model 30 Mode 6 5 4 3 DRQ STEP F/F TRK0 nHDSEL 0 0 N/A 1 2 INDX 1 WP 0 nDIR N/A N/A 1 nDIRECTION, Bit 0 Active low status indicating the direction of head movement. A logic "0" indicating inward direction a logic "1" outward. Write Protect, Bit 1 Active high status of the WRITE PROTECT disk interface input. A logic "1" indicating that the disk is write protected. The nWRITE PROTECT bit also depends upon the state of the Force Write Protect bits in the Force FDD Status Change configuration register (see section CR17 on page 109). Index, Bit 2 Active high status of the INDEX disk interface input. nHEAD SELECT, Bit 3 Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0. Track, Bit 4 Active high status of the TRK0 disk interface input. Step, Bit 5 Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset. DMA Request, Bit 6 Active high status of the DRQ output pin. Interrupt Pending, Bit 7 Active high bit indicating the state of the Floppy Disk Interrupt output. SMSC DS ­ FDC37N3869 FDC37N3869 Page 20 Rev. 10/25/2000 STATUS REGISTER B (SRB) Status Register B (Base Address + 1) is read-only and monitors the state of several disk interface pins in PS/2 interface mode (Table 7) and Model 30 interface mode (Table 8). SRB can be accessed at any time when in these modes. During a read in PC/AT interface mode the data bus pins D0 - D7 are held in a high impedance state. PS/2 Interface Mode 7 1 RESET CONDITION 6 1 1 1 Table 7 - SRB PS/2 Mode 5 4 3 DRIVE WDATA RDATA SEL0 TOGGLE TOGGLE 0 0 0 2 1 0 WGATE MOT EN1 MOT EN0 0 0 0 Motor Enable 0, Bit 0 Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. Motor Enable 1, Bit 1 Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. Write Gate, Bit 2 Active high status of the WGATE disk interface output. Read Data Toggle, Bit 3 Every inactive edge of the RDATA input causes this bit to change state. Write Data Toggle, Bit 4 Every inactive edge of the WDATA input causes this bit to change state. Drive Select 0, Bit 5 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset, it is unaffected by a software reset. Reserved, Bits 6 - 7 Always read as a logic "1". SMSC DS ­ FDC37N3869 FDC37N3869 Page 21 Rev. 10/25/2000 PS/2 Model 30 Interface Mode 7 nDRV2 RESET CONDITION 6 nDS1 N/A 1 Table 8 - SRB PS/2 Model 30 Mode 5 4 3 nDS0 WDATA RDATA F/F F/F 1 0 0 2 WGATE F/F 0 1 nDS3 0 nDS2 1 1 nDRIVE SELECT 2, Bit 0 Active low status of the DS2 disk interface output. nDRIVE SELECT 3, Bit 1 Active low status of the DS3 disk interface output. Write Gate, Bit 2 Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register. Read Data, Bit 3 Active high status of the latched RDATA output signal. This bit is latched by the inactive going edge of RDATA and is cleared by the read of the DIR register. Write Data, Bit 4 Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE. nDRIVE SELECT 0, Bit 5 Active low status of the DS0 disk interface output. nDRIVE SELECT 1, Bit 6 Active low status of the DS1 disk interface output. nDRV2, Bit 7 The nDRV2 bit is always "1". SMSC DS ­ FDC37N3869 FDC37N3869 Page 22 Rev. 10/25/2000 DIGITAL OUTPUT REGISTER (DOR) The Digital Output register (Base Address + 2) controls the drive select and motor enables of the disk interface outputs (Table 9 and Table 10). The DOR also contains the DMA logic enable and a software reset bit. The DOR is read/write and unaffected by a software reset. Table 9 - Digital Output Register 7 6 5 4 3 MOT EN3 MOT EN2 MOT EN1 MOT EN0 DMAEN RESET CONDITION 0 0 0 0 0 2 nRESET 0 1 DRIVE SEL1 0 0 DRIVE SEL0 0 DOR Bit Descriptions DRIVE SELECT, Bits 0 - 1 These two bits are binary encoded for the four drive selects DS0-DS3, there by allowing only one drive to be selected at one time. nRESET, Bit 2 A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. DMAEN, Bit 3 PC/AT and Model 30 Interface Mode In PC/AT and Model 30 mode writing this bit to logic "1" will enable the DRQ, nDACK, TC and FINTR outputs. This bit being a logic "0" will disable the nDACK and TC inputs, and hold the DRQ and FINTR outputs in a high impedance state. In PC/AT and Model 30 mode the DMAEN bit is a logic "0" after a reset. PS/2 Interface Mode In PS/2 mode the DRQ, nDACK, TC and FINTR pins are always enabled. During a reset the DRQ, nDACK, TC, and FINTR pins will remain enabled, but the DMAEN bit will be cleared to a logic "0". MOTOR ENABLE 0, Bit 4 This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active. MOTOR ENABLE 1, Bit 5 This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active. MOTOR ENABLE 2, Bit 6 The MOTOR ENABLE 2 bit controls the MTR2 disk interface output. A logic "1" in this bit will cause the output pin to go active. MOTOR ENABLE 3, Bit 7 The MOTOR ENABLE 3 bit controls the MTR3 disk interface output. A logic "1" in this bit causes the output to go active. Table 10 - Drive Activation Values DRIVE DOR VALUE 0 1CH 1 2DH 2 4EH 3 8FH Table 11 - Internal 2 Drive Decode: Drives 0 and 1 DRIVE SELECT OUTPUTS MOTOR ON OUTPUTS DIGITAL OUTPUT REGISTER (ACTIVE LOW) (ACTIVE LOW) Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0 X X X 1 0 0 1 0 nBIT 5 nBIT 4 SMSC DS ­ FDC37N3869 FDC37N3869 Page 23 Rev. 10/25/2000 X X 1 0 X 1 X 0 1 X X 0 X X X 0 0 1 1 X 1 0 1 X 0 1 1 1 1 1 1 1 nBIT 5 nBIT 5 nBIT 5 nBIT 5 nBIT 4 nBIT 4 nBIT 4 nBIT 4 TAPE DRIVE REGISTER (TDR) The Tape Drive register (Base Address + 3) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future reference to that drive automatically invokes tape support. The Tape Select bits TDR.[1:0] determine the tape drive number. Table 12 illustrates the Tape Select bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The encoding of the TDR depends on the Floppy mode (see section Floppy Modes on page 17). The TDR is unaffected by a software reset. Table 12 - Tape Select Bits TAPE SEL1 TAPE SEL0 DRIVE SELECTED (TDR.1) (TDR.0) 0 0 NONE 0 1 1 1 0 2 1 1 3 Normal Floppy Mode In Normal mode the TDR contains only bits 0 and 1 (Table 13). During a read in Normal mode TDR bits 2 - 7 are high impedance. The Tape Select Bits are Read/Write. TDR DB7 Tri-state Table 13 - TDR Normal Floppy Mode DB6 DB5 DB4 DB3 DB2 Tri-state Tri-state Tri-state Tri-state Tri-state DB1 Tape Sel1 DB0 Tape Sel0 Enhanced Floppy Mode 2 (OS2) The configuration of the TDR in the Enhanced Floppy Mode 2 (OS/2 mode) is shown in Table 14. DB7 TDR DB6 Reserved Table 14 - TDR Enhanced Floppy Mode 2 DB5 DB4 DB3 DB2 Drive Type ID Floppy Boot Drive DB1 DB0 Tape Sel1 Tape Sel0 Reserved, Bits 6 - 7 Bits 6 and 7 are RESERVED. Reserved bits cannot be written and return 0 when read. SMSC DS ­ FDC37N3869 FDC37N3869 Page 24 Rev. 10/25/2000 Drive Type ID, Bits 4 - 5 The Drive Type ID bits depend on the last drive selected in the Digital Output Register and the Drive Type IDs that are programmed in configuration register 6 (Table 15). Table 15 - Drive Type ID DIGITAL OUTPUT REGISTER TDR - DRIVE TYPE ID Bit 1 Bit 0 Bit 5 Bit 4 0 0 CR6 - Bit 1 CR6 - Bit 0 0 1 CR6 - Bit 3 CR6 - Bit 2 1 0 CR6 - Bit 5 CR6 - Bit 4 1 1 CR6 - Bit 7 CR6 - Bit 6 Floppy Boot Drive, Bits 2 - 3 The Floppy Boot Drive bits come from Configuration Register 7: TDR Bit 3 = CR7 Bit 1; TDR Bit 2 = CR7 Bit 0. Tape Drive Select, Bits 0 - 1 The Tape Drive Select bits are the same as in Normal mode. These bits are Read/Write. MAIN STATUS REGISTER (MSR) The Main Status Register (Base Address + 4: Read-only) indicates the status of the disk controller (Table 16). The Main Status Register is valid in all modes and can be read at any time. The MSR indicates when the disk controller is ready to receive data via the Data Register. It should be read before transferring each byte to or from the data register, except in DMA mode. No delay is required when reading the MSR after a data transfer. MSR 7 RQM 6 DIO Table 16 - Main Status Register 5 4 3 NON DMA CMD DRV3 BUSY BUSY 2 DRV2 BUSY 1 DRV1 BUSY 0 DRV0 BUSY DRVx Busy, Bits 0 - 3 These bits are set to a "1" when a drive is in the seek portion of a command, including implied and overlapped seeks and recalibrates. Command Busy, Bit 4 This bit is set to a "1" when a command is in progress. This bit will go active after the command byte has been accepted and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate commands), this bit is returned to a "0" after the last command byte. Non-DMA, Bit 5 This mode is selected in the SPECIFY command and will be set to a "1" during the execution phase of a command. This is for polled data transfers and helps to differentiate between the data transfer phase and the reading of result bytes. DIO, Bit 6 Indicates the direction of a data transfer once an RQM is set. A "1" indicates a read and a "0" indicates a write is required. RQM, Bit 7 Indicates that the host can transfer data if set to a "1". No access is permitted if set to a "0". SMSC DS ­ FDC37N3869 FDC37N3869 Page 25 Rev. 10/25/2000 DATA RATE SELECT REGISTER (DSR) The Data Rate Select Register (Base Address + 4: Write-only) is used to program the data rate, amount of write precompensation, power down status, and software reset (Table 17). Note: the data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30 and Microchannel applications. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps. RESET CONDITION Table 17 - Data Rate Select Register 6 5 4 3 2 POWER 0 PREPREPREDOWN COMP2 COMP1 COMP0 0 0 0 0 0 7 S/W RESET 0 1 DRATE SEL1 1 0 DRATE SEL0 0 Data Rate Select, Bits 0 - 1 These bits control the data rate of the floppy controller. See Table 19 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset and are set to 250 Kbps after a hardware reset. Precompensation Select, Bits 2 - 4 These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 18 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. The starting track number can be changed using the Configure command. Undefined, Bit 5 Should be written as a logic "0". Low Power, Bit 6 A logic "1" written to this bit will put the floppy controller into Manual Low Power mode. The floppy controller clock and data separator circuits will be turned off. The controller will come out of manual low power mode after a software reset or following access to the Data Register or Main Status Register. Software Reset, Bit 7 This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing. Table 18 - Precompensation Delays PRECOMP SELECT PRECOMPENSATION DELAY 4 1 0 0 0 1 1 1 0 SMSC DS ­ FDC37N3869 FDC37N3869 3 1 0 1 1 0 0 1 0 2 1 1 0 1 0 1 0 0 0.00 ns-DISABLED 41.67 ns 83.34 ns 125.00 ns 166.67 ns 208.33 ns 250.00 ns Default (see Table 21) Page 26 Rev. 10/25/2000 Table 19 - Data Rates DRIVE RATE SELECT (CR0B) DRT1 0 0 0 0 0 0 0 0 1 1 1 1 DRT0 0 0 0 0 1 1 1 1 0 0 0 0 DATA RATE SELECT (DSR) SEL1 1 0 0 1 1 0 0 1 1 0 0 1 SEL0 1 0 1 0 1 0 1 0 1 0 1 0 DENSEL (Note 1) DATA RATE MFM 1Meg 500 300 250 1Meg 500 500 250 1Meg 500 2Meg 250 FM -250 150 125 -250 250 125 -250 -125 IDENT=1 1 1 0 0 1 1 0 0 1 1 0 0 IDENT=0 0 0 1 1 0 0 1 1 0 0 1 1 DRATE 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Note 1: This is for DENSEL in normal mode (see section CR05 on page 102). The DENSEL pin is set high after a hardware reset and is unaffected by the DOR and the DSR resets. DRIVE RATE DRT1 0 0 1 Table 20 - Drive Rate Table (Recommended) FORMAT DRT0 0 1 0 (see section CR0B on page 104 to program Drive Rate) 360K, 1.2M, 720K, 1.44M and 2.88M Vertical Format 3-Mode Drive 2 Meg Tape Table 21 - Default Precompensation Delays PRECOMPENSATION DELAYS DATA RATE 2 Mbps 1 Mbps 500 Kbps 300 Kbps 250 Kbps SMSC DS ­ FDC37N3869 FDC37N3869 125 ns 41.67 ns 125 ns 125 ns 125 ns Page 27 Rev. 10/25/2000 DATA REGISTER (FIFO) The Data Register (Base Address + 5) is used to transfer all command parameter information, disk data and result status between the host processor and the floppy disk controller. The Data Register is Read/Write. Data transfers are governed by the RQM and DIO bits in the Main Status Register. The Data Register defaults to FIFO disabled mode after any form of reset. This maintains PC/AT hardware compatibility. The default values can be changed through the Configure command (enable full FIFO operation with threshold control). The advantage of the FIFO is that it allows the system a larger DMA latency without causing a disk error. Table 22 gives several examples of service delays with a FIFO. The data is based upon the following formula: Threshold# × (8 ÷ Data Rate) - 1.5µS = DELAY µ At the start of a command the FIFO action is always disabled and command parameters must be sent based upon the RQM and DIO bit settings. As the command execution phase is entered, the FIFO is cleared of any data to ensure that invalid data is not transferred. An overrun or underrun will terminate the current command and the transfer of data. Disk writes will complete the current sector by generating a 00 pattern and valid CRC. Reads require the host to remove the remaining data so that the result phase may be entered. Table 22 - Example FIFO Service Delays EXAMPLE DATA RATES FIFO THRESHOLD EXAMPLES 1 byte 1 x 4µs - 1.5µs = 2.5µs 1 x 8µs - 1.5µs = 6.5µs 1 x 16µs - 1.5µs = 14.5µs 2 bytes 2 x 4µs - 1.5µs = 6.5µs 2 x 8µs - 1.5µs = 14.5µs 2 x 16µs - 1.5µs = 30.5µs 8 bytes 8 x 4µs - 1.5µs = 30.5µs 8 x 8µs - 1.5µs = 62.5µs 8 x 16µs - 1.5µs = 126.5µs 15 bytes 15 x 4µs - 1.5µs = 58.5µs 15 x 8µs - 1.5µs = 118.5µs 15 x 16µs - 1.5µs = 238.5µs 2Mbps 1Mbps 500Kbps DIGITAL INPUT REGISTER (DIR) The Digital Input Register (Bass Address + 7: Read-only) is read-only in all modes. Table 23 shows the DIR in PC/AT mode, Table 24 shows the DIR in PS/2 mode, and Table 25 shows the DIR in Model 30 mode. PC-AT Interface Mode RESET CONDITION Table 23 - DIR PC/AT Interface Mode 7 6 5 4 3 2 DSK CHG N/A N/A N/A N/A N/A N/A 1 0 N/A N/A Undefined, Bits 0 - 6 The data bus outputs D0 - 6 will remain in a high impedance state during a read of this register. DSK CHG, Bit 7 The DSK CHG bit monitors the state of the pin of the same name and reflects the opposite value seen on the disk cable. The DSK CHG bit also depends upon the Force Disk Change bits in the Force FDD Status Change register (see section CR17 on page 107). SMSC DS ­ FDC37N3869 FDC37N3869 Page 28 Rev. 10/25/2000 PS/2 Interface Mode 7 DSK CHG RESET CONDITION N/A Table 24 - DIR PS/2 Interface Mode 6 5 4 3 2 1 1 1 1 DRATE SEL1 N/A N/A N/A N/A N/A 1 DRATE SEL0 N/A 0 nHIGH DENS 1 nHIGH DENS, Bit 0 This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are selected. Data Rate Select, Bits 1 - 2 These bits control the data rate of the floppy controller. See Table 19 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. Undefined, Bits 3 - 6 Always read as a logic "1" DSK CHG, Bit 7 The DSK CHG bit monitors the pin of the same name and reflects the opposite value seen on the disk cable. The DSK CHG bit also depends upon the Force Disk Change bits in the Force FDD Status Change register (see section CR17 on page 107). Model 30 Interface Mode RESET CONDITION 7 DSK CHG N/A Table 25 - DIR Model 30 Interface Mode 6 5 4 3 2 0 0 0 DMAEN NOPREC 0 0 0 0 0 1 0 DRATE SEL1 DRATE SEL0 1 0 Data Rate Select, Bits 0 - 1 These bits control the data rate of the floppy controller. See Table 19 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250kb/s after a hardware reset Noprec, Bit 2 This bit reflects the value of the NOPREC bit set in the CCR register. DMAEN, Bit 3 This bit reflects the value of DMAEN bit set in the DOR register bit 3. Undefined, Bits 4 - 6 Always read as a logic "0" DSK CHG, Bit 7 The DSK CHG bit monitors the pin of the same name and reflects the opposite value seen on the pin. The DSK CHG bit also depends upon the Force Disk Change bits in the Force FDD Status Change register (see section CR17 on page 107). CONFIGURATION CONTROL REGISTER (CCR) The Configuration Control Register (Bass Address + 7: Write-only) is write-only in all modes. Table 26 shows the CCR in PC/AT mode and PS/2 mode. Table 27 shows the CCR in Model 30 mode. PC/AT and PS/2 Interface Modes Table 26 - CCR PC/AT and PS/2 Interface Modes 7 6 5 4 3 2 1 SMSC DS ­ FDC37N3869 FDC37N3869 Page 29 0 Rev. 10/25/2000 RESET CONDITION N/A N/A N/A N/A N/A N/A DRATE SEL1 1 DRATE SEL0 0 Data Rate Select, Bits 0 - 1 These bits determine the data rate of the floppy controller. See Table 19 for the appropriate values. Reserved, Bits 2 - 7 Bits 2 to 7 are RESERVED. Reserved bits cannot be written and return 0 when read. Model 30 Interface Mode 7 RESET CONDITION N/A Table 27 - CCR Model 30 Interface Mode 6 5 4 3 2 1 NOPREC DRATE SEL1 N/A N/A N/A N/A N/A 1 0 DRATE SEL0 0 Data Rate Select, Bits 0 - 1 These bits determine the data rate of the floppy controller. See Table 19 for the appropriate values. No Precompensation, Bit 2 This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register mode. Unaffected by software reset. Reserved, Bits 3 - 7 Bits 3 to 7 are RESERVED. Reserved bits cannot be written and return 0 when read. SMSC DS ­ FDC37N3869 FDC37N3869 Page 30 Rev. 10/25/2000 Status Register Encoding During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the command just executed. Table 28 - Status Register 0 BIT NO. SYMBOL NAME 7,6 IC Interrupt Code 5 SE Seek End 4 EC Equipment Check 3 2 H Head Address Drive Select 1,0 DS1,0 DESCRIPTION 00 - Normal termination of command. The specified command was properly executed and completed without error. 01 - Abnormal termination of command. Command execution was started, but was not successfully completed. 10 - Invalid command. The requested command could not be executed. 11 - Abnormal termination caused by Polling. The FDC completed a Seek, Relative Seek or Recalibrate command (used during a Sense Interrupt Command). The TRK0 pin failed to become a "1" after: 1. 80 step pulses in the Recalibrate command. 2. The Relative Seek command caused the FDC to step outward beyond Track 0. Unused. This bit is always "0". The current head address. The current selected drive. Table 29 - Status Register 1 BIT NO. 7 SYMBOL NAME EN End of Cylinder 6 5 DE Data Error 4 OR Overrun/ Underrun 3 2 ND No Data 1 NW 0 MA Not Writable Missing Address Mark SMSC DS ­ FDC37N3869 FDC37N3869 DESCRIPTION The FDC tried to access a sector beyond the final sector of the track (255D). Will be set if TC is not issued after Read or Write Data command. Unused. This bit is always "0". The FDC detected a CRC error in either the ID field or the data field of a sector. Becomes set if the FDC does not receive CPU or DMA service within the required time interval, resulting in data overrun or underrun. Unused. This bit is always "0". Any one of the following: 1. Read Data, Read Deleted Data command - the FDC did not find the specified sector. 2. Read ID command - the FDC cannot read the ID field without an error. 3. Read A Track command - the FDC cannot find the proper sector sequence. WP pin became a "1" while the FDC is executing a Write Data, Write Deleted Data, or Format A Track command. Any one of the following: 1. The FDC did not detect an ID address mark at the specified track after encountering the index pulse from the IDX pin twice. 2. The FDC cannot detect a data address mark or a deleted data address mark on the specified track. Page 31 Rev. 10/25/2000 Table 30 - Status Register 2 BIT NO. 7 6 SYMBOL NAME CM Control Mark 5 DD 4 WC Data Error in Data Field Wrong Cylinder 3 2 1 BC Bad Cylinder 0 MD Missing Data Address Mark DESCRIPTION Unused. This bit is always "0". Any one of the following: 1. Read Data command - the FDC encountered a deleted data address mark. 2. Read Deleted Data command - the FDC encountered a data address mark. The FDC detected a CRC error in the data field. The track address from the sector ID field is different from the track address maintained inside the FDC. Unused. This bit is always "0". Unused. This bit is always "0". The track address from the sector ID field is different from the track address maintained inside the FDC and is equal to FF hex, which indicates a bad track with a hard error according to the IBM soft-sectored format. The FDC cannot detect a data address mark or a deleted data address mark. Table 31 - Status Register 3 BIT NO. SYMBOL 7 6 WP 5 4 3 2 1,0 NAME Write Protected T0 Track 0 HD Head Address Drive Select DS1,0 DESCRIPTION Unused. This bit is always "0". Indicates the status of the WP pin. The Write Protected bit also depends upon the state of the Force Write Protect bits in the Force FDD Status Change configuration register (see section CR17 on page 109). Unused. This bit is always "1". Indicates the status of the TRK0 pin. Unused. This bit is always "1". Indicates the status of the HDSEL pin. Indicates the status of the DS1, DS0 pins. Reset There are three sources of system reset on the FDC: the RESET pin of the FDC37N3869 FDC37N3869, a reset generated via a bit in the DOR, and a reset generated via a bit in the DSR. At power on, a Power On Reset initializes the FDC. All resets take the FDC out of the power down state. All operations are terminated upon a RESET, and the FDC enters an idle state. A reset while a disk write is in progress will corrupt the data and CRC. On exiting the reset state, various internal registers are cleared, including the Configure command information, and the FDC waits for a new command. Drive polling will start unless disabled by a new Configure command. RESET PIN (HARDWARE RESET) The RESET pin is a global reset and clears all registers except those programmed by the Specify command. The DOR reset bit is enabled and must be cleared by the host to exit the reset state. SMSC DS ­ FDC37N3869 FDC37N3869 Page 32 Rev. 10/25/2000 DOR RESET VS. DSR RESET (SOFTWARE RESET) These two resets are functionally the same. Both will reset the FDC core, which affects drive status information and the FIFO circuits. The DSR reset clears itself automatically while the DOR reset requires the host to manually clear it. DOR reset has precedence over the DSR reset. The DOR reset is set automatically upon a pin reset. The user must manually clear this reset bit in the DOR to exit the reset state. DMA Transfers DMA transfers are enabled with the Specify command and are initiated by the FDC by activating the FDRQ pin during a data transfer command. The FIFO is enabled directly by asserting nDACK and addresses need not be valid. Note that if the DMA controller (i.e. 8237A) is programmed to function in verify mode, a pseudo read is performed by the FDC based only on nDACK. This mode is only available when the FDC has been configured into byte mode (FIFO disabled) and is programmed to do a read. With the FIFO enabled, the FDC can perform the above operation by using the new Verify command; no DMA operation is needed. Controller Phases For simplicity, command handling in the FDC can be divided into three phases: Command, Execution, and Result. Each phase is described in the following sections. COMMAND PHASE After a reset, the FDC enters the command phase and is ready to accept a command from the host. For each of the commands, a defined set of command code bytes and parameter bytes has to be written to the FDC before the command phase is complete. (Refer to Table 33 for the command set descriptions). These bytes of data must be transferred in the order prescribed. Before writing to the FDC, the host must examine the RQM and DIO bits of the Main Status Register. RQM and DIO must be equal to "1" and "0" respectively before command bytes may be written. RQM is set false by the FDC after each write cycle until the received byte is processed. The FDC asserts RQM again to request each parameter byte of the command unless an illegal command condition is detected. After the last parameter byte is received, RQM remains "0" and the FDC automatically enters the next phase as defined by the command definition. The FIFO is disabled during the command phase to provide for the proper handling of the "Invalid Command" condition. EXECUTION PHASE All data transfers to or from the FDC occur during the execution phase, which can proceed in DMA or non-DMA mode as indicated in the Specify command. After a reset, the FIFO is disabled. Each data byte is transferred by an FINT or FDRQ depending on the DMA mode. The Configure command can enable the FIFO and set the FIFO threshold value. The following paragraphs detail the operation of the FIFO flow control. In these descriptions, is defined as the number of bytes available to the FDC when service is requested from the host and ranges from 1 to 16. The parameter FIFOTHR, which the user programs, is one less and ranges from 0 to 15. A low threshold value (i.e. 2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. The host reads (writes) from (to) the FIFO until empty (full), then the transfer request goes inactive. The host must be very responsive to the service request. This is the desired case for use with a "fast" system. A high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests. SMSC DS ­ FDC37N3869 FDC37N3869 Page 33 Rev. 10/25/2000 Non-DMA Mode Transfers FIFO to Host The FINT pin and RQM bits in the Main Status Register are activated when the FIFO contains (16-) bytes or the last bytes of a full sector have been placed in the FIFO. The FINT pin can be used for interrupt-driven systems,and RQM can be used for polled systems. The host must respond to the request by reading data from the FIFO. This process is repeated until the last byte is transferred out of the FIFO. The FDC will deactivate the FINT pin and RQM bit when the FIFO becomes empty. Host to FIFO The FINT pin and RQM bit in the Main Status Register are activated upon entering the execution phase of data transfer commands. The host must respond to the request by writing data into the FIFO. The FINT pin and RQM bit remain true until the FIFO becomes full. They are set true again when the FIFO has bytes remaining in the FIFO. The FINT pin will also be deactivated if TC and nDACK both go inactive. The FDC enters the result phase after the last byte is taken by the FDC from the FIFO (i.e. FIFO empty condition). DMA Mode Transfers FIFO to Host The FDC activates the DDRQ pin when the FIFO contains (16 - ) bytes, or the last byte of a full sector transfer has been placed in the FIFO. The DMA controller must respond to the request by reading data from the FIFO. The FDC will deactivate the DDRQ pin when the FIFO becomes empty. FDRQ goes inactive after nDACK goes active for the last byte of a data transfer (or on the active edge of nIOR, on the last byte, if no edge is present on nDACK). A data underrun may occur if FDRQ is not removed in time to prevent an unwanted cycle. Host to FIFO The FDC activates the FDRQ pin when entering the execution phase of the data transfer commands. The DMA controller must respond by activating the nDACK and nIOW pins and placing data in the FIFO. FDRQ remains active until the FIFO becomes full. FDRQ is again set true when the FIFO has bytes remaining in the FIFO. The FDC will also deactivate the FDRQ pin when TC becomes true (qualified by nDACK), indicating that no more data is required. FDRQ goes inactive after nDACK goes active for the last byte of a data transfer (or on the active edge of nIOW of the last byte, if no edge is present on nDACK). A data overrun may occur if FDRQ is not removed in time to prevent an unwanted cycle. Data Transfer Termination The FDC supports terminal count explicitly through the TC pin and implicitly through the underrun/overrun and endof-track (EOT) functions. For full sector transfers, the EOT parameter can define the last sector to be transferred in a single or multi-sector transfer. If the last sector to be transferred is a partial sector, the host can stop transferring the data in mid-sector, and the FDC will continue to complete the sector as if a hardware TC was received. The only difference between these implicit functions and TC is that they return "abnormal termination" result status. Such status indications can be ignored if they were expected. Note that when the host is sending data to the FIFO of the FDC, the internal sector count will be complete when the FDC reads the last byte from its side of the FIFO. There may be a delay in the removal of the transfer request signal of up to the time taken for the FDC to read the last 16 bytes from the FIFO. The host must tolerate this delay. RESULT PHASE The generation of FINT determines the beginning of the result phase. For each of the commands, a defined set of result bytes has to be read from the FDC before the result phase is complete. These bytes of data must be read out for another command to start. RQM and DIO must both equal "1" before the result bytes may be read. After all the result bytes have been read, the RQM and DIO bits switch to "1" and "0" respectively, and the CB bit is cleared, indicating that the FDC is ready to accept the next command. SMSC DS ­ FDC37N3869 FDC37N3869 Page 34 Rev. 10/25/2000 Command Set/Descriptions Commands can be written whenever the FDC is in the command phase. Each command has a unique set of needed parameters and status results. The FDC checks to see that the first byte is a valid command and, if valid, proceeds with the command. If it is invalid, an interrupt is issued. The user sends a Sense Interrupt Status command which returns an invalid command error. Refer to Table 32 for explanations of the various symbols used. Table 33 lists the required parameters and the results associated with each command that the FDC is capable of performing. SYMBOL C D D0, D1, D2, D3 DIR DS0, DS1 DTL EC EFIFO EIS EOT GAP GPL H/HDS HLT HUT LOCK MFM Table 32 - Description of Command Symbols NAME DESCRIPTION Cylinder Address The currently selected address; 0 to 255. Data Pattern The pattern to be written in each sector data field during formatting. Drive Select 0-3 Designates which drives are perpendicular drives on the Perpendicular Mode Command. A "1" indicates a perpendicular drive. Direction Control If this bit is "0", then the head will step out from the spindle during a relative seek. If set to a "1", the head will step in toward the spindle. Disk Drive Select DS1 DS0 DRIVE 0 0 Drive 0 0 1 Drive 1 1 0 Drive 2 1 1 Drive 3 Special Sector By setting N to zero (00), DTL may be used to control the number of bytes Size transferred in disk read/write commands. The sector size (N = 0) is set to 128. If the actual sector (on the diskette) is larger than DTL, the remainder of the actual sector is read but is not passed to the host during read commands; during write commands, the remainder of the actual sector is written with all zero bytes. The CRC check code is calculated with the actual sector. When N is not zero, DTL has no meaning and should be set to FF HEX. Enable Count When this bit is "1" the "DTL" parameter of the Verify command becomes SC (number of sectors per track). Enable FIFO This active low bit when a 0, enables the FIFO. A "1" disables the FIFO (default). Enable Implied When set, a seek operation will be performed before executing any read Seek or write command that requires the C parameter in the command phase. A "0" disables the implied seek. End of Track The final sector number of the current track. Alters Gap 2 length when using Perpendicular Mode. Gap Length The Gap 3 size. (Gap 3 is the space between sectors excluding the VCO synchronization field). Head Address Selected head: 0 or 1 (disk side 0 or 1) as encoded in the sector ID field. Head Load Time The time interval that FDC waits after loading the head and before initializing a read or write operation. Refer to the Specify command for actual delays. Head Unload The time interval from the end of the execution phase (of a read or write Time command) until the head is unloaded. Refer to the Specify command for actual delays. Lock defines whether EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE COMMAND can be reset to their default values by a "software Reset" (A reset caused by writing to the appropriate bits of either the DSR or DOR). MFM/FM Mode A one selects the double density (MFM) mode. A zero selects single Selector density (FM) mode. SMSC DS ­ FDC37N3869 FDC37N3869 Page 35 Rev. 10/25/2000 SYMBOL MT N NCN ND NAME Multi-Track Selector Sector Size Code New Cylinder Number Non-DMA Mode Flag OW Overwrite PCN Present Cylinder Number Polling Disable POLL PRETRK R RCN SC SK SRT ST0 ST1 ST2 ST3 WGATE Precompensation Start Track Number Sector Address Relative Cylinder Number Number of Sectors Per Track Skip Flag Step Rate Interval Status 0 Status 1 Status 2 Status 3 Write Gate SMSC DS ­ FDC37N3869 FDC37N3869 DESCRIPTION When set, this flag selects the multi-track operating mode. In this mode, the FDC treats a complete cylinder under head 0 and 1 as a single track. The FDC operates as this expanded track started at the first sector under head 0 and ended at the last sector under head 1. With this flag set, a multitrack read or write operation will automatically continue to the first sector under head 1 when the FDC finishes operating on the last sector under head 0. This specifies the number of bytes in a sector. If this parameter is "00", then the sector size is 128 bytes. The number of bytes transferred is determined by the DTL parameter. Otherwise the sector size is (2 raised to the "N'th" power) times 128. All values up to "07" hex are allowable. "07"h would equal a sector size of 16k. It is the user's responsibility to not select combinations that are not possible with the drive. N SECTOR SIZE 00 128bytes 01 256bytes 02 512bytes . . 07 16Kbytes The desired cylinder number. When set to "1", indicates that the FDC is to operate in the non-DMA mode. In this mode, the host is interrupted for each data transfer. When set to 0, the FDC operates in DMA mode, interfacing to a DMA controller by means of the DRQ and nDACK signals. The bits D0-D3 of the Perpendicular Mode Command can only be modified if OW is set to "1". OW id defined in the Lock command. The current position of the head at the completion of Sense Interrupt Status command. When set, the internal polling routine is disabled. When clear, polling is enabled. Programmable from track 00 to FFH. The sector number to be read or written. In multi-sector transfers, this parameter specifies the sector number of the first sector to be read or written. Relative cylinder offset from present cylinder as used by the Relative Seek command. The number of sectors per track to be initialized by the Format command. The n