PC98/99 82077AA NS16C550A 16C550 PC98/PC99 CLK32OUT IRQ/IRQ15 CLK/IRQ14/GP50 - Datasheet Archive

 

128 Pin Enhanced Super I/O Controller with ACPI Support FEATURES · · · · · · ·

 

FDC37B72x 128 Pin Enhanced Super I/O Controller with ACPI Support FEATURES · · · · · · · · · · · · · 5 Volt Operation PC98/99 PC98/99 and ACPI 1.0 Compliant Battery Back-up for Wake-Events ISA Host Interface ISA Plug-and-Play Compatible Register Set 12 IRQ Options 15 Serial IRQ Options 16 Bit Address Qualification Four DMA Options 12mA AT Bus Drivers BIOS Buffer 20 GPI/O Pins 32 kHz Standby Clock Output Soft Power Management ACPI/PME Support SCI/SMI Support Watchdog timer Power Button Override Event Either Edge Triggered Interrupts Intelligent Auto Power Management Shadowed Write-only Registers Programmable Wake-up Event Interface 8042 Keyboard Controller 2K Program ROM 256 Bytes Data RAM Asynchronous Access to Two Data Registers and One Status Register Supports Interrupt and Polling Access 8 Bit Timer/Counter - · · · Port 92 Support Fast Gate A20 and Hardware Keyboard Reset 2.88MB Super I/O Floppy Disk Controller Relocatable to 480 Different Addresses Licensed CMOS 765B Floppy Disk Controller Advanced Digital Data Separator SMSC's Proprietary 82077AA 82077AA Compatible Core Sophisticated Power Control Circuitry (PCC) Including Multiple Powerdown Modes for Reduced Power Consumption Supports Two Floppy Drives Directly Software Write Protect FDC on Parallel Port Low Power CMOS Design Supports Vertical Recording Format 16 Byte Data FIFO 100% IBM® Compatibility Detects All Overrun and Underrun Conditions 24mA Drivers and Schmitt Trigger Inputs Enhanced FDC Digital Data Separator Low Cost Implementation No Filter Components Required 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates Programmable Precompensation Modes Serial Ports Relocatable to 480 Different Addresses - · Two High Speed NS16C550A NS16C550A Compatible UARTs with Send/Receive 16 Byte FIFOs Programmable Baud Rate Generator Modem Control Circuitry Including 230K and 460K Baud IrDA 1.0, HP-SIR, ASK-IR Support Ring Wake Filter · 2 Multi-Mode Parallel Port with ChiProtect Relocatable to 480 Different Addresses Standard Mode IBM PC/XT®, PC/AT®, and PS/2 Compatible Bidirectional ParallelPort Enhanced Mode Enhanced Parallel Port (EPP) Compatible EPP 1.7 and EPP 1.9 (IEEE 1284 Compliant) High Speed Mode Microsoft and Hewlett Packard Extended Capabilities Port (ECP) Compatible (IEEE 1284 Compliant) Incorporates ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On 14 mA Output Drivers 128 Pin QFP Package TABLE OF CONTENTS FEATURES.1 GENERAL DESCRIPTION .5 DESCRIPTION OF PIN FUNCTIONS .7 BUFFER TYPE DESCRIPTIONS .10 GENERAL PURPOSE I/O PINS .11 REFERENCE DOCUMENTS.12 FUNCTIONAL DESCRIPTION .14 SUPER I/O REGISTERS.14 HOST PROCESSOR INTERFACE .14 FLOPPY DISK CONTROLLER.15 FDC INTERNAL REGISTERS .15 COMMAND SET/DESCRIPTIONS .38 INSTRUCTION SET .41 DATA TRANSFER COMMANDS .53 CONTROL COMMANDS.62 SERIAL PORT (UART) .69 INFRARED INTERFACE.85 PARALLEL PORT.86 IBM XT/AT COMPATIBLE, BI-DIRECTIONAL AND EPP MODES .88 EXTENDED CAPABILITIES PARALLEL PORT .94 OPERATION .102 PARALLEL PORT FLOPPY DISK CONTROLLER.107 POWER MANAGEMENT.109 UART POWER MANAGEMENT.113 PARALLEL PORT .113 INTERNAL PWRGOOD .113 32.768 KHZ STANDBY CLOCK OUTPUT.114 SERIAL IRQ.115 BIOS BUFFER.120 GENERAL PURPOSE I/O .121 DESCRIPTION .121 RUN STATE GPIO DATA REGISTER ACCESS.122 GPIO CONFIGURATION .122 WATCH DOG TIMER .126 8042 KEYBOARD CONTROLLER DESCRIPTION .128 SOFT POWER MANAGEMENT .136 BUTTON OVERRIDE FEATURE .139 3 ACPI/PME/SMI FEATURES .141 ACPI FEATURES .141 PME SUPPORT .143 ACPI, PME AND SMI REGISTERS.143 EITHER EDGE TRIGGERED INTERRUPTS .155 CONFIGURATION.157 SYSTEM ELEMENTS .10 CONFIGURATION SEQUENCE .10 CONFIGURATION REGISTERS .162 OPERATIONAL DESCRIPTION.199 MAXIMUM GUARANTEED RATINGS* .199 DC ELECTRICAL CHARACTERISTICS .199 AC TIMING .204 CAPACITIVE LOADING .204 ECP PARALLEL PORT TIMING.229 80 Arkay Dr. Hauppauge, NY 11788 (516) 435-6000 FAX: (516) 273-3123 4 GENERAL DESCRIPTION These features include support of both legacy and ACPI power management models through the selection of SMI or SCI. It implements a power button override event (4 second button hold to turn off the system) and either edge triggered interrupts. The FDC37B72x incorporates a keyboard interface, SMSC's true CMOS 765B floppy disk controller, advanced digital data separator, 16 byte data FIFO, two 16C550 16C550 compatible UARTs, one Multi-Mode parallel port which includes ChiProtect circuitry plus EPP and ECP support, on-chip 12 mA AT bus drivers, and two floppy direct drive support, soft power management and SMI support and Intelligent Power Management including PME and SCI/ACPI support. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures in addition to providing data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC's patented data separator technology, allowing for ease of testing and use. Both on-chip UARTs are compatible with the NS16C550A NS16C550A. The parallel port is compatible with IBM PC/AT architecture, as well as EPP and ECP. The FDC37B72x incorporates sophisticated power control circuitry (PCC) which includes support for keyboard, mouse, modem ring, power button support and other wake-up events. The PCC supports multiple low power down modes. The FDC37B72x provides support for the ISA Plug-and-Play Standard (Version 1.0a) and provides for the recommended functionality to support Windows '95/'98 and PC98/PC99 PC98/PC99. Through internal configuration registers, each of the FDC37B72x's logical device's I/O address, DMA channel and IRQ channel may be programmed. There are 480 I/O address location options, 12 IRQ pin options or Serial IRQ option, and four DMA channel options for each logical device. The FDC37B72x Floppy Disk Controller and separator do not require any external components and are therefore easy to use, lower system cost and reduced board area. FDC is software and register compatible SMSC's proprietary 82077AA 82077AA core. The FDC37B72x provides features for compliance with the "Advanced Configuration and Power Interface Specification" (ACPI). data filter offer The with IBM, PC/XT and PC/AT are registered trademarks and PS/2 is a trademark of International Business Machines Corporation SMSC is a registered trademark and Ultra I/O, ChiProtect, and MultiMode are trademarks of Standard Microsystems Corporation 5 DRVDEN0 DRVDEN1/GP52/IRQ8/nSMI nMTR0 nMTR1/GP16 nDS0 nDS1/GP17 VSS nDIR nSTEP nWDATA nWGATE nHDSEL nINDEX nTRK0 nWRTPRT nRDATA nDSKCHG CLK32OUT CLK32OUT nPOWERON BUTTON_IN nPME/SCI/IRQ9 CLOCKI SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 PD7 VSS SLCT PE BUSY nACK nERROR nALF nSTROBE RXD1 TXD1 nDSR1 nRTS1/SYSOP nCTS1 nDTR1 nRI1 nDCD1 nRI2 VCC nDCD2 RXD2/IRRX TXD2/IRTX nDSR2 nRTS2 nCTS2 nDTR2 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 FDC37B72x 128 Pin QFP FIGURE 1 - FDC37B72x PIN CONFIGURATION 6 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 IOCHRDY TC VCC DRQ3 nDACK3 DRQ2 nDACK2 DRQ1 nDACK1 DRQ0 nDACK0 RESET_DRV SD7 SD6 SD5 SD4 VSS SD3 SD2 SD1 SD0 AEN nIOW nIOR SER_IRQ/IRQ15 IRQ/IRQ15 PCI_CLK/IRQ14/GP50 CLK/IRQ14/GP50 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PD6 PD5 PD4 PD3 PD2 PD1 PD0 nSLCTIN nINIT VCC nROMOE/IRQ12/GP54/EETI nROMCS/IRQ11/GP53/EETI RD7/IRQ10/GP67 RD7/IRQ10/GP67 RD6/IRQ8/GP66 RD6/IRQ8/GP66 RD5/IRQ7/GP65 RD5/IRQ7/GP65 RD4/IRQ6/GP64/P17 RD4/IRQ6/GP64/P17 RD3/IRQ5/GP63/WDT RD3/IRQ5/GP63/WDT RD2/IRQ4/GP62/nRING RD1/IRQ3/GP61/LED RD1/IRQ3/GP61/LED RD0/IRQ1/GP60/nSMI GP15/IRTX2 GP15/IRTX2 GP14/IRRX2 GP14/IRRX2 GP13/LED GP13/LED GP12/WDT/P17/EETI GP12/WDT/P17/EETI GP11/nRING/EETI GP10/nSMI A20M KBDRST VSS MCLK MDAT KCLK KDAT VTR XTAL2 AVSS XTAL1 VBAT DESCRIPTION OF PIN FUNCTIONS TABLE 1 - DESCRIPTION OF PIN FUNCTIONS PIN No./QFP 44-47, 49-52 23-38 43 64 53 40 39 55 57 59 54 56 58 61 60 63 41 42 System Data Bus NAME TOTAL SYMBOL PROCESSOR/HOST INTERFACE (40) 8 SD[0:7] 16-bit System Address Bus Address Enable I/O Channel Ready ISA Reset Drive Serial IRQ/IRQ15 IRQ/IRQ15 PCI Clock/IRQ14/GP50 DMA Request 0 DMA Request 1 DMA Request 2 DMA Acknowledge 0 DMA Acknowledge 1 DMA Acknowledge 2 DMA Request 3 DMA Acknowledge 3 Terminal Count I/O Read I/O Write 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SA[0:15] AEN IOCHRDY RESET_DRV SER_IRQ PCI_CLK DRQ0 DRQ1 DRQ2 nDACK0 nDACK1 nDACK2 DRQ3 nDACK3 TC nIOR nIOW 1 1 1 1 CLOCKI XTAL1 XTAL2 CLK32OUT CLK32OUT +5V Supply Voltage 3 4 IO12 VCC Digital Ground BUFFER TYPE I I OD12 IS IO12 IO12 O12 O12 O12 I I I O12 I I I I VSS CLOCKS (4) 22 66 68 18 14.318MHz Clock Input 32.768kHz Crystal Input 32.768kHz Crystal Driver 32.768kHz Clock Out ICLK ICLK OCLK2 O8 POWER PINS (10) 62, 93, 121 7, 48, 74, 104 67 69 65 19 20 21 16 11 10 Analog Ground Trickle Supply Voltage Battery Voltage 1 1 1 POWER MANAGEMENT (3) Power On 1 Button In 1 Power Management Event/SCI/IRQ9 1 FDD INTERFACE (16) Read Disk Data 1 Write Gate 1 Write Disk Data 1 7 AVSS VTR VBAT nPOWERON BUTTON_IN nPME nRDATA nWGATE nWDATA OD24 I O12 IS O24 O24 PIN No./QFP 12 8 9 17 5 6 3 4 15 14 13 1 2 112 113 115 NAME TOTAL Head Select 1 Step Direction 1 Step Pulse 1 Disk Change 1 Drive Select 0 1 Drive Select 1/GP17 1/GP17 1 Motor On 0 1 Motor On 1/GP16 1/GP16 1 Write Protected 1 Track 0 1 Index Pulse Input 1 Drive Density Select 0 1 Drive Density Select 1/GP52/IRQ8/nSMI 1 GENERAL PURPOSE I/O (6) General Purpose 10/nSMI 1 General Purpose 11/nRING/EETI (Note 4) 1 General Purpose 12/WDT/P17/P12/EETI 12/WDT/P17/P12/EETI 1 (Note 4) General Purpose 13/LED 13/LED Driver 1 General Purpose 14/Infrared Rx 1 General Purpose 15/Infrared Tx (Note 3) 1 BIOS INTERFACE (10) ROM Bus 0/IRQ1/GP60/nSMI 1 ROM Bus 1/IRQ3/GP61/LED 1/IRQ3/GP61/LED 1 ROM Bus 2/IRQ4/GP62/nRING 1 ROM Bus 3/IRQ5/GP63/WDT 3/IRQ5/GP63/WDT 1 ROM Bus 4/IRQ6/GP64/P17/P12 4/IRQ6/GP64/P17/P12 1 ROM Bus 5/IRQ7/GP65 5/IRQ7/GP65 1 ROM Bus 6/IRQ8/GP66 6/IRQ8/GP66 1 ROM Bus 7/IRQ10/GP67 7/IRQ10/GP67 1 nROMCS/IRQ11/GP53/EETI (Note 4) 1 nROMOE/IRQ12/GP54/EETI (Note 4) 1 SERIAL PORT 1 INTERFACE (8) Receive Serial Data 1 1 Transmit Serial Data 1 1 Request to Send 1 1 116 117 114 119 118 Clear to Send 1 Data Terminal Ready 1 Data Set Ready 1 Data Carrier Detect 1 Ring Indicator 1 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 123 1 1 1 1 1 SERIAL PORT 2 INTERFACE (8) Receive Serial Data 2/Infrared Rx 1 8 SYMBOL nHDSEL nDIR nSTEP nDSKCHG nDS0 nDS1 nMTR0 nMTR1 nWRTPRT nTRKO nINDEX DRVDEN0 DRVDEN1 BUFFER TYPE O24 O24 O24 IS O24 IO24 O24 IO24 IS IS IS O24 IO24 GP10 GP11 GP12 IO12 IO4 IO4 GP13 GP14 GP15 IO24 IO4 IO24 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 nROMCS nROMOE IO12 IO24 IO12 IO12 IO12 IO12 IO12 IO12 IO12 IO12 RXD1 TXD1 nRTS1/ SYSOP nCTS1 nDTR1 nDSR1 nDCD1 nRI1 I O4 IO4 RXD2/IRRX I O4 I I I I PIN No./QFP 124 126 127 128 125 122 120 96-103 95 94 110 111 107 108 106 105 109 70 71 72 73 75 76 NAME TOTAL SYMBOL Transmit Serial Data 2/Infrared Tx (Note 3) 1 TXD2/IRTX Request to Send 2 1 nRTS2 Clear to Send 2 1 nCTS2 Data Terminal Ready 1 nDTR2 Data Set Ready 2 1 nDSR2 Data Carrier Detect 2 1 nDCD2 Ring Indicator 2 1 nRI2 PARALLEL PORT INTERFACE (17) Parallel Port Data Bus 8 PD[0:7] Printer Select 1 nSLCTIN Initiate Output 1 nINIT Auto Line Feed 1 nALF Strobe Signal 1 nSTROBE Busy Signal 1 BUSY Acknowledge Handshake 1 nACK Paper End 1 PE Printer Selected 1 SLCT Error at Printer 1 nERROR KEYBOARD/MOUSE INTERFACE (6) Keyboard Data 1 KDAT Keyboard Clock 1 KCLK Mouse Data 1 MDAT Mouse Clock 1 MCLK Keyboard Reset 1 KBDRST (Note 2) Gate A20 1 A20M BUFFER TYPE O24 O4 I O4 I I I IOP14 IOP14 OP14 OP14 OP14 OP14 I I I I I IOD16 IOD16 IOD16 IOD16 IOD16 IOD16 IOD16 IOD16 O4 O4 Note 1: The "n" as the first letter of a signal name indicates an "Active Low" signal. Note 2: KBDRST is active low. Note 3: This pin defaults to an output and low. When configured as IRTX (or IRTX2), this pin is low when the IR block is not transmitting. Note 4: EETI is the Either Edge Triggered Interrupt Input function. 9 BUFFER TYPE DESCRIPTIONS TABLE 2 - BUFFER TYPES SYMBOL I IS ICLK OCLK2 IO4 IOP4 O4 O8 IO12 O12 OP12 OD12 IOP14 IOP14 OD14 OP14 IOD16 IOD16 O24 OD24 DESCRIPTION Input, TTL compatible. Input with Schmitt trigger. Clock Input. Clock Output, 2mA sink, 2mA source. Input/Output, 4mA sink, 2mA source. Input/Output, 4mA sink, 2mA source. Backdrive Protected. Output, 4mA sink, 2mA source. Output, 8mA sink, 4mA source. Input/Output, 12mA sink, 6mA source. Output, 12mA sink, 6mA source. Output, 12mA sink, 6mA source. Backdrive Protected. Output, Open Drain, 12 mA sink. Input/Output, 14mA sink, 14mA source. Backdrive Protected. Output, Open Drain, 14mA sink. Output, 14mA sink, 14mA source. Backdrive Protected. Input/Output, Open Drain, 16mA sink Output, 24mA sink, 12mA source. Output, Open Drain, 24mA sink. 10 GENERAL PURPOSE I/O PINS TABLE 3 - GENERAL PURPOSE I/O PIN FUNCTIONS PIN NO. QFP DEFAULT FUNCTION ALTERNATE FUNCTION 1 ALTERNATE FUNCTION 2 ALTERNATE FUNCTION 3 - 77 GPIO nSMI - 78 79 80 81 82 4 GPIO GPIO GPIO GPIO GPIO nMTR1 nRING WDT LED IRRX2 IRTX2 GPIO EETI 4 P17/P12 P17/P12 - 1 EETI - 6 nDS1 GPIO - - 39 PCI_CLK IRQ14 IRQ14 GPIO - 2 DRVDEN1 GPIO IRQ8 nSMI 91 nROMCS 2 IRQ11 IRQ11 GPIO EETI 92 nROMOE 2 IRQ12 IRQ12 GPIO EETI 83 RD0 2,3 IRQ1 GPIO nSMI 84 RD1 2,3 IRQ3 GPIO LED 85 RD2 2,3 IRQ4 GPIO nRING 86 RD3 2,3 IRQ5 GPIO WDT 87 RD4 2,3 IRQ6 GPIO P17/P12 P17/P12 88 RD5 2,3 IRQ7 GPIO - 89 RD6 2,3 IRQ8 GPIO - 90 RD7 2,3 IRQ10 IRQ10 GPIO - 1 1 1 4 BUFFER 5 TYPE IOP4/(OP12/ OP12/ OD12) IOP4/I/I IOP4/O4/IO4/I IOP4/O24 IOP4/O24 IOP4/I IOP4/O24 IOP4/O24 (O24/OD24 O24/OD24)/ IOP4 (O24/OD24 O24/OD24)/ IOP4 CLKIN/(O12/ OD12)/IOP4 (O24/OD24 O24/OD24) /IOP4/ (OP12/OD12 OP12/OD12)/ (OP12/OD12 OP12/OD12) IO12/ IO12/(O12/ OD12)/IOP4/I IO12/ IO12/(O12/ OD12)/IOP4/I IO12/ IO12/(O12/ OD12)/IOP4/ (OP12/OD12 OP12/OD12) IO12/ IO12/(O12/ OD12)/IOP4/ O24 IO12/ IO12/(O12/ OD12)/IOP4/I IO12/ IO12/(O12/ OD12)/IOP4/ O4 IO12/ IO12/(O12/ OD12)/IOP4/ IO4 IO12/ IO12/(O12/ OD12)/IOP4 IO12/ IO12/(OP12/ OP12/ OD12)/IOP4 IO12/ IO12/(O12/ OD12)/IOP4 INDEX REG. GPIO GP1 GP10 GP1 GP1 GP1 GP1 GP1 GP1 GP11 GP12 GP13 GP14 GP15 GP16 GP1 GP17 GP5 GP50 GP5 GP52 GP5 GP53 GP5 GP54 GP6 GP60 GP6 GP61 GP6 GP62 GP6 GP63 GP6 GP64 GP6 GP65 GP6 GP66 GP6 GP67 Note 1: Either Edge Triggered Interrupt Inputs. Note 2: At power-up, RD0-7, nROMCS and nROMOE function as the XD Bus. To use RD0-7 for alternate functions, nROMCS must stay high until those pins are finished being programmed. Note 3: These pins cannot be programmed as open drain pins in their original function. 11 Note 4: The function of P17 or P12 is selected via the P17/P12 P17/P12 select bit in the Ring Filter Select Register in Logical Device 8 at 0xC6. Default is P17. Note 5: Buffer types per function are separated by a forward slash "/". Multiple buffer types per function are separated by a forward slash "/" and enclosed in parentheses; e.g., IRQ outputs can be open drain or push-pull and are shown as "(O12/OD12 O12/OD12)". REFERENCE DOCUMENTS IEEE 1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.14, July 14, 1993. Hardware Description of the 8042, Intel 8 bit Embedded Controller Handbook. PCI Bus Power Management Interface Specification, Rev. 1.0, Draft, March 18, 1997. 12 nSMI* nPME/SCI nPowerOn Button_In SOFT POWER MANAGEMENT PME/ ACPI BIOS BUFFER nSMI nROMOE * nROMCS * RD[0:7]* POWER MANAGEMENT SER_IRQ PD0-7 MULTI-MODE PARALLEL PORT/FDC MUX DATA BUS nERROR , nACK nSTB, nSLCTIN , nINIT, nALF SERIAL IRQ PCI_CLK BUSY, SLCT, PE, GENERAL PURPOSE I/O ADDRESS BUS nIOR GP6[0:7]* TXD1 CONFIGURATION 16C550 16C550 COMPATIBLE SERIAL PORT 1 REGISTERS nIOW GP1[0:7]* GP5[0,2:4]* AEN RXD1 nDSR1, nDCD1, nRI1, nDTR1 nCTS1, nRTS1 CONTROL BUS SA[0:15] IRTX SD[O:7] IRRX HOST DRQ[0:3] WDATA 16C550 16C550 COMPATIBLE SERIAL PORT 2 WITH INFRARED CPU WCLOCK INTERFACE nDACK [0:3] SMSC DIGITAL DATA SEPARATOR WITH WRITE PRECOM- PROPRIETARY TC 82077 COMPATIBLE VERTICAL IRQ[1,3-12,14] FLOPPYDISK CONTROLLER RESET_DRV CORE TXD2(IRTX) RXD2(IRRX) nDSR2, nDCD2, nRI2, nDTR2 nCTS2, nRTS2 KCLK PENSATION KDATA RCLOCK 8042 IOCHRDY MCLK MDATA RDATA P20, P21 P17/P12 P17/P12* nINDEX nTRK0 nDSKCHG nWRPRT nWGATE VCC VTR VBAT DENSEL CLK32OUT CLK32OUT nDS0,1 CLOCK nDIR nMTR0,1 GEN nSTEP DRVDEN0 nHDSEL nWDATA nRDATA CLOCKI (14.318) XTAL1 DRVDEN1 XTAL2 *Multi-Function I/O Pin - Optional VSS FIGURE 2 - FDC37B72x BLOCK DIAGRAM 13 FUNCTIONAL DESCRIPTION SUPER I/O REGISTERS HOST PROCESSOR INTERFACE The address map, shown below in Table 1, shows the addresses of the different blocks of the Super I/O immediately after power up. The base addresses of the FDC, serial and parallel ports can be moved via the configuration registers. Some addresses are used to access more than one register. The host processor communicates with the FDC37B72x through a series of read/write registers. The port addresses for these registers are shown in Table 1. Register access is accomplished through programmed I/O or DMA transfers. All registers are 8 bits wide. All host interface output buffers are capable of sinking a minimum of 12 mA. TABLE 4 - SUPER I/O BLOCK ADDRESSES LOGICAL ADDRESS BLOCK NAME DEVICE Base+(0-5) and +(7) Floppy Disk 0 3 Parallel Port SPP Base+(0-3) EPP Base+(0-7) ECP Base+(0-3), +(400-402) ECP+EPP+SPP Base+(0-7), +(400-402) Base+(0-7) Serial Port Com 1 4 Base+(0-7) Serial Port Com 2 5 60, 64 KYBD 7 Base + (0-17h) ACPI, PME, SMI A Base + (0-1) Configuration NOTES IR Support Note 1: Refer to the configuration register descriptions for setting the base address 14 The FDC is compatible to the 82077AA 82077AA using SMSC's proprietary floppy disk controller core. FLOPPY DISK CONTROLLER The Floppy Disk Controller (FDC) provides the interface between a host microprocessor and the floppy disk drives. The FDC integrates the functions of the Formatter/Controller, Digital Data Separator, Write Precompensation and Data Rate Selection logic for an IBM XT/AT compatible FDC. The true CMOS 765B core guarantees 100% IBM PC XT/AT compatibility in addition to providing data overflow and underflow protection. FDC INTERNAL REGISTERS The Floppy Disk Controller contains eight internal registers that facilitate the interfacing between the host microprocessor and the disk drive. TABLE 5 shows the addresses required to access these registers. Registers other than the ones shown are not supported. The rest of the description assumes that the primary addresses have been selected. TABLE 5 - STATUS, DATA AND CONTROL REGISTERS (Shown with base addresses of 3F0 and 370) PRIMARY SECONDARY ADDRESS ADDRESS R/W REGISTER Status Register A (SRA) R 370 3F0 Status Register B (SRB) R 371 3F1 Digital Output Register (DOR) R/W 372 3F2 Tape Drive Register (TSR) R/W 373 3F3 Main Status Register (MSR) R 374 3F4 Data Rate Select Register (DSR) W 374 3F4 Data (FIFO) R/W 375 3F5 Reserved 376 3F6 Digital Input Register (DIR) R 377 3F7 Configuration Control Register (CCR) W 377 3F7 15 accessed at any time when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F0. STATUS REGISTER A (SRA) Address 3F0 READ ONLY This register is read-only and monitors the state of the FINTR pin and several disk interface pins in PS/2 and Model 30 modes. The SRA can be RESET COND. 7 INT PENDING 0 6 nDRV2 5 STEP 1 PS/2 Mode 4 3 2 nTRK0 HDSEL nINDX 0 N/A 0 N/A 1 nWP 0 DIR N/A 0 Active low status of the TRK0 disk interface input. BIT 0 DIRECTION Active high status indicating the direction of head movement. A logic "1" indicates inward direction; a logic "0" indicates outward direction. BIT 5 STEP Active high status of the STEP output disk interface output pin. BIT 1 nWRITE PROTECT Active low status of the WRITE PROTECT disk interface input. A logic "0" indicates that the disk is write protected. (See also Force Write Protect Function) BIT 6 nDRV2 Active low status of the DRV2 disk interface input pin, indicating that a second drive has been installed. Note: This function is not supported in this chip. (Always 1, indicating 1 drive) BIT 2 nINDEX Active low status of the INDEX disk interface input. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. BIT 3 HEAD SELECT Active high status of the HDSEL disk interface input. A logic "1" selects side 1 and a logic "0" selects side 0. BIT 4 nTRACK 0 16 PS/2 Model 30 Mode RESET COND. 7 INT PENDING 0 6 DRQ 0 5 STEP F/F 0 4 TRK0 3 nHDSEL 2 INDX 1 WP 0 nDIR N/A 1 N/A N/A 1 BIT 4 TRACK 0 Active high status of the TRK0 disk interface input. BIT 0 nDIRECTION Active low status indicating the direction of head movement. A logic "0" indicates inward direction; a logic "1" indicates outward direction. BIT 5 STEP Active high status of the latched STEP disk interface output pin. This bit is latched with the STEP output going active, and is cleared with a read from the DIR register, or with a hardware or software reset. BIT 1 WRITE PROTECT Active high status of the WRITE PROTECT disk interface input. A logic "1" indicates that the disk is write protected. (See also Force Write Protect Function) BIT 6 DMA REQUEST Active high status of the DRQ output pin. BIT 2 INDEX Active high status of the INDEX disk interface input. BIT 7 INTERRUPT PENDING Active high bit indicating the state of the Floppy Disk Interrupt output. BIT 3 nHEAD SELECT Active low status of the HDSEL disk interface input. A logic "0" selects side 1 and a logic "1" selects side 0. 17 when in PS/2 mode. In the PC/AT mode the data bus pins D0 - D7 are held in a high impedance state for a read of address 3F1. STATUS REGISTER B (SRB) Address 3F1 READ ONLY This register is read-only and monitors the state of several disk interface pins in PS/2 and Model 30 modes. The SRB can be accessed at any time 7 1 RESET COND. 6 1 1 1 PS/2 Mode 5 4 3 2 DRIVE WDATA RDATA WGATE SEL0 TOGGLE TOGGLE 0 0 0 0 1 MOT EN1 0 0 MOT EN0 0 BIT 4 WRITE DATA TOGGLE Every inactive edge of the WDATA input causes this bit to change state. BIT 0 MOTOR ENABLE 0 Active high status of the MTR0 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 5 DRIVE SELECT 0 Reflects the status of the Drive Select 0 bit of the DOR (address 3F2 bit 0). This bit is cleared after a hardware reset and it is unaffected by a software reset. BIT 1 MOTOR ENABLE 1 Active high status of the MTR1 disk interface output pin. This bit is low after a hardware reset and unaffected by a software reset. BIT 6 RESERVED Always read as a logic "1". BIT 2 WRITE GATE Active high status of the WGATE disk interface output. BIT 7 RESERVED Always read as a logic "1". BIT 3 READ DATA TOGGLE Every inactive edge of the RDATA input causes this bit to change state. 18 PS/2 Model 30 Mode 7 nDRV2 RESET COND. 6 nDS1 5 nDS0 N/A 1 1 4 WDATA F/F 0 3 RDATA F/F 0 2 WGATE F/F 0 1 nDS3 0 nDS2 1 1 edge of RDATA and is cleared by the read of the DIR register. BIT 4 WRITE DATA Active high status of the latched WDATA output signal. This bit is latched by the inactive going edge of WDATA and is cleared by the read of the DIR register. This bit is not gated with WGATE. BIT 0 nDRIVE SELECT 2 The DS2 disk interface is not supported. (Always 1) BIT 1 nDRIVE SELECT 3 The DS3 disk interface is not supported. (Always 1) BIT 2 WRITE GATE Active high status of the latched WGATE output signal. This bit is latched by the active going edge of WGATE and is cleared by the read of the DIR register. BIT 5 nDRIVE SELECT 0 Active low status of the DS0 disk interface output. BIT 3 READ DATA Active high status of the latched RDATA output signal. This bit is latched by the inactive going BIT 7 nDRV2 Active low status of the DRV2 disk interface input, this is not supported. (Always 1). BIT 6 nDRIVE SELECT 1 Active low status of the DS1 disk interface output. 19 contains the enable for the DMA logic and a software reset bit. The contents of the DOR are unaffected by a software reset. The DOR can be written to at any time. DIGITAL OUTPUT REGISTER (DOR) Address 3F2 READ/WRITE The DOR controls the drive select and motor enables of the disk interface outputs. It also RESET COND. 7 MOT EN3 0 6 MOT EN2 0 5 MOT EN1 0 4 MOT EN0 0 3 DMAEN 0 2 1 0 nRESE DRIVE DRIVE T SEL1 SEL0 0 0 0 impedance state. This bit is a logic "0" after a reset and in these modes. PS/2 Mode: In this mode the DRQ, nDACK, TC and FINTR pins are always enabled. During a reset, the DRQ, nDACK, TC, and FINTR pins will remain enabled, but this bit will be cleared to a logic "0". BIT 0 and 1 DRIVE SELECT These two bits are binary encoded for the drive selects, thereby allowing only one drive to be selected at one time. BIT 2 nRESET A logic "0" written to this bit resets the Floppy disk controller. This reset will remain active until a logic "1" is written to this bit. This software reset does not affect the DSR and CCR registers, nor does it affect the other bits of the DOR register. The minimum reset duration required is 100ns, therefore toggling this bit by consecutive writes to this register is a valid method of issuing a software reset. BIT 4 MOTOR ENABLE 0 This bit controls the MTR0 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 5 MOTOR ENABLE 1 This bit controls the MTR1 disk interface output. A logic "1" in this bit will cause the output pin to go active. BIT 3 DMAEN PC/AT and Model 30 Mode: Writing this bit to logic "1" will enable the DRQ, nDACK, TC and FINTR outputs. This bit being a logic "0" will disable the nDACK and TC inputs, and hold the DRQ and FINTR outputs in a high BIT 6 MOTOR ENABLE 2 The MTR2 disk interface output is not. (Always 0) BIT 7 MOTOR ENABLE 3 The MTR3 disk interface output is not. (Always 0) TABLE 6 - DRIVE ACTIVATION VALUES DRIVE 0 1 DOR VALUE 1CH 2DH 20 TAPE DRIVE REGISTER (TDR) Address 3F3 READ/WRITE TABLE 7 - TAPE SELECT BITS TAPE SEL1 (TDR.1) 0 0 1 1 TAPE SEL0 (TDR.0) 0 1 0 1 DRIVE SELECTED None 1 2 3 TABLE 7 illustrates the Tape Select Bit encoding. Note that drive 0 is the boot device and cannot be assigned tape support. The remaining Tape Drive Register bits TDR.[7:2] are tristated when read. The TDR is unaffected by a software reset. The Tape Drive Register (TDR) is included for 82077 software compatibility and allows the user to assign tape support to a particular drive during initialization. Any future references to that drive automatically invokes tape support. The TDR Tape Select bits TDR.[1:0] determine the tape drive number. TABLE 8 - INTERNAL 2 DRIVE DECODE - NORMAL DRIVE SELECT OUTPUTS MOTOR ON OUTPUTS DIGITAL OUTPUT REGISTER (ACTIVE LOW) (ACTIVE LOW) Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0 X X X 1 0 0 1 0 nBIT 5 nBIT 4 X X 1 X 0 1 0 1 nBIT 5 nBIT 4 X 1 X X 1 0 1 1 nBIT 5 nBIT 4 1 X X X 1 1 1 1 nBIT 5 nBIT 4 0 0 0 0 X X 1 1 nBIT 5 nBIT 4 TABLE 9 - INTERNAL 2 DRIVE DECODE - DRIVES 0 AND 1 SWAPPED DRIVE SELECT MOTOR ON OUTPUTS DIGITAL OUTPUT REGISTER OUTPUTS (ACTIVE LOW) (ACTIVE LOW) Bit 7 Bit 6 Bit 5 Bit 4 Bit1 Bit 0 nDS1 nDS0 nMTR1 nMTR0 X X X 1 0 0 0 1 nBIT 4 nBIT 5 X X 1 X 0 1 1 0 nBIT 4 nBIT 5 X 1 X X 1 0 1 1 nBIT 4 nBIT 5 1 X X X 1 1 1 1 nBIT 4 nBIT 5 0 0 0 0 X X 1 1 nBIT 4 nBIT 5 21 Normal Floppy Mode Normal mode. Register 3F3 contains only bits 0 and 1. When this register is read, bits 2 - 7 are a high impedance. REG 3F3 DB7 Tri-state DB6 Tri-state DB5 Tri-state DB4 Tri-state DB3 Tri-state DB2 Tri-state DB1 tape sel1 DB0 tape sel0 DB1 tape sel1 DB0 tape sel0 Enhanced Floppy Mode 2 (OS2) Register 3F3 for Enhanced Floppy Mode 2 operation. DB7 DB6 REG 3F3 Reserved Reserved DB5 DB4 Drive Type ID DB3 DB2 Floppy Boot Drive TABLE 10 - DRIVE TYPE ID DIGITAL OUTPUT REGISTER REGISTER 3F3 - DRIVE TYPE ID Bit 1 Bit 0 Bit 5 Bit 4 0 0 L0-CRF2 - B1 L0-CRF2 - B0 0 1 L0-CRF2 - B3 L0-CRF2 - B2 1 0 L0-CRF2 - B5 L0-CRF2 - B4 1 1 L0-CRF2 - B7 L0-CRF2 - B6 Note:L0-CRF2-Bx = Logical Device 0, Configuration Register F2, Bit x. 22 and PS/2 Model 30 and Microchannel applications. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps. DATA RATE SELECT REGISTER (DSR) Address 3F4 WRITE ONLY This register is write only. It is used to program the data rate, amount of write precompensation, power down status, and software reset. The data rate is programmed using the Configuration Control Register (CCR) not the DSR, for PC/AT RESET COND. 7 6 S/W POWER RESET DOWN 0 0 5 0 0 4 PRECOMP2 0 3 PRECOMP1 0 2 1 0 PREDRATE DRATE COMP0 SEL1 SEL0 0 1 0 BIT 5 UNDEFINED Should be written as a logic "0". BIT 0 and 1 DATA RATE SELECT These bits control the data rate of the floppy controller. See Table 11 for the settings corresponding to the individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset. BIT 6 LOW POWER A logic "1" written to this bit will put the floppy controller into manual low power mode. The floppy controller clock and data mode after a software reset or access to the Data Register or Main Status Register. BIT 2 through 4 PRECOMPENSATION SELECT These three bits select the value of write precompensation that will be applied to the WDATA output signal. Table 10 shows the precompensation values for the combination of these bits settings. Track 0 is the default starting track number to start precompensation. this starting track number can be changed by the configure command. BIT 7 SOFTWARE RESET This active high bit has the same function as the DOR RESET (DOR bit 2) except that this bit is self clearing. Note: The DSR is Shadowed in the Floppy Data Rate Select Shadow Register, LD8:CRC2[7:0]. separator circuits will be turned off. The controller will come out of manual low power. 23 TABLE 11 - PRECOMPENSATION DELAYS PRECOMP PRECOMPENSATION 432 DELAY (nsec)