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F100K

Catalog Datasheet MFG & Type PDF Document Tags

F100K

Abstract: B1165 Many F100K designs require that certain inputs be preset to a HIGH or LOW level Because of the construction of the F100K input circuitry a LOW can be realized by simply leaving the input OPEN However a , temperature and VEE DESIGN CONSIDERATIONS The ranges of VIH and VIL across VEE (b4 2V to b5 7V for F100K , these ranges the input conditions are assured Figure 1 shows the voltage versus current for the F100K , inputs at voltage and current levels typical of F100K as shown in Figure 3 Figure 4 shows in more
National Semiconductor
Original
B1165 DIODE semiconductores 1203A AN-682 C1995 B870 D-82256

SSOP36

Abstract: LA73056 8.2 8.7 dB ICC1 VG VIN=1Vp-p,f=4.43MHz 1 VF1 VIN=1Vp-p,f=100k/5MHz 1,2,3ch -1.0 0 1.0 dB 2 VF2 VIN=1Vp-p,f=100k/10MHz 4,5,6ch -1.0 0 1.0 dB 3 VF3 VIN=1Vp-p,f=100k/27MHz 1,2,3ch -25 -20 dB 4 VF4 VIN=1Vp-p,f=100k/54MHz 4,5,6ch -25 -20 dB GD f=100k/4.43MHz ±15 ±20 ns
-
Original
LA73056 LA73052 SSOP36 A0246 75VTRDVD O0406 B8-7207 A0246-1/6

F100K

Abstract: AN682 equivalent Fairchild Semiconductor Application Note July 1992 Revised November 2001 Terminating F100K ECL Inputs Introduction Many F100K designs require that certain inputs be presented with a HIGH or LOW level. Because of the construction of the F100K input circuitry, a LOW can be realized by simply , -5.7V for F100K ECL 300 Series) are -870 mV to -1165 mV and -1475 mV to -1830 mV respectively. By , current for the F100K input transistor. If the input is tied to VCC/VCCA the input transistor saturates
Fairchild Semiconductor
Original
AN682 equivalent ECL300
Abstract: F100K INTRODUCTION Competitive pressure in the data processing industry, with ever-increasing , window. The new F100K standard subnanosecond ECL family has been designed to meet all these requirements , implementations were carefully considered prior to selecting the optimum gate configuration for the F100K family , compensation and extended temperature characteristics External wired-OR capability F100K circuits operate with , F100K directly interfaces with the widely available 2-ns ECL circuits. It should be empha sized that -
OCR Scan
F100117 F100118

B199 RF transistor datasheet

Abstract: F100K ECL 300 series and design guide noise margins When F100K ECL output signal interconnection lengths are direct and short enough , operation Please refer to section seven of the ``F100K ECL Logic Databook and Design Guide'' for a more , OPERATION AND WHY Figure 1 shows F100K logic elements operating in standard negative supply ECL , inherent F100K voltage compensation permits stable input and output levels over a broad range of VEE's i e b4 2 to b 5 7 VDC for 300 Series F100K Thus ECL logic operating from a b4 2V VEE is compatible to
National Semiconductor
Original
AN-780 B199 RF transistor datasheet F100K ECL 300 series and design guide F100K ECL book AN-780 national 7474-ttl

F100K ECL 300 series and design guide

Abstract: F100K ECL book to the stable passive Ground (0V). The inherent F100K voltage compensation permits stable input and output levels over a broad range of VEE's; i.e., -4.2 to -5.7 VDC for 300 Series F100K. Thus ECL logic , and preserve ECL noise margins. When F100K ECL output signal interconnection lengths are direct and , required for logic operation. Please refer to section seven of the "F100K ECL Logic Databook and Design , . STANDARD NEGATIVE SUPPLY ECL OPERATION AND WHY Figure 1 shows F100K logic elements operating in
Fairchild Semiconductor
Original
F100K300 F100K ECL 300 series databook and design guide

10K ECL

Abstract: F100K F100K 10K ECL 10K ECL 10K ECL F100K F100K Figure 6 CLC007 AB A.C
National Semiconductor
Original
SMPTE259M GS9007 CLC006 10K ECL CLC0072 125/W 105/W CLC730056

LA73053

Abstract: 70dBS 6.2 6.7 dB ICC1 VG VIN=1Vp-p,f=4.43MHz 1 VF1 VIN=1Vp-p,f=100k/5MHz 1,2,3ch -1.0 0 1.0 dB 2 VF2 VIN=1Vp-p,f=100k/10MHz 4,5,6ch -1.0 0 1.0 dB 3 VF3 VIN=1Vp-p,f=100k/27MHz 1,2,3ch -25 -20 dB 4 VF4 VIN=1Vp-p,f=100k/54MHz 4,5,6ch -25 -20 dB GD f=100k/4.43MHz ±10 ±15 ns
-
Original
LA73053 70dBS B8751 B8-7512 35VDC

LA73050

Abstract: SSOP36 =4.43MHz 1 VF1 VIN=1Vp-p,f=100k/5MHz 2 VF2 min typ max unit 56.1 66 75.9 mA 5.7 6.2 6.7 dB -1.0 0 1.0 dB VIN=1Vp-p,f=100k/27MHz -25 -20 dB GD f=100k/4.43MHz ±10 ±15 ns VO max f=1kHz,THD=1% 3.0 H VcntH
-
Original
LA73050 B8-7297 B8-5698 A0241-1/6 A0241-2/6

ENC 03

Abstract: 14pin connector -0.5 0.5 dB Vin=1.0Vpp , f=100k/6.75MHz FCV-LPF2 -38 -27 dB Vin=1.0Vpp , f=100kHz , 5.5 7.5 mA GVPS0 -0.7 -0.2 0.3 dB Vin=1Vpp , f=100kHz GVPS6 5.7 6.2 6.7 dB Vin=1Vpp , f=100kHz GAD0 -0.8 -0.3 0.2 dB Vin=1Vpp , f=100kHz GAD2 1.4 1.9 2.4 dB Vin=800mVpp , f=100kHz GL1AUX6 5.5 6.0 6.5 dB Vin=1Vpp , f=100kHz GL1AUX8 7.7 8.2 8.7 dB Vin=800mVpp , f=100kHz GAUX6-1 5.7 6.2
ROHM
Original
BH7624KS2 BD3825FS ENC 03 14pin connector ASW4 SW11

F100K ECL 300 series and design guide

Abstract: F100K ECL book passive Ground (0V). The inherent F100K voltage compensation permits stable input and output levels over a broad range of VEE's; i.e., -4.2 to -5.7 VDC for 300 Series F100K. Thus ECL logic operating from , nature of the transient IEE demands. Figure 1 shows F100K logic elements operating in standard , and preserve ECL noise margins. When F100K ECL output signal interconnection lengths are direct and , required for logic operation. Please refer to section seven of the "F100K ECL Logic Databook and Design
Fairchild Semiconductor
Original

F100K ECL 300 series and design guide

Abstract: ESD diode passive Ground (0V). The inherent F100K voltage compensation permits stable input and output levels over a broad range of VEE's; i.e., -4.2 to -5.7 VDC for 300 Series F100K. Thus ECL logic operating from , nature of the transient IEE demands. Figure 1 shows F100K logic elements operating in standard , and preserve ECL noise margins. When F100K ECL output signal interconnection lengths are direct and , required for logic operation. Please refer to section seven of the "F100K ECL Logic Databook and Design
Fairchild Semiconductor
Original
ESD diode
Abstract: F100K LOGIC GATE ARRAY DESCRIPTION The F100K Logic Gate Array is a 168 gate array consisting of a 6 x 6 array of internal cells, each cell consisting of 4-2 input gates and 24 output buffer gates arranged 12 on each side. Each of the 24 output buffer gates has 2 inputs and fo r every 2 output gates , to be F100K com patible. The internal gates are actually not fu lly compensated except that the bias , masks that are applied to the basic 168-switch array to form the LSI circuit. 10-90 168 GATE, F100K -
OCR Scan
LSI-168

LA73052

Abstract: SSOP36 =1Vp-p,f=4.43MHz 1 VF1 VIN=1Vp-p,f=100k/5MHz 2 VF2 typ max unit 46.8 55 63.2 mA 5.7 6.2 6.7 dB -1.0 0 1.0 dB VIN=1Vp-p,f=100k/27MHz -25 -20 dB GD f=100k/4.43MHz ±10 ±15 ns VO max f=1kHz,THD=1% 3.0 H VcntH
-
Original
B8-7298 B8-5738 A0244-1/6 A0244-2/6 A0244-3/6

TR20X3

Abstract: OR02D delay Flexible array architecture with only two cell types: Internal cells and I/O cells F100K, 10K or , power consumption. With F100K inputs and outputs, the FGA se ries is designed to operate from a standard , F100K F10K F100K/TTL F10K/TTL Pseudo TTL Vcc(V) GND GND GND GND Vttl Vtt (V)(Note 2) -1 .9 to -2.1 -1 .9 , FGA 30000 4.5 to 5.5 4.5 to 5.5 4.75 to 5.25 F100K ECL DC Characteristics VEE = -4.5V , Vjt = , . Either F100K, 10K, or 10KH interface capability is available on all FGA Series arrays. All input
-
OCR Scan
TR20X3 OR02D DFI01

LA73051

Abstract: SSOP24J VF1 VIN=1Vp-p,f=100k/5MHz 2 VF2 min typ max unit 28.9 34.0 39.1 mA 5.7 6.2 6.7 dB -1.0 0 1.0 dB VIN=1Vp-p,f=100k/27MHz -25 -20 dB GD f=100k/4.43MHz ±10 ±15 ns VO max f=1kHz,THD=1% 3.0 H VcntH 7
-
Original
LA73051 SSOP24J B8-7296 B8-5737 A0243-1/5

10K ECL

Abstract: CLC005 Figure 6 CLC005 AB A.C. D.C. F100K 10K ECL 10K ECL 10K ECL F100K F100K 5 http://www.national.com CLC005 CLC005 H L Figure 8 pin3 REXT-L
National Semiconductor
Original
CLC005ITU-T 2-17-16TEL

F100K ECL book

Abstract: Fair-Rite affected by packaging For this reason National has chosen to supply F100K minimum-skew devices in packaging complementing their inherent performance F100K devices are supplied in SOIC PCC and flatpak , considerations can be found in the ``F100K ECL Logic Databook and Design Guide'' Chapter 5 POWER SUPPLY , the system pass-band helps accomplish all goals of efficient bypassing The ``F100K ECL Logic , to be optimally effective Supply bypassing is generally less critical in F100K ECL systems than in
National Semiconductor
Original
Fair-Rite 6-hole Ferroxcube AN817 AN470 AN8171 an-470 national
Abstract: /7MHz Vin=1.0Vpp , f=100k/6.75MHz Vin=1.0Vpp , f=100kHz/27MHz Vin=1.0Vpp , f=100k/6.75MHz Vin=1.0Vpp , f=100kHz , dB dB dB dB dB dB dB dB dB dB dB Vp-p Vp-p Vp-p Vp-p Vp-p Vp-p Vp-p Vp-p Vin=1Vpp , f=100kHz Vin=1Vpp , f=100kHz Vin=1Vpp , f=100kHz Vin=800mVpp , f=100kHz Vin=1Vpp , f=100kHz Vin=800mVpp , f=100kHz Vin=450mVpp , f=100kHz Vin=450mVpp , f=100kHz Vin=360mVpp , f=100kHz Vin=450mVpp , f=100kHz Vin=360mVpp , f=100kHz Vin=450mVpp , f=100kHz Vin=360mVpp , f=100kHz Vin=700mV , f=100kHz Vin=560mV , f=100kHz Vin=560mV , f=100kHz ROHM
Original

LA7109

Abstract: 810av 6.2 6.7 dB 1 VF1 VIN=1Vp-p,f=100k/7MHz -1.0 0 1.0 dB 2 VF2 VIN=1Vp-p,f=100k/27MHz -25 -20 dB GD f=100k/4.43MHz ±10 ±15 ns V0 max f
-
Original
LA7109 810av LA71 B8-5104 A0640-1/5 A0640-2/5 A0640-3/5
Abstract: 8.2 8.7 dB ICC1 VG VIN=1Vp-p,f=4.43MHz 1 VF1 VIN=1Vp-p,f=100k/5MHz 1,2,3ch -1.0 0 1.0 dB 2 VF2 VIN=1Vp-p,f=100k/10MHz 4,5,6ch -1.0 0 1.0 dB 3 VF3 VIN=1Vp-p,f=100k/27MHz 1,2,3ch -25 -20 dB 4 VF4 VIN=1Vp-p,f=100k/54MHz 4,5,6ch -25 -20 dB GD f=100k/4.43MHz ±15 ±20 ns -
OCR Scan
100WVDC 630WVDC 675-I760

F100K ECL 300 series and design guide

Abstract: Amos 6.2 6.7 dB ICC1 VG VIN=1Vp-p,f=4.43MHz 1 VF1 VIN=1Vp-p,f=100k/5MHz 1,2,3ch -1.0 0 1.0 dB 2 VF2 VIN=1Vp-p,f=100k/10MHz 4,5,6ch -1.0 0 1.0 dB 3 VF3 VIN=1Vp-p,f=100k/27MHz 1,2,3ch -25 -20 dB 4 VF4 VIN=1Vp-p,f=100k/54MHz 4,5,6ch -25 -20 dB GD f=100k/4.43MHz ±10 ±15 ns
Fairchild Semiconductor
Original
AN-817 Amos AN467 an-468 national 300-SERIES

AN817

Abstract: F100K ECL 300 series and design guide the F100K 300 Series devices is 6X when the output is conditioned to a HIGH level and 8X when , lower impedance also reduces the effects of noise The National Semiconductor F100K 300 Series octal , specifications for most of the F100K 300 Series devices The table (shown in Figure 3 ) gives the resistor , layout decoupling and thermal effects must all be considered When designing a backplane with F100K 300 , away from the threshold SYSTEM DESIGN CONSIDERATIONS Wired-OR Configuration F100K 300 Series
Fairchild Semiconductor
Original
F100311 opti databook RADIOTRON

AN-768 national

Abstract: PC MOTHERBOARD POWER DISTRIBUTION from National Semiconductor's F100K ECL 300 Series product line Focus will be on Dual Rail , ECL with the 100324 ECL to TTL with F100K ECL Dual Rail Translators F100K ECL Dual Rail , to the traditional ceramic DIP and Flatpak packages the F100K 300 Series translators offer a 28 , cache TL F 10938 ­ 5 FIGURE 4 Two Way Set Associative Cache System 5 F100K ECL Dual Rail , '' Fourth Edition 1988 Copyright Motorola Inc ``F100K ECL Logic Databook and Design Guide'' 1990 Edition
National Semiconductor
Original
AN-768 national PC MOTHERBOARD POWER DISTRIBUTION AN-768

F100K ECL 300 series and design guide

Abstract: F100K ECL Users Handbook FCT F100K 300 Series ECL Total Dose Degradation of the Device's Switchpoint Low Dose Rate , for RHA Qualification FACT QS ACTQ Products Proposed for RHA Qualification FACT FCT Logic F100K 300 , Test Results F100K 300 Series ECL Products Proposed for RHA Qualification SCAN System & Board Test , are built. F100K 300 Series ECL: Having F100K ECL speed and performance, National's F100K 300 , a particular application. Logic Family FACTTM FACT Quiet SeriesTM HC HCS F100K 300 Series
National Semiconductor
Original
F100K ECL Users Handbook AN768J AN-784 national AN7841 AN-784 ECL88

ASTM-F-1892

Abstract: 38510R75001 =1Vp-p,f=4.43MHz 1 VF1 VIN=1Vp-p,f=100k/5MHz 2 VF2 typ max unit 46.8 55 63.2 mA 5.7 6.2 6.7 dB -1.0 0 1.0 dB VIN=1Vp-p,f=100k/27MHz -25 -20 dB GD f=100k/4.43MHz ±10 ±15 ns VO max f=1kHz,THD=1% 3.0 H VcntH
National Semiconductor
Original
ASTM-F-1892 38510R75001 ASTM-F1892 54AC14 MDS 54AC00 seu 54ACTQ574 00E-08 00E-05 75E-06 62E-06 51E-06 20E-04
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