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Part Manufacturer Description Datasheet BUY
PHYTERA-ETHERNETINTEGRITY-SW Texas Instruments PHYTER? Ethernet Integrity Utility visit Texas Instruments
TNETE2004PBE Texas Instruments DATACOM, ETHERNET TRANSCEIVER, PQFP120, PLASTIC, HQFP-120 visit Texas Instruments
TNETE2008PBE Texas Instruments DATACOM, ETHERNET TRANSCEIVER, PQFP120, PLASTIC, HQFP-120 visit Texas Instruments
TLK1201IRCPRG4 Texas Instruments DATACOM, ETHERNET TRANSCEIVER, PQFP64, PLASTIC, HVQFP-64 visit Texas Instruments
TNETE2004PAC Texas Instruments DATACOM, ETHERNET TRANSCEIVER, PQFP128, PLASTIC, HQFP-128 visit Texas Instruments
LM3S6965 Texas Instruments Ethernet Evaluation Kits visit Texas Instruments

Ethernet to HDLC

Catalog Datasheet MFG & Type PDF Document Tags

Ethernet to HDLC

Abstract: hdlc -port Ethernet to HDLC (High-level Data Link Control) bridge. The chip for connecting Ethernet to HDLC is , processor that can transform Ethernet frame to HDLC frame and conversely. It can simultaneously receive 8 HDLC frames and 8 Ethernet frames. At the same time, it can transmit 8 HDLC frames and 8 Ethernet , shaping circuit to adjust data flow rate · Reduced function set of Ethernet MAC · CRC generation , eight Ethernet MACs that can be operated at 100Mbps in full duplex. Each of the Ethernet MAC engines
MCS Logic
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Ethernet to HDLC

Abstract: MLN7000 Introduction MLN7000 is a cost-effective single chip solution for 8-port Ethernet to HDLC bridge. The bridge chip for connecting Ethernet to HDLC is usually installed in various IP-based xDSL network such as ADSL, SDSL, VDSL and G.HDSL. The MLN7000 has eight Ethernet MACs that can be operated at 100Mbps in , Ethernet frame to HDLC frame and conversely. It can simultaneously receive 8 HDLC frames and 8 Ethernet frames. At the same time, it can transmit 8 HDLC frames and 8 Ethernet frames. MLN7000 has an internal
MCS Logic
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Ethernet to HDLC ethernet network switch CIRCUIT diagram DSLAM ip dslam hdlc HDLC to Ethernet 10M/100M

Ethernet to HDLC

Abstract: mii to hdlc single-chip for 1-port Ethernet to HDLC (High-level Data Link Control) bridge. The Ethernet Interface , backpressure for flow control in half duplex. It ijqnterfaces with standard Ethernet devices using the IEEE 802.3 MII (Media Independent Interface) and other common Ethernet interfaces. HDLC can transform Ethernet frame to HDLC frame. MLN7010 supports the HDLC bit-synchronous interface mode. No external , Ethernet-to-HDLC and HDLC-to-Ethernet frame conversion · IEEE 802.3 compliant Ethernet · Media Independent
MCS Logic
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mii to hdlc ethernet

MLN7010

Abstract: Ethernet to HDLC Introduction MLN7010 is a highly integrated and cost-effective single-chip for 1-port Ethernet to HDLC (High-level Data Link Control) bridge. The Ethernet Interface supports 10 Mbps and 100 Mbps data rates, full , backpressure for flow control in half duplex. It interfaces with standard Ethernet devices using the IEEE 802.3 MII (Media Independent Interface) and other common Ethernet interfaces. HDLC can transform Ethernet frame to HDLC frame. MLN7010 supports the HDLC bit- and byte-synchronous interface mode. No external
MCS Logic
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8023X automatic room power control circuit block diagram

Ethernet to HDLC

Abstract: Redux development required · E1/T1/J1 to Ethernet protocol conversion · Ethernet to Ethernet processing · Ethernet to HDLC WAN link support ar TDM over Ethernet/IP Bridging in · tunneling E1/T1/J1 , the Central Office ·Ethernet interface to the subscriber premises LAN or router connection in the Central Office ·Service interface, configurable to Ethernet or HDLC operation, for connection to the high , : · Subscriber - MII/RMII at up to 100 Mbps ·TDM/Bitstream - E1, T1 or J1 · Service - MII or HDLC at
Redux Communications
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RS-160 Redux tdmoip RS-160Q RS-0160Q DC-DS-0160 DC-PB-0160-A

Ethernet to HDLC

Abstract: LXT970 path of data transformation (from Ethernet to HDLC packet) on its way to WAN access. The bottom of , to add a multi-port Fast Ethernet repeater to the router as shown in Figure 3. Use the LXT970A to , clients and servers, through repeaters, and on to the router, which examines Ethernet packet IP addresses , LAN Phy MAC NRZ packet HDLC Buffer Memory NRZ payload Ethernet Application Note , , by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as
Intel
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MP860T LXT970 LXT441 intel ethernet 249107 LXT980 AN095 10BASE-T 100BASE-TX

3G ATM

Abstract: AAL5 ATM PHY Figure 21 - Using MT922x0 to Bridge AAL5 and UDP/IP/Ethernet Packet in HDLC , convert 1023 full-duplex PCM or ADPCM voice channels, or 4096 HDLC channels to RTP/UDP/IP packets, and , MT922x0 supports a variety of layer 2 to layer 4 protocols including: · · · Layer 2: Ethernet II, 802.3 , being handed over to Packet Routing module. From this point forward, all Ethernet packets from MII , to CPU interface for CPU processing. 2. HDLC Process. The whole RTP packet or UDP payload can be
Zarlink Semiconductor
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3G ATM ZLAN-15 MT922 MT92220 MT92210

cd 1619 CP

Abstract: pin configuration of cd 1619 cp interface. For example, FCC1 supports UTOPIA 8 (ATM), MII (Ethernet and Fast Ethernet), HDLC (serial and , RXD6 RXD5 RXD4 RXD3 RXD2 RXD1 RXD0 Channels, Interfaces and Protocols FCC1 HDLC/ Ethernet , / Ethernet transp. HDLC MII Serial Nibble TX_ER RX_DV TX_EN RX_ER RTS TXD0 RXD0 RXD1 RXD2 RXD3 , Ethernet, UTOPIA 8 Slave/Master direct polling, HDLC serial/nibble, Transparent FCC2: HDLC serial/nibble, Transparent SCC1: Ethernet, HDLC serial, UART, Transparent SCC2: Ethernet, HDLC serial, UART, Transparent
Motorola
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MSC8101 cd 1619 CP pin configuration of cd 1619 cp cd 1619 CP diagram FCC2 MCC12 MPC8260 AN1854/D

RFC5086

Abstract: pwe3 rtp ) for transmission over a 100/1000Mbps Ethernet port. Each TDM port's bit rate can vary from 64Kbps to 2.048Mbps to support T1/E1 or slower TDM rates. PW interworking for TDM-based serial HDLC data is also , of TDMoP and/or HDLC PWs PSN Protocols: L2TPv3 or UDP Over IP (IPv4 or IPv6), Metro Ethernet , Timing For Structured T1/E1, Each TDM Port Includes DS0 TSA Block for any Time Slot to Any PW 32 HDLC , HDLC/SAT Engine (32 Total) Any data rate from 64Kbps to 2.048Mbps 32-Bit or 16-Bit CPU Processor Bus
Maxim Integrated Products
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DS34S132 RFC5086 pwe3 rtp EPON based VOIP SMti Ram DS34T101 100/1000M 676-B

redux 204

Abstract: LTXD e3 support Ethernet Bridging at up to 100 Mbps The RS-120 provides Ethernet bridging at full wire , up to 10,000 MAC addresses. MII and HDLC Interfaces Applications - layer 2 front end for , a standard HDLC controller at speeds of up to 100 Mbps making the RS-120 ideal for a variety of , HDLC Controller or Ethernet MAC Subscriber Interface Ethernet MAC DCLKO DCLKI WDCE , an Ethernet MII port. Each type of port is described in its own column. The MII and HDLC ports can
Redux Communications
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redux 204 LTXD e3 V54C365164VCT8PC DC-DS-0120 LCFG MA10 CS004 RS-120Q CS-029 RS-120F

GFP 740

Abstract: EoPDH -1 links or serial HDLC links through a switched-IP or MPLS packet network, while integrating up to eight , ·HDLC controller in Tx and Rx paths with access to FDL, Sa, or a single DS0 channel ·High impedance in , Ethernet over 1 T1/E1 HDLC with integrated T1/E1 transceiver Ethernet over OC-3/STM-1 at less than 1W of , ; CESoPSN, SAToP, HDLC, TDMoIP; EV kit Pseudowire circuit emulation of E1/T1/E3/T3/STS-1 over Ethernet , standards (GFP/HDLC) with VCAT/LCAS link aggregation up to 16 PDH links (416Mbps); 1 GbE or 2 10/100; QoS
Maxim Integrated Products
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GFP 740 EoPDH E1 to ethernet converter circuit HDB3 to LVDS 10G BERT DS26514 DS33X162
Abstract: higher-level functions such as Ethernet MAC functions, HDLC framing, etc. are all intended to be done outside , HDLC or Ethernet encapsulated data is presented to the user at either the HDLC or Ethernet interfaces , core. â'" Supports a fast C&M channel based on a serial Ethernet interface (84.48 Mbps max.) to the user logic, a non-standard rate MII Ethernet interface to a MAC, or a 100 Mbps MII interface to a PHY device. Accepts a user-selected pointer to the CPRI subchannel where the Ethernet link starts. The Lattice Semiconductor
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IPUG56 LFE3-95E-7FN1156CES D-2009 12L-1

MC68360 microcode ethernet

Abstract: MC145574 tasks for the device. It currently supports seven protocols: Ethernet, HDLC/SDLC, HDLC Bus, AppleTalk , are difficult to implement using an unaltered HDLC controller. These functions include: counting the , 10 Mbit Ethernet, 2 x 2.048 Mbit HDLC 2 x 4 Mbit HDLC, 2 x 19.2 Kbit SMC UART 1 x 6 Mbit HDLC, 2 x , can be constructed to link remote Ethernet LANs over E1 telecommunications links. E1 ATM Frame , available Asynchronous HDLC bandwidth is used, the remaining RISC processing power can be used to run other
Motorola
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MC68360 MC68EN360 MC68360 microcode ethernet MC145574 MC68160 M68360SWATM1-DOS M68360MC/D

DS34S132

Abstract: EPON ONU ) for transmission over a 100/1000Mbps Ethernet port. Each TDM port's bit rate can vary from 64Kbps to 2.048Mbps to support T1/E1 or slower TDM rates. PW interworking for TDM-based serial HDLC data is also , of TDMoP and/or HDLC PWs PSN Protocols: L2TPv3 or UDP Over IP (IPv4 or IPv6), Metro Ethernet , Timing For Structured T1/E1, Each TDM Port Includes DS0 TSA Block for any Time Slot to Any PW 32 HDLC , HDLC/SAT Engine (32 Total) Any data rate from 64Kbps to 2.048Mbps 32-Bit or 16-Bit CPU Processor Bus
Maxim Integrated Products
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EPON ONU MAC layer sequence number MPLS over optical packet switching structure of GMII packet with VLAN Tag TDAT31 23C/W

Profibus microcode

Abstract: MC68360 microcode ethernet processing tasks for the device. It currently supports seven protocols: Ethernet, HDLC/SDLC, HDLC Bus , that are difficult to implement using an unaltered HDLC controller. These functions include: counting , . Using the Ethernet channel available on the QUICC, remote LAN bridging equipment can be constructed to , INFORMATION MOTOROLA Ethernet Figure 3. Asynchronous HDLC Block Diagram KEY FEATURES â'¢ Flexible data , HDLC, 9.6 Kbit SMC UART 2 x 230 Kbit/s 15% 1 x 10Mbit Ethernet, 1 x 1.5 Mbit HDLC, 9.6 Kbit SMC UART
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OCR Scan
Profibus microcode Profibus UART MTP LAYER MC145572 hecs 50 1ATX31787-0

18 pin encoder ic for 40MHz remote controller

Abstract: 4 ch long range ir remote control -ch HDLC I&D Cache (8K) Host to PCI Bridge SRAM (2K) 2-ch UART 2-ch Timer (32 , Ethernet Controller (10/100M MAC) HDLC UART DMA IIC bus interface Timer Interrupt Etc. z , ethernet controller(MAC) and HDLC · Higher memory efficiency Various peripherals such as IIC bus, UART , -word burst transfer mode Count for counting transferred bytes from HRxFIFO to memory HDLC frame length , , or 8K SRAM Mode) 2-channel UART 2-channel HDLC with DMA IIC Bus (Simple master) 2-channel DMA 2
Samsung Electronics
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KS32C5000 18 pin encoder ic for 40MHz remote controller 4 ch long range ir remote control ATM25 R4000 196-QFP KS32C5100

444 NDK

Abstract: 444 NDK 27 current form of the driver and HDLC module includes a low level API (similar to the Ethernet packet driver , LogicIO ETHC6000 HAL libraries Source code to the simulated Ethernet library Source code to the NULL (or "stubbed") Ethernet library The libraries are individually described in , driver is called from "kernel mode" to pass in its pending Ethernet packets. Additional HAL devices can , 's Reference Guide, and the interface to the HDLC framer is documented in Appendix C. The source code supplied
Texas Instruments
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TMS320C6000 444 NDK 444 NDK 27 TL16C750 PI DSP BIOS example source code SPRU401 SPRU030

464c

Abstract: AU4-64c KHATANGA 10 Gigabit Ethernet MAC and PHY / OC-192c POS Framer and Mapper General Description Features · Single STS-192c/STM-64 framer/mapper device to support 10 Gigabit Ethernet (10GbE) serial WAN, serial LAN and STS-192c/AU-4-64c POS applications. · POS processing includes HDLC framing, payload , , pad insertion, and CRC generation. · Supports full duplex mapping of Ethernet frames into a single , baseline specification for 10GbE over the WAN. · 10GbE MAC receive processing includes Ethernet
Applied Micro Circuits
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S19205CBI GR-253 S3091 464c AU4-64c amcc 783 P802 OC-192 STS-192

XAPP761C

Abstract: DS611 (Ethernet) and Slow (HDLC) Control and Management (C&M) Channels · Designed to CPRI Specification v2.1 . , Ethernet MAC to be attached to the core to provide a high-speed channel for management information. · , Ethernet, HDLC, 6 IQ channels (WIDTH = 10) Master 1785 1993 5 1 1 HDLC, 6 IQ channels (WIDTH = 10) Master 1257 1476 2 1 1 Ethernet, HDLC, 6 IQ channels (WIDTH = 10 , 1 1 Ethernet, HDLC, 12 IQ channels (WIDTH = 8) Master 1948 2289 5 1 1
Xilinx
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DS611 XAPP761C design of HDLC controller using vhdl ethernet xilinx vhdl Xilinx Ethernet development cpri
Abstract: voice channels over IP/UDP/RTP connections or AAL2 VC â'¢ Up to 4096 HDLC channels carrying , links (Ethernet, ATM, Packet over SONET) â'¢ RTP packaging is optional per connection â'¢ HDLC , â'¢ Up to 4096 connections â'¢ Up to 1023 PCM/ADPCM channels â'¢ Support for up to 4096 HDLC , CID can interlace up to 64 PCM/ADPCM channels â'¢ HDLC packets contain application data (UDP , HDLC encapsulated mini-packets with asynchronous timing â'¢ Support of HDLC streams ranging from 1 to Zarlink Semiconductor
Original
DS5659
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