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Part : EP910DI-35 Supplier : Rochester Electronics LLC Manufacturer : Avnet Stock : - Best Price : $125.1084 Price Each : $136.6316
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Part : EP910LC-30 Supplier : Rochester Electronics LLC Manufacturer : Avnet Stock : - Best Price : $97.3855 Price Each : $106.3553
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Part : RGH2012-2E-P-910-B Supplier : Susumu Manufacturer : Newark element14 Stock : - Best Price : $0.0890 Price Each : $0.1080
Part : EP910DI-30 Supplier : Rochester Electronics LLC Manufacturer : Rochester Electronics Stock : 144 Best Price : $135.0100 Price Each : $155.52
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Part : EP910ILI-12 Supplier : Rochester Electronics LLC Manufacturer : Rochester Electronics Stock : - Best Price : - Price Each : -
Part : EP910ILI-12 Supplier : Altera Manufacturer : Rochester Electronics Stock : 734 Best Price : $33.97 Price Each : $41.81
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Part : EP910PC-40 Supplier : Altera Manufacturer : America II Electronics Stock : - Best Price : - Price Each : -
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EP910 Datasheet

Part Manufacturer Description PDF Type
EP910 Altera User Configurable Logic Data Book Scan
EP9100 PCA Electronics Delay Line TAPPED 5TAP 1IN 5NS ABS 25NS MAX Original
EP9101 PCA Electronics SMD 28 Pin 5 Tap TTL Compatible Active Delay Line Original
EP9102 PCA Electronics Delay Line TAPPED 5TAP 1IN 7NS ABS 35NS MAX Original
EP9103 PCA Electronics Delay Line TAPPED 5TAP 1IN 8NS ABS 40NS MAX Original
EP910-30 Altera High-performance, 16-macrocell Classic EPLD Original
EP910-30 Altera Classic EPLD Family Scan
EP910-30CERDIP40 Altera SPLD Original
EP910-30PDIP40 Altera SPLD Original
EP910-30PLCC44 Altera SPLD Original
EP910-35 Altera High-performance, 24-macrocell Classic EPLD Original
EP910-35 Altera Classic EPLD Family Scan
EP910-35CERDIP40 Altera SPLD Original
EP910-35PDIP40 Altera SPLD Original
EP910-35PLCC44 Altera SPLD Original
EP9104 PCA Electronics Delay Line TAPPED 5TAP 1IN 9NS ABS 45NS MAX Original
EP910-40 Altera High-performance, 16-macrocell Classic EPLD Original
EP910-40 Altera Classic EPLD Family Scan
EP910-40CERDIP40 Altera SPLD Original
EP910-40PDIP40 Altera SPLD Original
Showing first 20 results.

EP910

Catalog Datasheet MFG & Type PDF Document Tags

EP910

Abstract: altera EP910 Operating Conditions: EP910 N o te s (1 ), (2 ) EP910-30 EP910T-30 EP910-35 EP910-40 , EPLD AC Operating Conditions: EP910I Notes ( 1), (2) EP910I-12 EP910I-15 EP910I-25 Non-Turbo , PDIP EP910-35 35 28 MHz 37 MHz 44-pin 44-pin 40-pin 40-pin JLCC PLCC CerDIP PDIP EP910-40 40 25 , compatible pin-, function-, and programming file-compatible: EP910, EP910T, and EP910I Programmable Clock , EP910 EP910T EP910I 40-Pin DIP EP910 EP910T EP910I Altera Corporation 357 EP910 EPLD
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altera EP910
Abstract: 0 ns EP910-30 EP910-35 EP910-40 C1 = 35 pF C1 = 5 pF, See Note (10) l CLR , Availability Operating Temperature Availability Commercial (0° C to 70° C) EP910-30, EP910-35, EP910-40 Industrial (-40° C to 85° C) EP910-35, EP910-40 Military (-55° C to 125° C , capacitance V ,N = 0 V , f = 1.0MHz 20 pF AC Operating Conditions See Note (5) EP910-30 , Input to output enable tpxz Input to output disable Min Max Min Max EP910-40 Min -
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EP910A

EP910

Abstract: EPLDs The EP910 EPLD is pin-, function-, and JEDEC-File-compatible with the EP910A and EP910T EPLDs , The EP910A is a high-speed version of the EP910 EPLD. It is available with maximum tPD values of 15 , EP910T EPLD is a lower-cost version of the EP910 device. This device operates in Turbo mode only. The , EP910 EPLDs 'A Data Sheet September 1991, ver. 2 Features â¡ â¡ â¡ â¡ â , support A ltera's EP910 Erasable Programmable Logic Devices (EPLDs) can implement up to 900 equivalent
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EP910

Abstract: P L D is pin-, function-, and JEDEC-Eile-com patible w ith the EP910A and EP910T EPLD s. JE D E C , EP910A The EP910A is a high-speed version of the EP910 E P L D . It is available with maximum values of , The EP910T E P L D is a lower-cost version of the EP910 device. This device operates in Turbo mode , EP910 EPLDs / a n U High-Performance 24-Macrocell Devices September 1991, ver. 2 Data , support Features tPD Classic EPLDs u General Description A lte ra's EP910
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altera EP9101

Abstract: altera ep910i Parameters Notes (1), (2) Symbol Parameter Conditions EP9101-12 EP910I-15 EP910I-25 Non-Turbo Unit , delay Register setup time Register hold time Condition EP910I-12 EP9101-15 EP9101-25 Unit Min Max , Maximum internal array clock frequency Conditions EP910-30 EP910-35 EP910-40 Non- Unit Turbo Min Max , delay Register clear time Condition EP910-30 EP910-35 EP910-40 Unit Min Max Min Max Min Max 9.0 , Programmable I/O architecture with up to 36 inputs or 24 outputs EP910 and EP910I devices are pin-, function
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altera EP9101 altera ep910i ALTERA MAX 5000 programming

altera ep900i

Abstract: IC MSI ADDER tcLR EP9101-12 EP910I-15 EP910I-25 P a ra m e te r input pad and buffer delay I/O input , External Timing Parameters Sym bol *PD1 tpD2 tpzx 'pxz Notes ( 1), (2) EP910-30 EP910-35 EP910-40 , EP9101-15 EP910I-25 P a ra m e te r Input to non-registered output, Note (4) I/O input to , EP910-35 EP910-40 P a ra m e te r Input pad and buffer delay I/O input pad and buffer delay Logic , . Output Drive Characteristics of EP910 Devices EP910EPLDs EP910I EPLDs < E o 3 Q. D o o
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altera ep900i IC MSI ADDER EP900I

ALTERA MAX 5000 programming

Abstract: osbt EPLD AC Operating Conditions: EP910 Notes (1), (2) EP910-30 EP910T-30 EP910-35 EP910-40 Non-Turbo , Features Feature EP910-30 EP910-35 EP910-40 EP910T EP910I tpo 30 35 40 30 12 Counter frequency 33 MHz , ¡5^5372 00042flû 22T H 363 EP910 EPLD AC Operating Conditions: EP910I Notes (1), (2) â I EP910I-12 EP910I-15 , -, function-, and programming file-compatible: EP910, EP910T, and EP910I Programmable Clock option for , ¡ INPUT â¡ INPUT â¡ CLK2 44-Pin J-Lead 40-Pin DIP EP910 EP910T EP910I EP910 EP910T EP910I Altera
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osbt EP910-t 24-MACROCELL

altera EP910I

Abstract: EP910-T Operating Conditions: EP910 Notes ( 1), (2) EP910-30 EP910T-30 EP910-35 EP910-40 Non-Turbo Adder Symbol , : EP910I Notes ( 1), (2) EP910I-12 EP910I-15 EP910I-25 Non-Turbo Adder Note (3) 40 40 40 40 0 40 0 0 0 14 , compatible pin-, function-, and programming file-compatible: EP910, EP910T, and EP910I Programmable Clock , INPUT INPUT CLK2 44-Pin J-Lead EP910 EP910T EP910I 40-Pin DIP EP910 EP910T EP910I Altera , . EP910 Device Features Feature tpD Counter frequency Pipeline data rates Packages EP910-30 30 33
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Altera Classic EPLDs DD04E

EP910

Abstract: ep910-30 Output capacitance Clock pin capacitance AC Operating Conditions Note (5) EP910-30 EP910-35 EP910-40 , ) Availability EP910-30, EP910-35, EP910-40 EP910-35, EP910-40 Consult factory C la ssic Altera , maximum frequency Note (7) 18 30 33.3 EP910-30 28.6 24 40 25.0 EP910-40 0 0 0 Non-Turbo Adder , tp z x tp x z *CLR ho C1 = 5 pF, Note (10) C1 = 35 pF 30 33 3 EP910-30 Global Clock Mode Symbol f MAX *SU EP910-35 E P910-40 Parameter Maximum frequency Input setup time Input hold
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ALTED001
Abstract: to 125 C) EP910-40 Availability EP910-30. EP910-35, EP910-40 EP910-35. EP910-40 N o t e : O n , V, f = 1.0 MHz AC Operating Conditions See Note (5) EP910-30 EP910-35 EP910-40 Non-Turbo , delay C1 = 35 pF 33 3 38 3 43 3 30 0 ns ns Uo Global Clock Mode EP910-30 EP910-35 EP910-40 Non-Turbo Adder Symbol f MAX *SU Parameter Maxim um frequency Input , EP910-35 EP910-40 Non-Turbo Adder Symbol f MAX Parameter Maxim um frequency Input setup -
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EP910PC-40

Abstract: EP910PC-30 (PLCC) 0°C - 70°C 30 ns 35 ns 40 ns EP910DC-30 EP910DC-35 EP910DC-40 EP910JC-30 EP910JC-35 EP910JC-40 EP910PC-30 EP91OPC-35 EP910PC-40 EP910LC-30 EP910LC-35 EP910LC-40 â'"40°C - 85°C 45 ns EP910DI-45 , , turbo bit on PARAMETERt TEST CONDITIONS EP910-30 EP910-35 EP910-40 unit MIN MAX MIN MAX MIN MAX , 3 ns combinational mode, turbo bit off PARAMETERt TEST CONDITIONS EP910-30 EP910-35 EP910-40 UNIT , clock mode PARAMETERt TEST CONDITIONS EP910-30 EP910-35 EP910-40 UNIT MIN MAX MIN MAX MIN MAX 'max
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bit 3501 Architecture EP910LI PACKAGE EP910DC EP910 texas EP910DC30 ali 3501 D3187 1988-BEVISED 40-PIN 44-PIN

altera EP910

Abstract: EP910EPLD See Note (5) EP910-30 EP910-35 EP910-40 Non-Turbo Adder Note (9) 30 30 30 30 30 0 t i Unit ns , ^ACH *ACL *AC01 *ACMT f ACNT EP910-30 EP910-35 EP910-40 Non-Turbo Adder Note (9) 0 30 0 0 , Note (10) C1 = 35 pF 30 33 3 m o r C fl Global Clock Mode Symbol f MAX EP910-30 EP910-35 , , EP910-35, EP910-40 EP910-35, EP910-40 EP910-40 N ote: Only military-tem perature-range devices are , EP910A EPLD | AC Operating Conditions See Note (3) ËP910A-15 EP910A-25 Note (6) Symbol tpDI
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EP910EPLD IEP910 altera eplds 00020TM EP910-30T

P9101

Abstract: 3721d External Timing Parameters Symbol Parameter Notes (1), (2) EP910I-12 EP910I-15 EP9101-25 Non-Turbo , EP910-30 Min Max 9.0 3.0 14.0 7.0 7.0 7.0 EP910-35 Min Max 10.0 3.0 16.0 9.0 9.0 9.0 13.0 12.0 19.0 , V (EP910) or -0.5 V (EP910I) or overshoot to 7.0 V (EP910) or Vc c + 0.5 V (EP9101) for input , Notes (1), (2) EP910-30 Min Max 30.0 33.0 30.0 30,0 33.0 41.7 24.0 0.0 12.0 12.0 37.0 27.0 0.0 13.0 , 21.0 35.0 25.0 10.0 15.0 17.0 17.0 1.0 43.0 40.0 30.0 0.0 0.0 Conditions EP910-35 Min Max 35.0
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P9101 3721d

altera EP9101

Abstract: , Parameters S ym bol *PD1 *PD2 · pzx *PXZ *CLR *MAX *SU Notes (1), (2) EP910I-12 EP910I-15 EP910I-25 , *PZX Notes (1), (2) EP 910-30 EP910-35 EP910-40 Non-Turbo Adder Param eter Input lo , delay Feedback delay {CLR Register clear time C1 = 35 pF C1 = 35 pF C1 = 5 p F EP910I-12 E P , Programmable I/O architecture with up to 36 inputs or 24 outputs EP910 and EP9101 devices that are pin
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910I-15 910I-25

EP610

Abstract: ep910 programmer Parameters EP9101-12 EP9101-15 EP910I-25 Non-Turbo Adder Symbol Parameter Conditions Min Max Min Max , Timing Parameters EP9101-12 EP9101-15 EP910I-25 Symbol Parameter Condition Min Max Min Max Min Max , Parameters EP910-30 EP910-35 EP910-40 Non-Turbo Adder Symbol Parameter Conditions Min Max Min Max Min , Parameters EP910-30 EP910-35 EP910-40 Symbol Parameter Condition Min Max Min Max Min Max Unit Ã/N , EP910I devices. EP910& EP9101 De vice Absolute Maximum Ratings Noie ( 1) EP910 EP910I Symbol
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EP610 EP1810 ep910 programmer TI EP610 EP6101-10 EP610-25 EP610I EP181G

EP910dm

Abstract: EP910PC-30 ns ns ns ns ns ns MHz ns ns ns ns ns ns ns MHz Conditions EP910-30 EP910-35 EP910-40 , ), (2) Conditions EP910I-12 EP910I-15 EP910I-25 Non-Turbo Unit Adder Min Max Min Max Min Max (3 , delay Global clock delay Feedback delay Register clear time Condition EP910-30 Min Max 9.0 3.0 14.0 EP910-35 Min Max 10.0 3.0 16.0 9.0 9.0 9.0 13.0 12.0 EP910-40 Min Max 13.0 3.0 17.0 10.0 , Family Data Sheet Table 22. EP910I Internal Timing Parameters Symbol Parameter Condition EP910I-12
Altera
Original
EP610SC-15 EP910dm EP1810LC-35 EP610DI-30 EP1810LC-20 EP610PC-15 Programming EP910JI-35 LC-15 EP610ILC-25 EP610ILI-15 EP610ILI-25 EP610IPC-15 EP610IPC-25

EP910

Abstract: EP910-35 Commercial, C) (Vcc = 5V ± 10%, Ta = -40°C to 85°C for Industrial, I) EP910-30, EP910-35, EP910-40, EP910-45 \'U/ â'" 'V/ - â'". .â'" Note (5) f EP910-30 EP910-35 EP910-40 EP910-45 NON-TURBO , Commercial (0°C to 70° C) c EP910-30 EP910-35 EP910-40 Industrial (-40"C to 85° C) I EP910-45 Military , /O input buffer delay 3 3 3 3 0 ns SYNCHRONOUS CLOCK MODE EP9I0-30 EP910-35 EP910-40 , frequency (1/tcNT) note (7) 33.3 28.6 25.0 22.2 0 MHz ASYNCHRONOUS CLOCK MODE EP910-30 EP910-35
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FLIPFLOP SCHEMATIC 10KHZ 74HC 20//A

EP910PC-40

Abstract: EP910 texas ) C E R A M IC C H IP C A R R IE R (C LC C ) E P910JC-30 EP910JC-35 E P910JC-40 EP910JI-45 P L A S T IC t D U A L -IN -L IN E P A C K A G E (P D IP ) E P910PC-30 E P910PC-35 EP910PC-40 EP910PI-45 , ) E P910LC-30 E P910LC-35 E P910LC-40 EP910LI-45 2-47 EP910 HIGH-PERFORMANCE 24 , EP910D1-45 tT h is p acka g e is fo r O ne-T im e -P rog ra m m ab le (OTP) devices. PRO D U CTIO N D , + Tu rb o bit on Tu rb o bit off TE ST C O N D IT IO N S E P 910-30 M IN 10 40 15 15 15 MAX EP910-35
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1988-REVISED

EP910PC-30

Abstract: EP910PC-40 IE R (C LC C) EP910JC-30 EP910JC-35 EP910JC-40 EP910JI-45 P LA ST IC * DUAL-IN-LINE P A C K A G E (PDIP) EP910PC-30 EP910PC-35 EP910PC-40 EP910P1-45 P LA ST IC t C H IP C A R R IE R (PLCC) EP910LC-30 EP910LC-35 EP910LC-40 EP910LI-45 RANGE 30 ns 0°C - 70°C -40°C - 85C C 35 ns 40 ns 45 ns EP910DC-30 , delay Cl = Cl Cl T E S T C O N D IT IO N S EP910-30 M IN MAX EP910-35 M IN MAX EP910-40 M IN MAX U N IT , N D IT IO N S EP910-30 M IN 24 54 0 12 12 MAX EP910-35 M IN 27 57 0 13 13 M AX EP910-40 M IN 31 61 0
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EP910PC35 EP9100c EP910J IC1724 EP910JC30 ep910pc

QLCC 24

Abstract: EP6101-10 ) External Timing Parameters EP9101-12 EP9101-15 EP910I-25 Non-Turbo Adder Symbol Parameter Conditions , Family Data Sheet Internal Timing Parameters EP9101-12 EP9101-15 EP910I-25 Symbol Parameter , Parameters EP910-30 EP910-35 EP910-40 Non-Turbo Adder Symbol Parameter Conditions Min Max Min Max Min , Timing Parameters EP910-30 EP910-35 EP910-40 Symbol Parameter Condition Min Max Min Max Min Max , EP910I devices. EP910& EP9101 De vice Absolute Maximum Ratings Nose ( 1) EP910 EP910I Symbol
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QLCC 24 programmer EPLD

application of ic 7483

Abstract: ic 7483 full adder Devices The architecture of the EP610, EP610I, EP910, EP910I, and EP1810 devices provides registered and , , EP610I, EP910, EP910I & EP1810 Device Timing Model If the register is bypassed, the delay between the , ) Combinatorial Delay Combinatorial Logic t PD1 MAX 5000 (multi-LAB) EP610, EP610I, EP910, EP910I , t IN + t LAC + ( t XZ or t ZX ) EP610, EP610I, EP910, EP910I, EP1810 t PXZ , t PZX = t , t PRE , t CLR = t IN + t LAC + ( t PRE or t CLR ) + t OD EP610, EP610I, EP910, EP910I
Altera
Original
application of ic 7483 ic 7483 full adder ic 7483 7483 IC 4 bit full adder EPM5032 EPM5064 7000E 7000S

FC SUFFIX altera

Abstract: EPB10 EP610T 600 300 16 20 15 (35) 83.3 (28.6) EP610I EP910 EP910T 900 450 24 36 30 33.3 , 0 Devices EP610, EP910, and EP1810 devices use sum -of-products logic and a program m able register , Corporation Classic EPLD Family The EP610, EP910, and EP1810 devices are supported by Altera's M A X +P , Data Sheet in this data book. In addition to the basic EP610, EP910, and EP1810 devices, Altera , EP910 devices acquired from Intel are designated by an "I" suffix in the ordering code. These devices
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FC SUFFIX altera EP22V10 EP22V10E
Showing first 20 results.