NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
OC-3/OC-12/OC-48 EP3SL340 EP3SE260 EP3SL200 EP4SE360 EP4SE680 EP4SE290 EP4SE110 - Datasheet Archive
560 560 560 560 560 736 736 560 2 736 Stratix III FPGAs Balanced logic, memory, DSP 480 2 480 2 1,152-pin 35 x 35 mm 736 736
Stratix IV FPGA family package and I/O selector guide 560 560 560 560 560 736 736 560 2 736 Stratix III FPGAs Balanced logic, memory, DSP 480 2 480 2 1,152-pin 35 x 35 mm 736 736 1,517-pin 40 x 40 mm 864 864 1,760-pin 43 x 43 mm 736 2 736 2 960 960 960 960 960 1,104 1 All data is preliminary 2 Hybrid package (flip chip) FBGA Stratix IV transceiver protocol support (GX only) Protocol Data rate Protocol Data rate PCI Express Gen1, Gen2 2.5, 5.0 DDR-XAUI 6.25 PCI Express Cable 2.5 SFI5.1 2.488 - 3.125 SAS 1.5, 3.0, 6.0 SONET OC-3/OC-12/OC-48 OC-3/OC-12/OC-48 0.155, 0.622, 2.488 SATA 1.5, 3.0 Ethernet-XAUI 4 x 3.125 SDI SD/HD 0.27/1.485 Gigabit Ethernet 1.25 3G SDI 2.97 CEI-6G/SR/LR 6.375/4.976 - 6.375/4.976 - 6.375 ASI 0.27 HiGig+ 3.75 CPRI 0.6144, 1.2288, 2.4576, 3.072 HiGig2 4.0625 0.768, 1.536, 3.072 Interlaken 3.125 - 6.375 OBSAI RapidIO® 1.25, 2.5, 3.125 Fibre Channel 1.0625, 2.125, 4.25, 8.5 GPON 1.244 uplink, 2.488 downlink HyperTransportTM 3.0 0.4, 2.4, 2.8, 3.2 SPAUI 3.2, 6.4 SerialLite II 0.6 - 6.375 Serial EP3SL340 EP3SL340 480 EP3SE260 EP3SE260 480 EP3SL200 EP3SL200 EP4SE360 EP4SE360 29 x 29 mm EP4SE680 EP4SE680 EP4SE290 EP4SE290 EP4SE110 EP4SE110 EP4SE230 EP4SE230 Body size 780-pin Pin count FBGA (F) EP4SE530 EP4SE530 Number indicates available user I/O pins. All Stratix series devices are offered in commercial and industrial temperatures and RoHS-compliant packages. 736 904 Stratix IV E FPGAs (0.9V) High density, high performance, low power 1 Vertical migration (same Vcc, GND, ISP, and input pins). EP4SGX530N EP4SGX530N 288 2 1 All data is preliminary 2 Hybrid package (flip chip) FBGA 480 EP4SGX530K EP4SGX530K 45 x 45 mm EP4SGX530H EP4SGX530H 1,932-pin EP4SGX360K EP4SGX360K 40 x 40 mm 560 EP4SGX360H EP4SGX360H 1,517-pin 368 288 2 EP4SGX360F EP4SGX360F 35 x 35 mm 368 EP4SGX290K EP4SGX290K 1,152-pin EP4SGX290H EP4SGX290H 368 35 x 35 mm EP4SGX290F EP4SGX290F 368 1,152-pin EP4SGX230K EP4SGX230K 29 x 29 mm Pin count FBGA (F) EP4SGX230H EP4SGX230H EP4SGX110D EP4SGX110D 780-pin All Stratix® series devices are offered in commercial and industrial temperatures and RoHS-compliant packages. EP4SGX230F EP4SGX230F Body size EP4SGX70D EP4SGX70D Vertical migration (same Vcc, GND, ISP, and input pins). User I/O may be less than labelled for vertical migration. EP4SGX230D EP4SGX230D Number indicates available user I/O pins. EP4SGX110F EP4SGX110F 368 Stratix IV GX FPGAs (0.9V) up to 8.5-Gbps transceivers 1 960 1,104 Stratix IV FPGA family features Part 1 of 2 EP4SGX110D EP4SGX110D EP4SGX110F EP4SGX110F EP4SGX230D EP4SGX230D EP4SGX230F EP4SGX230F EP4SGX230H EP4SGX230H EP4SGX230K EP4SGX230K EP4SGX290F EP4SGX290F Equivalent LEs 72,600 105,600 105,600 228,000 228,000 228,000 228,000 291,200 ALMs Density and speed EP4SGX70D EP4SGX70D Stratix IV GX FPGAs (0.9V) up to 8.5-Gbps transceivers 1 29,040 42,240 42,240 91,200 91,200 91,200 91,200 116,480 Registers 2 58,080 84,480 84,480 182,400 182,400 182,400 182,400 232,960 M9K memory blocks 462 660 660 1,235 1,235 1,235 1,235 936 M144K M144K memory blocks 16 16 16 22 22 22 22 36 Embedded memory (Mbits) 6.3 8.1 8.1 13.9 13.9 13.9 13.9 13.3 MLAB memory (Kbits) 908 1,320 1,320 2,850 2,850 2,850 2,850 3,640 Max. 18-bit x 18-bit multipliers 384 512 512 1,288 1,288 1,288 1,288 832 Speed grades (fastest to slowest) -3, -4 -3, -4 -3, -4 -3, -4 -3, -4 -2, -3, -4 -2, -3, -4 -3, -4 Architectural features Embedded processor available Nios® II processor Global clock networks 16 16 16 16 16 16 16 16 Regional clock networks 64 64 64 64 64 64 64 88 Periphery clock networks 56 56 56 88 88 88 88 88 3/27 3/27 4/34 3/27 6/54 6/54 8/68 6/54 Design security HardCopy® series device support PLLs/unique outputs HardCopy companion device HC4GX1 HC4GX2 HC4GX3 I/O standards supported I/O features Medium performance LVDS channels HC4GX4 1.2, 1.5, 1.8, 2.5, 3.3 I/O voltage levels supported (V) 3 LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, Differential SSTL-15 SSTL-15, Differential SSTL-18 SSTL-18, Differential SSTL-2, Differential HSTL-12 HSTL-12, Differential HSTL-15 HSTL-15, Differential HSTL-18 HSTL-18, SSTL-15 SSTL-15 (I and II), SSTL-18 SSTL-18 (I and II), SSTL-2 (I and II), 1.2V HSTL (I and II), 1.5V HSTL (I and II), 1.8V HSTL (I and II) 128 128 128 128 192 192 192 192 28/28 28/28 28/28 28/28 44/44 44/44 88/88 Embedded DPA circuitry Series and differential on-chip termination Programmable drive strength 8 8 16 16 24 16 Number of LVDS channels, 1.6 Gbps (receive/transmit) 600 Mbps - 8.5 Gbps with PCS + PMA Transceiver (SERDES) data rate range Transceiver (SERDES) channels 44/44 8 16 600 Mbps - 3.2 Gbps with PMA only Transceiver (SERDES) data rate range Configuration file sizes 8 12 PCI Express hard IP blocks External memory interfaces Transceiver (SERDES) channels4 1 1 2 1 2 2 2 2 102 140 DDR3, DDR2, DDR, QDR II, RLDRAM II SDR Memory devices supported Configuration file size (Mbits) 52 52 52 102 1 All data is preliminary 2 This is the base core logic register count. The ALM can support three registers when used in LUTREG mode, which increases total register count by an additional 50 percent. 3 3.3V compliant, requires a 3.0V power supply 4 These are additional transceivers, total transceiver count is sum of 8.5-Gbps transceivers plus 3.2-Gbps transceivers. 102 102 Part 2 of 2 EP4SGX290K EP4SGX290K EP4SGX360F EP4SGX360F EP4SGX360H EP4SGX360H EP4SGX360K EP4SGX360K EP4SGX530H EP4SGX530H EP4SGX530K EP4SGX530K EP4SGX530N EP4SGX530N Equivalent LEs 291,200 291,200 353,600 353,600 353,600 531,200 531,200 531,200 ALMs Density and speed EP4SGX290H EP4SGX290H Stratix IV GX FPGAs (0.9V) up to 8.5-Gbps transceivers 1 116,480 116,480 141,440 141,440 141,440 212,480 212,480 212,480 Registers 2 232,960 232,960 282,880 282,880 282,880 424,960 424,960 424,960 M9K memory blocks 936 936 1,248 1,248 1,248 1,280 1,280 1,280 M144K M144K memory blocks 36 36 48 48 48 64 64 64 Embedded memory (Mbits) 13.3 13.3 17.7 17.7 17.7 20.3 20.3 20.3 MLAB memory (Kbits) 3,640 3,640 4,420 4,420 4,420 6,640 6,640 6,640 832 832 1,040 1,040 1,040 1,024 1,024 1,024 -2, -3, -4 -2, -3, -4 -3, -4 -2, -3, -4 -2, -3, -4 -3, -4 -3, -4 -3, -4 Global clock networks 16 16 16 16 16 16 16 16 Regional clock networks 88 88 88 88 88 88 88 88 Periphery clock networks 88 88 88 88 88 112 112 112 6/54 12/96 6/54 6/54 12/96 6/54 8/68 12/96 Design security HardCopy series device support Max 18-bit x 18-bit multipliers Speed grades (fastest to slowest) Architectural features Embedded processor available PLLs/unique outputs Nios II processor HC4GX4 HardCopy companion device HC4GX5 I/O standards supported I/O features Medium performance LVDS channels HC4GX6 1.2, 1.5, 1.8, 2.5, 3.33 I/O voltage levels supported (V) LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, Differential SSTL-15 SSTL-15, Differential SSTL-18 SSTL-18, Differential SSTL-2, Differential HSTL-12 HSTL-12, Differential HSTL-15 HSTL-15, Differential HSTL-18 HSTL-18, SSTL-15 SSTL-15 (I and II), SSTL-18 SSTL-18 (I and II), SSTL-2 (I and II), 1.2V HSTL (I and II), 1.5V HSTL (I and II), 1.8V HSTL (I and II) 192 192 192 192 192 192 192 256 44/44 88/88 44/44 44/44 88/88 44/44 88/88 Embedded DPA circuitry Series and differential on-chip termination Programmable drive strength 16 24 16 16 24 32 Number of LVDS channels, 1.6 Gbps (receive/transmit) 600 Mbps - 8.5 Gbps with PCS + PMA Transceiver (SERDES) data rate range Transceiver (SERDES) channels 98/98 16 24 600 Mbps - 3.2 Gbps with PMA only Transceiver (SERDES) data rate range Configuration file sizes 8 12 8 12 8 12 16 PCI Express hard IP blocks External memory interfaces Transceiver (SERDES) channels4 2 2 2 2 2 4 4 4 189 189 DDR3, DDR2, DDR, QDR II, RLDRAM II SDR Memory devices supported Configuration file size (Mbits) 140 140 140 140 1 All data is preliminary 2 This is the base core logic register count. The ALM can support three registers when used in LUTREG mode, which increases total register count by an additional 50 percent. 3 3.3V compliant, requires a 3.0V power supply. 4 These are additional transceivers, total transceiver count is sum of 8.5-Gbps transceivers plus 3.2-Gbps transceivers 140 189 Stratix IV FPGA family features EP4SE230 EP4SE230 EP4SE290 EP4SE290 EP4SE360 EP4SE360 EP4SE530 EP4SE530 EP4SE680 EP4SE680 Equivalent LEs 105,600 228,000 291,200 353,600 531,200 681,100 ALMs Density and speed EP4SE110 EP4SE110 Stratix IV E FPGAs (0.9V) High density, high performance, low power 1 42,240 91,200 116,480 141,440 212,480 272,440 Registers 2 84,480 182,400 232,960 282,880 424,960 544,880 M9K memory blocks 660 1,235 936 1,248 1,280 1,529 M144K M144K memory blocks 16 22 36 48 64 64 Embedded memory (Mbits) 8.1 13.9 13.3 17.7 20.3 22.4 1,320 2,850 3,640 4,420 6,640 8,514 512 1,288 832 1,040 1,024 1,360 -2, -3, -4 -2, -3, -4 -2, -3, -4 -2, -3, -4 -3, -4 -3, -4 Global clock networks 16 16 16 16 16 16 Regional clock networks 88 88 88 88 88 88 Periphery clock networks 56 88 88 88 112 112 6/54 12/96 6/54 6/54 12/96 6/54 Design security HardCopy series device support HC4GX1 HC4GX2 HC44 HC4GX3 HC46 HC47 MLAB memory (Kbits) Max 18-bit x 18-bit multipliers Speed grades (fastest to slowest) Architectural features Embedded processor available PLLs/unique outputs HardCopy companion device Nios II processor 1.2, 1.5, 1.8, 2.5, 3.33 I/O voltage levels supported (V) I/O features I/O standards supported Medium performance LVDS channels LVTTL, LVCMOS, PCI, PCI-X, LVDS, mini-LVDS, RSDS, LVPECL, Differential SSTL-15 SSTL-15, Differential SSTL-18 SSTL-18, Differential SSTL-2, Differential HSTL-12 HSTL-12, Differential HSTL-15 HSTL-15, Differential HSTL-18 HSTL-18, SSTL-15 SSTL-15 (I and II), SSTL-18 SSTL-18 (I and II), SSTL-2 (I and II), 1.2V HSTL (I and II), 1.5V HSTL (I and II), 1.8V HSTL (I and II) 128 128 256 256 256 288 88/88 88/88 112/112 132/132 Embedded DPA circuitry Programmable drive strength External memory interfaces 56/56 Series and differential on-chip termination Configuration file sizes 56/56 Number of LVDS channels, 1.6 Gbps (receive/transmit) DDR3, DDR2, DDR, QDR II, RLDRAM II SDR Memory devices supported Configuration file size (Mbits) 52 102 140 140 189 230 1 All data is preliminary 2 This is the base core logic register count. The ALM can support three registers when used in LUTREG mode, which increases total register count by an additional 50 percent. 3 3.3V compliant, requires a 3.0V power supply Copyright © 2008 Altera Corporation. All rights reserved. Altera, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, mask work rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. May 2008; 3K SG-01005-1 SG-01005-1.1