F256/ X16/X18 F256/U256 EP3C120 - Datasheet Archive

 

Version 1.3 Notes (1), (2) Bank Number VREFB Group Pin Name/ Function B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREFB1N0 VREFB1N0

 

Pin Information for the Cyclone® III EP3C5 Device Version 1.3 Notes (1), (2) Bank Number VREFB Group Pin Name/ Function B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 IO IO IO IO VCCINT IO IO IO IO IO nSTATUS IO IO IO B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 IO IO DCLK IO nCONFIG TDI TCK VCCIO1 TMS GND TDO nCE CLK0 CLK1 CLK2 CLK3 IO IO IO VCCIO2 IO GND IO VCCINT IO IO B2 B2 B2 B2 B2 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 IO IO IO IO IO PT-EP3C5-1.3 Copyright © 2009 Altera Corp. Optional Function(s) E144 (3) M164 F256/ F256/ U256 1 2 3 4 5 B2 B1 A1 C1 D4 E5 F5 B1 FLASH_nCE, nCSO 6 7 8 D2 D1 E1 nSTATUS DIFFIO_L1p DIFFIO_L1n VREFB1N0 DIFFIO_L2p DIFFIO_L2n Configuration Function 9 E2 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 F2 F1 F3 G1 G2 G3 H2 G2 G1 H1 H2 H5 H4 H3 H1 J5 H3 H4 J2 J1 K3 J3 J4 J3 E2 E1 M2 M1 J2 J1 J6 DATA1, ASDO DIFFIO_L3p DIFFIO_L3n DIFFIO_L4p DIFFIO_L4n DCLK DATA0 nCONFIG TDI TCK TMS TDO nCE DIFFCLK_0p DIFFCLK_0n DIFFCLK_1p DIFFCLK_1n DIFFIO_L5p DIFFIO_L5n DQS for X8/X9 in E144 DQS for X8/X9 in M164 DQS for X16/X18 X16/X18 in F256/U256 F256/U256 DQS2L/CQ3L C2 C1 F3 D2 D1 F4 G5 F2 F1 DQS0L/CQ1L, DPCLK0 DQS0L/CQ1L, DPCLK0 DQS0L/CQ1L, DPCLK0 DQS1L/CQ1L#, DPCLK1 DQS1L/CQ1L#, DPCLK1 DQS1L/CQ1L#, DPCLK1 26 DIFFIO_L6p DIFFIO_L6n K6 27 28 29 K1 DIFFIO_L7p DIFFIO_L7n DIFFIO_L8p DIFFIO_L8n VREFB2N0 DIFFIO_L9p DIFFIO_L9n L6 K2 K1 30 31 L2 K2 L1 L3 Pin List L2 L1 L3 N2 N1 Page 1 of 12 Pin Information for the Cyclone® III EP3C5 Device Version 1.3 Notes (1), (2) Bank Number VREFB Group Pin Name/ Function Optional Function(s) B2 B2 B2 B2 B2 B2 B2 B2 B2 B3 B3 B3 B3 B3 B3 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 IO IO IO IO IO IO VCCA1 GNDA1 VCCD_PLL1 IO IO IO IO VCCIO3 GND RUP1 RDN1 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B4 B4 B4 B4 B4 B4 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 IO IO IO VCCINT IO IO IO IO VCCIO3 IO GND IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO VCCIO4 PT-EP3C5-1.3 Copyright © 2009 Altera Corp. Configuration Function E144 (3) M164 F256/ F256/ U256 32 33 34 M1 M2 M3 K5 L4 DIFFIO_L10p DIFFIO_L10n DIFFIO_B1p DIFFIO_B1n DIFFIO_B2p DIFFIO_B2n 35 36 37 38 39 R1 P1 P2 R2 R3 P3 DQS for X8/X9 in E144 DQS for X8/X9 in M164 DQS for X16/X18 X16/X18 in F256/U256 F256/U256 R1 P2 P1 L5 M5 N4 N3 P3 R3 T3 DQS3L/CQ3L# DM5B1/BWS#5B1 DQ5B 40 41 PLL1_CLKOUTp PLL1_CLKOUTn 42 43 44 45 DQS1B/CQ1B#, DPCLK2 DQS1B/CQ1B#, DPCLK2 T2 R4 T4 P6 N5 N5 N6 M6 P6 DQ5B DQ5B DQ5B M7 DQS3B/CQ3B# DIFFIO_B4p DIFFIO_B4n VREFB3N0 DQS1B/CQ1B#, DPCLK2 R4 P5 R5 46 47 DIFFIO_B5p 48 DIFFIO_B5n DIFFIO_B6p DIFFIO_B6n DIFFIO_B7p DIFFIO_B7n DIFFIO_B8p DIFFIO_B8n DIFFIO_B9p DIFFIO_B9n DIFFIO_B10p DIFFIO_B10n DIFFIO_B11p DIFFIO_B11n DIFFIO_B12p DIFFIO_B12n DIFFIO_B13p DIFFIO_B13n DIFFIO_B14p 49 50 51 R6 R7 P7 52 53 54 55 N6 N7 P8 R8 K8 R5 T5 R6 T6 L7 R7 T7 L8 M8 N8 P8 R8 T8 R9 T9 K9 L9 M9 DQ5B DQ5B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B DQ5B DQ5B DQS5B/CQ5B# DQ5B DM5B0/BWS#5B0 DQ5B DQ5B 56 Pin List Page 2 of 12 Pin Information for the Cyclone® III EP3C5 Device Version 1.3 Notes (1), (2) Bank Number VREFB Group Pin Name/ Function Optional Function(s) B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 IO GND IO IO IO IO VCCINT IO IO VCCIO4 IO GND IO IO IO IO IO IO IO IO DIFFIO_B14n B4 B4 B4 B4 B4 B4 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 B5 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 PT-EP3C5-1.3 Copyright © 2009 Altera Corp. IO IO IO IO IO IO IO IO IO IO IO IO IO IO VCCINT IO IO IO IO IO IO VCCIO5 IO GND IO IO DIFFIO_B15p DIFFIO_B15n DIFFIO_B16p DIFFIO_B16n Configuration Function E144 (3) M164 F256/ F256/ U256 DQS for X8/X9 in E144 DQS for X8/X9 in M164 DQS for X16/X18 X16/X18 in F256/U256 F256/U256 N9 57 58 59 60 61 R9 N8 P9 DIFFIO_B17p DIFFIO_B17n R10 T10 R11 T11 DQ5B DQ1B DQ1B DQ1B DQ1B DQ1B DQ1B R12 T12 DQ5B DQS4B/CQ5B DQ5B DQ5B DQ5B 62 DIFFIO_B18p K10 63 DIFFIO_B18n VREFB4N0 DIFFIO_B19p DIFFIO_B19n RUP2 RDN2 DIFFIO_B20p DIFFIO_B20n DIFFIO_B21p DIFFIO_B21n DIFFIO_B22p DIFFIO_B22n 64 65 66 67 68 69 70 71 72 P10 R10 N11 P11 N12 P12 R11 R12 N10 73 74 75 RUP3 RDN3 DIFFIO_R11n DIFFIO_R11p R14 R13 P14 P15 R15 76 77 N15 M14 L10 P9 P11 R13 T13 M10 N11 T14 T15 R14 P14 L11 M11 N12 N13 M12 L12 K12 N14 P15 P16 R16 DQS2B/CQ3B DQ5B DQ1B DQ1B DQ1B DQ1B DQS0B/CQ1B, DPCLK3 DQS0B/CQ1B, DPCLK3 DQ5B DQS0B/CQ1B, DPCLK3 DQS3R/CQ3R# 78 DIFFIO_R10n DIFFIO_R10p VREFB5N0 79 80 M15 L14 L15 DIFFIO_R9n K11 N16 N15 L14 L13 L16 81 DIFFIO_R9p DIFFIO_R8n K12 82 83 84 L15 K13 J12 J11 K16 Pin List Page 3 of 12 Pin Information for the Cyclone® III EP3C5 Device Version 1.3 Notes (1), (2) Bank Number VREFB Group Pin Name/ Function Optional Function(s) B5 B5 B5 B5 B5 B5 B5 B5 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB5N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 IO IO IO IO IO IO CLK7 CLK6 CLK5 CLK4 CONF_DONE VCCIO6 MSEL0 GND MSEL1 MSEL2 IO IO IO IO IO IO VCCINT IO DIFFIO_R8p DIFFIO_R7n DIFFIO_R7p DIFFIO_R6n DIFFIO_R6p B6 B6 B6 B6 B6 B6 B6 B6 B6 B6 B7 B7 B7 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB6N0 VREFB7N0 VREFB7N0 VREFB7N0 IO IO IO IO IO IO IO VCCA2 GNDA2 VCCD_PLL2 IO IO IO DIFFIO_T21n DIFFIO_T21p DIFFIO_T20n B7 B7 B7 B7 B7 B7 B7 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 IO IO IO IO IO IO IO DIFFIO_T20p DIFFIO_T19n DIFFIO_T19p PLL2_CLKOUTn PLL2_CLKOUTp RUP4 RDN4 PT-EP3C5-1.3 Copyright © 2009 Altera Corp. Configuration Function DIFFCLK_3n DIFFCLK_3p DIFFCLK_2n DIFFCLK_2p CONF_DONE MSEL0 MSEL1 MSEL2 DIFFIO_R5n DIFFIO_R5p DIFFIO_R4n DIFFIO_R4p INIT_DONE CRC_ERROR DIFFIO_R3n nCEO DIFFIO_R3p CLKUSR VREFB6N0 DIFFIO_R2n DIFFIO_R2p DIFFIO_R1n DIFFIO_R1p M164 F256/ F256/ U256 85 86 87 K14 K15 J13 88 89 90 91 92 93 94 95 96 97 J15 J14 H15 H14 H13 K15 J16 J15 J14 J12 J13 M16 M15 E16 E15 H14 G13 H13 G14 G15 98 99 100 101 102 103 F13 F14 F15 E14 H12 G12 H16 H15 G16 G15 F13 F16 E15 F15 104 105 D14 D15 106 C15 107 108 109 DEV_OE DEV_CLRn E144 (3) A15 B15 B14 B16 F14 D16 D15 G11 C16 C15 F12 E12 D13 C14 D14 D11 B13 110 A14 111 112 113 114 115 A13 B12 A12 B11 A11 Pin List D12 A13 B13 A14 B14 E11 E10 DQS for X8/X9 in E144 DQS for X8/X9 in M164 DQS for X16/X18 X16/X18 in F256/U256 F256/U256 DQS1R/CQ1R#, DPCLK4 DQS1R/CQ1R#, DPCLK4 DQS1R/CQ1R#, DPCLK4 DQS0R/CQ1R, DPCLK5 DQS0R/CQ1R, DPCLK5 DQS0R/CQ1R, DPCLK5 DQS2R/CQ3R DQ5T DQS0T/CQ1T, DPCLK6 DQS0T/CQ1T, DPCLK6 DQS0T/CQ1T, DPCLK6 DQ5T DQ1T DQ1T DQ1T DQ1T Page 4 of 12 Pin Information for the Cyclone® III EP3C5 Device Version 1.3 Notes (1), (2) Bank Number VREFB Group Pin Name/ Function B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B7 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 B8 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB7N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VREFB8N0 VCCINT IO IO VCCIO7 IO GND IO IO IO IO IO IO IO VCCIO7 IO GND IO IO IO IO IO IO IO VCCIO8 IO GND IO IO IO IO IO VCCINT IO IO IO IO IO IO IO IO VCCIO8 GND IO IO IO IO IO PT-EP3C5-1.3 Copyright © 2009 Altera Corp. Optional Function(s) Configuration Function E144 (3) M164 F256/ F256/ U256 DQS for X8/X9 in E144 DQS for X8/X9 in M164 DQS for X16/X18 X16/X18 in F256/U256 F256/U256 116 DIFFIO_T18n DIFFIO_T18p A12 B12 DQ5T DQ5T A11 DQ5T B11 C11 F10 F9 F11 A15 A10 DQ5T 117 DIFFIO_T17n 118 DIFFIO_T17p VREFB7N0 DIFFIO_T16n DIFFIO_T16p DIFFIO_T15n DIFFIO_T15p DIFFIO_T14n 119 120 121 B10 A10 C9 DQ1T DQ1T DQS2T/CQ3T DQ5T 122 DIFFIO_T14p B10 DQ5T C9 D9 E9 A9 B9 A8 B8 DQ5T DM5T0/BWS#5T0 DQS4T/CQ5T C8 DQS5T/CQ5T# 123 DIFFIO_T13n DIFFIO_T13p 124 125 126 127 128 129 130 DIFFIO_T12n DIFFIO_T12p DIFFIO_T11n DIFFIO_T11p D9 D8 A9 B9 A8 B8 A7 131 DIFFIO_T10n DIFFIO_T10p DIFFIO_T9n DIFFIO_T9p DATA2 DATA3 DATA4 C7 B7 B6 A6 134 135 DIFFIO_T8n DIFFIO_T8p VREFB8N0 DIFFIO_T7n DIFFIO_T7p DIFFIO_T6n 132 133 136 DATA5 DATA6 DATA7 137 138 C6 A5 B4 A4 D8 E8 F8 A7 B7 F6 F7 C6 A6 B6 E7 E6 A5 DQ1T DQ1T DQ1T DQ1T DQ1T DQ5T DQ5T DQ5T DQ5T DQ1T DQ1T DQ1T DQS3T/CQ3T# DQ5T DQ5T DQ5T DQ5T 139 140 DIFFIO_T5n DIFFIO_T5p DIFFIO_T4n DIFFIO_T4p DIFFIO_T3n 141 C4 Pin List A2 B5 A4 B4 D5 DQ5T DM5T1/BWS#5T1 Page 5 of 12 Pin Information for the Cyclone® III EP3C5 Device Version 1.3 Notes (1), (2) Bank Number VREFB Group Pin Name/ Function Optional Function(s) B8 B8 VREFB8N0 VREFB8N0 IO IO DIFFIO_T3p DIFFIO_T2n B8 B8 B8 VREFB8N0 VREFB8N0 VREFB8N0 IO IO IO VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO8 VCCIO8 VCCIO8 GND GND GND GND GND GND GND GND GND GND GND GND GND DIFFIO_T2p DIFFIO_T1n DIFFIO_T1p PT-EP3C5-1.3 Copyright © 2009 Altera Corp. Configuration Function E144 (3) M164 F256/ F256/ U256 DQS for X8/X9 in E144 DQS for X8/X9 in M164 DQS for X16/X18 X16/X18 in F256/U256 F256/U256 DQS1T/CQ1T#, DPCLK7 DQ1T DM1T DQS1T/CQ1T#, DPCLK7 DQ1T DM1T D6 A3 142 143 144 A3 A2 B3 D3 D6 N2 D10 F12 H12 M8 M11 F4 J4 M5 M6 M9 N9 L13 D13 C10 C11 B5 C5 E3 G12 D7 N14 M7 N1 P13 P4 K4 N4 G4 D5 C12 Pin List B3 C3 D3 G6 G7 G8 G9 G10 H6 H11 K7 E3 G3 K3 M3 P4 P7 T1 P10 P13 T16 K14 M14 E14 G14 A16 C10 C13 A1 C4 C7 H7 H8 H9 H10 J7 J8 J9 J10 B2 B15 C5 C12 D7 DQS1T/CQ1T#, DPCLK7 Page 6 of 12 Pin Information for the Cyclone® III EP3C5 Device Version 1.3 Notes (1), (2) Bank Number VREFB Group Pin Name/ Function GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration Function E144 (3) M164 F256/ F256/ U256 D11 C14 M13 M10 C2 C8 E13 DQS for X8/X9 in E144 DQS for X8/X9 in M164 DQS for X16/X18 X16/X18 in F256/U256 F256/U256 D10 E4 E13 G4 G13 K4 K13 M4 M13 N7 N10 P5 P12 R2 R15 Notes: (1) If the p pin or n pin is not available for the package, this means that the particular differential pair is not supported. (2) DQS pins that do not have the associated DQ pins are not supported. (3) The E144 package has an exposed pad at the bottom of the package. This exposed pad is a ground pad that must be connected to the ground plane on your PCB. This exposed pad is used for electrical connectivity, and not for thermal purposes. PT-EP3C5-1.3 Copyright © 2009 Altera Corp. Pin List Page 7 of 12 Pin Information for the Cyclone® III EP3C5 Device Version 1.3 Notes (1) Pin Name Pin Type (1st, 2nd, and 3rd Function) VCCINT Power Pin Description Supply and Reference Pins These are internal logic array voltage supply pins. VCCIO[1.8] GND Power Ground VREFB[1.8]N[0.2] VCCA[1.4] VCCD_PLL[1.4] I/O Power Power These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage level. VCCIO supplies power to the input and output buffers for all I/O standards. VCCIO powers up the JTAG pins (TCK, TMS, TDI and TDO) and the following configuration pins: nCONFIG, DCLK, DATA[15.0], nCE, nCEO, nWE, nRESET, nOE, FLASH_nCE,nCSO and CLKUSR. Device ground pins. All GND pins should be connected to the board GND plane. Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-referenced pins for the bank. If voltage-referenced I/O standards are not used in the bank, the VREF pins are available as user I/O pins. Supply (analog) voltage for PLLs[1.4] and other analog circuits in the device. Supply (digital) voltage for PLLs[1.4]. RUP[1.4] I/O, Input Reference pins for on-chip termination (OCT) block in I/O banks 2, 4, 5, and 7. The external precision resistor RUP must be connected to the designated RUP pin within the same bank. If not required, this pin is a regular I/O pin. RDN[1.4] GNDA[1.4] NC I/O, Input Ground No Connect DATA0 Input (PS, FPP, AS) Bidirectional open drain (AP) MSEL[3.0] nCE Input Input Reference pins for on-chip termination (OCT) block in I/O banks 2, 4, 5, and 7. The external precision resistor RDN must be connected to the designated RDN pin within the same bank. If not required, this pin is a regular I/O pin. Ground for PLL[1.4]. You can connect these pins to GND plane on the board. Do not drive signals into these pins. Dedicated Configuration/JTAG Pins Dedicated configuration data input pin. In serial configuration modes, bit-wide configuration data is received through this pin. In AS mode, DATA0 has an internal pull-up resistor that is always active. After AS configuration, DATA0 is a dedicated input pin with optional user control. After PS or PP configuration, DATA0 is available as a user I/O pin and the state of this pin depends on the Dual-Purpose Pin settings. After AP configuration, DATA0 is a dedicated bidirectional pin with optional user control. Configuration input pins that set the Cyclone III device configuration scheme. These pins must be hardwired to VCCA or GND. Some of the smaller devices or package options do not support the AP flash programming and do not have the MSEL[3] pin. Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled. Dedicated configuration control input. Pulling this pin low during user mode causes the FPGA to lose its configuration data, enter a reset state, and tristate all I/O pins. Returning this pin to a logic high level will initiate reconfiguration.The input buffer on this pin supports hysteresis using Schmitt trigger circuitry. This is a dedicated configuration status pin. As a status output, the CONF_DONE pin drives low before and during configuration. Once all configuration data is received without error and the initialization cycle starts, CONF_DONE is released. As a status input, CONF_DONE goes high after all data is received. Then the device initializes and enters user mode. nCONFIG Input CONF_DONE Bidirectional (open-drain) nSTATUS TCK TMS TDI TDO Bidirectional (open-drain) Input Input Input Output This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after power-up and releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs during configuration. As a status input, the device enters an error state when nSTATUS is driven low by an external source during configuration or initialization. Dedicated JTAG input pin. The JTAG circuitry can be disabled by connecting TCK to GND. Dedicated JTAG input pin. The JTAG circuitry can be disabled by connecting TMS to VCC. Dedicated JTAG input pin. The JTAG circuitry can be disabled by connecting TDI to VCC. Dedicated JTAG output pin. Clock and PLL Pins Clock, Input Dedicated global clock input pins that can also be used for the positive terminal inputs for differential global clock input or user input pins. Clock, Input Dedicated global clock input pins that can also be used for the negative terminal inputs for differential global clock input or user input pins. I/O pins that be used as two single-ended clock output pins or one differential clock output pair.These pins can only use the differential I/O standard if it is being fed by a PLL output. CLK[0,2,4,6,9,11,13,15], DIFFCLK_[0.7]p CLK[1,3,5,7,8,10,12,14], DIFFCLK_[0.7]n PLL[1.4]_CLKOUT[p,n] PT-EP3C5-1.3 Copyright © 2009 Altera Corp. I/O, Output Pin Definitions Page 8 of 12 Pin Information for the Cyclone® III EP3C5 Device Version 1.3 Notes (1) Pin Name DCLK nCEO Pin Type (1st, 2nd, and 3rd Function) Input (PS, FPP) I/O,Output (AS, AP) I/O, Output Pin Description Optional/Dual-Purpose Configuration Pins Configuration clock pin. In PS and PP configuration modes, DCLK is used to clock configuration data from an external source into the Cyclone III device. In AS and AP modes, DCLK is an output from the Cyclone III device that provides timing for the configuration interface. After AS or AP configuration, this pin is available as a user I/O pin with optional user control. Output that drives low when device configuration is complete. This pin functions as FLASH_nCE in AP mode, and nCSO in AS mode. This pin has an internal pull-up resistor that is always active. nCSO: Output control signal from the Cyclone III device to the serial configuration device in AS mode that enables the configuration device. FLASH_nCE, nCSO I/O, Output FLASH_nCE: Output control signal from the Cyclone III device to the parallel flash in AP mode that enables the flash. This pin functions as DATA1 in PS, FPP, and AP modes, and as ASDO in AS mode. DATA1: Data input in non-AS mode. Byte-wide or word-wide configuration data is presented to the target device on DATA[7.0] or DATA[15.0] respectively. In PS configuration scheme, DATA1 functions as user I/O pin during configuration, which means it is tri-stated. After FPP configuration, DATA1 is available as a user I/O pin and the state of this pin depends on the Dual-Purpose Pin settings. After AP configuration, DATA1 is a dedicated bidirectional pin with optional user control. DATA1, ASDO DATA[7.2] Input (FPP) Output (AS) Bidirectional open-drain (AP) ASDO: Control signal from the Cyclone III device to the serial configuration device in AS mode used to read out configuration data. In AS mode, this ASDO pin has an internal pull-up resistor that is always active. After AS configuration, this pin is a dedicated output pin with optional user control. Input (FPP) Bidirectional open-drain (AP) Data inputs. Byte-wide or word-wide configuration data is presented to the target device on DATA[7.0] or DATA[15.0] respectively. In AS or PS configuration scheme, they function as user I/O pins during configuration, which means they are tri-stated. After FPP configuration, DATA[7.2] are available as user I/O pins and the state of these pins depends on the Dual-Purpose Pin settings. After AP configuration, DATA[7.2] are dedicated bidirectional pins with optional user control. Data inputs. Btye-wide or word-wide configuration data is presented to the target device on DATA[15.0]. In PS, FPP, or AS configuration scheme, they function as user I/O pins during configuration, which means they are tri-stated. After AP configuration, DATA[15.8] are dedicated bidirectional pins with optional user control. 24-bit address bus from the Cyclone III device to the parallel flash in AP mode. Active-low reset output. Driving the nRESET pin low resets the parallel flash. Active-low address valid output. Driving the nAVD pin low during read or write operation indicates to the parallel flash that valid address is present on the PADD[23.0] address bus. DATA[15.8] PADD[23.0] nRESET Bidirectional open-drain (AP) I/O, Output (AP) I/O, Output (AP) nAVD I/O, Output (AP) nOE I/O, Output (AP) nWE I/O, Output (AP) Active-low output enable to the parallel flash. Driving the nOE pin low during read operation enables the parallel flash outputs (DATA[15.0]). Active-low write enable to the parallel flash. Driving the nWE pin low during write operation indicates to the parallel flash that data on the DATA[15.0] bus is valid. CRC_ERROR I/O, Output Active-high signal that indicates that the error-detection circuit has detected errors in the configuration SRAM bits. This pin is optional and is used when the CRC error-detection circuit is enabled.This pin can be set in Quartus software to support open-drain output. DEV_CLRn I/O (when option off), Input (when option on) Optional chip-wide reset pin that allows you to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as programmed. The DEV_CLRn pin does not affect JTAG boundary-scan or programming operations. This pin is enabled by turning on the Enable device-wide reset (DEV_CLRn) option in the Quartus II software. DEV_OE I/O (when option off), Input (when option on) INIT_DONE I/O, Output (open-drain) PT-EP3C5-1.3 Copyright © 2009 Altera Corp. Optional pin that allows you to override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high, all I/O pins behave as defined in the design. This pin is enabled by turning on the Enable device-wide output enable (DEV_OE) option in the Quartus II software. This is a dual-purpose status pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, a transition from low to high at the pin indicates when the device has entered user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user I/O pin after configuration. This pin is enabled by turning on the Enable INIT_DONE output option in the Quartus II software. Pin Definitions Page 9 of 12 Pin Information for the Cyclone® III EP3C5 Device Version 1.3 Notes (1) Pin Name CLKUSR DIFFIO_[L,R,T,B][0.61][n,p] Pin Type (1st, 2nd, and 3rd Function) I/O, Input I/O, TX/RX channel Pin Description Optional user-supplied clock input. Synchronizes the initialization of one or more devices. If this pin is not enabled for use as a user-supplied configuration clock, it can be used as a user I/O pin. This pin is enabled by turning on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus II software. Dual-Purpose Differential and External Memory Interface Pins Dual-purpose differential transmitter/receiver channels. These channels can be used for transmitting/receiving LVDS-compatible signals. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If not used for differential signaling, these pins are available as user I/O pins. DQS[0.5][L,R,T,B]/CQ[1,3,5][L,R,T,B][ #],DPCLK[0.11] I/O, DQS/CQ, DPCLK Dual-purpose DPCLK/DQS pins can connect to the global clock network for high fan-out control signals such as clocks, asynchronous clears, presets, and clock enables. It can also be used as optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase-shift circuitry, which allows for the fine tuning of the phase shift for input clocks or strobes to properly align clock edges needed to capture data. DQS[0.5][L,R,T,B]/CQ[1,3,5][L,R,T,B][ #],CDPCLK[0.7] I/O, DQS/CQ, CDPCLK DQ[0.5][L,R,T,B] I/O, DQ Dual-purpose CDPCLK/DQS pins can connect to the global clock network for high fan-out control signals such as clocks, asynchronous clears, presets, and clock enables. Only one of the two CDPCLK in each corner can feed the clock control block at a time. The other pin can be used as general-purpose I/O pin. The CDPCLK signals incur more delay to the clock block control because they are multiplexed before being driven into the clock block control. It can also be used as optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase-shift circuitry, which allows for the fine tuning of the phase shift for input clocks or strobes to properly align clock edges needed to capture data. Optional data signal for use in external memory interfaces. DM[0.5][L,R,B,T][0.1]/BWS#[0.5][L,R ,T,B] I/O, DM/BWS# The data mask pins are only required when writing to DDR SDRAM and DDR2 SDRAM devices. QDRII SRAM devices use the BWS signal to select the byte to be written into memory. A low signal on the DM/BWS# pin indicates that the write is valid. Driving the DM/BWS# pin high results in the memory masking the DQ signals. Note: (1) The pin definitions are prepared based on the device with the largest density, EP3C120 EP3C120. Refer to the pin list for the availability of pins in each density. PT-EP3C5-1.3 Copyright © 2009 Altera Corp. Pin Definitions Page 10 of 12 Pin Information for the Cyclone® III EP3C5 Device Version 1.3 VREF0B8 VREF0B7 PLL2 VREF0B6 VREB0B5 B5 B6 B1 VREF0B4 B2 B4 VREF0B3 VREF0B1 B7 B3 VREB0B2 B8 PLL1 Notes: (1) This is a top view of the silicon die. (2) This is only a pictorial representation to get an idea of placement on the device. Refer to the pin list and the Quartus ® II software for exact locations. PT-EP3C5-1.3 Copyright © 2009 Altera Corp. Bank & PLL Diagram Page 11 of 12 Pin Information for the Cyclone® III EP3C5 Device Version 1.3 Version Number 1.0 1.1 1.2 1.3 Changes Made Initial release. Added support for M164 package. Updated pin function for CRC_ERROR pin. Updated DQ/DQS support for UBGA package. Updated pin function for PLL[1.4]_CLKOUT[p,n] pin. Remove RDY from Pin Definitions worksheet. Incorporated pin connection guideline into Pin Definitions worksheet. Incorporated VCCA and VCCD Decoupling recommendations. Removed Pin Connection Guideline from Pin Definitions worksheet. Removed VCCA and VCCD Decoupling recommendations. Removed PKG notes from Pin List Worksheet. Updated pin function for DCLK pin. PT-EP3C5-1.3 Copyright © 2009 Altera Corp. Revision History Date 5/24/2007 11/23/2007 5/9/2008 10/7/2009 Page 12 of 12