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LT1017MJ8/883 Linear Technology LT1017 - Micropower Dual Comparator; Package: CERDIP; Pins: 8; Temperature: Military visit Linear Technology - Now Part of Analog Devices
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EP3C25 pin diagram

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EP3C25 pin diagram

Abstract: EP3C25 pin guideline Pin Information for the Cyclone® III EP3C25 Device Version 1.5 Notes (2), (3) Bank Number , 11 Pin Information for the Cyclone® III EP3C25 Device Version 1.5 Notes (2), (3) Bank Number , ® III EP3C25 Device Version 1.5 Notes (2), (3) Bank Number VREFB Group Pin Name / Function , /CQ1R#, DPCLK6 DQ1R DQ1R Page 4 of 11 Pin Information for the Cyclone® III EP3C25 Device , Cyclone® III EP3C25 Device Version 1.5 Notes (2), (3) Bank Number VREFB Group Pin Name
Altera
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EP3C25 pin diagram EP3C25 pin guideline PT-EP3C25-1 F256/

EP3C25

Abstract: EP3C25 pin diagram Diagram Page 14 of 15 Pin Information for the Cyclone® III EP3C25 Device Version 1.1 Version , Pin Information for the Cyclone® III EP3C25 Device Version 1.1 Notes (2),(3) Bank VREFB Number , L6 L2 L1 DQ1L DQ1L L4 DQ1L EP3C25 Pin List Adj. Adj. Page 1 of 15 Pin , DQ3B DM5B/BWS#5B DQ5B DQ5B EP3C25 Pin List DQ5B DQ3B DQS3B/CQ3B#, DPCLK2 DQS3B/CQ3B , Res. Res. Res. Res. DQ5B Page 2 of 15 Pin Information for the Cyclone® III EP3C25 Device
Altera
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F324 altera cyclone III EP3c25 234A2 PADD15 E144 F256

EP3C25

Abstract: F324 Pin Information for the Cyclone® III EP3C25 Device Version 1.4 Notes (2), (3) Bank Number , 14 Pin Information for the Cyclone® III EP3C25 Device Version 1.4 Notes (2), (3) Bank Number , of 14 Pin Information for the Cyclone® III EP3C25 Device Version 1.4 Notes (2), (3) Bank , Pin Information for the Cyclone® III EP3C25 Device Version 1.4 Notes (2), (3) Bank Number VREFB , DQ1R Pin List Page 4 of 14 Pin Information for the Cyclone® III EP3C25 Device Version 1.4
Altera
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U256

ttl to mini-lvds

Abstract: mini-lvds connector left and right I/O banks, some of the differential pin pairs (p and n pins) of the dedicated output drivers are not located on adjacent pins. In these cases, a power pin is located between the p and n pins. Refer to the pin tables on the Altera web site at www.altera.com for more details about the location of , differential output drivers that require an external resistor network. Refer to the pin tables on the Altera , Differential Channels Device Package Pin Count User I/O Clock Pin Total 4 20 EP3C5
Altera
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ttl to mini-lvds mini-lvds connector point-to-point mini-lvds EQFP-144 mini-lvds cyclone iii CIII51008-1 TIA/EIA-644

point-to-point mini-lvds

Abstract: EP3CLS200 . On the left and right I/O banks, some of the differential pin pairs (p and n pins) of the true output drivers are not located on adjacent pins. In these cases, a power pin is located between the p , 49 8 4 61 FBGA 115 8 4 127 FBGA EP3C40 31 FBGA FBGA EP3C25 , Devices 5 4 9 EP3C5 and EP3C25 6 4 10 EP3C10 and EP3C16 5 4 9 6 4 , 4 14 EP3C16 and EP3C25 23 8 31 EP3C16 and EP3C40 11 8 19 EP3C25 and
Ember
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EP3CLS200 EP3CLS150 EP3C80U484 EP3CLS100 mini lvds mini-lvds source driver CIII51008-3

DDR2 sdram pcb layout guidelines

Abstract: Memory Interfaces , a DM pin and DQ pins. DQ groups on the left and right sides of EP3C16, EP3C25, and EP3C40 (of the , EP3C25 (of the 144-pin EQFP package) do not support DM pin. Data and Data Clock/Strobe Pins Cyclone , Package EP3C25 144-pin EQFP (2) Side Number Number Number Number Number Number of ×8 of ×9 , to Figure 9­4: (1) The DQS/CQ/CQ# pin locations in this diagram applies to all packages in the Cyclone III family except EP3C5, EP3C10, EP3C16 and EP3C25 devices in 144-pin EQFP package. 9­8
Altera
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DDR2 sdram pcb layout guidelines Memory Interfaces BGA and eQFP Package 144pin eqfp pin information ep3c10 sdram bga pcb layout guide CIII51009-1

EQFP-144

Abstract: mini-lvds source driver interfaces. The Altera® Quartus® II software completes the solution with powerful pin planning features that , chapter contains the following sections: Overview Each Cyclone III device I/O pin is fed , Devices (EP3C5, EP3C10, EP3C25, EP3C55, EP3C80, and EP3C120) Column I/O Block Contains up to Four IOEs , io_datain (combinational or registered) inputs. The pin's datain signals can drive the logic array. The , Resistor aclr/prn Chip-Wide Reset Output Pin Delay Output Register D sclr/ preset Current
Altera
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altera cyclone III SSTL-18 CIII51007-1

74 series family

Abstract: EP3C10 completes the solution with powerful pin planning features that allow you to plan and optimize I/O system , Resistor aclr/prn Chip-Wide Reset Output Pin Delay Output Register D sclr/ preset Current , clkin oe_in Q Bus Hold Input Pin to Input Register Delay or Input Pin to Logic Array , offers a range of programmable features for an I/O pin. These features increase the flexibility of I/O , Cyclone III device family I/O pin has a programmable current strength control for certain I/O standards
Ember
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74 series family mini-lvds driver EP3C16M164 AN-447 EP3CLS70 receiver altLVDS CIII51007-3

565 PLL

Abstract: pll 566 current, per pin ­25 40 mA VE S D H B M Electrostatic discharge voltage using the human , Figure 1­1, overshoot voltage is shown in red and is present on the Cyclone III input pin at over 4.1 V , , pin capacitance, on chip termination tolerance, and bus hold specifications for Cyclone III devices , design. Table 1­4 lists I/O pin leakage current for Cyclone III devices. Table 1­4. Cyclone III I/O Pin Leakage Current Notes (1), (2) (Part 1 of 2) Symbol Parameter Conditions Min Typ
Altera
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CIII52001-1 565 PLL pll 566 pll 565 ma 8601 pll 565 application

8609 396 81 15 765

Abstract: CV 7599 diode voltage DC output current, per pin Electrostatic discharge voltage using the human body model , Cyclone III input pin at over 4.1 V but below 4.2 V. From Table 1­1, for an overshoot of 4.1 V the , . DC Characteristics This section lists the I/O leakage currents, pin capacitance, on chip termination , Power Estimator to get the supply current estimates for your design. Table 1­4 lists I/O pin leakage current for Cyclone III devices. Table 1­4. Cyclone III I/O Pin Leakage Current Notes (1), (2) (Part 1
Altera
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8609 396 81 15 765 CV 7599 diode PCI 6602 A 3120 0532 8 pin

3841 9904

Abstract: DR 6236 078 EP3C5 EP3C10 EP3C16 EP3C25 EP3C40 EP3C55 EP3C80 EP3C120 Parameter Input Pin Leakage Current , 5 Unit pF pF pF Notes to Table 1­9: CV R E F T B for EP3C25 is 30 pF. When VREF pin is used , PLL DC input voltage DC output current, per pin Electrostatic discharge voltage using the human body , input pin at over 4.1 V but below 4.2 V. From Table 1­1, for an overshoot of 4.1 V, the percentage of , currents, pin capacitance, on-chip termination tolerance, and bus hold specifications for Cyclone III
Altera
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3841 9904 DR 6236 078 5053 resistor NCE 7190 CIII52001-2

5252 F 1105 transistor

Abstract: TMS 3617 . 9­3 Cyclone III Memory Interfaces Pin Support , . 10­7 Configuration and JTAG Pin I/O Requirements
Altera
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5252 F 1105 transistor TMS 3617 max 8770 transistor c 5936 circuit diagram c 5296 Horizontal Output transistor, fa 5571 CIII51001-1

tms 3878

Abstract: pF pF pF pF pF Notes to Table 1­9: (1) CVREFTB for EP3C25 is 30 pF. (2) When VREF pin is used as , (digital) voltage for PLL DC input voltage DC output current, per pin Electrostatic discharge voltage using , , overshoot voltage is shown in red and is present on the Cyclone III input pin at over 4.1 V but below 4.2 V , Characteristics This section lists the I/O leakage currents, pin capacitance, on-chip termination tolerance, and , get the supply current estimates for your design. Table 1­4 lists I/O pin leakage current for Cyclone
Altera
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tms 3878

4046 PLL Designers Guide

Abstract: 8135 diode ) voltage for PLL DC input voltage DC output current, per pin Electrostatic discharge voltage using the , and is present on the Cyclone III input pin at over 4.1 V but below 4.2 V. From Table 1­1, for an , Characteristics This section lists the I/O leakage currents, pin capacitance, on-chip termination tolerance, and , . Table 1­4 lists I/O pin leakage current for Cyclone III devices. Table 1­4. Cyclone III I/O Pin Leakage Current Notes (1), (2) (Part 1 of 2) Symbol II IOZ IC C I N T 0 Parameter Input Pin Leakage
Altera
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4046 PLL Designers Guide 8135 diode

i7 3612

Abstract: pF pF pF pF pF Notes to Table 1­9: (1) CVREFTB for EP3C25 is 30 pF. (2) When VREF pin is used as , input voltage DC output current, per pin Electrostatic discharge voltage using the human body model , red and is present on the Cyclone III input pin at over 4.1 V but below 4.2 V. From Table 1­1, for an , Characteristics This section lists the I/O leakage currents, pin capacitance, on-chip termination tolerance, and , get the supply current estimates for your design. Table 1­4 lists I/O pin leakage current for Cyclone
Altera
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i7 3612

TE 555-1

Abstract: 4046 PLL Designers Guide IOUT DC output current, per pin ­25 40 mA VE S D H B M Electrostatic discharge , Figure 1­1, overshoot voltage is shown in red and is present on the Cyclone III input pin at over 4.1 V , leakage currents, pin capacitance, on chip termination tolerance and and bus hold specifications for , your design. Table 1­4 lists I/O pin leakage current for Cyclone III. Table 1­4. Cyclone III I/O Pin Leakage Current Notes (1), (2) (Part 1 of 2) Symbol Parameter Conditions Min Typ
Altera
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TE 555-1 linear application handbook national semiconductor IC 7439 datasheet u 1096

4046 PLL Designers Guide

Abstract: CIII52001-1 . 1­36 User I/O Pin Timing Parameters . 1­36 Dedicated Clock Pin Timing Parameters , 1.8 V VI DC input voltage ­0.5 3.95 V IOUT DC output current, per pin ­25 , voltage is shown in red and is present on the Cyclone III input pin at over 4.1 V but below 4.2 V. From , within 3 ms. DC Characteristics This section lists the I/O leakage currents, pin capacitance, on chip
Altera
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CIII52

EP3C16

Abstract: A7 v72 diode input voltage DC output current, per pin Electrostatic discharge voltage using the human body model , . In the example in Figure 1­1, overshoot voltage is shown in red and is present on the input pin of , operating range within 3 ms. DC Characteristics This section lists the I/O leakage current, pin , . Table 1­4 lists I/O pin leakage current for Cyclone III devices. Table 1­4. Cyclone III Devices I/O Pin Leakage Current (Note 1), (2) Symbol II IOZ Parameter Input pin leakage current Tristated I/O pin leakage
Altera
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A7 v72 diode qdrii sram CIII52001-3

pin diagram of ic 7489

Abstract: 4046 PLL Designers Guide current, per pin ­25 40 mA VE S D H B M Electrostatic discharge voltage using the human , Figure 1­1, overshoot voltage is shown in red and is present on the Cyclone III input pin at over 4.1 V , leakage currents, pin capacitance, on chip termination tolerance and and bus hold specifications for , your design. Table 1­4 lists I/O pin leakage current for Cyclone III. Table 1­4. Cyclone III I/O Pin Leakage Current Notes (1), (2) (Part 1 of 2) Symbol Parameter Conditions Min Typ
Altera
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pin diagram of ic 7489 679-6 PIN IC 7308 2801 as 7542 E 7805 4148 3216

cl 5403

Abstract: 3841 9904 . 9­3 Cyclone III Memory Interfaces Pin Support , . 10­7 Configuration and JTAG Pin I/O Requirements
Altera
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cl 5403 din 7984
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