DQ1L10 DQ1L11 DQ1L12 DQ1L13 DQ1L14 DQ1L15 DQ1L16 DQ1L17 DQ1B17 DQ1B16 DQ1B15 - Datasheet Archive

 

PT-EP2C8-1.9 © 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera

 

Cyclone® II EP2C8 & EP2C8A Device Pin-Out PT-EP2C8-1.9 © 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services. The pin connection guidelines in the device pin-out are considered preliminary. These pin connection guidelines should only be used as a recommendation, not as a specification. The use of the pin connection guidelines for any particular design should be verified for device operation, with the datasheet and Altera. PLEASE REVIEW THE FOLLOWING TERMS AND CONDITIONS CAREFULLY BEFORE USING THE DEVICE PIN-OUT("PIN-OUT") PROVIDED TO YOU. BY USING THE PIN-OUT, YOU INDICATE YOUR ACCEPTANCE OF SUCH TERMS AND CONDITIONS, WHICH CONSTITUTE THE LICENSE AGREEMENT ("AGREEMENT") BETWEEN YOU AND ALTERA CORPORATION ("ALTERA"). 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Disclaimer Page 1 of 16 ® Pin Information for the Cyclone II EP2C8 and EP2C8A Devices Version 1.9 Notes (1), (2) Bank Number B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 VREFB Group VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N0 VREFB1N1 Pin Name / Function IO IO IO IO IO IO VCCIO1 IO GND IO IO IO VCCIO1 IO IO IO IO IO GND IO IO IO IO IO VCCIO1 TDO TMS TCK TDI DATA0 DCLK nCE CLK0 CLK1 GND nCONFIG CLK2 Optional Function(s) Configuration Function ASDO ASDO nCSO nCSO LVDS15p CRC_ERROR LVDS15n CLKUSR LVDS14p LVDS14n LVDS13p LVDS13n LVDS12p LVDS12n VREFB1N0 LVDS11p LVDS11n LVDS10p LVDS10n 7 LVDS9p LVDS9n LVDS8p LVDS8n DATA0 DCLK TDO TMS TCK TDI DATA0 DCLK nCE nCONFIG PT-EP2C8-1.9.xls Copyright © 2008 Altera Corp. 13 8 9 LVDSCLK0p/input(3) LVDSCLK0n/input(3) LVDSCLK1p/input(3) T144 Q208 F256 DQS for x8/x9 in T144 1 1 C3 2 2 F4 3 3 C1 4 4 C2 5 D5 6 E5 5 7 8 F5 6 9 10 11 D3 12 D4 14 15 10 11 12 13 14 15 16 17 18 19 20 21 16 17 18 19 20 21 22 23 24 25 26 27 DQS for x8/x9 in Q208 DQS for x16/x18 in DQS for x8/x9 in Q208 F256 DQ1L0 DQ1L1 DQ1L2 DQ1L3 DQ0L0 DQ0L1 DPCLK0/DQS0L DPCLK0/DQS0L DPCLK0/DQS0L DQ1L0 DQ1L1 DQ0L2 DQ0L3 DQ0L4 F3 D2 D1 E3 E4 G4 J6 H6 E1 E2 DQS for x16/x18 in F256 DQ1L2 DQ1L3 DQ1L4 DPCLK0/DQS0L DQ0L5 DPCLK0/DQS0L DQ1L5 G2 G1 F2 H5 F1 H4 G5 H2 H1 J5 J2 EP2C8 and EP2C8A Pin List Page 2 of 16 ® Pin Information for the Cyclone II EP2C8 and EP2C8A Devices Version 1.9 Notes (1), (2) Bank Number B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B1 B4 B4 B4 VREFB Group VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB1N1 VREFB4N1 VREFB4N1 VREFB4N1 Pin Name / Function CLK3 VCCIO1 IO IO IO VCCINT IO IO IO GND IO GND IO VCCIO1 IO IO IO GND IO IO IO IO IO VCCIO1 IO IO IO IO IO IO GND GND_PLL1 VCCD_PLL1 GND_PLL1 VCCA_PLL1 GNDA_PLL1 GND Optional Function(s) Configuration T144 Q208 Function LVDSCLK1n/input(3) 22 28 23 29 LVDS7p 24 30 LVDS7n 25 31 LVDS6p 26 32 LVDS6n 33 34 LVDS5p 35 27 36 LVDS5n VREFB1N1 28 37 LVDS4p LVDS4n LVDS3p 38 39 40 41 29 LVDS0p LVDS0n PT-EP2C8-1.9.xls Copyright © 2008 Altera Corp. DQS for x8/x9 in Q208 DQS for x16/x18 in DQS for x8/x9 in Q208 F256 DQS for x16/x18 in F256 K2 K1 K4 DPCLK1/DQS1L DPCLK1/DQS1L DPCLK1/DQS1L DQ1L6 DQ1L7 DPCLK1/DQS1L K5 L1 DQ1L4 DQ1L5 DQ1L6 30 31 32 33 34 35 36 37 38 39 42 43 44 45 46 47 48 49 50 51 52 53 54 55 DPCLK1/DQS1L DQ0L6 DQ0L7 DQ1L8 DM0L DM1L0/BWS#1L0 DQ1L0 DQ1L9 DQ1L1 DQ1L2 L2 DQ1L10 DQ1L10 DQ1L11 DQ1L11 DQ1L3 DQ1L4 DQ1L5 DQ1L6 DQ1L12 DQ1L12 DQ1L13 DQ1L13 DQ1L14 DQ1L14 DQ1L15 DQ1L15 DQ1L7 DQ1L8 DM1L/BWS#1L DQ1L16 DQ1L16 DQ1L17 DQ1L17 DM1L1/BWS#1L1 J4 M1 M2 M3 LVDS3n LVDS2p LVDS2n LVDS1p LVDS1n PLL1_OUTp PLL1_OUTn F256 DQS for x8/x9 in T144 J1 L3 N1 N2 P1 P2 N3 N4 P3 L4 M4 DQ1L7 DQ1L8 DM1L/BWS#1L L5 L6 N5 M5 M6 EP2C8 and EP2C8A Pin List Page 3 of 16 ® Pin Information for the Cyclone II EP2C8 and EP2C8A Devices Version 1.9 Notes (1), (2) Bank Number B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 VREFB Group VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N1 VREFB4N0 VREFB4N0 VREFB4N0 Pin Name / Function IO IO IO IO IO IO VCCIO4 IO GND IO IO IO IO VCCIO4 GND IO GND IO IO IO VCCINT IO VCCIO4 GND IO IO IO IO IO VCCIO4 IO GND IO IO IO IO GND Optional Function(s) Configuration Function LVDS77n DEV_OE LVDS77p LVDS76p LVDS76n LVDS75p LVDS75n LVDS74p T144 Q208 F256 DQS for x8/x9 in T144 40 56 R3 41 57 T3 DM1B/BWS#1B 42 58 P5 DQ1B8 43 59 P4 DQ1B7 44 60 T4 DQ1B6 45 61 R4 DQ1B5 46 62 47 63 T5 DPCLK2/DQS1B LVDS74n 48 64 49 65 LVDS73p LVDS73n LVDS72p LVDS70p LVDS70n LVDS69p LVDS69n LVDS68p LVDS68n LVDS67p LVDS67n LVDS66p LVDS66n PT-EP2C8-1.9.xls Copyright © 2008 Altera Corp. DQS for x16/x18 in DQS for x8/x9 in Q208 F256 DQS for x16/x18 in F256 DM1B/BWS#1B DQ1B8 DQ1B7 DQ1B6 DQ1B5 DM1B1/BWS#1B1 DQ1B17 DQ1B17 DQ1B16 DQ1B16 DQ1B15 DQ1B15 DQ1B14 DQ1B14 DM1B/BWS#1B DQ1B8 DQ1B7 DQ1B6 DQ1B5 DM1B1/BWS#1B1 DQ1B17 DQ1B17 DQ1B16 DQ1B16 DQ1B15 DQ1B15 DQ1B14 DQ1B14 DPCLK2/DQS1B DPCLK2/DQS1B DPCLK2/DQS1B DPCLK2/DQS1B DQ1B4 DQ1B13 DQ1B13 DQ1B3 DQ1B2 DQ1B12 DQ1B12 DQ1B11 DQ1B11 DQ1B1 DQ1B0 DQ1B10 DQ1B10 DQ1B9 R5 N7 K7 K6 T6 LVDS72n LVDS71p LVDS71n VREFB4N1 DQS for x8/x9 in Q208 R6 P6 N6 50 51 66 67 52 68 69 53 54 55 56 57 58 59 60 61 70 71 72 73 74 75 76 77 78 N8 T7 R7 L7 L8 T8 DQ1B4 DQ1B4 DQ1B3 DQ1B13 DQ1B13 DQ1B12 DQ1B12 DQ1B3 DQ1B2 DQ1B11 DQ1B11 R8 DQ1B2 DQ1B1 DQ1B10 DQ1B10 T9 R9 N9 N10 DQ1B1 DQ1B0 DQ1B0 DQ1B9 EP2C8 and EP2C8A Pin List DM1B0/BWS#1B0 Page 4 of 16 ® Pin Information for the Cyclone II EP2C8 and EP2C8A Devices Version 1.9 Notes (1), (2) Bank Number B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B4 B3 B3 B3 B3 B3 B3 B3 VREFB Group VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB4N0 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 Pin Name / Function IO VCCINT IO VCCIO4 IO GND IO IO VCCIO4 IO GND IO IO IO IO IO VCCIO4 IO GND IO IO IO IO VCCIO4 IO GND IO IO IO IO IO IO IO IO IO IO VCCIO3 Optional Function(s) Configuration T144 Q208 F256 DQS for x8/x9 in Function T144 LVDS65p T11 62 79 LVDS65n R11 80 66 67 68 69 70 71 72 73 74 75 76 77 107 108 109 LVDS63p 63 LVDS61n LVDS60p LVDS60n 64 65 LVDS59p LVDS59n LVDS58p LVDS58n LVDS57p LVDS57n LVDS56n LVDS56p LVDS55n LVDS55p LVDS54n LVDS54p PT-EP2C8-1.9.xls Copyright © 2008 Altera Corp. INIT_DONE nCEO DQS for x16/x18 in F256 DM0B DQ1B8 L9 L10 LVDS64p LVDS64n LVDS63n LVDS62p LVDS62n VREFB4N0 LVDS61p DQS for x16/x18 in DQS for x8/x9 in Q208 F256 P11 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 DQS for x8/x9 in Q208 R10 DM0B DM1B0/BWS#1B0 DQ1B8 DQ1B7 DQ1B6 DQ0B7 DQ1B7 DQ0B7 DQ0B6 DQ0B5 DQ1B5 DQ0B6 DQ1B6 DQ0B4 DQ1B4 DQ0B5 DQ1B5 DPCLK4/DQS0B DPCLK4/DQS0B DPCLK4/DQS0B DQ0B4 DPCLK4/DQS0B DQ1B4 T13 DQ0B3 DQ0B2 DQ1B3 DQ1B2 DQ0B3 DQ1B3 R13 DQ0B1 DQ1B1 DQ0B2 DQ1B2 T14 R14 M11 L11 N12 M12 L12 K13 N13 N14 DQ0B0 DQ1B0 DQ0B1 DQ0B0 DQ1B1 DQ1B0 DM1R/BWS#1R DM1R1/BWS#1R1 T10 K11 K10 N11 P12 P13 T12 R12 DPCLK4/DQS0B DM1R/BWS#1R DQ1R8 EP2C8 and EP2C8A Pin List Page 5 of 16 ® Pin Information for the Cyclone II EP2C8 and EP2C8A Devices Version 1.9 Notes (1), (2) Bank Number B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 VREFB Group VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N1 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 Pin Name / Function IO GND IO IO IO IO IO IO IO IO VCCIO3 IO GND IO GND IO IO IO VCCINT nSTATUS VCCIO3 CONF_DONE GND MSEL1 MSEL0 IO IO CLK7 CLK6 CLK5 CLK4 IO IO IO VCCIO3 IO IO Optional Function(s) Configuration T144 Q208 Function LVDS53n 110 78 111 LVDS53p 112 LVDS52n 113 LVDS52p 114 LVDS51n LVDS51p VREFB3N1 LVDS50n 79 115 116 117 LVDS50p DQS for x16/x18 in F256 DM1R1/BWS#1R1 P16 N15 N16 P14 DQ1R7 DQ1R6 DQ1R5 DQ1R16 DQ1R16 DQ1R15 DQ1R15 DQ1R14 DQ1R14 DQ1R8 DQ1R7 DQ1R6 DQ1R5 DQ1R17 DQ1R17 DQ1R16 DQ1R16 DQ1R15 DQ1R15 DQ1R14 DQ1R14 DQ1R4 DQ1R3 DQ1R13 DQ1R13 DQ1R12 DQ1R12 DQ1R4 DQ1R13 DQ1R13 DQ1R3 DQ1R2 DQ1R12 DQ1R12 DQ1R11 DQ1R11 DQ1R1 DPCLK6/DQS1R DQ1R10 DQ1R10 DPCLK6/DQS1R M14 M15 DQ1R2 DQ1R11 DQ1R11 L14 L15 L16 nSTATUS 81 82 CONF_DONE 83 MSEL1 MSEL0 PT-EP2C8-1.9.xls Copyright © 2008 Altera Corp. DQS for x16/x18 in DQS for x8/x9 in Q208 F256 DQ1R17 DQ1R17 DM1R/BWS#1R 118 119 LVDS49n LVDS49p LVDS46p LVDS45n DQS for x8/x9 in Q208 DQ1R8 M16 80 LVDS48n LVDS48p LVDSCLK3n/input(3) LVDSCLK3p/input(3) LVDSCLK2n/input(3) LVDSCLK2p/input(3) LVDS47n LVDS47p LVDS46n F256 DQS for x8/x9 in T144 P15 84 85 86 87 88 89 90 91 92 93 94 95 96 97 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 M13 L13 K12 J13 K16 K15 J16 J15 H15 H16 H12 J12 G16 DQ1R7 DPCLK6/DQS1R DQ1R1 DPCLK6/DQS1R DQ1R10 DQ1R10 DPCLK6/DQS1R DQ1R6 DPCLK7/DQS0R DQ1R5 DQ1R0 DPCLK7/DQS0R DM0R DQ1R9 DQ1R0 DPCLK7/DQS0R DPCLK7/DQS0R DM1R0/BWS#1R0 DM0R DQ1R9 DPCLK7/DQS0R DM1R0/BWS#1R0 G15 F15 DQ1R4 DQ1R3 DQ0R7 DQ1R8 DQ1R7 DQ1R8 DQ1R7 EP2C8 and EP2C8A Pin List DQ0R7 Page 6 of 16 ® Pin Information for the Cyclone II EP2C8 and EP2C8A Devices Version 1.9 Notes (1), (2) Bank Number B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B3 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB Group VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB3N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 Pin Name / Function IO GND IO IO IO IO IO IO IO VCCIO3 IO IO IO GND IO IO IO IO VCCIO3 IO IO IO IO GND GND_PLL2 VCCD_PLL2 GND_PLL2 VCCA_PLL2 GNDA_PLL2 GND IO IO IO IO IO IO VCCIO2 Optional Function(s) Configuration T144 Q208 Function LVDS45p 139 98 140 LVDS44n 141 LVDS44p 142 LVDS43n LVDS43p LVDS42n 143 LVDS42p 144 VREFB3N0 99 145 F256 DQS for x8/x9 in T144 F16 DQS for x8/x9 in Q208 DQ0R6 DQS for x16/x18 in DQS for x8/x9 in Q208 F256 DQ1R6 DQ0R6 J11 H11 G12 G13 E13 F13 H13 DQ0R5 DQ0R4 DQ1R5 DQ1R4 LVDS41n LVDS41p LVDS40n D15 D16 E15 LVDS40p E16 F14 C15 C16 LVDS39n LVDS39p LVDS38n LVDS38p PLL2_OUTp PLL2_OUTn LVDS37n LVDS37p LVDS36n LVDS36p LVDS35n LVDS35p PT-EP2C8-1.9.xls Copyright © 2008 Altera Corp. 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 C14 D13 E14 D14 DQS for x16/x18 in F256 DQ1R6 DQ1R2 DQ1R1 DQ0R1 DQ0R0 DQ1T0 DQ1T1 DQ1T2 DQ1T3 DQ1T4 DQ1R0 DQ0T0 DQ0T1 DQ0T2 DQ0T3 DQ0T4 DQ1T0 DQ1T1 DQ1T2 DQ1T3 DQ1T4 DQ1R1 DQ1R0 DQ0T0 DQ0T1 DQ0T2 DQ0T3 DQ0T4 DQ1R1 DQ0R0 DQ1R3 DQ1R2 DQ1R5 DQ1R4 DQ1R3 DQ1R2 DQ0R1 DQ0R3 DQ0R2 DQ0R5 DQ0R4 DQ0R3 DQ0R2 DQ1R0 F12 F11 D12 E12 E11 B14 A14 C13 C12 B13 A13 EP2C8 and EP2C8A Pin List Page 7 of 16 ® Pin Information for the Cyclone II EP2C8 and EP2C8A Devices Version 1.9 Notes (1), (2) Bank Number B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB Group VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N0 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 Pin Name / Function GND IO IO IO IO VCCIO2 IO GND IO IO IO VCCIO2 IO GND IO IO IO GND VCCINT IO VCCIO2 IO GND IO IO IO IO VCCIO2 IO GND IO GND IO IO IO VCCINT IO Optional Function(s) Configuration T144 Function 117 LVDS34n 118 LVDS34p 119 VREFB2N0 120 LVDS33n 121 LVDS32n LVDS32p LVDS31n Q208 F256 DQS for x8/x9 in T144 167 168 B12 169 A12 DPCLK8/DQS0T 170 C11 171 B11 172 173 A11 174 G10 G11 175 B10 LVDS31p 176 LVDS33p 122 LVDS30n LVDS30p DQS for x8/x9 in Q208 DQS for x16/x18 in DQS for x8/x9 in Q208 F256 DPCLK8/DQS0T DPCLK8/DQS0T DQ0T5 DPCLK8/DQS0T DQ1T5 DPCLK8/DQS0T DQ0T5 DQ1T5 DQ0T6 DQ1T6 DQ0T6 DQ1T6 DQ0T7 DQ1T7 DQ0T7 DQ1T7 A10 DQS for x16/x18 in F256 DQ1T8 DQ1T8 F10 F9 D9 LVDS29n 123 124 125 177 178 179 D11 DQ1T0 LVDS29p 126 180 D10 DQ1T1 181 182 A9 B9 A8 B8 LVDS28n LVDS28p LVDS27n LVDS27p 127 184 185 186 187 188 189 190 191 LVDS26n LVDS26p 131 PT-EP2C8-1.9.xls Copyright © 2008 Altera Corp. DM0T DM1T0/BWS#1T0 DQ1T0 A7 LVDS25n LVDS25p LVDS24n LVDS24p DM1T0/BWS#1T0 DQ1T9 183 128 129 130 DM0T B7 DQ1T2 F7 F8 EP2C8 and EP2C8A Pin List DQ1T0 DQ1T9 DQ1T1 DQ1T2 DQ1T10 DQ1T10 DQ1T11 DQ1T11 DQ1T3 DQ1T12 DQ1T12 Page 8 of 16 ® Pin Information for the Cyclone II EP2C8 and EP2C8A Devices Version 1.9 Notes (1), (2) Bank Number B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 B2 VREFB Group VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 VREFB2N1 Pin Name / Function IO IO VCCIO2 IO GND IO IO IO IO VCCIO2 IO GND IO IO IO IO IO VCCIO2 IO GND IO IO IO IO VCCINT VCCINT VCCINT VCCINT VCCINT VCCINT VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO4 VCCIO4 VCCIO4 Optional Function(s) Configuration T144 Q208 Function VREFB2N1 132 192 LVDS23n 133 193 194 LVDS23p 134 195 196 LVDS22n LVDS22p F256 DQS for x8/x9 in T144 D8 B6 DQ1T3 DQS for x8/x9 in Q208 DQS for x16/x18 in DQS for x8/x9 in Q208 F256 DQS for x16/x18 in F256 DQ1T4 DQ1T13 DQ1T13 DQ1T1 DQ1T10 DQ1T10 A6 DQ1T5 DQ1T14 DQ1T14 DQ1T2 DQ1T3 DQ1T11 DQ1T11 DQ1T12 DQ1T12 DQ1T4 DQ1T13 DQ1T13 LVDS21n 197 G6 G7 D7 D6 LVDS21p 198 DQ1T4 C6 LVDS20n LVDS20p LVDS19n LVDS19p LVDS18n LVDS18p LVDS17p LVDS17n LVDS16p LVDS16n PT-EP2C8-1.9.xls Copyright © 2008 Altera Corp. DEV_CLRn 135 136 137 138 139 140 141 142 143 144 199 200 201 202 203 204 205 206 207 208 C5 C4 B5 A5 B4 DQ1T5 DPCLK10/DQS1T DPCLK10/DQS1T DPCLK10/DQS1T DPCLK10/DQS1T DPCLK10/DQS1T DPCLK10/DQS1T DQ1T6 DQ1T6 DQ1T15 DQ1T15 DQ1T5 DQ1T6 DPCLK10/DQS1T DPCLK10/DQS1T DQ1T7 DQ1T14 DQ1T14 DQ1T15 DQ1T15 DPCLK10/DQS1T DPCLK10/DQS1T DQ1T16 DQ1T16 A4 DQ1T7 DQ1T7 DQ1T16 DQ1T16 DQ1T8 DQ1T17 DQ1T17 A3 B3 E6 F6 G9 H7 H10 J7 J10 K8 B1 G3 K3 R1 M7 M10 P7 DQ1T8 DQ1T8 DQ1T17 DQ1T17 DM1T/BWS#1T DM1T1/BWS#1T1 DM1T/BWS#1T DM1T/BWS#1T DM1T1/BWS#1T1 EP2C8 and EP2C8A Pin List Page 9 of 16 ® Pin Information for the Cyclone II EP2C8 and EP2C8A Devices Version 1.9 Notes (1), (2) Bank Number VREFB Group Pin Name / Function VCCIO4 VCCIO4 VCCIO4 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Optional Function(s) Configuration T144 Q208 F256 DQS for x8/x9 in Function T144 P10 T2 T15 B16 G14 K14 R16 A2 A15 C7 C10 E7 E10 G8 H8 H9 J8 J9 K9 A1 A16 B2 B15 C8 C9 E8 E9 H3 H14 J3 J14 M8 M9 P8 P9 R2 R15 PT-EP2C8-1.9.xls Copyright © 2008 Altera Corp. EP2C8 and EP2C8A Pin List DQS for x8/x9 in Q208 DQS for x16/x18 in DQS for x8/x9 in Q208 F256 DQS for x16/x18 in F256 Page 10 of 16 ® Pin Information for the Cyclone II EP2C8 and EP2C8A Devices Version 1.9 Notes (1), (2) Bank Number VREFB Group Pin Name / Function GND GND Optional Function(s) Configuration T144 Q208 F256 DQS for x8/x9 in Function T144 T1 T16 DQS for x8/x9 in Q208 DQS for x16/x18 in DQS for x8/x9 in Q208 F256 DQS for x16/x18 in F256 Notes: (1) The optional functions (e.g. LVDS, DDR) are not available for some pins in certain packages. For example, for the EP2C8 device, the LVDS70 LVDS70 pair is available for the Q208 and F256 packages, but not for the T144 package. (2) The DQS0T, DQS1T, DQS0B, and DQS1B pin functions are only available in the F672 and F896 packages. (3) If the dedicated CLK pins are not used to feed the global clock networks, they can be used as general-purpose input pins to feed the core logic. The dedicated CLK pins do not support the I/O register. PT-EP2C8-1.9.xls Copyright © 2008 Altera Corp. EP2C8 and EP2C8A Pin List Page 11 of 16 Pin Information for the Cyclone® II EP2C8 and EP2C8A Devices Version 1.9 Note (1) Pin Name Pin Type (1st, 2nd, and 3rd Function) VCCINT Power Connection Guidelines Supply and Reference Pins These are internal logic array voltage supply pins. VCCINT also supplies power to the input buffers used for the LVPECL, LVDS (regular I/O and CLK pins), differential HSTL, and differential SSTL I/O Connect all VCCINT pins to 1.2 V. Decoupling depends on the design decoupling requirements standards. of the specific board. (Note 2) VCCIO[1.8] GND Power Ground These are I/O supply voltage pins for banks 1 through 8. Each bank can support a different voltage level. VCCIO supplies power to the output buffers for all I/O standards. VCCIO also supplies power to the input buffers used for the LVTTL, LVCMOS, 1.5-V, 1.8-V, 2.5-V, 3.3-V PCI, and 3.3-V PCI-X, differential SSTL, differential HSTL, and LVDS (regular I/O) I/O standards. Device ground pins. VREFB[1.8]N[0.3] I/O Input reference voltage for each I/O bank. If a bank uses a voltage-referenced I/O standard, then these pins are used as the voltage-referenced pins for the bank. Pin Description Verify that the VCCIO voltage level connected is consistent with the .pin report from the ® Quartus II software. Decoupling depends on the design decoupling requirements of the specific board. (Note 2) Connect all GND pins to the board GND plane. If voltage-referenced I/O standards are not used in the bank, the VREF pins are available as user I/O pins. Decoupling depends on the design decoupling requirements of the specific board. (Note 2) Connect these pins to 1.2 V, even if the PLL is not used. Use an isolated linear supply for better jitter performance. You can connect all VCCA_PLL pins to a single linear supply to minimize cost. Power on the PLLs should be decoupled. Decoupling depends on the design decoupling requirements of the specific board (Note 2) . For more information on this pin, refer to the PLLs in Cyclone II Devices chapter in the Cyclone II Device Handbook. Connect these pins to the quietest digital supply on board (1.2 V), which is also supplied to the VCCINT, even if the PLL is not used. Power on the PLLs should be decoupled. Decoupling depends on the design decoupling requirements of the specific board (Note 2) . For more information on this pin, refer to the PLLs in Cyclone II Devices chapter in the Cyclone II Device Handbook. Connect these pins directly to the same ground plane as the digital ground of the device, even if the PLL is not used. For more information on this pin, refer to the PLLs in Cyclone II Devices chapter in the Cyclone II Device Handbook. Connect these pins to the GND plane on the board. Do not drive signals into these pins. VCCA_PLL[1.4](Note 4) Power Analog power for PLLs[1.4]. VCCD_PLL[1.4](Note 4) Power Digital power for PLLs[1.4]. GNDA_PLL[1.4](Note 4) GND_PLL[1.4](Note 4) NC Ground Ground No Connect Analog ground for PLLs[1.4]. Ground for PLLs[1.4]. No Connect Input (PS) Output (AS) Dedicated Configuration/JTAG Pins Dedicated configuration clock pin. In PS configuration, DCLK is used to clock configuration data from an external source into the Cyclone II device. In AS mode, DCLK is an output from the Cyclone II device that provides timing for the configuration interface. The input buffer on this pin supports DCLK should not be left floating. You should drive it high or low, whichever is more convenient hysteresis using the Schmitt trigger circuitry. on the board. DATA0 Input Dedicated configuration data input pin. In serial configuration modes, bit-wide configuration data is received through this pin. In AS mode, DATA0 has an internal pull-up resistor that is always active. The input buffer on this pin supports hysteresis using the Schmitt trigger circuitry. MSEL[0.1] Input Configuration input pins that set the Cyclone II device configuration scheme. DATA0 should not be left floating. You should drive it high or low, whichever is more convenient on the board. These pins must be hardwired to VCCIO of the bank they reside in or GND. Do not leave these pins floating. When these pins are unused, connect them to GND. For MSEL pin settings for different configuration schemes, refer to the Configuring Cyclone II Devices chapter in the Cyclone II Device Handbook. nCE Input nCONFIG Input Dedicated active-low chip enable. When nCE is low, the device is enabled. When nCE is high, the device is disabled. The input buffer on this pin supports hysteresis using the Schmitt trigger circuitry. Dedicated configuration control input. Pulling this pin low during user mode causes the FPGA to lose its configuration data, enter a reset state, and tri-state all I/O pins. Returning this pin to a logic high level initiates reconfiguration. The input buffer on this pin supports hysteresis using the Schmitt trigger circuitry. In a multi-device configuration, nCE of the first device is tied low while its nCEO pin drives the nCE of the next device in the chain. In a single-device configuration, nCE is tied low. nCONFIG should be pulled high by an external 10-k pull-up resistor to a 3.3-V supply. If the configuration scheme uses an enhanced configuration device or EPC2, nCONFIG can be tied directly to the nINIT_CONF pin of the configuration device. If this pin is not used, this pin can be connected through a resistor to VCCIO. Bidirectional (open-drain) This is a dedicated configuration status pin. As a status output, the CONF_DONE pin drives low before and during configuration. Once all configuration data is received without error and the initialization cycle starts, CONF_DONE is released. As a status input, CONF_DONE goes high after CONF_DONE should be pulled high by an external 10-k pull-up resistor to a 3.3-V supply. If all data is received. Then the device initializes and enters user mode. It is not available as a user I/O internal pull-up resistors on the enhanced configuration device are used, external 10-k pull-up pin. The input buffer on this pin supports hysteresis using the Schmitt trigger circuitry. resistors should not be used on this pin. DCLK CONF_DONE PT-EP2C8-1.9.xls Copyright © 2008 Altera Corp. Pin Definitions Page 12 of 16 Pin Information for the Cyclone® II EP2C8 and EP2C8A Devices Version 1.9 Note (1) Pin Type (1st, 2nd, and 3rd Function) Pin Name nSTATUS Bidirectional (open-drain) TCK Input TMS Input TDI TDO Input Output CLK[0,2,4,6,8,10,12,14], LVDSCLK[0.7]p Clock, Input CLK[1,3,5,7,9,11,13,15], LVDSCLK[0.7]n Clock, Input PLL[1.4]_OUTp(Note 4) I/O, Output PLL[1.4]_OUTn(Note 4) I/O, Output nCEO I/O, Output nCSO I/O, Output ASDO I/O, Output CRC_ERROR DEV_CLRn DEV_OE INIT_DONE CLKUSR Pin Description Connection Guidelines This is a dedicated configuration status pin. The FPGA drives nSTATUS low immediately after powerup and releases it after POR time. As a status output, the nSTATUS is pulled low if an error occurs during configuration. As a status input, the device enters an error state when nSTATUS is driven low by an external source during configuration or initialization. It is not available as a user I/O pin. The input buffer on this pin supports hysteresis using the Schmitt trigger circuitry. nSTATUS should be pulled high by an external 10-k pull-up resistor to a 3.3-V supply. Dedicated JTAG clock input pin. This pin has weak internal pull-down resistors. The input buffer on Connect this pin to GND via a 1-k resistor. If the JTAG circuitry is not used, connect TCK to this pin supports hysteresis using the Schmitt trigger circuitry. GND. Dedicated JTAG input pin that provides the control signal to determine the transitions of the TAP controller state machine. This pin has weak internal pull-up resistors. The input buffer on this pin Connect this pin to a 1-k resistor via the VCCIO of the bank it resides in. If the JTAG circuitry supports hysteresis using the Schmitt trigger circuitry. is not used, connect TMS to VCCIO. Dedicated JTAG test data input pin for instructions, and test and programming data. This pin has weak internal pull-up resistors. The input buffer on this pin supports hysteresis using the Schmitt Connect this pin to a 1-k resistor via the VCCIO of the bank it resides in. If the JTAG circuitry trigger circuitry. is not used, connect TDI to VCCIO. Dedicated JTAG data output pin for instructions, and test and programming data. When not in JTAG mode, this pin should be left unconnected. Clock and PLL Pins Dedicated global clock input pins that can also be used for the positive terminal inputs for differential global clock input or user input pins. Dedicated global clock input pins that can also be used for the negative terminal inputs for differential global clock input or user input pins. Optional positive terminal for external clock outputs from PLLs[1.4]. These pins can only use the differential I/O standard if it is being fed by a PLL output. Optional negative terminal for external clock outputs from PLLs[1.4]. These pins can only use the differential I/O standard if it is being fed by a PLL output. Optional/Dual-Purpose Configuration Pins Output that drives low when device configuration is complete. Output control signal from the Cyclone II FPGA to the nCS pin of the serial configuration device in AS mode that enables the configuration device by driving it low. In AS mode, the nCSO has internal weak pull-up resistor, which is always active. Output control signal from the Cyclone II FPGA to the serial configuration device in AS mode used to read out configuration data. In AS mode, the ASDO has internal weak pull-up resistor, which is always active. Active-high signal that indicates the error-detection circuit has detected errors in the configuration SRAM bits. This pin is optional and is used when the CRC error-detection circuit is enabled. Optional chip-wide reset pin that allows you to override all clears on all device registers. When this pin is driven low, all registers are cleared; when this pin is driven high, all registers behave as programmed. The DEV_CLRn pin does not affect JTAG boundary-scan or programming operations. I/O (when option off), This pin is enabled by turning on the Enable device-wide reset (DEV_CLRn) option in the Quartus II Input (when option on) software. Optional pin that allows you to override all tri-states on the device. When this pin is driven low, all I/O pins are tri-stated; when this pin is driven high, all I/O pins behave as defined in the design. This pin I/O (when option off), is enabled by turning on the Enable device-wide output enable (DEV_OE) option in the Quartus II Input (when option on) software. This is a dual-purpose status pin and can be used as an I/O pin when not enabled as INIT_DONE. When enabled, a transition from low to high at the pin indicates when the device has entered user mode. If the INIT_DONE output is enabled, the INIT_DONE pin cannot be used as a user I/O pin I/O, Output after configuration. This pin is enabled by turning on the Enable INIT_DONE output option in the (open-drain) Quartus II software. Optional user-supplied clock input. Synchronizes the initialization of one or more devices. If this pin is not enabled for use as a user-supplied configuration clock, it can be used as a user I/O pin. This pin is enabled by turning on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus II software. I/O, Input Dual-Purpose Differential & External Memory Interface Pins I/O, Output PT-EP2C8-1.9.xls Copyright © 2008 Altera Corp. Pin Definitions Connect unused pins to GND. Connect unused pins to GND. When not used as PLL output pins, these pins can be used as user I/O pins. When these pins are not used, they may be left floating. When not used as PLL output pins, these pins can be used as user I/O pins. When these pins are not used, they may be left floating. During a multi-device configuration, this pin feeds the nCE pin of a subsequent device and must be pulled high to VCCIO by an external 10-k pull-up resistor. During a single-device configuration and for the last device in a multi-device configuration, this pin can be left unconnected or used as an user I/O after configuration. When not programming the device in AS mode, the nCSO pin can be used as user I/O. When this pin is not used as an I/O, Altera recommends that you leave the pin unconnected. When not programming the device in AS mode, the ASDO pin can be used as user I/O. When this pin is not used as an I/O, Altera recommends that you leave the pin unconnected. When the dedicated output for CRC_ERROR is not used and this pin is not used as an I/O, Altera recommends that you leave the pin unconnected. When the dedicated output for DEV_CLRn is not used and this pin is not used as an I/O, Altera recommends that you tie this pin to the VCCIO of the bank that it resides in or ground. (Note 6) When the dedicated output for DEV_OE is not used and this pin is not used as an I/O, Altera recommends that you tie this pin to the VCCIO of the bank that it resides in or ground. (Note 6) When INIT_DONE is enabled, connect this pin to a 10-k resistor via the VCCIO of the bank that it resides in. If the CLKUSR pin is not used as a configuration clock input and the pin is not used as an I/O, Altera recommends that you connect this pin to ground. Page 13 of 16 Pin Information for the Cyclone® II EP2C8 and EP2C8A Devices Version 1.9 Note (1) Pin Type (1st, 2nd, and 3rd Function) Pin Name LVDS[0-256][p,n](Note 3) DPCLK[0.11]/ DQS[[0,1]L,[3,5,4,2]B,[1,0]R,[2,4,5,3]T] (Note 5) Pin Description I/O, TX/RX channel Dual-purpose differential transmitter/receiver channels 0 to 256. These channels can be used for transmitting or receiving LVDS-compatible signals. Pins with a "p" suffix carry the positive signal for the differential channel. Pins with an "n" suffix carry the negative signal for the differential channel. If When these pins are not used, they can be tied to the VCCIO of the bank that they reside in or not used for differential signaling, these pins are available as user I/O pins. GND. (Note 6) I/O, DPCLK/DQS Dual-purpose DPCLK/DQS pins can connect to the global clock network for high-fanout control signals such as clocks, asynchronous clears, presets, and clock enables. It can also be used as optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phase-shift circuitry, which allows for the fine-tuning of the phase shift for input clocks or strobes to When these pins are not used, they can be tied to the VCCIO of the bank that they reside in or properly align clock edges needed to capture data. GND. (Note 6) Connection Guidelines CDPCLK[0.7]/ DQS[[2,3]L,[1,0]B,[3,2]R,[0,1]T](Note 5) I/O, CDPCLK/DQS DQ[[[1,3][L,R]],[[3,5][B,T]]][0.17](Note 5) I/O, DQ DQ[[[0.3][L,R]],[[0.5][B,T]]][0.8](Note 5) I/O, DQ Dual-purpose CDPCLK/DQS pins can connect to the global clock network for high-fanout control signals such as clocks, asynchronous clears, presets, and clock enables. Only one of the two CDPCLK in each corner can feed the clock control block at a time. The other pin can be used as a general-purpose I/O pin. The CDPCLK signals incur more delay to the clock block control because they are multiplexed before being driven into the clock block control. It can also be used as optional data strobe signal for use in external memory interfacing. These pins drive to dedicated DQS phaseshift circuitry, which allows for the fine-tuning of the phase shift for input clocks or strobes to properly When these pins are not used, they can be tied to the VCCIO of the bank that they reside in or align clock edges needed to capture data. GND. (Note 6) When these pins are not used, they can be tied to the VCCIO of the bank that they reside in or Optional data signal for use in external memory interfacing in the x16 or x18 modes. GND. (Note 6) When these pins are not used, they can be tied to the VCCIO of the bank that they reside in or Optional data signal for use in external memory interfacing in the x8 or x9 modes. GND. (Note 6) I/O, DM Optional data mask pins for x8/x9 modes are required when writing to DDR SDRAM and DDR2 SDRAM devices. A low signal indicates that the write is valid. If the DM signal is high, the memory masks the DQ signals. Each group of DQ and DQS signals requires a DM pin. DM[[[0.3][L,R]],[[0.5][B,T]]](Note 5 ) DM[[[1,3][L,R]],[[3,5][B,T]]][0,1](Note 5 ) I/O, DM DM[[[0.3][L,R]],[[0.5][B,T]]](Note 5) DM[[[1,3][L,R]],[[3,5][B,T]]][0,1](Note 5 ) I/O, BWS I/O, BWS Optional data mask pins for x16/x18 modes are required when writing to DDR SDRAM and DDR2 SDRAM devices. A low signal indicates that the write is valid. If the DM signal is high, the memory masks the DQ signals. Each group of DQ and DQS signals requires a DM pin. Byte Write Select is an active-low pin. When asserted active, BWS selects which byte is written into the device during write operation. Bytes not written remain unchanged. Deselecting BWS causes write data to be ignored and not written into device. the device during write operation. Bytes not written remain unchanged. Deselecting BWS causes When these pins are not used, they can be tied to the VCCIO of the bank that they reside in or GND. (Note 6) When these pins are not used, they can be tied to the VCCIO of the bank that they reside in or GND. (Note 6) When these pins are not used, they can be tied to the VCCIO of the bank that they reside in or GND. (Note 6) y y GND. (Note 6) Altera provides these guidelines only as recommendations. It is the responsibility of the designer to apply simulation results to the design to verify proper device functionality. Notes: 1) These pin connection guidelines are created based on the largest Cyclone II device, EP2C70F896 EP2C70F896. Refer to the pin list for the availability of pins in each density. 2) Capacitance values for the power supply should be selected after considering the amount of power they need to supply over the frequency of operation of the particular circuit being decoupled. A target impedance for the power plane should be calculated based on current draw and voltage droop requirements of the device or supply. The power plane should then be decoupled using the appropriate number of capacitors. On-board capacitors do not decouple higher than 100 MHz due to "Equivalent Series Inductance" of the mounting of the packages. Proper board design techniques such as interplaning capacitance with low inductance should be considered for higher frequency decoupling. 3) The differential transmitter/receiver channel count for each device and package is different; smaller packages may contain less than the maximum number of differential transmitter/receiver channels. For details on the differential transmitter/receiver channel count for each device, refer to the corresponding pin-out from www.altera.com. 4) The EP2C5, EP2C8, and EP2C8A devices have only PLL1 and PLL2. 5) The DQ, DQS, DM, and BWS# bus mode count for each device and package is different. Smaller packages may contain less than the maximum number of DQ, DQS, DM, and BWS# bus modes. For details on the DQ, DQS, DM, and BWS# bus mode count for each device, refer to the corresponding pin-out from www.altera.com. 6) Make sure that unused pins are set to input tristated in the Quartus II software. For instructions on how to set this, refer to the Quartus II Handbook. PT-EP2C8-1.9.xls Copyright © 2008 Altera Corp. Pin Definitions Page 14 of 16 Pin Information for the Cyclone® II EP2C8 and EP2C8A Devices, ver 1.9 VREFB2N1 VREFB2N0 B2 VREFB3N0 VREFB3N1 VREFB1N1 B3 B1 VREFB1N0 PLL2 B4 PLL1 VREFB4N1 VREFB4N0 Notes: 1. This is a top view of the silicon die. 2. This is only a pictorial representation to get an idea of placement on the device. Refer to the pin list and the Quartus® II software for exact locations. PT-EP2C8-1.9.xls Copyright © 2008 Altera Corp. Bank & PLL Diagram Page 15 of 16 Pin Information for the Cyclone® II EP2C8 and EP2C8A Devices Version 1.9 Version Number 1.0 1.1 1.2 Date 10/6/2004 2/24/2005 4/27/2005 1.3 1.4 6/2/2005 2/10/2006 1.5 1.6 1.7 3/1/2006 6/16/2006 11/13/2006 1.8 1.9 3/7/2007 4/25/2008 PT-EP2C8-1.9.xls Copyright © 2008 Altera Corp. Changes Made Initial revision Modified Pin Definitions for DATA0 pin Added CRC_ERROR pin in Pin List and Pin Definition Changed pin name from GNDD_PLL and GNDG_PLL to GND_PLL Finalize Modified Pin Type column in Pin Definitions for VREFB[1.8]N[0.1] pins Added footnote for pins that do not support Optional Functions (LVDS, DDR, etc) Added footnote for DQS0T, DQS1T, DQS0B and DQS1B pins Modified pin definition for NC pins Modified Pin Description of VREFB[1.4]N[0.1] pins Modified Pin Description of VCCA_PLL[1.4] and VCCD_PLL[1.4] pins Added Pin Description for BWS pins Added comment for PLL_OUT pins in Pin Definitions Added EP2C8A support Modified Pin Description for number of PLLs available from 4 to 2. Modified Pin Description of VCCIO and VCCINT. Added "I/O" to pin type of pin nCEO, nCSO and ASDO Moved nCEO Discription from section "Dedicated Configuration/JTAG Pins" to section "Optional/Dual-Purpose Configuration Pins" Modified Pin Description for MSEL Incorporated pin connection guidelines into pin definitions worksheet. Revision History Page 16 of 16