EP1C12 Datasheet, Circuit, PDF, Cross Reference, & Application Note Results |
| Datasheet Search Results |
1 - 50 of about 94 for EP1C12 |
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EP1C12 |
Altera Corporation |
Cyclone Fpga Family |
545.01 Kb, 94 Pages. |
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EP1C12F100C6ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F100C7ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F100C8ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F100I6ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F100I7ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F100I8ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F144C6ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F144C7ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F144C8ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F144I6ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F144I7ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F144I8ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F240C6ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F240C7ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F240C8ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F240I6ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F240I7ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F240I8ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F256C6 |
Altera Corporation |
Cyclone FPGA 12K FBGA-256 |
782.39 Kb, 106 Pages. |
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EP1C12F256C6ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F256C6N |
Altera Corporation |
Cyclone FPGA 12K FBGA-256 |
782.39 Kb, 106 Pages. |
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EP1C12F256C7 |
Altera Corporation |
Cyclone FPGA 12K FBGA-256 |
782.39 Kb, 106 Pages. |
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EP1C12F256C7ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F256C7N |
Altera Corporation |
Cyclone FPGA 12K FBGA-256 |
782.39 Kb, 106 Pages. |
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EP1C12F256C8 |
Altera Corporation |
Cyclone FPGA 12K FBGA-256 |
782.39 Kb, 106 Pages. |
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EP1C12F256C8ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F256C8N |
Altera Corporation |
Cyclone FPGA 12K FBGA-256 |
782.39 Kb, 106 Pages. |
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EP1C12F256I6ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F256I7 |
Altera Corporation |
Cyclone FPGA 12K FBGA-256 |
782.39 Kb, 106 Pages. |
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EP1C12F256I7ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F256I7N |
Altera Corporation |
Cyclone FPGA 12K FBGA-256 |
782.39 Kb, 106 Pages. |
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EP1C12F256I8ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F324C6 |
Altera Corporation |
FPGA, Cyclone Family, SRAM Switch Tech., Reprogrammable, 12060 Logic Cells, 12060 Reg., 1.5V Supply, 6 Speed Grade, 324BGA |
469.81 Kb, 74 Pages. |
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EP1C12F324C6 |
Altera Corporation |
Cyclone FPGA 12K FBGA-324 |
782.39 Kb, 106 Pages. |
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EP1C12F324C6ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F324C6N |
Altera Corporation |
Cyclone FPGA 12K FBGA-324 |
782.39 Kb, 106 Pages. |
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EP1C12F324C7 |
Altera Corporation |
FPGA, Cyclone Family, SRAM Switch Tech., Reprogrammable, 12060 Logic Cells, 12060 Reg., 1.5V Supply, 7 Speed Grade, 324BGA |
469.81 Kb, 74 Pages. |
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EP1C12F324C7 |
Altera Corporation |
Cyclone FPGA 12K FBGA-324 |
782.39 Kb, 106 Pages. |
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EP1C12F324C7ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F324C7N |
Altera Corporation |
Cyclone FPGA 12K FBGA-324 |
782.39 Kb, 106 Pages. |
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EP1C12F324C8 |
Altera Corporation |
FPGA, Cyclone Family, SRAM Switch Tech., Reprogrammable, 12060 Logic Cells, 12060 Reg., 1.5V Supply, 8 Speed Grade, 324BGA |
469.81 Kb, 74 Pages. |
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EP1C12F324C8 |
Altera Corporation |
Cyclone FPGA 12K FBGA-324 |
782.39 Kb, 106 Pages. |
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EP1C12F324C8ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F324C8N |
Altera Corporation |
Cyclone FPGA 12K FBGA-324 |
782.39 Kb, 106 Pages. |
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EP1C12F324I6 |
Altera Corporation |
FPGA, Cyclone Family, SRAM Switch Tech., Reprogrammable, 12060 Logic Cells, 12060 Reg., 1.5V Supply, 6 Speed Grade, 324BGA |
469.81 Kb, 74 Pages. |
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EP1C12F324I6ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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EP1C12F324I7 |
Altera Corporation |
FPGA, Cyclone Family, SRAM Switch Tech., Reprogrammable, 12060 Logic Cells, 12060 Reg., 1.5V Supply, 7 Speed Grade, 324BGA |
469.81 Kb, 74 Pages. |
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EP1C12F324I7 |
Altera Corporation |
Cyclone FPGA 12K FBGA-324 |
782.39 Kb, 106 Pages. |
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EP1C12F324I7ES |
Altera Corporation |
Cyclone FPGA Family |
544.54 Kb, 94 Pages. |
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Datasheets per page: 50 | 250 | 500 |
| Fulltext Datasheet Results |
1 - 50 of about 142 for EP1C12 |
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First line: Information CycloneTM EP1C12 Device Version Bank Number VREF Bank Name/Function VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF0B1 VREF Abstract: .. Pin Information for the CycloneTM EP1C12 Device. V ersion 1.4. PT-EP1C12-1.4 Copyright 2006 Altera Corp.. EP1C12 Pin List. Page 1 of 15. Bank Number VREF Bank Pin Name/Function Optional Function .. Tags: F324 EP1C12 pin diagram EP1C12 LVDS23p LVDS23n LVDS22p LVDS22n LVDS21p LVDS21n |
234.14 Kb |
15 Pages |
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First line: uBGA 25 CUSTOMER ADVISORY ADV0601 Rev01 ADDITION ASSEMBLY PLANT FBGA PACKAGES Change Description: Amkor, Philippines, will added additional assembly source Altera® FineLine BGA® (FBGA) Ultra FineLine (UBGA) packages using BT-based substrates. This will affect current moisture rating these pa Abstract: .. EP1C12. EP1C6. EP1K10 EP1K10 . EP1K100 EP1K100 . EPF10K100E EPF10K100E . EPF10K10A EPF10K10A . EPF10K30A EPF10K30A . EP1K30 EP1K30 . EPF10K30E EPF10K30E . EP1K50 EP1K50 .. EP1C12. EP1C4. EP20K100 EP20K100 . 324. EP20K60E EP20K60E . FBGA. 400 EP1C4. EPM7032B EPM7032B . UBGA 49. EPM7064B EPM7064B . Altera .. Tags: uBGA 25 ADV0601 |
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First line: Altera 1kx4 Cyclone Copyright 2003 Altera® Corporation Altera Abstract: .. EP1C12. EP1C20 EP1C20 . Вертикальная миграция 324-Pin 324-Pin . FBGA. 1.0 mm 19 x 19. 249. 249. 233. 240-Pin 240-Pin PQFP. 0.5 mm 32 .. -7 -7 -7 EP1C12. -7 -7 -7 EP1C6. -7 -7 EP1C4. -7, -8 -7 EP1C3. Q240 Q240 . T144 T144 . F400 F400 . F324 F324 . F256 F256 . T100 T100 . Device .. Tags: q201 EP1C3 EP1C20F324C6 EP1C12 ALTERA 1kx4 datasheet abstract.. |
758.74 Kb |
36 Pages |
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First line: Package Information Cyclone Devices C52006-1.3 This data sheet provides package information Altera® devices. includes following sections: Abstract: .. EP1C12 Non-Thermally Enhanced FineLine BGA 256. Non-Thermally Enhanced FineLine BGA 324. EP1C20 EP1C20 Non-Thermally Enhanced FineLine BGA 324. Non-Thermally Enhanced FineLine BGA 400. C52006-1 C52006-1 .3 .. Tags: C52006-1 |
47.09 Kb |
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First line: altera date code format PROCESS CHANGE NOTIFICATION PCN0304 WAFER SCHEDULE Change Description Effective September 2003, Altera will begin manufacturing StratixTM CycloneTM product families wafers using 0.13µm process technology TSMC. existing wafer processes same, identical circuit layout used Abstract: .. EP1C12 B 9H. EP1C20 EP1C20 B 9H. Process code 9E and 9H represent wire-bond packages while process code 9D represents flip-chip packages. Page 2 of 2. Altera Corporation 5/30/03 PCN0304 PCN0304 . Transition Dates .. Tags: altera date code format PCN0304 |
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First line: Package Information Cyclone Devices C52006-1.2 This data sheet provides package information Altera® devices. includes these sections: Section Page Abstract: .. EP1C12 Non-Thermally Enhanced FineLine BGA 256. Non-Thermally Enhanced FineLine BGA 324. EP1C20 EP1C20 Non-Thermally Enhanced FineLine BGA 324. Non-Thermally Enhanced FineLine BGA 400. C52006-1 C52006-1 .2 .. Tags: EP1C12 C5200* altera cyclone 3 C52006-1 |
47.89 Kb |
3 Pages |
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First line: PROCESS CHANGE NOTIFICATION PCN0413 ADDITIONAL WAFER FABRICATION SITE (FAB Change Description: Beginning October 2004, Altera will shipping 0.13 products from TSMC's fabrication site, addition Fabs Reason Change: TSMC being added 300-mm wafer source ensure product availability. Products Affected: in Abstract: .. fabricated at TSMC Fab 14 are the Stratix EP1S25 EP1S25 , EP1S60 EP1S60 , and EP1S80 EP1S80 , and the CycloneTM EP1C12 and EP1C6. Additional products may also be added at Fab 14 in the future. Qualification Data: The TSMC .. Tags: PCN0413 |
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First line: Section VII. Cyclone Device Package Information This section provides information board layout designers successfully layout their boards Cyclone devices. contains required layout guidelines, device tables, package specifications. This section includes following chapter: Chapter Package Information Abstract: .. EP1C12 Non-Thermally Enhanced FineLine BGA 256. Non-Thermally Enhanced FineLine BGA 324. EP1C20 EP1C20 Non-Thermally Enhanced FineLine BGA 324. Non-Thermally Enhanced FineLine BGA 400. C52006-1 C52006-1 .3 .. Tags: datasheet abstract.. |
49.99 Kb |
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First line: Section VII. Layout Guidelines This section provides information board layout designers successfully layout their boards Cyclone devices. contains required layout guidelines, device tables, package specifications. This section includes following chapter: Chapter Package Information Cyclone Devices Abstract: .. EP1C12 Non-Thermally Enhanced FineLine BGA 256. Non-Thermally Enhanced FineLine BGA 324. EP1C20 EP1C20 Non-Thermally Enhanced FineLine BGA 324. Non-Thermally Enhanced FineLine BGA 400. C52006-1 C52006-1 .2 .. Tags: C5200* altera cyclone 3 datasheet abstract.. |
52.22 Kb |
5 Pages |
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First line: G700 MPM7128 EME-G700 SUMITOMO EME G700 SUMITOMO G700 PROCESS CHANGE NOTICE PCN0504 STANDARDIZED EME-G700 SERIES MOLD COMPOUND PACKAGES Change Description: Altera will standardizing Sumikon EME-G700 series mold compound Altera's quad flat pack (QFP) packages. packages assembled Malaysia Amkor Korea Abstract: .. EP1C6, EP1C12. EPF6016 EPF6016 , EPF6024A EPF6024A . EPF81188A EPF81188A , EPF81500A EPF81500A . EPF10K30A EPF10K30A . EPF10K50V EPF10K50V . EPF10K50E EPF10K50E .. Tags: SUMITOMO G700 SUMITOMO EME G700 EME-G700 MPM7128 G700 PCN0504 |
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First line: 100 PIN tQFP ALTERA DIMENSION C51001-1.5 Cyclone® field programmable gate array family based 1.5-V, 0.13-m, all-layer copper SRAM process, with densities 20,060 logic elements (LEs) Kbits RAM. With features like phase-locked loops (PLLs) clocking dedicated double data rate (DDR) interface meet S Abstract: .. Feature EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 EP1C20 . LEs 2,910 4,000 5,980 12,060 20,060. M4K RAM blocks 128 × 36 bits 13 17 20 52 64. C51001-1 C51001-1 .5. 1–2 Altera Corporation. Preliminary May 2008. Cyclone Device Handbook .. Tags: 100 PIN tQFP ALTERA DIMENSION EP1C3 256-pin Plastic BGA 17 x 17 C51001-1 |
54.12 Kb |
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First line: EPC2 Cyclone FPGA Series Package Matrix Number indicates available user pins. Vertical migration (Same Vcc, GND, ISP, input pins). User less than labelled vertical migration. Cyclone (1.2 Abstract: .. EP2C15 EP2C15 EP2C20 EP2C20 EP2C35 EP2C35 EP2C50 EP2C50 EP2C70 EP2C70 EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 EP1C20 Confi guration File Size Mbits 1.26 1.98 3.89 3.89 6.85 9.96 14.31 0.63 0.93 1.17 2.32 3.56 Number of EPCS1 Devices 1 Mbit 1 .. Tags: EPC2 EP2C20 datasheet abstract.. |
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First line: altera date code format EP1K30FC256-2 EP1C6F256C8N EP1C12F324C6N EP1C6F256I7N Revision: 1.1.0 PROCESS CHANGE NOTIFICATION PCN0901 SUBSTRATE CHANGE SELECTED FBGA PACKAGES Change Description Abstract: .. EP1C12 Now May 2009. EP1C4 Now May 2009. 324. EP1C12 Now May 2009. EP1C4 Now May 2009. Cyclone FPGA. FBGA. 400. EP1C20 EP1C20 Now May 2009. For device samples please visit http://www.samplecomponents.com/scripts .. Tags: EP1C6F256I7N EP1C12F324C6N EP1C6F256C8N EP1K30FC256-2 altera date code format PCN0901 |
192.06 Kb |
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First line: EPM2210 324 SUMITOMO sumitomo G770 PROCESS CHANGE NOTIFICATION PCN0515 MOLD COMPOUND CHANGE FBGA PACKAGES Change Description: Altera adopting Sumitomo G770 series mold compound standard mold material Altera® FineLine BGA® (FBGA) device packages. Devices FBGA packages currently molded with N Abstract: .. EP1C12 EP1C20 EP1C20 EP1C4 EP20K100 EP20K100 EP20K100E EP20K100E EP20K30E EP20K30E EP20K60E EP20K60E EPM2210 EPM2210 . 324. EPM2210G EPM2210G EP1C20 EP1C20 . 400. EP1C4 EP1K100 EP1K100 EP1K50 EP1K50 EP20K160E EP20K160E EP20K200 EP20K200 EP20K200C EP20K200C EP20K200E EP20K200E EPF EPF10K100E EPF10K100E EPF10K130E EPF10K130E EPF10K200S EPF10K200S .. Tags: sumitomo G770 SUMITOMO EPM2210 324Â PCN0515 |
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First line: jtag pin PQFP ALTERA 160 C51001-1.4 Cyclone® field programmable gate array family based 1.5-V, 0.13-m, all-layer copper SRAM process, with densities 20,060 logic elements (LEs) Kbits RAM. With features like phaselocked loops (PLLs) clocking dedicated double data rate (DDR) interface meet SDRAM f Abstract: .. Feature EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 EP1C20 . LEs 2,910 4,000 5,980 12,060 20,060. M4K RAM blocks 128 × 36 bits 13 17 20 52 64. Total RAM bits 59,904 78,336 92,160 239,616 294,912. PLLs 1 2 2 2 2. Maximum user .. Tags: PQFP ALTERA 160 jtag pin EP1C12 256-pin Plastic BGA 17 x 17 C51001-1 |
60.81 Kb |
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First line: C51001-1.2 CycloneTM field programmable gate array family based 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities 20,060 logic elements (LEs) Kbits RAM. With features like phaselocked loops (PLLs) clocking dedicated double data rate (DDR) interface meet SDRAM fast cycle (FCRAM) mem Abstract: .. Feature EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 EP1C20 . LEs 2,910 4,000 5,980 12,060 20,060. M4K RAM blocks 128 × 36 bits 13 17 20 52 64. Total RAM bits 59,904 78,336 92,160 239,616 294,912. PLLs 1 2 2 2 2. Maximum user .. Tags: 256-pin Plastic BGA 17 x 17 C51001-1 |
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First line: ISO/IEC 14495-1 JPEG-LS Compliance Programmable local gradient JPEGLS-E JPEG-LS Encoder Megafunction Abstract: .. Cyclone EP1C12-C6 10,673 LEs 80 MHz 29 M4K. Stratix EP1S20-C6 EP1S20-C6 . 11,316 LEs 83 MHz 29 M4K. CycloneII EP2C20-C6 EP2C20-C6 10,894 LEs 99 MHz 29 M4K. StratixII EP2S15-C3 EP2S15-C3 9,875 ALUTs 102 MHz 29 M4K. HardcopyII HC210 HC210 .. Tags: jpeg* datasheet abstract.. |
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First line: EP2C8F256CXNAA altera marking Code Formats Cyclone 2 EPM240T100C5N EPM1270GT144C4* EP1C12Q240I7 datasheet download pdf Revision: 1.0.0 PROCESS CHANGE NOTIFICATION PCN0813 POLYIMIDE WAFER COAT REMOVAL SELECTED ALTERA DEVICES Change Description Abstract: .. EP1C12 Q240 Q240 , F256 F256 , F324 F324 Dec 2008. Cyclone FPGA. EP1C20 EP1C20 F324 F324 , F400 F400 Dec 2008. EPM240 EPM240 Dec 2008. EPM240G EPM240G . T100 T100 ,F100 F100 ,M100 M100 Dec 2008. EPM570 EPM570 Dec 2008. EPM570G EPM570G . T100 T100 ,T144 T144 ,F100 F100 , F256 F256 ,M100 M100 ,M256 M256 Dec 2008. EPM1270 EPM1270 .. Tags: EP1C12Q240I7 datasheet download pdf EPM1270GT144C4* EPM240T100C5N altera marking Code Formats Cyclone 2 EP2C8F256CXNAA PCN0813 |
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First line: Nitto* sumitomo g770 Nitto GE 100 sumitomo g770 SUMITOMO EME G770 Revision: 1.0.1 PROCESS CHANGE NOTIFICATION PCN0712 MOLD COMPOUND CHANGES BGA, UBGA, MBGA FBGA PACKAGES Change Description: Abstract: .. EP1C12 EP1C6 EP1K10 EP1K10 . EP1K100 EP1K100 EP1K30 EP1K30 EP1K50 EP1K50 EP2C15A EP2C15A . EP2C20 EP2C20 EP2C5 EP2C8 EP2C8A EPF10K100E EPF10K100E . EPF10K30A EPF10K30A EPF10K30E EPF10K30E EPF10K50E EPF10K50E EPF10K50S EPF10K50S . EPF6016A EPF6016A EPM1270 EPM1270 EPM1270G EPM1270G EPM2210 EPM2210 EPM2210G EPM2210G EPM3128A EPM3128A EPM3256A EPM3256A .. Tags: SUMITOMO EME G770 sumitomo g770 Nitto GE 100 sumitomo g770Â Nitto* PCN0712 |
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First line: EP1C3T144C8 EPM7064AETC44-10 EP1K30TC144-3 EP1K100QC208-3 EP1K50QC208-3 White Paper Using Extended Temperature Devices Quartus Software Altera® MAX® 7000AE, ACEX® CycloneTM device families support extended range temperatures (see Table meet production needs automotive, communications, mi Abstract: .. EP1C12 256-pin 256-pin FineLine BGA. 324-pin 324-pin FineLine BGA. Cyclone 1 , 2 , 3 EP1C20 EP1C20 400-pin 400-pin FineLine BGA. Using Extended Temperature Range Devices in the Quartus II Software Altera Corporation. 2. Notes .. Tags: EP1K50QC208-3 EP1K100QC208-3 EPM7064AETC44-10 EP1C3T144C8 TQFP 144 PACKAGE EPM7128AETI100-7 EPM7128AETC100-10 EPM7064AETC100-10 EPCS4SI8 EPC2LI20 EP1K50F* EP1K50 EP1K30TI144-2 EP1K30TC144-3 EP1K30 datasheet abstract.. |
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First line: EPM7064AETC* ep1K50QC208-3 Datasheet pdf Technical Brief Using Extended Temperature Range Devices Quartus Software Altera® MAX® 7000AE, ACEX® Cyclone® device families support extended range temperatures (see Table meet production needs automotive, communications, military, industrial Abstract: .. EP1C12 256-pin 256-pin FineLine BGA. 324-pin 324-pin FineLine BGA. EP1C20 EP1C20 400-pin 400-pin FineLine BGA. Using Extended Temperature Range Devices in Quartus II Software Altera Corporation. 2. For MAX 7000AE 7000AE devices, the .. Tags: ep1K50QC208-3 Datasheet pdf EPM7064AETC* TQFP 144 PACKAGE EPM7256AETI144-7 EPM7256AE 144 EPM7128AETI100-7 EPM7128AETC100-10 EPM7064AETC44-10 EPM7064AETC100-10 EPC2LI20 ALTERA EPC2LI20 EP1K50QC208-3 EP1K50QC208 datasheet abstract.. |
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First line: dct verilog code Baseline ISO/IEC 10918-1 JPEG Compliance Programmable Huffman Tables JPEG-E Baseline JPEG Encoder Megafunction Abstract: .. Cyclone EP1C12-C6 7,201 LEs. 125 MHz 9 M4K 7.1. Cyclone-II EP2C20-C6 EP2C20-C6 5,337 LEs. 154 MHz. 9 M4K 19 DSP. 7.1. Cyclone-III EP3C16-C6 EP3C16-C6 5,259 LEs. 161 MHz. 9 M4K 19 DSP. 7.1. Stratix EP1S10-C5 EP1S10-C5 5,389 LEs. 143 MHz 8 M4K .. Tags: dct verilog code huffman code book in verilog datasheet abstract.. |
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First line: Baseline ISO/IEC 10918-1 JPEG Compliance JPEG-D Baseline JPEG Decoder Megafunction Implements high-performance image video decoder that complies with baseline ISO/IEC 10918-1 JPEG standard. fastest available JPEG megafunctions, JPEG-D provides highperformance solution variety image video decompressi Abstract: .. Cyclone EP1C12-C6. 8,796 LEs 85 MHz 7 M4K. Cyclone-II EP2C8-C6. 6,796 LEs 112 MHz. 7 M4K 19 DSP. Stratix EP1S10-C5 EP1S10-C5 . 6,158 LEs 95 MHz. 7 M4K / 1 M512 M512 18 DSP. Stratix-II EP2S15-C3 EP2S15-C3 6,053 ALUTs 140 MHz 7 M4K / 1 M512 M512 .. Tags: datasheet abstract.. |
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First line: Baseline ISO/IEC 10918-1 JPEG Compliance JPEG-D Baseline JPEG Decoder Megafunction Implements high-performance image video decoder that complies with baseline ISO/IEC 10918-1 JPEG standard. fastest available JPEG megafunctions, JPEG-D provides highperformance solution variety image video decompressi Abstract: .. Cyclone EP1C12-C6. 8,796 LEs 85 MHz 7 M4K. Cyclone-II EP2C8-C6. 6,796 LEs 112 MHz. 7 M4K 19 DSP. Stratix EP1S10-C5 EP1S10-C5 . 6,158 LEs 95 MHz. 7 M4K / 1 M512 M512 18 DSP. Stratix-II EP2S15-C3 EP2S15-C3 6,053 ALUTs 140 MHz 7 M4K / 1 M512 M512 .. Tags: datasheet abstract.. |
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First line: Baseline ISO/IEC 10918-1 JPEG Compliance JPEG-E Baseline JPEG Encoder Megafunction Implements high-performance image encoder that complies with baseline ISO/IEC 10918-1 JPEG standard. fastest available JPEG megafunctions, JPEG-E provides highperformance solution variety image video compression appli Abstract: .. Cyclone EP1C12-6. 7,201 LEs. 125 MHz 9 M4K 7.1. Cyclone-II EP2C20-6 EP2C20-6 . 5,337 LEs. 154 MHz. 9 M4K 19 DSP. 7.1 .. Tags: datasheet abstract.. |
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First line: Compliant with IEEE 1284- 2000 parallel interface protocol standard ECP_Slave Extended Capabilities Parallel Port Slave Megafunction Abstract: .. Cyclone EP1C12-7. 496 - 119. Stratix EP1S20-6 EP1S20-6 . 496 - 130. Support. The megafunction as delivered is .. Tags: datasheet abstract.. |
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First line: jtag mhz Configuration Testing C51003-1.4 IEEE Std. 1149.1 (JTAG) Boundary Scan Support Cyclone® devices provide JTAG circuitry that complies with IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan testing performed either before after, during configuration. Cyclone devices also JTAG port Abstract: .. EP1C12 0000 0010 0000 1000 0011 000 0110 1110 1. EP1C20 EP1C20 0000 0010 0000 1000 0100 000 0110 1110 1. Notes to Table 3–3 : 1 The most significant bit MSB is on the left. 2 The IDCODE’s least significant .. Tags: jtag mhz C51003-1 |
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First line: Switching Characteristics C51004-1.7 Operating Conditions Cyclone® devices offered both commercial, industrial, extended temperature grades. However, industrial-grade extendedtemperature-grade devices have limited speed-grade availability. Tables through 4-16 provide information absolute maximum Abstract: .. EP1C12 — 8 — mA. EP1C20 EP1C20 — 12 — mA. RCONF 9 Value of I/O pin pull-up resistor before and during configuration VI = 0 V; VCCI0 = 3.3 V 15 25 50 kΩ. VI = 0 V; VCCI0 = 2.5 V 20 45 70 kΩ. VI = 0 V; VCCI0 = 1.8 V 30 65 100 kΩ. VI .. Tags: C51004-1 |
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First line: Configuration Testing C51003-1.3 IEEE Std. 1149.1 (JTAG) Boundary Scan Support Cyclone® devices provide JTAG circuitry that complies with IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan testing performed either before after, during configuration. Cyclone devices also JTAG port configura Abstract: .. EP1C12 0000 0010 0000 1000 0011 000 0110 1110 1. EP1C20 EP1C20 0000 0010 0000 1000 0100 000 0110 1110 1. Notes to Table 3–3 : 1 The most significant bit MSB is on the left. 2 The IDCODE’s least significant .. Tags: C51003-1 |
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First line: EP1C3 Switching Characteristics C51004-1.6 Operating Conditions Cyclone® devices offered both commercial, industrial, extended temperature grades. However, industrial-grade extendedtemperature-grade devices have limited speed-grade availability. Tables through 4-16 provide information absolute m Abstract: .. EP1C12 8 mA. EP1C20 EP1C20 12 mA. RCONF 9 Value of I/O pin pull-up resistor before and during configuration VI = 0 V; VCCI0 = 3.3 V 15 25 50 kΩ. VI = 0 V; VCCI0 = 2.5 V 20 45 70 kΩ. VI = 0 V; VCCI0 = 1.8 V 30 65 100 kΩ. VI = 0 V .. Tags: EP1C3 C51004 C51004-1 |
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First line: Error Detection Using Altera FPGA Devices Application Note Abstract: .. EP1C12 - - 2 C3 C2 -. EP1C20 EP1C20 - - - - C2 C2. Altera Corporation 5. Preliminary. Error Detection Timing .. EP1C12 3.5 0.90. EP1C20 EP1C20 5.4 1.4. Altera Corporation 7. Preliminary. Software Support. Software .. Tags: af20 ae21 "Error Detection" datasheet abstract.. |
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First line: marking ic 2008 ep1k30 pin Revision: 1.3.0 PROCESS CHANGE NOTIFICATION PCN0714 UPDATE ASSEMBLY PLANT CHANGE PQFP TQFP PACKAGES Change Description: Abstract: .. EP1C12 October 2010. EP1C6 October 2010. EP2C20 EP2C20 October 2010. EP3C16 EP3C16 October 2010. EP3C25 EP3C25 October 2010. PQFP 240. EP3C40 EP3C40 October 2010. EP3C5 January 2011. EP3C10 EP3C10 January 2011. EP3C16 EP3C16 January 2011. EQFP .. Tags: ep1k30 pin marking ic 2008 PCN0714 |
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First line: cbc 327 Conforms Advanced Encryption Standard (AES) standard (FIPS 197) AES-C Optimized Encrypt/Decrypt Megafunction AES-C megafunction implements hardware data encryption decryption using Rijndael encoding compliance with FIPS-197 Advanced Encryption Standard (AES). runs common block-cipher modes: Abstract: .. Cyclone EP1C12-6 792 10 M4K 115 111 321 7.2. Cyclone-II EP2C20-6 EP2C20-6 779 10 M4K 115 119 345 7.2. Cyclone-III EP3C120-6 EP3C120-6 789 6 M9K 115 136 394 7.2. Stratix EP1S10-5 EP1S10-5 . 760 10 M4K 115 113 327 7.2. Stratix-II EP2S15 EP2S15 .. Tags: cbc 327 SP800-38A |
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First line: C1394A IEEE-1394a Link Layer Controller Core Conforms implements functionality IEEE 13941995 IEEE 1394a-2000 standards Based Texas Instruments TSB12LV32 General Purpose Link Layer controller Supports device data transmission 400, Mbps Includes 32-bit AMBA Slave microprocessor interface (other standa Abstract: .. Cyclone EP1C12-6 6,597 8 M4Ks 32,768 112 MHz. Stratix EP1S10-5 EP1S10-5 6,746 8 M4Ks 32,768 120 MHz. Stratix-II EP2S15-3 EP2S15-3 6,103 8 M4Ks 32,768 160 MHz. Support. The core as delivered is warranted against defects .. Tags: TSB12LV32 |
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First line: logic diagram to setup adder and subtractor using Section Cyclone FPGA Family Data Sheet This section provides designers with data sheet specifications Cyclone® devices. chapters contain feature definitions internal architecture, configuration JTAG boundary-scan testing information, operating co Abstract: .. Feature EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 EP1C20 . LEs 2,910 4,000 5,980 12,060 20,060. M4K RAM blocks 128 × 36 bits 13 17 20 52 64. C51001-1 C51001-1 .5. 1–2 Altera Corporation. Preliminary May 2008. Cyclone Device Handbook .. Tags: logic diagram to setup adder and subtractor using 256-pin Plastic BGA 17 x 17 datasheet abstract.. |
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First line: Section Cyclone FPGA Family Data Sheet This section provides designers with data sheet specifications Cyclone devices. chapters contain feature definitions internal architecture, configuration JTAG boundary-scan testing information, operating conditions, timing parameters, reference power consumptio Abstract: .. EP1C12 devices. Updated timing information in Tables 4-25 through 4-26 and Tables 4-30 through 4-51. Updated PLL specifications in Table 4-52. July 2003 v1.1. Updated timing information. Timing .. Tags: 256-pin Plastic BGA 17 x 17 datasheet abstract.. |
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First line: Section Cyclone FPGA Family Data Sheet This section provides designers with data sheet specifications Cyclone® devices. chapters contain feature definitions internal architecture, configuration JTAG boundary-scan testing information, operating conditions, timing parameters, reference power consu Abstract: .. Feature EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 EP1C20 . LEs 2,910 4,000 5,980 12,060 20,060. M4K RAM blocks 128 × 36 bits 13 17 20 52 64. Total RAM bits 59,904 78,336 92,160 239,616 294,912. PLLs 1 2 2 2 2. Maximum user .. Tags: 256-pin Plastic BGA 17 x 17 datasheet abstract.. |
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First line: Switching Characteristics C51004-1.3 Operating Conditions Cyclone devices offered both commercial, industrial, extended temperature grades. However, industrial-grade extendedtemperature-grade devices have limited speed-grade availability. Tables through 4-16 provide information absolute maximum rati Abstract: .. EP1C12 8 mA. EP1C20 EP1C20 12 mA. RCONF Value of I/O pin pull-up resistor before and during configuration. VCCIO = 3.0 V 9 20 50 kΩ. VCCIO = 2.375 V 9 30 80 kΩ. VCCIO = 1.71 V 9 60 150 kΩ. Table 4–4. LVTTL Specifications .. Tags: C51004-1 |
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First line: ep1c6-144 High-Speed Differential Signaling Cyclone Devices C51009-1.6 From high-speed backplane applications high-end switch boxes, low-voltage differential signaling (LVDS) technology choice. LVDS low-voltage differential signaling standard, allowing higher noise immunity than single-ended technol Abstract: .. EP1C12 — 451 to 640 300 to 450 Mbps. EP1C20 EP1C20 551 to 640 300 to 550 — Mbps. Table 9–9. Receiver PLL Phase Settingsfor Right and Left I/O Banks. Device. Phase Shift Degree Unit. –22.5 0 22.5 45. EP1C3 — — 451 to .. Tags: ep1c6-144 C51009-1 |
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First line: ic 311 pdf datasheets downloads High-Speed Differential Signaling Cyclone Devices C51009-1.5 From high-speed backplane applications high-end switch boxes, low-voltage differential signaling (LVDS) technology choice. LVDS low-voltage differential signaling standard, allowing higher noise immunity tha Abstract: .. EP1C12 451 to 640 300 to 450 Mbps. EP1C20 EP1C20 551 to 640 300 to 550 Mbps. Table 9–9. Receiver PLL Phase Settingsfor Right & Left I/O Banks. Device. Phase Shift Degree Unit. –22.5 0 22.5 45. EP1C3 451 to 640 300 .. Tags: ic 311 pdf datasheets downloads altera cyclone 3 C51009-1 |
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First line: Quartus Device Support Release Notes June 2006 Quartus version Service Pack This document provides late-breaking information about device support this version Altera® Quartus® software. information about memory, disk space, system requirements, refer readme.txt file your \altera\quartus<v Abstract: .. EP1C12 3.0 SP1. Cyclone. EP1C20 EP1C20 3.0. EP2C5 6.0. EP2C8 5.1 SP2. EP2C20 EP2C20 5.1 SP2. EP2C35 EP2C35 5.1 SP2. EP2C50 EP2C50 6.0 .. Tags: HC240 |
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First line: EP3C5* EP3C120F780I7* EP3C16Q240C8N EP3C10E144C8N EP3C16F484C6N Revision: 1.2.0 PROCESS CHANGE NOTIFICATION PCN0904 Cyclone® Family Process Shrink from 65-nm 60-nm Package Bill Material Change Change Description Abstract: .. EP1C12 Cu Bondwire F324 F324 . Temperature Cycle “B” -55 C to 125 C 1000 cyc 0 / 50. High Temp Bake @ 150 C 1000 hrs 0 / 77. Biased HAST 130 C / 85%RH 96 hrs 0 / 77. Autoclave 121 C / 15 psi 96 hrs 0 / 77. EP1C6 .. Tags: EP3C16F484C6N EP3C10E144C8N EP3C16Q240C8N EP3C120F780I7* EP3C5* PCN0904 |
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First line: EPC2LC20 1C12 Package 100-TQFP 100-TQFP 100-TQFP 44-TQFP 44-TQFP 44-TQFP 44-TQFP 84-PLCC 100-TQFP 100-TQFP 100-TQFP 144-TQFP 100-TQFP 100-TQFP 144-TQFP Tube Macro Cells CPLD's (Cont.) Logic Elements 1,250 1,250 1,250 1,250 1,250 1,250 1,250 2,500 2,500 2,500 2,500 2,500 2,500 5,000 5,000 Pin-Pin Del Abstract: .. 544-1137-ND 544-1137-ND NIOS II Evaluation Kit with Cyclone EP1C12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$312.70. The University Program UP3 Education Kit was designed to meet the needs of universities .. Tags: 1C12 TQFP 32 PACKAGE EPM7256AETC100-10 EPM7128* kit EPM7064AETC44-4 EPCS4SI8 EPCS16SI16N* EPC4QC100 EPC2LC20 EPC1PI8 epc1pc8 EPC16QI100 EPM7064AETC100-10 EPM7064AETC100-4 EPM7064AETC100-7 EPM7064AETC44-10 EPM7064AETC44-4 EPM7064AETC44-7 EPM7064AETI44-7 EPM7128AELC84-10 EPM7128AETC100-10 EPM7128AETC100-5 EPM7128AETC100-7 EPM7128AETC144-10 EPM7128AETI100-7 EPM7256AETC100-10 |
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First line: EP1S60F1020I6 Technical Brief Extended Temperature Support 7000AE, Cyclone, Stratix, ACEX Devices Altera® MAX® 7000AE, Cyclone®, Stratix®, ACEX® device families support extended range temperatures (see Table meet production needs automotive, communications, military, industrial a Abstract: .. EP1C12 256-pin 256-pin FBGA. 324-pin 324-pin FBGA. EP1C20 EP1C20 400-pin 400-pin FBGA. Stratix 3 EP1S30 EP1S30 780-pin 780-pin FBGA. EP1S40 EP1S40 .. Tags: EP1S60F1020I6 EP1S30F780I6 EP1K50QC208-3 EP1K50F* EP1K50* EP1K30TC144-3 EP1K10TC100-3 EP1K100QC208-3 ALTERA EP1K100QC208-3 EP1C3T144C8 EP1C20F400C8 datasheet abstract.. |
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First line: 527 MOSFET TRANSISTOR motorola Cyclone Device Handbook, Volume Innovation Drive Jose, 95134 (408) 544-7000 http://www.altera.com C5V1-1.0 Abstract: .. Feature EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 EP1C20 . LEs 2,910 4,000 5,980 12,060 20,060. M4K RAM blocks 128 × 36 bits 13 17 20 52 64. Total RAM bits 59,904 78,336 92,160 239,616 294,912. PLLs 1 2 2 2 2. Maximum user .. Tags: 527 MOSFET TRANSISTOR motorola BGA and QFP Altera Package mounting SOIC Package 8-Pin Surface Mount 601 EIA standards 783 DATASHEET OF 8 pin DIP IC 741 zener smd h10 SURFACE MOUNT GENERAL RECTIFIER M7 motorola volume 1 MOTOROLA linear handbook motorola handbook motorola 986 MIL GRADE TRANSISTOR ARRAY DATA SHEET m7 smd diodes lot Code Formats altera cyclone linear switching voltage regulator handbook FDS8936A datasheet abstract.. |
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First line: Cyclone FPGA Family Abstract: .. Feature EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 EP1C20 . LEs 2,910 4,000 5,980 12,060 20,060. M4K RAM blocks 128 × 36 bits 13 17 20 52 64. Total RAM bits 59,904 78,336 92,160 239,616 294,912. PLLs 1 2 2 2 2. Maximum user .. Tags: PS 117 B 892 data sheet 256-pin Plastic BGA 17 x 17 datasheet abstract.. |
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First line: Cyclone FPGA Family Abstract: .. Feature EP1C3 EP1C6 EP1C12 EP1C20 EP1C20 . LEs 2,910 5,980 12,060 20,060. M4K RAM blocks 128 × 36 bits 13 20 52 64. Total RAM bits 59,904 92,160 239,616 294,912. PLLs 1 2 2 2. Maximum user I/O pins 1 104 185 249 .. Tags: 256-pin Plastic BGA 17 x 17 datasheet abstract.. |
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First line: Quartus Software Release Notes April 2003 Quartus version Service Pack This document provides late-breaking information about following areas this version Altera® Quartus® software. information about memory, disk space, system requirements, refer readme.txt file your quartus directory. Featu Abstract: .. packages Adds full programming support for Cyclone EPC1C3, EP1C6, and EP1C12 devices Adds full programming support for StratixTM EP1S10 EP1S10 , EP1S20 EP1S20 , EP1S40 EP1S40 , EP1S60 EP1S60 , and EP1S80 EP1S80 devices Adds support .. Tags: datasheet abstract.. |
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First line: logic diagram to setup adder and subtractor using Cyclone Architecture C51002-1.6 Functional Description Cyclone® devices contain two-dimensional row- column-based architecture implement custom logic. Column interconnects varying speeds provide signal interconnects between LABs embedded memory b Abstract: .. Figure 2–1 shows a diagram of the Cyclone EP1C12 device. C51002-1 C51002-1 .6. 2–2 Altera Corporation. Preliminary May 2008. Cyclone Device Handbook, Volume 1. Figure 2–1. Cyclone EP1C12 Device Block Diagram .. Tags: logic diagram to setup adder and subtractor using EP1C12 |
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First line: Cyclone Architecture C51002-1.5 Functional Description Cyclone® devices contain two-dimensional row- column-based architecture implement custom logic. Column interconnects varying speeds provide signal interconnects between LABs embedded memory blocks. logic array consists LABs, with each LAB. s Abstract: .. Figure 2–1 shows a diagram of the Cyclone EP1C12 device. C51002-1 C51002-1 .5. 2–2 Altera Corporation. Preliminary January 2007. Cyclone Device Handbook, Volume 1. Figure 2–1. Cyclone EP1C12 Device Block .. Tags: 32 bit carry select adder EP1C12 |
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