EN5914A LC75396NE 50698RM 3159-QFP64E QFP64E - Datasheet Archive

 

SANYO Semiconductors DATA SHEET LC75396NE CMOS IC Single-Chip Electronic Volume Control System Overview The LC75396NE is an

 

Ordering number : EN5914A EN5914A SANYO Semiconductors DATA SHEET LC75396NE LC75396NE CMOS IC Single-Chip Electronic Volume Control System Overview The LC75396NE LC75396NE is an electronic volume control system providing control over volume, balance, 5-band equalizer, and input switching based on serial inputs. Functions · Volume control: The chip provides 81 levels of volume attenuation: in 1-dB step between 0 dB and ­79 dB and ­. Independent control over left front/rear and right front/rear channels provides balance control. · Equalizer: The chip provides control in 2-dB steps over the range between +10 dB and ­10 dB. Four of the five bands have peaking equalization; the remaining one, shelving equalization. · Selector: The left and right channels each offer a choice of five inputs. The L5 and R5 inputs can be turned on and off independently. An external constant determines the amplification for the input signal. · Serial data input - Supports CCB* format communication with the system controller. Features · Built-in buffer amplifiers reduce the number of external parts required. · Silicon gate CMOS process reduces the noise of built-in switch. · VDD/2 reference voltage generation circuit built in. · CCB is a trademark of SANYO ELECTRIC CO., LTD. · CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO. Specifications Absolute Maximum Ratings at Ta = 25°C, V SS = 0 V Parameter Maximum supply voltage Symbol Conditions VDD max Maximum input voltage VIN max CL, DI, CE, L1 to L5, R1 to R5, LTIN, RTIN, LFIN, RFIN, LRIN, RRIN Allowable power dissipation Pd max Ratings VDD Ta 75°C, with PC board Unit 11 V VSS ­ 0.3 to VDD + 0.3 V 550 mW Operating temperature Topr ­30 to +75 °C Storage temperature Tstg ­40 to +125 °C Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before using any SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein. TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 50698RM 50698RM (OT) No. 5914-1/19 LC75396NE LC75396NE Allowable Operating Ranges at Ta = ­ 30 to + 75°C, V SS = 0 V Parameter Symbol Conditions Ratings min typ max Unit Supply voltage VDD VDD 6.0 10.5 V Input high level voltage VIH CL, DI, CE 4.0 VDD V Input low level voltage VIL CL, DI, CE VSS 1.0 V VIN CL, DI, CE, L1 to L5, R1 to R5, LTIN, RTIN, LFIN, RFIN, LRIN, RRIN VSS VDD Vp-p tøW Input voltage amplitude Input pulse width CL 1.0 µs Setup time tSETUP CL, DI, CE 1.0 µs Hold time tHOLD CL, DI, CE 1.0 Operating frequency fopg CL µs 500 kHz Electrical Characteristics at Ta = 25°C, V DD = 10 V, V SS = 0 V Parameter Symbol Conditions Ratings min typ max Unit [Input block] Input resistance Rin L1 to L5, R1 to R5 Clipping level Vcl LSELO, RSELO: THD = 1.0% Output load resistance RL LSELO, RSELO Rin LFIN, LRIN, RFIN, RRIN Geq Max, boost/cut 50 k 3.00 Vrms 10 k [Volume control block] Input resistance 100 k [Equalizer control block] Control range dB ±8 ±10 ±12 Step resolution Estep 1 2 3 dB Internal feedback resistance Rfeed 17 28 39 k 0.01 % [Overall characteristics] Total harmonic distortion THD CT Crosstalk VIN = 1 Vrms, f = 1 kHz, with all controls flat overall VIN = 1 Vrms, f = 1 kHz, with all controls flat overall, Rg = 1 k 80 dB VN 1 Output at maximum attenuation With all controls flat overall, BW = 20 to 20kHz 2.9 µV VN 2 Output noise voltage GEQ F1 Band = +10dB, With all controls overall, BW = 20 to 20kHz 17 µV VO min VIN = 1 Vrms, f = 1 kHz, main volume ­ ­90 Current drain IDD VDD ­ V SS = 10.5 V 46.5 Input high level current IIH CL, DI, CE, V IN = 10.5 V Input low level current IIL CL, DI, CE, V IN = 0 V dB mA 10 ­10 55.8 µA µA Package Dimensions unit: mm 3159-QFP64E 3159-QFP64E [LC75396NE LC75396NE] SANYO: QFP64E QFP64E No. 5914-2/19 LC75396NE LC75396NE Sample Application Circuit No. 5914-3/19 LC75396NE LC75396NE Test Circuits Total Harmonic Distortion No. 5914-4/19 LC75396NE LC75396NE Output Noise Voltage No. 5914-5/19 LC75396NE LC75396NE Crosstalk No. 5914-6/19 LC75396NE LC75396NE Pin Assignment No. 5914-7/19 LC75396NE LC75396NE Pin Functions Pin No. Pin 55 L1 54 L2 53 L3 52 L4 51 L5 57 R1 58 R3 60 R4 61 Equivalent circuit R2 59 Function R5 50 LINVIN1 62 RINVIN1 49 LSELO 63 RSELO 48 LTIN 64 RTIN 47 LF1C2 Inverting inputs to the operational amplifier that sets the input gain Input selector outputs LF1C1 46 Signal inputs 45 LF1C3 1 RF1C1 2 RF1C2 3 LF2C1 43 LF2C2 · Connections for the capacitors that form the equalizer F1 band filters RF1C3 44 Equalizer inputs 42 LF2C3 4 RF2C1 5 RF2C2 6 LF3C2 LF1C2 (RF1C2) and LF1C3 (RF1C3). · Connections for the capacitors that form the equalizer F2 band filters LF3C1 40 LF1C1 (RF1C1) and LF1C2 (RF1C2), and between RF2C3 41 Capacitors must be connected between: 39 LF3C3 7 RF3C1 8 RF3C2 9 LF4C2 LF2C2 (RF2C2) and LF2C3 (RF2C3). · Connections for the capacitors that form the equalizer F3 band filters LF4C1 37 LF2C1 (RF2C1) and LF2C2 (RF2C2), and between RF3C3 38 Capacitors must be connected between: 36 LF4C3 10 RF4C1 11 RF4C2 12 Capacitors must be connected between: LF3C1 (RF3C1) and LF3C2 (RF3C2), and between LF3C2 (RF3C2) and LF3C3 (RF3C3). · Connections for the capacitors that form the equalizer F4 band filters RF4C3 Capacitors must be connected between: LF4C1 (RF4C1) and LF4C2 (RF4C2), and between LF4C2 (RF4C2) and LF4C3 (RF4C3). Continued on next page. No. 5914-8/19 LC75396NE LC75396NE Continued from preceding page. Pin No. Pin Function 35 LF5 · Connections for the capacitors that form the equalizer F5 band filters 13 RF5 Equivalent circuit Connections for external capacitors 33 LFIN · Input to the left channel front 4-dB step volume control. 30 LRIN · Input to the left channel rear 4-dB step volume control. 15 RFIN · Input to the right channel front 4-dB step volume control. 18 RRIN · Input to the right channel rear 4-dB step volume control. 32 LFCOM · Common pin for the left channel front 1-dB step volume control. 29 LRCOM · Common pin for the left channel rear 1-dB step volume control. 16 RFCOM · Common pin for the right channel front 1-dB step volume control. 19 RRCOM · Common pin for the right channel rear 1-dB step volume control. 31 LFOUT · Left channel front volume control output 28 LROUT · Left channel rear volume control output 17 RFOUT · Right channel front volume control output 20 RROUT · Right channel rear volume control output 34 LTOUT 14 RTOUT 22 Vref · Equalizer outputs · A capacitor of a few tens of µF must be inserted between Vref and AVSS (VSS) to handle power supply ripple in the VDD/2 voltage generation circuit. 27 LVref 21 RVref 56 VDD · Power supply 26 VSS · Ground 25 CE · Internal analog system grounds · Chip enable 24 DI 23 CL When this pin goes from high to low, data is written to an internal latch and the analog switches operate. Data transfers are enabled when this pin is at the high level. · Serial data and clock inputs for chip control. No. 5914-9/19 LC75396NE LC75396NE Equivalent Circuit Diagram Selector Control Block Equalizer Control Block No. 5914-10/19 LC75396NE LC75396NE Volume Control Block Calculating the Size of External Capacitors The LC75396NE LC75396NE supports four bands with peaking characteristics and one band with shelving characteristics 1. Peaking Characteristics (bands F1 to F4) The external capacitor functions as the structural element of a simulated inductor. The equivalent circuit and the calculations required to achieve the desired center frequency are shown below. · Equivalent circuit for the simulated inductor Zo: Impedance at resonance No. 5914-11/19 LC75396NE LC75396NE · Calculation example Specifications: Central frequency, FO = 107 Hz Q factor at maximum boost, Q+10 dB = 0.8 - Calculate QO, the sharpness of the simulated inductance itself. Note: R4 is from the separately issued internal block diagram. QO = (R1 + R4)/R1 × Q+10dB 4.270 - Calculate C1 C1 = 1/2FOR1QO 0.536 (µF) - Calculate C2 C2 = QO/2FOR2 0.021 (µF) · Sample results Central frequency FO (Hz) C1 (F) C2 (F) 107 0.536 µ 0.021 µ 340 0.169 µ 6663 P 1070 0.054 µ 2117 P 3400 0.017 µ 666 P 2. Shelving characteristics (Band F5) Achieving the desired control of 2-dB steps over the range between +10 dB to ­10 dB requires choosing a capacitor, C3, with an impedance of 650 . Control System Timing and Data Formats To control the LC75396NE LC75396NE, specified sequences are required to be input through the pins CE, CL, and DI. Each sequence consists of 48 bits: an 8-bit address followed by 40 bits of data. No. 5914-12/19 LC75396NE LC75396NE 1. Address Code (B0 to A3) This product uses an 8-bit address code, and supports the same specifications as other Sanyo CCB serial bus products. Address code (LSB) 2. Control Code Allocations Input switching control Input switching control Five band equalizer control Operation Operation Band f1 Band f2 Band f3 Band f4 Band f5 No. 5914-13/19 LC75396NE LC75396NE Volume control Operation Channel selection control Operation Initial setting Simulataneous left and right Left channel volume rear/front control Operation Control is enabled when D33 = 1 Operation Control is enabled when D32 = 1 Rear Front Right channel volume rear/front control Rear Front Test mode control Operation These bits are for chip testing and must all be set to 0 in application systems. Notes: After power is first applied, applications must initialize this chip by sending the initial data (1) and (2) described below. Initial data . (1) Address 01000001 Data: (Set the volume to ­set both D34 and D35 to 1, and set all other data to 0) (2) Address 01000001 Data: (Set the volume to ­, set both D34 and D35 to 0, and set all other data to 0) After transferring that data, set the left and right channel initial settings before turning off the mute function. No. 5914-14/19 LC75396NE LC75396NE fO ( Center Frequency) Characteristics Volume Step Characteristics Flat overall When step = ­ Front and rear volume set to ­ THD ­ Frequency Characteristics (1) 80-kHz low pass weighting Gain: 0 dB Graphic equalizer: flat No. 5914-15/19 LC75396NE LC75396NE THD ­ Frequency Characteristics (3) Total harmonic distortion, THD - % Total harmonic distortion, THD - % THD ­ Frequency Characteristics (2) 80-kHz low pass weighting Gain: 0 dB Graphic equalizer: flat Volume: ­10 dB position Volume: 0 dB position 80-kHz low pass weighting Gain: 0 dB Graphic equalizer: flat : 0 dB All bands cut Flat dB position positio n Supply voltage, VDD - V THD ­ Supply Voltage Characteristics (1) Total harmonic distortion, THD - % Total harmonic distortion, THD - % THD ­ Supply Voltage Characteristics (1) Volume All bands boosted Frequency, f - Hz Frequency, f - Hz Volume: ­10 80-kHz low pass weighting Gain: 0 dB Volume: 0 dB position 80-kHz low pass weighting Gain: 0 dB Graphic equalizer: flat Volume: ­10 dB position Volume: 0 dB position Supply voltage, VDD - V No. 5914-16/19 LC75396NE LC75396NE 80-kHz low pass weighting Gain: 0 dB Volume: 0 dB position All bands boos ted All bands cut Flat THD ­ Input Level Characteristics (1) Total harmonic distortion, THD - % Total harmonic distortion, THD - % THD ­ Supply Voltage Characteristics (3) 80-kHz low pass weighting Gain: 0 dB Volume: 0 dB position Graphic equalizer: flat Supply voltage, VDD - V Input level, VIN - dBV 80-kHz low pass weighting Gain: 0 dB Volume: ­10 dB position Graphic equalizer: flat Input level, VIN - dBV THD ­ Input Level Characteristics (3) Total harmonic distortion, THD - % Total harmonic distortion, THD - % THD ­ Input Level Characteristics (2) 80-kHz low pass weighting Gain: 0 dB Volume: 0 dB position Al lb Al an ds lb ds cu t an bo os Fla ted t Input level, VIN - dBV No. 5914-17/19 LC75396NE LC75396NE 80-kHz low pass weighting Gain: 0 dB Volume: 0 dB position Graphic equalizer: flat Outut level, VO - dBV THD ­ Output Level Characteristics (2) Total harmonic distortion, THD - % Total harmonic distortion, THD - % THD ­ Output Level Characteristics (1) 80-kHz low pass weighting Gain: 0 dB Volume: ­10 dB position Graphic equalizer: flat Outut level, VO - dBV Total harmonic distortion, THD - % THD ­ Output Level Characteristics (3) 80-kHz low pass weighting Gain: 0 dB Volume: 0 dB position Al lb Al an ds lb ds bo os an cu ted t Fla t Outut level, VIN - dBV Usage Notes · When the power is first applied, the internal analog switches are in indeterminate states. The chip therefore requires muting or other external measures until it has received the proper data. · After power is first applied, applications must initialize this chip by sending the initial data (1) and (2) described below. Initial data . (1) Address 01000001 Data: (Set the volume to ­, set both D34 and D35 to 0, and set all other data to 0) (2) Address 01000001 Data: (Set the volume to ­, set both D34 and D35 to 1, and set all other data to 0) After transferring that data, set the left and right channel initial settings before turning off the mute function. · Provide grounding patterns or shielding for the lines to the CL, DI, and CE pins so as to prevent their high-frequency digital signals from interfering with the operation of nearby analog circuits. No. 5914-18/19 LC75396NE LC75396NE Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of May, 1998. Specifications and information herein are subject to change without notice. No. 5914-19/19