EM78P507N EM78P507NQ/LQ44J/S EM78P507NL48J/S P95/AD21 P94/AD22 P93/AD0 P92/AD1 - Datasheet Archive

 

8-Bit Microcontroller Product Specification DOC. VERSION 1.0 ELAN MICROELECTRONICS CORP. April 2010 Trademark Acknowledgments:

 

EM78P507N EM78P507N 8-Bit Microcontroller Product Specification DOC. VERSION 1.0 ELAN MICROELECTRONICS CORP. April 2010 Trademark Acknowledgments: IBM is a registered trademark and PS/2 is a trademark of IBM. Windows is a trademark of Microsoft Corporation. ELAN and ELAN logo are trademarks of ELAN Microelectronics Corporation. Copyright © 2010 by ELAN Microelectronics Corporation All Rights Reserved Printed in Taiwan The contents of this specification are subject to change without further notice. ELAN Microelectronics assumes no responsibility concerning the accuracy, adequacy, or completeness of this specification. ELAN Microelectronics makes no commitment to update, or to keep current the information and material contained in this specification. Such information and material may change to conform to each confirmed order. In no event shall ELAN Microelectronics be made responsible for any claims attributed to errors, omissions, or other inaccuracies in the information or material contained in this specification. ELAN Microelectronics shall not be liable for direct, indirect, special incidental, or consequential damages arising from the use of such information or material. The software (if any) described in this specification is furnished under a license or nondisclosure agreement, and may be used or copied only in accordance with the terms of such agreement. ELAN Microelectronics products are not intended for use in life support appliances, devices, or systems. Use of ELAN Microelectronics product in such applications is not supported and is prohibited. NO PART OF THIS SPECIFICATION MAY BE REPRODUCED OR TRANSMITTED IN ANY FORM OR BY ANY MEANS WITHOUT THE EXPRESSED WRITTEN PERMISSION OF ELAN MICROELECTRONICS. ELAN MICROELECTRONICS CORPORATION Hong Kong: Headquarters: st No. 12, Innovation 1 Road Hsinchu Science Park Hsinchu, TAIWAN 30076 Tel: +886 3 563-9977 Fax: +886 3 563-9966 webmaster@emc.com.tw http://www.emc.com.tw USA: Elan (HK) Microelectronics Corporation, Ltd. Flat A, 19F., World Tech Centre 95 How Ming Street, Kwun Tong Kowloon, HONG KONG Tel: +852 2723-3376 Fax: +852 2723-7780 Elan Information Technology Group (U.S.A.) PO Box 601 Cupertino, CA 95015 U.S.A. Tel: +1 408 366-8225 Fax: +1 408 366-8225 Shenzhen: Shanghai: Elan Microelectronics Shenzhen, Ltd. Elan Microelectronics Shanghai, Ltd. 3F, SSMEC Bldg., Gaoxin S. Ave. I Shenzhen Hi-tech Industrial Park (South Area), Shenzhen CHINA 518057 Tel: +86 755 2601-0565 Fax: +86 755 2601-0500 elan-sz@elanic.com.cn #34, First Fl., 2nd Bldg., Lane 122, Chunxiao Rd. Zhangjiang Hi-Tech Park Shanghai, CHINA 201203 Tel: +86 21 5080-3866 Fax: +86 21 5080-4600 elan-sh@elanic.com.cn Contents Contents 1 General Description . 1 2 Features . 1 3 Pin Assignment. 2 4 Pin Description . 4 4.2 EM78P507N EM78P507N LQFP/QFP 44 pins. 4 4.1 EM78P507N EM78P507N LQFP 48 Pins. 6 5 Block Diagram . 8 6 Function Description. 9 6.1 Operational Registers. 9 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6 1.8 6.1.9 6.1.10 6.1.11 6.1.12 6.1.13 6.1.14 6.1.15 6.1.16 6.1.17 6.1.18 6.1.19 6.1.20 6.1.21 6.1.22 6.1.23 6.1.24 6.1.25 6.1.26 6.1.27 6.1.28 6.1.29 6.1.30 R0 (Indirect Addressing Register) .9 R1 (ROM Page and RAM Bank Select Register).9 R2 (Program Counter) and Stack.9 R3 (Status Register) .12 R4 (RAM Select Register).12 Bank 0 R5 TBLP (Low Byte of Table Pointer Register).13 Bank 0 R6 TBHP (High Byte of Table Pointer Register) .13 Bank 0 R7 ~ RB (Port 7 ~ Port B) .13 Bank 0 RC SOCR (System Clock Control Register).13 Bank 0 RD TWTCR (TCC and WDT Timer Control Register).14 Bank 0 RE IMR (Interrupt Mask Register).15 Bank 0 RF ISR (Interrupt Status Register) .15 Bank 1 R5 ADCR1 (A/D Control Register 1).16 Bank 1 R6 ADCR2 (A/D Control Register) .16 Bank 1 R7 ADDL (A/D Low 8-Bit Data Buffer).17 Bank 1 R8 ADDH (A/D High 8-Bit Data Buffer) .17 Bank 1 R9 ADIC1 (A/D Input Control Register 1) .18 Bank 1 RA ADIC2 (A/D Input Control Register 2) .18 Bank 1 RB ADIC3 (A/D Input Control Register 3) .18 Bank 1 RC COCR (Clock Output Control Register).18 Bank 1 RE EIMR (External Interrupt Mask Register).19 Bank 1 RF EISR (External Interrupt Status Register) .19 Bank 2 R5 T1CR (Timer 1 Control Register) .19 Bank 2 R6 TSR (Timer 1 Status Register) .20 Bank 2 R7 T1PD (Timer 1 Period Buffer).21 Bank 2 R8 T1TD (Timer 1 Duty Buffer) .21 Bank 2 R9 T2CR (Timer 2 Control Register) .21 Bank 2 RA T2PD (Timer 2 Period Buffer).22 Bank 2 RB T2TD (Timer 2 Duty Buffer).22 Bank 2 RC T3CR1 (Timer 3 Control Register 1).22 Product Specification (V1.0) 04.16.2010 · iii Contents 6.1.31 6.1.32 6.1.33 6.1.34 6.1.35 6.1.36 6.1.37 6.1.38 6.1.39 6.1.40 6.1.41 6.1.42 6.1.43 6.1.44 6.1.45 6.1.46 6.1.47 6.1.48 6.1.49 6.1.50 6.1.51 6.1.52 6.1.53 6.1.54 6.1.55 6.1.56 6.1.57 6.1.58 6.1.59 6.1.60 6.1.61 6.1.62 6.1.63 6.1.64 6.1.65 6.1.66 6.1.67 6.1.68 6.1.69 6.1.70 6.1.71 6.1.72 6.1.73 iv · Bank 2 RD T3CR2 (Timer 3 Control Register 2).23 Bank 2 RE T3PD (Timer 2 Period Buffer) .23 Bank 2 RF TCC (Timer Clock/Counter).23 Bank 3 R5 URC (UART Control Register) .24 Bank 3 R6 URS (UART Status).24 Bank 3 R7 URRD (UART_RD Data Buffer) .25 Bank 3 R8 URTD (UART_TD Data Buffer) .25 Bank 3 R9 URC1 (UART Status).25 Bank 3 RA SPIS (SPI Status Register) .26 Bank 3 RB SPIC (SPI Control Register) .27 Bank 3 RC SPIR (SPI Read Buffer) .28 Bank 3 RD SPIW (SPI Write Buffer).28 Bank 3 RE EIESH (External Interrupt Edge Select Control Register) .28 Bank 3 RF EIESL (External Interrupt Edge Select Control Register) .28 Bank 4 R7 IOC7 (Port 7 I/O Control Register) .29 Bank 4 R8 IOC8 (Port 8 I/O Control Register) .29 Bank 4 R9 IOC9 (Port 9 I/O Control Register) .29 Bank 4 RA IOCA (Port A I/O Control Register).29 Bank 4 RB IOCB (Port B I/O Control Register).30 Bank 4 RC IOCC (Port C I/O Control Register) .30 Bank 4 RF WKCR (Wake-up Control Register) .30 Bank 5 R7 P7PHCR (Port 7 Pull-High Control Register) .30 Bank 5 R8 P8PHCR (Port 8 Pull-High Control Register) .30 Bank 5 R9 P9PHCR (Port 9 Pull-High Control Register) .31 Bank 5 RA PAPHCR (Port A Pull-High Control Register).31 Bank 5 RB PBPHCR (Port B Pull-High Control Register).31 Bank 5 RC PCPHCR (Port C Pull-High Control Register) .31 Bank 6 R7 P7ODCR (Port 7 Open-Drain Control Register).31 Bank 6 R8 P8ODCR (Port 8 Open-Drain Control Register).32 Bank 6 R9 P9ODCR (Port 9 Open-Drain Control Register).32 Bank 6 RA PAODCR (Port A Open-Drain Control Register) .32 Bank 6 RB PBODCR (Port B Open-Drain Control Register) .32 Bank 6 RC (Port C) .32 Bank 7 R5 I2CCR1 (I2C Status and Control Register 1) .33 Bank 7 R6 I2CCR2 (I2C Status and Control Register 2) .34 Bank 7 R7 I2CSA (I2C Slave Address Register).34 Bank 7 R8 I2CDA (I2C Device Address Register) .35 Bank 7 R9 I2CA (I2C Address Register) .35 Bank 7 RA I2CDB (I2C Data Buffer) .35 Bank 7 RB DACDL (DA Conversion Low Data Buffer).36 Bank 7 RC DACDH (DA Conversion High Data Buffer).36 Bank 7 RD DACC (DA Conversion Control Register) .36 Bank 7 RF I2CCR3 (I2C Control Register 3) .37 Product Specification (V1.0) 04.16.2010 Contents 6.2 TCC/WDT and Prescaler. 37 6.3 I/O Port . 38 6.4 Reset and Wake-up. 40 6.4.1 6.4.2 6.4.3 Reset and Wake-up Function.40 Wake-up and Interrupt Modes Operation Summary .41 Status of T and P of the Status Register .42 6.5 Interrupt . 44 6.6 Analog-to-Digital Converter (ADC) . 46 6.6.1 6.6.2 6.6.3 6.6.4 6.7 SPI (Serial Peripheral Interface). 48 6.7.1 6.7.2 6.7.3 6.7.4 6.7.5 6.8 Registers for SPI Circuit.48 Overview and Features .48 SPI Functional Block Diagrams.50 SPI Signal and Pin Description .51 SPI Mode Timing .53 I2C Function. 54 6.8.2 6.8.2 6.8.3 6.8.4 6.9 Registers for ADC Circuit .46 ADC Data Register.47 A/D Sampling Time.47 A/D Conversion Time .47 7-Bit Slave Address .57 10-Bit Slave Address .58 Master Mode .61 Slave Mode .61 Timer/Counter 1. 61 6.9.1 6.9.2 6.9.3 6.9.4 Timer Mode .62 T1OUT Mode.62 Capture Mode.63 PWM Mode.63 6.10 Timer 2 . 64 6.10.1 Timer Mode .65 6.10.2 PWM Mode.65 6.11 Timer 3 . 66 6.11.1 Timer Mode .67 6.11.2 T3OUT Mode.67 6.12 Universal Asynchronous Receiver Transmitter (UART) . 67 6.12.1 6.12.2 6.12.3 6.12.4 6.12.5 UART MODE: .69 Transmitting.69 Receiving.69 Baud Rate Generator .70 UART Timing .70 6.13 DA Conversion . 71 6.14 Registers Initialized Values after Reset . 72 Product Specification (V1.0) 04.16.2010 ·v Contents 6.15 Oscillator . 82 6.15.1 6.15.2 6.15.3 6.15.4 Oscillator Modes.82 Crystal Oscillator/Ceramic Resonators (Crystal).82 External RC Oscillator Mode.83 Internal RC Oscillator Mode .84 6.16 Power-On Considerations . 86 6.16.1 External Power-on Reset Circuit .86 6.16.2 Residue-Voltage Protection.87 6.17 Code Option . 87 6.17.1 Code Option Register (Word 0).88 6.17.2 Code Option Register (Word 1).89 6.17.3 Code Option Register (Word 2).90 6.18 Instruction Set . 90 7 Absolute Maximum Ratings. 92 8 Electrical Characteristics. 93 8.1 8.2 9 DC Electrical Characteristic. 93 AC Electrical Characteristic. 94 Timing Diagrams . 94 APPENDIX A Package Type. 96 Specification Revision History Doc. Version 1.0 vi · Revision Description Initial Offical Release Version Date 2010/04/16 Product Specification (V1.0) 04.16.2010 EM78P507N EM78P507N 8-Bit Microcontroller 1 General Description The EM78P507N EM78P507N is an 8-bit microprocessors designed and developed with low-power and high-speed CMOS technology. Integrated onto a single IC are on-chip Watchdog Timer (WDT), RAM, ROM, programmable real time clock counter (TCC), internal/external interrupt, power down mode, four 8-bit timers, SPI, I2C, UART, Current type DA Converter,10 bits/24 channels AD , LVD, and tri-state I/O. It is equipped with a 6K×13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). With its enhanced OTP-ROM features, the EM78P507N EM78P507N provides a convenient way of developing and verifying user's programs. Moreover, this OTP-ROM device offers the advantages of easy and effective program updates, using development and programming tools. Users can avail of the ELAN Writer to easily program their development codes. 2 Features CPU Configuration · 6K×13 bits on-chip ROM · 272×8 bits on-chip registers · 8-level stacks for subroutine nesting · Dual clock operation mode · Four operation modes: Normal, Green, Idle, & Sleep · Two programmable Level Voltage Detector (LVD): 2.3V, 3.0V · Power-on reset Level Voltage: 1.9 reset level, 2.0 release · Less than 2.0 mA at 3.3V / 4 MHz · Typically 15 A, at 3V / 32kHz · Typically 2 A, during Sleep mode I/O Port Configuration · 6 bidirectional I/O ports: P7, P8, P9, PA, PB and PC · 45 I/O pins & 1I pin · 45 programmable pull-high I/O pins · 39 programmable open-drain I/O pins · External interrupt with Wake-up : P74~P77, P82~P83, PB0~PB3 Operating Voltage · 2.2V~3.6V at -40°C~85°C (Industrial) Operating Frequency · Crystal/IRC/ERC oscillation circuit selected by code option for system clock · IRC oscillation circuit selected by code option or register Main Clock Crystal Mode: DC~20 MHz/2clks@3.3V; Special Features · Programmable free running watchdog timer · High ESD immunity · Power saving Sleep mode · Selectable Oscillation mode Peripheral Configuration · One clock output pin can output the currently working frequency · 8-bit real time clock/counter (TCC) · 24-channel Analog-to-Digital Converter (ADC) with 12-bit resolution in Vref mode · Three 8-bit timers · 8-bit Timer 1, auto reload counter/timer which can be an interrupt source. Function modes: Timer, Toggle output, UART baud rate generator, Capture, & PWM · 8-bit Timer 2, auto reload timer which can be an interrupt source. Function modes: Timer, SPI baud rate generator, & PWM · Two sets of 8 bits auto reload counter/timer which can be cascaded to one 16-bit counter/timer · 8-bit Timer 3 with external clock source, can generate a 50% duty pulse output from T3OUT Pin. · Universal Asynchronous Receiver/Transmitter (UART) available (operates at 16 MHz/2Mbps, 2.2V) · I2C-bus function, including 7-bit/10-bit address 8-bit data transmit/ receive mode and 16 bytes buffer to save the data. · Serial Peripheral Interface (SPI) · Digital-to-Analog Converter (DAC) current type with 10-bit resolution DC~100ns inst. cycle @ 3.3V; Single instruction cycle commands DC~16 MHz/2 clks @ 2.2V; DC~250ns inst. cycle @ 2.2V 22 available interrupts: 10 external, 12 internal · TCC overflow interrupt · Ten external interrupts (wake-up from sleep mode) · Three timer interrupts · A/D converter interrupt · SPI interrupt · Two I2C interrupts · Three UART interrupts · Low voltage detect (LVD) ERC mode: IRC mode: DC~16 MHz/2 clks @ 2.2V ; DC~400ns inst. cycle @ 2.2V Sub Clock: IRC mode : 16kHz Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) ·1 EM78P507N EM78P507N 8-Bit Microcontroller Package Type: · 44 pin QFP/LQFP 10×10mm: EM78P507NQ/LQ44J/S EM78P507NQ/LQ44J/S · 48 pin LQFP 7×7mm: EM78P507NL48J/S EM78P507NL48J/S 3 NOTE These are Green products which do NOT contain hazardous substances. Pin Assignment Figure 3-1a EM78P507N EM78P507N 44-pin QFP/LQFP Package 2· Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) P95/AD21 P95/AD21 P94/AD22 P94/AD22 P93/AD0 P93/AD0 P92/AD1 P92/AD1 P91/AD2/CLKOUT P91/AD2/CLKOUT P90/AD3/PWM2 P90/AD3/PWM2 P87/AD4 P87/AD4 P86/AD5 P86/AD5 P85/AD6 P85/AD6 P84/VREF P84/VREF P83/INT9/AD7 P83/INT9/AD7 P82/INT8/AD8 P82/INT8/AD8 PB2/INT6/AD11 PB2/INT6/AD11 PB3/INT7/AD12 PB3/INT7/AD12 P70/AD13 P70/AD13 P71/AD14 P71/AD14 P72/AD15/DACO P72/AD15/DACO P73/AD16 P73/AD16 PB4/RX PB5/TX PB6 PB7 PC4 PC5 8-Bit Microcontroller EM78P507N EM78P507N Figure 3-1b EM78P507N EM78P507N 48-pin LQFP Package ·3 EM78P507N EM78P507N 8-Bit Microcontroller 4 Pin Description 4.2 EM78P507N EM78P507N LQFP/QFP 44 pins Symbol Pin No. Type Function OSCI 6 I Crystal type: Crystal input terminal or external clock input pin RC type: RC oscillator input pin O Crystal type: Output terminal for crystal oscillator or external clock input pin RC type: Clock output with a period of 1 instruction cycle time External clock signal input I/O P70~P77 are bidirectional I/O pins P70 can be used as AD13 P71 can be used as AD14 P72 can be used as AD15, DACO P73 can be used as AD16 P74 can be used as INT0 P75 can be used as INT1, T1OUT, and PWM1 P76 can be used as INT2 and T1CK P77 can be used as INT3 and T1CAP I/O P80, P82~P87are bidirectional I/O pins P81 only act as input pin P80 can be used as T3CLK P81 can be used as /RESET P82 can be used as INT8 and AD8 P83 can be used as INT9 and AD7 P84 can be used as Vref P85 can be used as AD6 P86 can be used as AD5 P87 can be used as AD4 I/O P90~P97are bidirectional I/O pins P90 can be used as AD3 and PWM2 P91 can be used as AD2 and CLKOUT P92 can be used as AD1 P93 can be used as AD0 P94 can be used as AD22 P95 can be used as AD21 P96 can be used as AD20 P97 can be used as AD19 OSCO P70 ~ P77 P80 ~ P87 P90 ~ P97 4· 7 39~42 1~4 9, 12 ~ 18 19 ~ 26 Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller (Continuation) Symbol PA0 ~ PA7 PB0 ~ PB5 PC0 ~ PC3 Pin No. 27 ~ 34 35 ~ 38 43 ~ 44 7~6 10 ~ 11 Type Function I/O PA0~PA7are bidirectional I/O pins PA0 can be used as AD18 PA1 can be used as AD17 PA2 can be used as SCL PA3 can be used as SDA PA4 can be used as SI PA5 can be used as SO PA6 can be used as SCK PA7 can be used as /SS I/O PB0~PB5are bidirectional I/O pins PB0 can be used as INT4 and AD9 PB1 can be used as INT5 and AD10 PB2 can be used as INT6 and AD11 PB3 can be used as INT7 and AD12 PB4 can be used as RX PB5 can be used as TX I/O PC0~PC3 are bidirectional I/O pins PC0 can be used as OSCO PC1 can be used as OSCI PC2 can be used as T3OUT PC3 can be used as AD23 /RESET 12 I If it remains at logic low, the device will be reset. Wakes-up from Sleep mode when pins status changes. Voltage on /RESET must not be over VDD during Normal mode. VDD 5 - Power supply for IC emulation. Can be adjusted as per customer requirement. VSS 6 - Ground Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) ·5 EM78P507N EM78P507N 8-Bit Microcontroller 4.1 EM78P507N EM78P507N LQFP 48 Pins Symbol Pin No. Type OSCI 6 I Crystal type: Crystal input terminal or external clock input pin RC type: RC oscillator input pin O Crystal type: Output terminal for crystal oscillator or external clock input pin RC type: Clock output with a period of 1 instruction cycle time External clock signal input I/O P70~P77 are bidirectional I/O pins P70 can be used as AD13 P71 can be used as AD14 P72 can be used as AD15, DACO P73 can be used as AD16 P74 can be used as INT0 P75 can be used as INT1, T1OUT, and PWM1 P76 can be used as INT2 and T1CK P77 can be used as INT3 and T1CAP I/O P80, P82~P87are bidirectional I/O pins P81 only act as intupt pin P80 can be used as T3CLK P81 can be used as /RESET P82 can be used as INT8 and AD8 P83 can be used as INT9 and AD7 P84 can be used as Vref P85 can be used as AD6 P86 can be used as AD5 P87 can be used as AD4 I/O P90~P97are bidirectional I/O pins P90 can be used as AD3 and PWM2 P91 can be used as AD2 and CLKOUT P92 can be used as AD1 P93 can be used as AD0 P94 can be used as AD22 P95 can be used as AD21 P96 can be used as AD20 P97 can be used as AD19 OSCO P70 ~ P77 P80 ~ P87 P90 ~ P97 6· 7 39~42 1~4 9 12 ~ 18 19 ~ 26 Function Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller (Continuation) Symbol PA0 ~ PA7 PB0 ~ PB7 PC0 ~ PC5 Pin No. 27 ~ 34 35 ~ 38 43 ~ 46 7~6 10 ~ 11 47 ~ 48 Type Function I/O PA0~PA7are bidirectional I/O pins PA0 can be used as AD18 PA1 can be used as AD17 PA2 can be used as SCL PA3 can be used as SDA PA4 can be used as SI PA5 can be used as SO PA6 can be used as SCK PA7 can be used as /SS I/O PB0~PB7are bidirectional I/O pins PB0 can be used as INT4 and AD9 PB1 can be used as INT5 and AD10 PB2 can be used as INT6 and AD11 PB3 can be used as INT7 and AD12 PB4 can be used as RX PB5 can be used as TX I/O PC0~PC5 are bidirectional I/O pins PC0 can be used as OSCO PC1 can be used as OSCI PC2 can be used as T3OUT PC3 can be used as AD23 /RESET 12 I If it remains at logic low, the device will be reset. Wakes-up from Sleep mode when pin status changes Voltage on /RESET must not be over VDD during Normal mode VDD 5 - Power supply for IC emulation. Can be adjusted as per customer requirement. VSS 8 - Ground Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) ·7 EM78P507N EM78P507N 8-Bit Microcontroller 5 Block Diagram Figure 5-1 EM78P507N EM78P507N Functional Block Diagram 8· Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller 6 Function Description 6.1 Operational Registers 6.1.1 R0 (Indirect Addressing Register) R0 is not a physically implemented register. It is used as an indirect addressing pointer. Any instruction using R0 as a pointer actually accesses data pointed by the RAM Select Register (R4). 6.1.2 R1 (ROM Page and RAM Bank Select Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - PS2 PS1 PS0 0 BS2 BS1 BS0 Bit 7: Not used bits, fixed to "0" all the time. Bits 6~4 (PS2~PS0): Page Select Registers used to select Pages 0~15. These are read only. Bit 3: Not used bits, fixed to "0" all the time. Bits 2~0 (BS2~BS0): RAM Bank Select Registers used to select Banks 0~7 for R20~R3F or Banks 0~7 for control register. 6.1.3 R2 (Program Counter) and Stack R2 and hardware stacks are 10-bit wide. The structure is depicted in Figure 6-1. Generates 6K×13 bits on-chip ROM addresses to the relative programming instruction codes. One program page is 1024 words long. The contents of R2 are set to all "0"s upon a RESET condition. "JMP" instruction allows the direct loading of the lower 10 program counter bits. Thus, "JMP" allows PC to jump to any location within a page. "CALL" instruction loads the lower 10 bits of the PC, and then PC+1 is pushed onto the stack. Thus, the subroutine entry address can be located anywhere within a page. "LJMP" instruction allows direct loading of the lower 12 program counter bits. Therefore, "LJMP" allows PC to jump to any location within 6K (212). "LCALL" instruction loads the lower 12 bits of the PC, and then PC+1 is pushed onto the stack. Thus, the subroutine entry address can be located anywhere within 6K (212). "RET" ("RETL k", "RETI") instruction loads the program counter with the contents of the top of stack. Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) ·9 EM78P507N EM78P507N 8-Bit Microcontroller "ADD R2, A" allows a relative address to be added to the current PC, and the ninth and above bits of the PC will increase progressively. "MOV R2, A" allows to load an address from "A" register to the lower 8 bits of the PC, and the ninth and tenth bits (A8~A9) of the PC remain unchanged. Any instruction except "ADD R2,A" that is written to R2 (e.g., "MOV R2, A", "BC R2, 6", etc.) will cause the ninth and the tenth bits (A8~A9) of the PC to remain unchanged. In the case of EM78P507N EM78P507N, the most significant bits (A12~A10) will be loaded with the contents of PS2~PS0 in the status register (R1) upon the execution of a "JMP", "CALL", or any other instruction set which are written to R2. Program Counter Organization Reset Vector A12~A10 A9 ~ A0 000H 003H Interrupt Vector CALL RET RETL RETI 001 PAGE1 0400~07FF 010 PAGE2 0800~0BFF 011 PAGE3 0C00~0FFF 100 PAGE4 1000~13FF 101 PAGE5 1400~17FF Stack Level 1 Stack Level 2 Stack Level 3 Stack Level 4 Stack Level 5 Stack Level 6 Stack Level 7 Stack Level 8 User Memory Space 000 PAGE0 0000~03FF 042H On-chip Program Memory FFFH Figure 6-1 Program Counter Organization 10 · Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller Data Memory Configuration Addr. Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Registers Registers Registers Registers Registers Registers Registers Registers 00 R0 (Indirect Addressing Register, IAR) 01 R1 (ROM Page and RAM Bank Select Register, RPBSR) 02 R2 (Program Counter, PC) 03 R3 (Status Register, SR) 04 R4 (Select Indirect Address Register, RSR) 05 R5 (TBLP) R5 (ADCR1) R5 (T1CR) R5 (URC) Reserve Reserve Reserve R5 (I2CCR1) 06 R6 (TBHP) R6 (ADCR2) R6 (TSR) R6 (URS) Reserve Reserve Reserve R6 (I2CCR2) 07 R7 (Port 7) R7 (ADDL) R7 (T1PD) R7 (URRD) R7 (IOC7) R7 (P7PHCR) R7 (P7ODCR) R7 (I2CSA) 08 R8 (Port 8) R8 (ADDH) R8 (T1TD) R8 (URTD) R8 (IOC8) R8 (P8PHCR) R8 (P8ODCR) R8 (I2CDA) 09 R9 (Port 9) R9 (ADIC1) R9 (T2CR) R9 (URC2) R9 (IOC9) R9 (P9PHCR) R9 (P9ODCR) R9 (I2CA) 0A RA (Port A) RA (ADIC2) RA RA (T2PD) (SPIS) RA (IOCA) RA (PAPHCR) RA PAODCR) RA (I2CDB) 0B RB (Port B) RB (ADIC3) RB (T2TD) RB (SPIC) RB (IOCB) RB (PBPHCR) RB PBODCR) RB (DACDL) 0C RC (SCCR) RC (COCR) RC (T3CR1) RC (SPIR) RC (IOCC) RC (PCPHCR) RC (Port C) RC (DACDH) 0D RD (TWTCR) Reserve RD (T3CR2) RD (SPIW) Reserve Reserve Reserve RD (DACC) 0E RE (IMR) RE (EIMR) RE (T3PD) RE (EIESH) Reserve Reserve Reserve Reserve 0F RF (ISR) RF (EISR) RF (TCC) RF (EIESL) RF (WKCR) Reserve Reserve RF I2CCR3) 10 General Registers (16x8 bits) : 1F 20 : General Registers General Registers General Registers General Registers General Registers General Registers General Registers General Registers 3F (32×8 bits) (32×8 bits) (32×8 bits) (32×8 bits) (32×8 bits) (32×8 bits) (32×8 bits) (32×8 bits) Figure 6-2 Data Memory Configuration Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) · 11 EM78P507N EM78P507N 8-Bit Microcontroller 6.1.4 R3 (Status Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 VDB LVDEN LVDS T P Z DC C Bit 7 (VDB): Voltage Detector. This bit is read only. When VDD pin voltage is lower than Vdet (selected by LVDS), this bit will be cleared. 0: Low voltage is detected 1: Low voltage is not detected or LVD function is disabled. Bit 6 (LVDEN): Voltage Detect Enable bit 0: No action 1: Voltage detect enabled Bit 5 (LVDS): Detect Voltage select bits LVDS 0 2.3V 1 Bit 4 (T): Detect Voltage 3.0V Time-out bit. Set to "1" by the "SLEP" and "WDTC" commands or during power-on and reset to "0" by WDT time-out. This bit is read only. T P Remark WDT wake-up from Sleep mode Event 0 0 - WDT time out (not Sleep mode) 0 1 - /RESET wake-up from Sleep 1 0 - Power up 1 1 - Low pulse on /RESET × × ×: d'on't care Bit 3 (P): Power-down bit. Set to "1" during power-on or by a "WDTC" command and reset to "0" by a "SLEP" command. This bit is read only. Bit 2 (Z): Zero flag. Set to "1" if the result of an arithmetic or logic operation is zero. Bit 1 (DC): Auxiliary carry flag Bit 0 (C): Carry flag 6.1.5 R4 (RAM Select Register) Bits 7 ~ 6: Used to select Bank 0 ~ Bank 3 Bits 5~0: Used to select registers (Address: 00~3F) in indirect addressing mode. See the data memory configuration in Figure 6-2 above for details. 12 · Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller 6.1.6 Bank 0 R5 TBLP (Low Byte of Table Pointer Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RBit 7 RBit 6 RBit 5 RBit 4 RBit 3 RBit 2 RBit 1 RBit 0 Bits 7 ~ 0 (RBit 7 ~ RBit 0): Table Pointer Address Bits 0 ~7 6.1.7 Bank 0 R6 TBHP (High Byte of Table Pointer Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TBSHL 0 0 RBit 12 RBit 11 RBit 10 RBit 9 RBit 8 Bit 7 (TBSHL): Table address high and low bit selection 0: Take the low 8 bits of machine code to the "TBLP" register. 1: Take the high 5 bits of machine code to the "TBHP" register. Bits 4 ~ 0 (RBit 12 ~ RBit 8): Table Pointer Address Bits 12 ~ 8. 6 1.8 Bank 0 R7 ~ RB (Port 7 ~ Port B) R7 ~ RB: These are all I/O registers. 6.1.9 Bank 0 RC SOCR (System Clock Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 IDLE 0 0 CPUS Bits 7~4: Not used bits, fixed to "0" all the time. Bit 3 (IDLE): Idle Mode Enable bit. This bit will determine as to which mode to enter after SLEP instruction. IDLE="0"+SLEP instruction Sleep mode. IDLE="1"+SLEP instruction Idle mode. Bits 2 ~ 1: Not used bits, fixed to "0" all the time. Bit 0 (CPUS) : CPU Oscillator Source select 0: sub-oscillator (Fs) 1: main oscillator (Fosc) When CPUS=0, the CPU oscillator selects the sub-oscillator while the main oscillator is stopped. Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) · 13 EM78P507N EM78P507N 8-Bit Microcontroller CPU Operation Mode Code option HLFS=1 Normal Mode Code option HLFS=0 Fm: oscillation Fs: oscillation wake up Interrupt or wake up CPU: using Fm IDLE="0" + SLEP Sleep Mode CPUS="1" CPUS="0" Fm: stop Fs: stop IDLE="1" + SLEP IDLE="1" + SLEP Green Mode wake up Fm: stop Fs: oscillation IDLE="0" + SLEP CPU: stop RESET Idle Mode Fm: stop Fs: oscillation Interrupt or wake up CPU: using Fs CPU: stop Figure 6-3 CPU Operation Mode 6.1.10 Bank 0 RD TWTCR (TCC and WDT Timer Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 WDTE WPSR2 WPSR1 WPSR0 TCCS TPSR2 TPSR1 TPSR0 Bit 7 (WDTE): Watchdog Timer Enable bit. This control bit is used to enable the watchdog timer. 0: Disable WDT function 1: Enable WDT function Bits 6 ~ 4 (WPSR2 ~ WPSR0): WDT Prescaler bits WPSR2 WPSR0 WDT Rate 0 0 0 1:1 (Default) 0 0 1 1:2 0 1 0 1:4 0 1 1 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 Bit 3 (TCCS): WPSR1 1 1 1:128 TCC Clock Source select bit 0: Fm (main clock) 1: Fs (sub clock) 14 · Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller Bits 2 ~ 0 (TPSR2 ~ TPSR0): TCC Prescaler bits TPSR2 TPSR1 TPSR0 TCC Rate 110 0 0 1:2 (Default) 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 6.1.11 Bank 0 RE IMR (Interrupt Mask Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T1IE LVDIE ADIE SPIE URTIE EXIE9 EXIE8 TCIE NOTE "1" means with interrupt request; "0" means no interrupt occurs. Banks 0 ~ 1-RF can be cleared by instruction but cannot be set. Banks 0 ~ 1-RE are the interrupt mask registers. Reading Banks 0 ~ 1-RF will result to "logic AND" of Banks 0 ~ 1-RE and Banks 0 ~ 1-RF. Bits 7~0 (TCIE ~ T1IE) : Interrupt Enable bit. Enable interrupt source respectively. 0: Disable interrupt 1: Enable interrupt 6.1.12 Bank 0 RF ISR (Interrupt Status Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T1IF LVDIF ADIF SPIIF URTIF EXIF9 EXIF8 TCIF NOTE "1" means with interrupt request; "0" means no interrupt occurs. Bank 0-RF can be cleared by instruction but cannot be set. Bank 0-RE is the interrupt mask register. Reading Bank 0-RF will result to "logic AND" of Bank 0-RE and Bank 0-RF. Bit 7 (T1IF): Timer 1 Interrupt Flag Bit 6 (LVDIF): Low Voltage Detector Interrupt Flag Bit 5 (ADIF): A/D Conversion Complete Interrupt Flag Bits 4 (SPIIF): SPI Transfer Complete Interrupt Flag Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) · 15 EM78P507N EM78P507N 8-Bit Microcontroller Bits 3 (URTIF): UART Transmit Interrupt Flag Bits 2 (EXIF9): External Interrupt 9 Occur Flag Bits 1 (EXIF8): External Interrupt 8 Occur Flag Bits 0 (TCIF): TCC Overflow Interrupt Flag 6.1.13 Bank 1 R5 ADCR1 (A/D Control Register 1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADRUN ADP ADCK1 ADCK0 - - - - Bit 7 (ADRUN): Start AD Conversion 0: Reset on conversion completion by hardware. This bit cannot be reset by software. 1: Start Conversion Bit 6 (ADP): A/D Power Control Bits 5 ~ 4 (ADCK1~ADCK0): AD Conversion Time Select bits ADCK1 ADCK0 Clock Source Max. Operating Frequency (Fc) 0 0 Fc/4 1 MHz 0 1 Fc/16 4 MHz 1 0 Fc/32 8 MHz 1 1 Fc/64 16 MHz Bit 3 ~ Bit0: Not used bits, fixed to "0" all the time. 6.1.14 Bank 1 R6 ADCR2 (A/D Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 ADREF 0 ADIS4 ADIS3 ADIS2 ADIS1 ADIS0 Bit 7: Not used bit, fixed to "0" all the time. Bit 6 (ADREF): A/D Reference Voltage Input select. 0: Internal VDD, P84 is used as I/O 1: External reference pin, P84 is used as reference input pin. Bit 5: 16 · Not used bit, fixed to "0" all the time. Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller Bits 4~0 (ADIS4~ADIS0): A/D Input select bits ADIS4 ADIS3 ADIS2 ADIS1 ADIS0 Analog Input Pin 0 0 0 0 0 AD0 0 0 0 0 1 AD1 0 0 0 1 0 AD2 0 0 0 1 1 AD3 0 0 1 0 0 AD4 0 0 1 0 1 AD5 0 0 1 1 0 AD6 0 0 1 1 1 AD7 0 1 0 0 0 AD8 0 1 0 0 1 AD9 0 1 0 1 0 AD10 0 1 0 1 1 AD11 0 1 1 0 0 AD12 0 1 1 0 1 AD13 0 1 1 1 0 AD14 0 1 1 1 1 AD15 1 0 0 0 0 AD16 1 0 0 0 1 AD17 1 0 0 1 0 AD18 1 0 0 1 1 AD19 1 0 1 0 0 AD20 1 0 1 0 1 AD21 1 0 1 1 0 AD22 1 0 1 1 1 AD23 6.1.15 Bank 1 R7 ADDL (A/D Low 8-Bit Data Buffer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 Bits 7~0 (ADD7~ADD0): AD Low 8-bit Data Buffer 6.1.16 Bank 1 R8 ADDH (A/D High 8-Bit Data Buffer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 ADD11 ADD11 ADD10 ADD10 ADD9 ADD8 Bits 7~4: Not used bits, fixed to "0" all the time Bits 3~0 (ADD11 ADD11~ADD8): AD High 4-bit Data Buffer Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) · 17 EM78P507N EM78P507N 8-Bit Microcontroller 6.1.17 Bank 1 R9 ADIC1 (A/D Input Control Register 1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Bits 7~0 (ADE7~ADE0): AD Input pin enable control. 0: AD acts as I/O pin 1: AD acts as analog input pin 6.1.18 Bank 1 RA ADIC2 (A/D Input Control Register 2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADE15 ADE15 ADE14 ADE14 ADE13 ADE13 ADE12 ADE12 ADE11 ADE11 ADE10 ADE10 ADE9 ADE8 Bits 7~0 (ADE15 ADE15~ADE8): AD Input pin enable control. 0: Act as I/O pin 1: Act as analog input pin 6.1.19 Bank 1 RB ADIC3 (A/D Input Control Register 3) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADE23 ADE23 ADE22 ADE22 ADE21 ADE21 ADE20 ADE20 ADE19 ADE19 ADE18 ADE18 ADE17 ADE17 ADE16 ADE16 Bits 7~0 (ADE23 ADE23~ADE16 ADE16): AD Input pin enable control. 0: Act as I/O pin 1: Act as analog input pin 6.1.20 Bank 1 RC COCR (Clock Output Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 RCM1 RCM0 CLKOE CLKB1 CLKB0 Bits 7~5: Not used bits, fixed to "0" all the time. Bits 4~3 (RCM1~0): IRC Mode select bits RCM1 RCM0 Frequency 0 0 1 MHz 0 1 8 MHz 1 0 16 MHz 1 1 4 MHz Bit 2 (CLKOE): Port 9.1 used as CLK Output Pin 1: No action 0: Enable CLK output 18 · Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller Bits 1~0 (CLKB1~0): Clock Output Rate select bits. CLKB1 CLKB0 CLK Rate 0 0 1:1 0 1 1:2 1 0 1:4 1 1 1:8 6.1.21 Bank 1 RE EIMR (External Interrupt Mask Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXIE7 EXIE6 EXIE5 EXIE4 EXIE3 EXIE2 EXIE1 EXIE0 Bits 7~0 (EXIE7~EXIE0): Interrupt Enable bits. Enable interrupt source respectively. 6.1.22 Bank 1 RF EISR (External Interrupt Status Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXIF7 EXIF6 EXIF5 EXIF4 EXIF3 EXIF2 EXIF1 EXIF0 Bits 7~0 (EXIE7~EXIE0): Interrupt Flag of External Interrupts 0~7 occur 6.1.23 Bank 2 R5 T1CR (Timer 1 Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TIS1 TIS0 T1MS2 T1MS1 T1MS0 T1P2 T1P1 T1P0 Bits 7~6 (T1S1~0): Timer 1 and Timer 2 Interrupt Type select bits. These two bits are used when the Timer operates in PWM mode. TIS1 TIS0 0 0 Timer 1 and Timer 2 Interrupt Type Select TXPD underflow 0 1 TXTD underflow 1 × TXPD and TXTD underflow Bit 5~ (T1MS2~T1MS0): Timer 1 Operation Mode select bits T1MS2 T1MS1 T1MS0 0 0 0 Timer 1 0 0 1 T1OUT mode 0 1 0 Capture Mode Rising Edge 0 1 1 Capture Mode falling Edge 1 0 0 UART Baud Rate Generator 1 0 1 1 1 0 1 1 1 Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) Timer 1 Mode Select PWM1 · 19 EM78P507N EM78P507N 8-Bit Microcontroller Bits 2~0 (T1CSS1~T1CSS0): Timer 1 Clock Source select bits T1P2 T1P1 T1P0 Prescaler 0 0 0 1:2 (Default) 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1:32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 6.1.24 Bank 2 R6 TSR (Timer 1 Status Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T1MOD TRCB T1CSS1 T1CSS0 T2CSS T1EN 0 T1OC Bit 7 (T1MOD): Timer Operating Mode select bit 0: Two 8-bit Timers 1: Timer 1 and Timer 2 cascade to one 16-bit Timer NOTE By setting T1MOD to "1", the Timer can cascade to one 16-bit Timer. This 16-bit Timer is controlled by Timer 1, including enable clock source and prescaler. Timer 1 is MSB and Timer 2 is LSB in period and duty values. Bit 6 (TRCB): Timers 1, 2, & 3 Read Control bit 0: When this bit is set to "0", read data from T1PD, T2PD or T3PD. 1: When this bit is set to "1", read data from T1PD, T2PD or T3PD, but the value is timer counter read value. Bits 5~4 (T1CSS1~0): Timer 1 Clock Source select bits. T1CSS1 T1CSS0 Timer 1 Clock Source Select 0 0 Fm 0 1 Fs 1 × T1CK Bit 3 (T2CSS): Timer 2 Clock Source select bit 0: Main clock with prescaler 1: Sub clock with prescaler Bit 2 (T1EN): Timer 1 Start Bit 0: Timer 1 stop 1: Timer 1 start 20 · Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller Bit 1: Not used bits, fixed to "0" all the time. Bit 0 (T1OC): Timer 1 Output Flip-Flop Control bit 0: T-FF is low 1: T-FF is high 6.1.25 Bank 2 R7 T1PD (Timer 1 Period Buffer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PRD1[7] PRD1[6] PRD1[5] PRD1[4] PRD1[3] PRD1[2] PRD1[1] PRD1[0] Bits 7~0 (PRD1[7]~PRD1[0]): The content of this register is a period of Timer 1. 6.1.26 Bank 2 R8 T1TD (Timer 1 Duty Buffer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TD1[7] TD1[6] TD1[5] TD1[4] TD1[3] TD1[2] TD1[1] TD1[0] Bits 7~0 (TD1[7]~TD1[0]): The content of this register is a period of Timer 1 6.1.27 Bank 2 R9 T2CR (Timer 2 Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T2IF T2IE T2EN T2MS1 T2MS0 T2P2 T2P1 T2P0 Bit 7(T2IF): Interrupt Flag of Timer 2 Interrupt Bit 6(T2IE): Timer 2 Interrupt Mask bit 0: Disable Timer 2 interrupt 1: Enable Timer 2 interrupt Bit 5 (T2EN): Timer 2 Start Bit 0: Timer 2 stop 1: Timer 2 start Bits 4~3 (T2MS1~T2MS0): Timer 2 Operation Mode select bits T2MS1 T2MS0 0 0 Timer 2 0 1 SPI Baud Rate Generator 1 0 1 1 Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) Timer 2 Mode Select PWM2 · 21 EM78P507N EM78P507N 8-Bit Microcontroller Bits 2~0 (T2P2~T2P0): Timer 2 Prescaler bits T2P2 T2P1 T2P0 Prescaler 0 0 0 1:2 (Default) 0 0 1 1:4 0 1 0 1:8 0 1 1 1:16 1 0 0 1 :32 1 0 1 1:64 1 1 0 1:128 1 1 1 1:256 6.1.28 Bank 2 RA T2PD (Timer 2 Period Buffer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PRD2[7] PRD2[6] PRD2[5] PRD2[4] PRD2[3] PRD2[2] PRD2[1] PRD2[0] Bits 7~0 (PRD2[7] ~ PRD2[0]): The content of this register is a period of Timer 2. 6.1.29 Bank 2 RB T2TD (Timer 2 Duty Buffer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TD2[7] TD2[6] TD2[5] TD2[4] TD2[3] TD2[2] TD2[1] TD2[0] Bits 7~0 (TD2[7] ~ TD2[0]): The content of this register is a duty of Timer 2. 6.1.30 Bank 2 RC T3CR1 (Timer 3 Control Register 1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T3IF T3IE T3EN T3CSS1 T3CSS0 T3P2 T3P1 T3P0 Bit 7 (T3IF): Interrupt Flag of Timer 3 Interrupt Bit 6 (T3IE): Timer 3 Interrupt Mask bit 0: Disable Timer 3 interrupt 1: Enable Timer 3 interrupt Bit 5 (T3EN): Timer 3 Start Bit 0: Timer 3 stop 1: Timer 3 start Bits 4~3 (T3CSS1~T3CSS0): Timer 3 Clock Source selects bits T3CSS1 Timer 3 Clock Source Select 0 0 Fm 0 1 Fs 1 22 · T3CSS0 × T3CK Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller Bits 2~0 (T3P2~T3P0): Timer 3 Pre-scaler Bits T3P2 T3P1 T3P0 Prescaler 0 0 0 1:2 (Default) 0 0 1 1:4 0 1 0 1:8 0 1 1 1 : 16 1 0 0 1 : 32 1 0 1 1 : 64 1 1 0 1 : 128 1 1 1 1 : 256 6.1.31 Bank 2 RD T3CR2 (Timer 3 Control Register 2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 T3MS1 T3MS0 Bits 7~2: Not used bits, fixed to "0" all the time. Bits 1~0 (T3MS1~T3MS0): Timer 3 Operation Mode select bits T3MS1 T3MS0 Timer 3 Mode Select 0 0 Timer 3 0 1 T3OUT Mode 1 0 Reserved 1 1 Reserved 6.1.32 Bank 2 RE T3PD (Timer 2 Period Buffer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PRD2[7] PRD2[6] PRD2[5] PRD2[4] PRD2[3] PRD2[2] PRD2[1] PRD2[0] Bits 7~0 (PRD2[7] ~ PRD2[0]): The content of this register is a period of Timer 2 6.1.33 Bank 2 RF TCC (Timer Clock/Counter) Increased by the main oscillator clock (Fm), or sub oscillator clock (Fs). Controlled by TWTCR register. Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) · 23 EM78P507N EM78P507N 8-Bit Microcontroller 6.1.34 Bank 3 R5 URC (UART Control Register) Bit 7 URTD8 Bit 6 Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 BRATE2 UMODE1 UMODE0 Bit 3 BRATE1 BRATE0 UTBE TXE Bit 7 (URTD8): Transmission Data Bit 8 Bits 6~5 (UMODE1~UMODE0): UART Transmission Mode select bits. UMODE1 UMODE0 UART Mode 0 0 Mode 1 : 7 bits 0 1 Mode 2 : 8 bits 1 0 Mode 3 : 9 bits 1 1 Reserved Bits 4~2 (BRATE2~BRATE0): Transmit Baud Rate select (Tuart = Fc/16) BRATE2 BRATE1 RRATE0 Baud Rate e.g. Fc = 8 MHz 0 0 0 Tuart/13 38400 0 0 1 Tuart/26 19200 0 1 0 Tuart/52 9600 0 1 1 Tuart/104 4800 1 0 0 Tuart/208 2400 1 0 1 Tuart/416 1200 1 1 0 Timer 1 1 1 1 2M Bit 1 (UTBE): UART transfer buffer empty flag. Set to "1" when transfer buffer is empty. Reset to "0" automatically when in URTD register. The UTBE bit should be cleared by hardware when transmission is enabled. The UTBE bit is read-only. Therefore, writing to the URTD register is necessary when you want to start transmit shifting. Bit 0 (TXE): Enable transmission 0: Disable transmission 1: Enable transmission 6.1.35 Bank 3 R6 URS (UART Status) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 URRD8 EVEN PRE PRERR OVERR FMERR URBF RXE Bit 7(URRD8): Receive Data Bit 8 Bit 6 (EVEN): Select Parity Check 0: Odd parity 1: EVEN parity 24 · Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller Bits 5 (PRE): Enable Parity Addition 0: Disable 1: Enable Bit 4 (PRERR): Parity Error Flag Set to "1" when parity error occurs and clear to "0" by software. Bit 3 (OVERR): Overrun Error flag Set to "1" when overrun error occurs and clear to "0" by software. Bit 2 (FMERR): Framing Error Flag. Set to "1" when framing error occurs and clear to "0" by software. Bit 1 (URBF): UART Read Buffer Full Flag Set to "1" when one character is received. Resets to "0" automatically when read from URS register. URBF will be cleared by hardware when Receive is enabled, and that URBF bit is read-only. Therefore, read URS register is necessary to avoid overrun error. Bit 0 (RXE): Enable Receive 0: Disable Receive 1: Enable Receive 6.1.36 Bank 3 R7 URRD (UART_RD Data Buffer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 URRD7 URRD6 URRD5 URRD4 URRD3 URRD2 URRD1 URRD0 Bits 7~0 (URRD7~URRD0): UART Receive Data Buffer. Read only. 6.1.37 Bank 3 R8 URTD (UART_TD Data Buffer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 URTD7 URTD6 URTD5 URTD4 URTD3 URTD2 URTD1 URTD0 Bits 7~0 (URTD7~URTD0): UART Transmit Data Buffer. Write only. 6.1.38 Bank 3 R9 URC1 (UART Status) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 UARTE 0 UINVEN 0 0 URRIF Bits 7~6: Not used bits, fixed to "0" all the time. Bit 5 (UARTE): UART Function Enable. 0: UART function disabled, PB4, PB5 act as general I/O. 1: UART function enabled, PB4, PB5 act as UART Rx & Tx pins respectively. Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) · 25 EM78P507N EM78P507N 8-Bit Microcontroller Bit 4: Not used bit, fixed to "0" all the time. Bit 3 (UINVEN): Enable UART Tx and Rx Port Inverse Output 0: Disable Tx and Rx port inverse output. 1: Enable Tx and Rx port inverse output. Bits 2~1: Not used bits, fixed to "0" all the time. Bit 0 (URRIF): Interrupt flag of UART receive completed. Reset to "0" by software. 6.1.39 Bank 3 RA SPIS (SPI Status Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DORD TD1 TD0 0 OD3 OD4 0 RBF Bit 7 (DORD): Data Shift Control bit 0: Shift left (MSB first) 1: Shift right (LSB first) Bits 5~6 (TD0~TD1): SDO Status Output Delay Times Options TD1 TD0 Delay Time 0 0 8 clk 0 1 16 clk 1 0 24 clk 1 1 32 clk Bit 4: Not used bit, fixed to "0" all the time. Bit 3 (OD3): Open-drain Control bit 0: Open-drain disabled for SDO 1: Open-drain enabled for SDO Bit 2 (OD4): Open-Drain Control bit 0: Open-drain disabled for SCK 1: Open-drain enabled for SCK Bit 1: Not used bit, fixed to "0" all the time. Bit 0 (RBF): Read Buffer Full Flag 0: Receive is not completed and SPIR has not fully exchanged data 1: Receive is completed and SPIR has fully exchanged data. 26 · Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller 6.1.40 Bank 3 RB SPIC (SPI Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CES SPIEN SRO SSE SDOC SBRS2 SBRS1 SBRS0 Bit 7 (CES): Clock Edge Select Bit 0: Data shift out on a rising edge, and shifts in on a falling edge. Data is on hold during low-level. 1: Data shift out on a falling edge, and shifts in on a rising edge. Data is on hold during high-level. Bit 6 (SPIEN): SPI Enable bit 0: Disable SPI mode 1: Enable SPI mode Bit 5 (SRO): SPI Read Overflow bit 0: No overflow 1: A new data is received while the previous data is still being held in the SPIR register. In this situation, the data in SPIS register is destroyed. To avoid setting this bit, you should read the SPIRB register although only transmission is implemented. This can only occur during Slave mode. Bit 4 (SSE): SPI Shift Enable bit 0: Reset as soon as the shift is completed, and the next byte is read to shift. 1: Start to shift, and kept on "1" while the current byte is still being transmitted. Bit 3 (SDOC): SDO Output Status Control Bit 0: After the serial data is output, the SDO remains high. 1: After the serial data is output, the SDO remains low. 1 Bits 2~0 (SBRS2~SBRS0): SPI Baud Rate select bits SBRS2 SBRS1 SBRS0 Mode 0 0 0 Master Fosc/2 0 0 1 Master Fosc/4 0 1 0 Master Fosc/8 0 1 1 Master Fosc/16 1 0 0 Master Fosc/32 1 0 1 Master Timer 2 1 1 0 Slave /SS enable 1 1 1 Slave /SS disable 1 SPI Baud Rate If EM78P507N EM78P507N acts as the Master or Slave device to transmit and receive data, be sure to operate at Baud Rate lower than 3MHz and ensure that the operating voltage is higher than 2.5V. Product Specification (V1.0) 04.16.2010 · 27 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller 6.1.41 Bank 3 RC SPIR (SPI Read Buffer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRB7 SRB6 SRB5 SRB4 SRB3 SRB2 SRB1 SRB0 Bits 7~0 (SRB7 ~ SRB0): SPI Read Data Buffer 6.1.42 Bank 3 RD SPIW (SPI Write Buffer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0 Bits 7~0 (SWB7 ~ SWB0): SPI Read Data Buffer 6.1.43 Bank 3 RE EIESH (External Interrupt Edge Select Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EIES7 EIES6 EIES5 EIES4 EIES3 EIES2 EIES1 EIES0 Bits 7~0 (EIES7 ~ EIES0): External Interrupts 0~7 Edge Select Bit 0: Falling edge interrupt 1: Rising edge interrupt 6.1.44 Bank 3 RF EIESL (External Interrupt Edge Select Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LVDWE I2CWE SPIWE ADWK INTWK9 INTWK8 EIES9 EIES8 Bit 7 (LVDWE): LVD Wake-up Function Enable bit 0: Disable 1: Enable Bit 6 (I2CWE): I2C Receive Wake-up Function Enable bit 0: Disable 1: Enable Bit 5 (SPIWE): SPI Receive Wake-up Function Enable bit 0: Disable 1: Enable Bit 4 (ADWK): AD Converter Wake-up Function Enable bit 0: Disable 1: Enable Bit 3 (INTWK9): External Interrupts 9 Wake-up Function Enable bit 0: Disable 1: Enable 28 · Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller Bit 2 (INTWK8): External Interrupts 8 Wake-up Function Enable Bit 0: Disable 1: Enable Bits 1~0 (EIES9 ~ EIES8): External Interrupts 9~8 Edge Select Bit 0: Falling edge interrupt 1: Rising edge interrupt 6.1.45 Bank 4 R7 IOC7 (Port 7 I/O Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOC77 IOC77 IOC76 IOC76 IOC75 IOC75 IOC74 IOC74 IOC73 IOC73 IOC72 IOC72 IOC71 IOC71 IOC70 IOC70 Bits 7~0 (IOC77 IOC77~IOC70 IOC70): Port 7 8-Bit I/O Direction Control Register 0: Define Port 7 as output port 1: Define Port 7 as input port 6.1.46 Bank 4 R8 IOC8 (Port 8 I/O Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOC87 IOC87 IOC86 IOC86 IOC85 IOC85 IOC84 IOC84 IOC83 IOC83 IOC82 IOC82 IOC81 IOC81 IOC80 IOC80 Bits 7~0 (IOC87 IOC87~IOC80 IOC80): Port 8 8-Bit I/O Direction Control Register. P8.1 only acts as input pin. 0: Define Port 8 as output port 1: Define Port 8 as input port 6.1.47 Bank 4 R9 IOC9 (Port 9 I/O Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOC97 IOC97 IOC96 IOC96 IOC95 IOC95 IOC94 IOC94 IOC93 IOC93 IOC92 IOC92 IOC91 IOC91 IOC90 IOC90 Bits 7~0 (IOC97 IOC97~IOC90 IOC90): Port 9 8-Bit I/O Direction Control Register 0: Define Port 9 as output port 1: Define Port 9 as input port 6.1.48 Bank 4 RA IOCA (Port A I/O Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOCA7 IOCA6 IOCA5 IOCA4 IOCA3 IOCA2 IOCA1 IOCA0 Bits 7~0 (IOCA7~IOCA0): Port A 8-Bit I/O Direction Control Register 0: Define Port A as output port 1: Define Port A as input port Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) · 29 EM78P507N EM78P507N 8-Bit Microcontroller 6.1.49 Bank 4 RB IOCB (Port B I/O Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 IOCB1 IOCB0 Bits 7~0 (IOCB7~IOCB0): Port B 8-Bit I/O Direction Control Register 0: Define Port B as output port 1: Define Port B as input port 6.1.50 Bank 4 RC IOCC (Port C I/O Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 IOCC5 IOCC4 IOCC3 IOCC2 IOCC1 IOCC0 Bits 7~ 6: Not used fixed "0" Bits 5~0 (IOCC5~IOCC0): Port C 6-Bit I/O Direction Control Register 0: Define Port C as output port 1: Define Port C as input port 6.1.51 Bank 4 RF WKCR (Wake-up Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTWK7 INTWK6 INTWK5 INTWK4 INTWK3 INTWK2 INTWK1 INTWK0 Bits 7~ 0 (INTWK7 ~ INTWK0): External Interrupts 7~0 Wake-up Function Enable Bits 0: Disable 1: Enable 6.1.52 Bank 5 R7 P7PHCR (Port 7 Pull-High Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PH77 PH76 PH75 PH67 PH73 PH72 PH71 PH70 Bits 7~0 (PH77~PH70): Port 7 8-bit I/O Pull-high Control Registers 0: Pull-high disabled 1: Pull-high enabled 6.1.53 Bank 5 R8 P8PHCR (Port 8 Pull-High Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PH87 PH86 PH85 PH84 PH83 PH82 0 PH80 Bits 7~0 (PH87~PH80): Port 8 8-bit I/O Pull-high Control Registers 0: Pull-high disable 1: Pull-high enable 30 · Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller 6.1.54 Bank 5 R9 P9PHCR (Port 9 Pull-High Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PH97 PH96 PH95 PH94 PH93 PH92 PH91 PH90 Bits 7~0 (PH97~PH90): Port 9 8-bit I/O Pull-high Control Registers. 0: Pull-high disabled 1: Pull-high enabled 6.1.55 Bank 5 RA PAPHCR (Port A Pull-High Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PHA7 PHA6 PHA5 PHA4 PHA3 PHA2 PHA1 PHA0 Bits 7~0 (PHA7~PHA0): Port A 8-bit I/O Pull-high Control Registers. 0: Pull-high disable 1: Pull-high enable 6.1.56 Bank 5 RB PBPHCR (Port B Pull-High Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PHB7 PHB6 PHB5 PHB4 PHB3 PHB2 PHB1 PHB0 Bits 7~0 (PHB7~PHB0): Port B 8-bit I/O Pull high Control Registers. 0: Pull-high disabled 1: Pull-high enabled 6.1.57 Bank 5 RC PCPHCR (Port C Pull-High Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 PHC5 PHC4 PHC3 PHC2 PHC1 PHC0 Bits 7~0 (PHC7~PHC0): Port C 8-bit I/O Pull-high Control Registers. 0: Pull-high disabled 1: Pull-high enabled 6.1.58 Bank 6 R7 P7ODCR (Port 7 Open-Drain Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OD77 OD76 OD75 OD74 OD73 OD72 OD71 OD70 Bits 7~0 (OD77~OD70) : Port 7 8-bit I/O Open-drain Control Registers. 0: Open Drain disable 1: Open Drain enable Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) · 31 EM78P507N EM78P507N 8-Bit Microcontroller 6.1.59 Bank 6 R8 P8ODCR (Port 8 Open-Drain Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OD87 OD86 OD85 OD84 OD83 OD82 0 OD80 Bits 7~0 (OD87~OD80): Port 8 8-bit I/O Open Drain Control Registers 0: Open Drain disabled 1: Open Drain enabled 6.1.60 Bank 6 R9 P9ODCR (Port 9 Open-Drain Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OD97 OD96 OD95 OD94 OD93 OD92 OD91 OD90 Bits 7~0 (OD97~OD90): Port 9 8-bit I/O Open-drain Control Registers 0: Open-drain disabled 1: Open-drain enabled 6.1.61 Bank 6 RA PAODCR (Port A Open-Drain Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 ODA0 Bits 7~0 (ODA7~ODA0) : PortA 8-bits I/O Open-drain Control Registers. 0: Open-drain disabled 1: Open-drain enabled 6.1.62 Bank 6 RB PBODCR (Port B Open-Drain Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ODB7 ODB6 ODB5 ODB4 ODB3 ODB2 ODB1 ODB0 Bits 7~0 (ODB7~ODB0): Port B 8-bit I/O Open-drain Control Registers. 0: Open-drain disable 1: Open-drain enable 6.1.63 Bank 6 RC (Port C) RC is an I/O register 32 · Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller 6.1.64 Bank 7 R5 I2CCR1 (I2C Status and Control Register 1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Strobe/Pend IMS ISS STOP SAR_EMPTY ACK FULL EMPTY Bit 7 (Strobe/Pend): In Master mode, it is used as strobe signal to control the I2C circuit to send SCL clock. Resets automatically after receiving or transmitting handshake signal (ACK or nACK). In Slave mode, it is used as pending signal. You should clear it after writing data into the Tx buffer or reading data from Rx buffer to inform Slave I2C circuit to release the SCL signal. Bit 6 (IMS): I2C Master/Slave mode select bit. 0: Slave 1: Master Bit 5 (ISS): I2C Fast/Standard mode select bit. 0: Standard mode (100K bit/s) 1: Fast mode (400K bit/s) Bit 4 (STOP): In Master mode, if STOP=1 and R/nW=1, then EM78P507N EM78P507N must return a nACK signal to the Slave device before sending a STOP signal. If STOP=1 and R/nW=0 then EM78P507N EM78P507N sends a STOP signal after receiving an ACK signal. Resets when the EM78P507N EM78P507N sends a STOP signal to the Slave device. In Slave mode, if STOP=1 and R/nW=0 then the EM78P507N EM78P507N must return a nACK signal to the master device. Bit 3 (SAR_EMPTY): Set when the EM78P507N EM78P507N transmits a 1-byte data from the I2C Slave Address Register and receive an ACK (or nACK) signal. Reset when the MCU writes a 1-byte data to the I2C Slave Address Register. Bit 2 (ACK): The ACK condition bit is set to "1" by hardware when the device responds with an acknowledge (ACK). Resets when the device responds with a not- acknowledge (nACK) signal. Bit 1 (FULL): Set by hardware when I2C Receive Buffer Register is full. Reset by hardware when the MCU reads data from I2C Receive Buffer Register. Bit 0 (EMPTY): Set by hardware when the I2C Transmit Buffer Register is empty and receives an ACK (or nACK) signal. Reset by hardware when the MCU writes new data to the I2C Transmit Buffer Register. Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) · 33 EM78P507N EM78P507N 8-Bit Microcontroller 6.1.65 Bank 7 R6 I2CCR2 (I2C Status and Control Register 2) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 I2CRIF I2CRIE I2CTIF I2CTIE I2CTS1 I2CTS0 I2CCS I2CEN Bit 7 (I2CRIF): I2C Receive Interrupt Flag. Set when the I2C receives a 1 byte data and responds with an ACK signal. Reset by firmware or I2C disabled. Bits 6 (I2CRIE): I2C Interface Receive Interrupt Enable bit 0: Disable Interrupt 1: Enable Interrupt Bit 5 (I2CTIF): I2C Transmit Interrupt Flag. Set when I2C transmits 1 byte data and responds with an ACK signal. Reset by firmware or I2C disabled. Bits 4 (I2CTIE): I2C Interface Tx Interrupt Enable bit 0: Disable Interrupt 1: Enable Interrupt Bits 3~2 (I2CTS1~I2CTS0): I2C Transmit Clock Source Select bits (When I2CCS=0). I2C source must be low 6 MHz. I2CTS1 Source Max. Operating Fm(MHz) 0 0 Fm/1 4 0 1 Fm/2 8 1 Bit 1 (I2CCS): I2CTS0 × Fm/4 16 I2C Clock Source Select Bit 0: Fm (main clock) 1: Fs (sub clock) Bit 0 (I2CEN): I2C Enable bit 0: Disable I2C mode 1: Enable I2C mode 6.1.66 Bank 7 R7 I2CSA (I2C Slave Address Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SA6 SA5 SA4 SA3 SA2 SA1 SA0 IRW Bits 7~1 (SA6~SA0): When EM78P507N EM78P507N functions as Master device for I2C application, these bits are used as the Slave device address registers. Bit 0 (IRW): When EM78P507N EM78P507N functions as Master device for I2C application, this bit is used as Read/Write transaction control bit. 0: Write 1: Read 34 · Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller 6.1.67 Bank 7 R8 I2CDA (I2C Device Address Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 Bits 7~0 (DA7~DA0): When the EM78P507N EM78P507N is used as a Slave device for I2C application, these bits store the registers address of EM78P507N EM78P507N. The address register is used to identify the data on the I2C bus to extract the message delivered to the EM78P507N EM78P507N. 6.1.68 Bank 7 R9 I2CA (I2C Address Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 IBFULL AMB IBEN I2CSPE I2CSPF DA9 DA8 Bit 7: Not used, fixed to "0" all the time. Bit 6 (IBFULL): Set by hardware when the I2C 16-byte buffer is full. Reset by software when the MCU reads data from the I2C 16-byte buffer. Bit 5 (AMB): Don't care MSB bit of Slave address. If this bit (in 7-bit and 10-bit Address mode) is enabled and the two Slave devices have the same address, i.e., Bit 1 ~ Bit 6 or Bit 1~ Bit 9 (excluding MSB); the data will be received by the two Slave devices. 0: Disable AMB bit 1: Enable AMB bit Bit 4 (IBEN): I2C 16 bytes Buffer Enable bit. The EM78P507N EM78P507N I2C has a 16-byte buffer which is distributed in Bank 7 0x30 ~ 0x3F to save the received data. If this bit is disabled, the buffer will be a general purpose RAM 0: Disable the I2C Buffer 1: Enable the I2C Buffer Bit 3 (I2CSPE): I2C Interface Stop Interrupt Enable bit Bit 2 (I2CSPF): I2C Interface Interrupt Stop Flag. Set after the EM78P507N EM78P507N acting as Slave device, has received the STOP signal from the Master device and the I2CSPE bit has been enabled. Reset by software. Bits 1~0 (DA9~8): Device Address bits 6.1.69 Bank 7 RA I2CDB (I2C Data Buffer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Bits 7~0 (DB7~ DB0): I2C Receive/Transmit Data Buffer Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) · 35 EM78P507N EM78P507N 8-Bit Microcontroller 6.1.70 Bank 7 RB DACDL (DA Conversion Low Data Buffer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DACD7 DACD6 DACD5 DACD4 DACD3 DACD2 DACD1 DACD0 Bits 7~0 (DACD7 ~ DACD0): DA Conversion Low Data Buffer 6.1.71 Bank 7 RC DACDH (DA Conversion High Data Buffer) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 DACD9 DACD8 Bits 7~2: Not used, fixed to "0" all the time. Bits 1~0 (DACD9 ~ DACD8): DA Convert high Data Buffer 6.1.72 Bank 7 RD DACC (DA Conversion Control Register) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DARUN 0 0 SEMCL COF[3] COF[2] COF[1] COF[0] Bit 7 (DARUN): DA Conversion Start. Bits 6~5: Not used, fixed to "0" all the time. Bit 4 (SEMCL): Set the maximum output current 0: Output maximum current set at 3mA 1: Output maximum current set at 4mA Bits 3~0 (COF[3]~COF[0]): Control output maximum current levels: COF[3] COF[1] COF[0] DA Max Level (Ic = 3mA) 0 0 0 0 Ic/16 0 0 0 1 Ic/15 0 0 1 0 Ic/14 0 0 1 1 Ic/13 0 1 0 0 Ic/12 0 1 0 1 Ic/11 0 1 1 0 Ic/10 0 1 1 1 Ic/9 1 0 0 0 Ic/8 1 0 0 1 Ic/7 1 0 1 0 Ic/6 1 0 1 1 Ic/5 1 1 0 0 Ic/4 1 1 0 1 Ic/3 1 1 1 0 Ic/2 1 36 · COF[2] 1 1 1 Ic/1 Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller 6.1.73 Bank 7 RF I2CCR3 (I2C Control Register 3) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 GCEN I2CBF Bits 7~2: Not used, fixed to "0" all the time. Bit 1 (GCEN): I2C General Call Function Enable bit. If this bit is enabled and the Master device transmitted "0000000", the connected Slave device will respond with an acknowledgment. 0: Disable 1: Enable Bit 0 (I2CBF): I2C Busy Flag. If the Slave receives the address from the Master, this flag will be set. The flag is cleared after Slave receives the STOP signal from Master or I2C Slave address does not match. 0: I2C does not operate 1: I2C is in operation 6.2 TCC/WDT and Prescaler R_BANK Addr. Name Bank 0 Bit 7 Bit 6 Bit 5 Bit 4 0X0D TWTCR WDTE WPSR2 WPSR1 WPSR0 Bit 3 Bit 2 Bit 1 Bit 0 TCCS TPSR2 TPSR1 TPSR0 R/W 0x0E IMR ISR R/W R/W R/W R/W TCC[7] TCC[6] TCC[5] TCC[4] TCC[3] TCC[2] TCC[1] TCC[0] R/W R/W R/W R/W R/W R/W R/W T1IE LVDIE ADIE SPIIE URTIE EXIE9 EXIE8 TCIE R/W R/W R/W R/W R/W R/W R/W T1IF LVDIF ADIF SPIIF URTIF EXIF9 EXIF8 TCIF R/W Bank 0 0x0E TCC R/W R/W Bank 0 0X0F R/W R/W Bank 2 R/W R/W R/W R/W R/W R/W R/W R/W There are two 8-bit counters available as prescalers for the TCC and WDT respectively. The PST0~PST2 bits of the Bank 0 RD TWTCR register are used to determine the ratio of the TCC prescaler, and the PWR0~PWR2 bits of the Bank 0 RD register are used to determine the prescaler of WDT. The prescaler counter is cleared by instruction each time they are written into TCC. The WDT and prescaler are cleared by the "WDTC" and "SLEP" instructions. The following Figure 6-4 depicts the circuit diagram of TCC/WDT. Bank 2 RF (TCC) is an 8-bit timer/counter. The TCC clock source can be internal clock or external signal input (edge selectable from the TCC pin). If the TCC signal source is from an internal clock, the TCC will be incremented by 1 at every oscillator cycle (without prescaler). If the TCC signal source is from an external clock input, the TCC will be incremented by 1 at every falling edge or rising edge of the TCC pin. The TCC pin input time length (kept in high or low level) must be greater than 1CLK. Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) · 37 EM78P507N EM78P507N 8-Bit Microcontroller The watchdog timer is a free running on-chip RC oscillator. The WDT will keep running even if the oscillator driver has been turned off (i.e., in Sleep mode). During normal operation or Sleep mode, a WDT time-out (if enabled) will cause the device to reset. The WDT can be enabled or disabled any time during Normal mode through software programming. Refer to the WDTE bit of the TWTCR register in the above table. With no presacler, the WDT time-out period is approximately 18 ms 2 . T C C S (T C C C R) Fm Fs 0 1 MUX TC C P in 8-bit C ounter D ata B us 8 to 1 M U X 0 TC C MUX 1 TE (TC C C R) P rescaler TS (TC C C R) T C C overflow interrupt PSTE P S T2~0 (T C C C R ) (T C C C R ) WDT 8-bit C ounter 8 to 1 M U X P rescaler W D T Tim e out W D TE (W D T C R) PSW E P S W 2~0 (W D TC R ) (W D TC R ) Figure 6-4 TCC and WDT Block Diagram 6.3 I/O Port Port 7, Port 8, Port 9, Port A, Port B, and Port C the I/O registers are bidirectional tri-state I/O ports. The function of Pull-high and Open-drain can be set internally by Bank 5 R7, R8, R9, RA, RB, and RC, Bank 6 R7, R8, R9, RA, and RB respectively. Port 7 [4:7], Port 8 [2:3], and Port B [0:3] feature an input status (Rising or Falling edge) changed interrupt (or wake-up) function. Each I/O pin can be defined as "input" or "output" pin by the I/O control register (Bank 4 R7~RD IOC7~IOCC). P81 cannot be defined as pull-high and open drain. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuits for Port 7, Port 8, Port 9, Port A, and Port C are illustrated in the following figures. 2 Vdd = 3V, set up time period = 18ms ± 30% 38 · Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller PCRD Q P R D _ Q C L Q PORT CLK P R PCWR IOD D _ CLK Q C L PDWR PDRD M U X 0 1 Figure 6-5a I/O Port and I/O Control Register Interface Circuit for Port 7~Port C NOTE Pull-high and Open-drain are not shown in the figure. PCRD Q P R D _ CLK Q C L PCWR INT Q PORT P R D _ CLK Q IOD C L PDWR IMR D P R CLK C L 0 Q 1 _ M U X Q PDRD TI 0 INT Figure 6-5b I/O Port and I/O Control Register for INT NOTE Pull-high and Open-drain are not shown in the figure. Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) · 39 EM78P507N EM78P507N 8-Bit Microcontroller 6.4 Reset and Wake-up 6.4.1 Reset and Wake-up Function A reset is initiated by one of the following events(1) Power-on reset (2) /RESET pin input "low" (3) WDT time-out (if enabled) NOTE The power-on reset circuit is always enabled. It will reset the CPU at 1.9V and consumed about 0.5µA or lower less. The device is kept in a reset condition for a period of approximately 18ms (one oscillator start-up timer period) after the Power-on reset is detected. If the /Reset pin goes "low" or WDT time-out is active, a reset is generated. Once a Reset occurs, the following functions are performed: The oscillator is running, or will be started. The Program Counter (R2) is set to all "0". All I/O port pins are configured as input mode (high-impedance state). The Watchdog Timer and prescaler are cleared. When power is switched on, R1 is cleared. The bits of the P7ODCR, P8ODCR, P9ODCR, PAODCR, PBODCR registers are set to all "0". The bits of the P7PHCR, P8PHCR, P9PHCR, PAPHCR, PBPHCR, PCPHCR registers are set to all "0". Bits 7~0 of Bank 0 RE, RF registers and Bank 1 RE, RF registers are cleared. Executing the "SLEP" instruction will assert the Sleep (power down) mode. While going into Sleep mode, the Oscillator, TCC, and Timers 2~1 are stopped. The WDT (if enabled) is cleared but keeps on running. The controller can be awakened by one of the following events: 1) External reset input on /RESET pin 2) WDT time-out (if enabled) 3) External Interrupt status changes (if INTWE is enabled) 4) Low Voltage Detector initiated (if LVDWE is enabled) 40 · Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller The first two events will cause the EM78P507N EM78P507N to reset. The T and P flags of R3 can be used to determine the source of the reset (wake-up). Events 3 and 4 are considered the continuation of program execution and the global interrupt ("ENI" or "DISI" being executed) determines whether or not the controller branches to the interrupt vector following a wake-up. If ENI is executed before SLEP, the instruction will begin to execute from the Address 0x3~0x42 at each interrupt vector after wake-up. If DISI is executed before SLEP, the execution will restart from the instruction right next to SLEP after wake-up. Only one of Events 2 to 4 can be enabled before entering into Sleep mode. That is: a) If WDT is enabled before SLEP, all of Bank 0, 1 RE bit is disabled. Hence, the EM78P507 EM78P507 can be awaken only by Event 1 or 2. Refer to the section (Section 5) on Interrupt for further details. b) If External interrupt status change is used to wake-up the EM78P507N EM78P507N and INTWK bit of Banks 3, 4 RF register is enabled before SLEP, WDT must be disabled by software. Hence, the EM78P507N EM78P507N can be awaken only by Event 3. c) If Low voltage detector is used to wake-up the EM78P507N EM78P507N and LVDWE bit of Bank 3-RF register is enabled before SLEP, the WDT must be disabled by software. Hence, the EM78P507N EM78P507N can be awakened only with Event 4. 6.4.2 Wake-up and Interrupt Modes Operation Summary All categories under Wake-up and relative Interrupt modes are summarized below: Wake-up Signal Sleep Mode TCC time out × INT pin Wake-up + interrupt (if interrupt is enabled) + next instruction Timer 1 Idle Mode Green Mode Normal Mode Wake-up + interrupt + next instruction Interrupt Interrupt Wake-up + interrupt (if interrupt is enabled) + next instruction Interrupt Interrupt × Wake-up + interrupt + next instruction Interrupt Interrupt Timer 2 × Wake-up + interrupt + next instruction Interrupt Interrupt Timer 3 × Wake-up + interrupt + next instruction Interrupt Interrupt × Wake-up + interrupt (if interrupt is enabled) + next instruction Interrupt Interrupt UART Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) · 41 EM78P507N EM78P507N 8-Bit Microcontroller (Continuation) Wake-up Signal Sleep Mode Idle Mode LVD Wake-up + interrupt (if interrupt is enabled) + next instruction Wake-up + interrupt (if interrupt is enabled) + next instruction Green Mode Normal Mode Interrupt Interrupt I2C Wake-up Wake-up + interrupt + interrupt (if interrupt is enabled) + next instruction + next instruction Interrupt Interrupt SPI Wake-up Wake-up + interrupt + interrupt (if interrupt is enabled) + next instruction + next instruction Interrupt Interrupt A/D Wake-up + interrupt (if interrupt is enabled) + next instruction Wake-up + interrupt (if interrupt is enabled) + next instruction Interrupt Interrupt RESET RESET WDT time out RESET RESET NOTE User must set the wake up register (Bank 3 RF Bits 2~7 and Bank 4 RF Bits 0~7). Actions to be taken after Wake up through INT pin, A/D, UART, SPI, I2C, or LVD from Sleep and Idle modes: 1. If interrupt is enabled interrupt+ next instruction 2. If interrupt is disabled next instruction. 6.4.3 Status of T and P of the Status Register A reset condition is initiated by one of the following events: 1) Power-on condition 2) High-low-high pulse on the /RESET pin 3) Watchdog Timer time-out 42 · Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller The values of T and P, as listed in the table below, are used to check how the processor wakes up. Values of RST, T, and P after Reset Reset Type T P Power-on 1 1 /RESET during Operation mode *P *P /RESET wake-up during Sleep mode 1 0 WDT during Operation mode 0 *P WDT wake-up during Sleep mode 0 0 Wake-up on pin change during Sleep mode 1 0 *P: Previous status before reset The following table shows the events which may affect the status of T and P. Status of RST, T, and P affected by Events Events T P Power-on 1 1 WDTC instruction 1 1 WDT time-out 0 *P SLEP instruction 1 0 Wake-up on pin changed during Sleep mode 1 0 *P: Previous value before reset Controller Reset Block Diagram VDD D Oscillator Q CLK CLK CLR Power-On Reset Voltage Detector WTE WDT Timeout WDTE WDT Setup time Reset /RESET Figure 6-6 Controller Reset Functional Block Diagram Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) · 43 EM78P507N EM78P507N 8-Bit Microcontroller 6.5 Interrupt The EM78P507N EM78P507N has 21 interrupts as listed below: 1. Low Voltage Detector Interrupt 2. TCC Overflow Interrupt 3. External Interrupt (INT0~INT9) Pin 4. Timers 1~3 Underflow Interrupt 5. A/D Conversion Completed Interrupt 6. SPI Transmit/Receive Interrupt 7. UART Transmit/Receive/Error Completed Interrupt 8. I2C Transmit/Receive Interrupt External interrupt can select the detector edge in Banks 3 RE and RF (EIESH, EIESL). During a power source unsteady situation, such as external power noise interference or EMS test condition, it will cause the power to vibrate fiercely. While VDD is still erratic, the voltage supply may be below the required operational voltage. When this condition occurs, the IC kernel must automatically keep all the register status. ISR is the Interrupt Status Register that records the interrupt requests in the relative flags/bits. IMR is an Interrupt Mask Register. The global interrupt is enabled by the ENI instruction and is disabled by the DISI instruction. When one of the interrupts (if enabled) occurs, the next instruction will be fetched from its address. Once in the interrupt service routine, the source of an interrupt can be determined by polling the flag bits in ISR. The interrupt flag bit must be cleared by instructions before leaving the interrupt service routine to avoid recursive interrupts. The flag in the Interrupt Status Register is set regardless of the status of its mask bit or ENI execution. Note that the outcome of ISR will be the logic AND of ISR and IMR. The RETI instruction ends the interrupt routine and enables the global interrupt (ENI execution). Interrupt sources ACC ENI/DISI Interrupt occurs R1 R2 STACKACC STACKR1 RETI R3 STACKR2 STACKR3 Figure 6-7a Interrupt Backup Diagram With EM78P507N EM78P507N, each individual interrupt source has its own interrupt vector as depicted in the following table. 44 · Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller Interrupt Vector Interrupt Status 0003H 0003H Low voltage detector interrupt 0006H 0006H TCC overflow interrupt 0009H 0009H External INT0 interrupt 000CH 000CH External INT1 interrupt 000FH 000FH External INT2 interrupt 0012H 0012H External INT3 interrupt 0015H 0015H External INT4 interrupt 0018H 0018H External INT5 interrupt 001BH 001BH External INT6 interrupt 001EH 001EH External INT7 interrupt 0021H 0021H External INT8 interrupt 0024H 0024H External INT9 interrupt 0027H 0027H Timer 1 overflow interrupt 002AH 002AH Timer 2 overflow interrupt 002DH 002DH Timer 3 overflow interrupt 0030H 0030H A/D Converter complete interrupt 0033H 0033H SPI transmti/receive complete interrupt 0036H 0036H UART transmit complete interrupt 0039H 0039H UART error complete interrupt 003CH 003CH UART receive complete interrupt 003FH 003FH I2C transmit/receive complete interrupt 0042H 0042H I2C Slave stop interrupt VDD D /IRQn PR Q CLK CL Q RFRD IRQn . . IRQm ISR INT ENI / DISI Q PR D Q CLK CL IOD IOCFWR IMR /RESET IOCFRD RFWR Figure 6-7b Interrupt Input Circuit Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) · 45 EM78P507N EM78P507N 8-Bit Microcontroller 6.6 Analog-to-Digital Converter (ADC) 6.6.1 Registers for ADC Circuit R_BANK Addr. Name Bank 1 Bit 7 Bit 6 0×05 ADCR1 ADRUN ADP Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - R/W - - - - ADCK1 ADCK0 R/W Bank 1 0×08 0×09 ADIS2 ADIS1 ADIS0 R/W R/W R/W R/W R/W R/W ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 R R R R R R R ADD11 ADD11 ADDL ADIS3 ADD10 ADD10 ADD9 ADD8 R/W Bank 1 0×07 ADIS4 ADD7 0×06 ADCR2 ADREF R Bank 1 - Bank 1 R/W R/W R/W R/W R/W ADDH Bank 0 0×0B 0×0E ADE3 ADE2 ADE1 ADE0 R/W R/W R/W R/W R/W R/W R/W ADE14 ADE14 ADE13 ADE13 ADE12 ADE12 ADE11 ADE11 ADE10 ADE10 ADE9 ADE8 R/W R/W R/W R/W R/W R/W R/W ADE23 ADE23 ADIC3 ADE4 ADE22 ADE22 ADE21 ADE21 ADE20 ADE20 ADE19 ADE19 ADE18 ADE18 ADE17 ADE17 ADE16 ADE16 R/W Bank 1 ADE5 ADE15 ADE15 ADIC2 ADE6 R/W 0×0A ADE7 R/W Bank 1 ADIC1 R/W R/W R/W R/W R/W R/W R/W IMR ADIE R/W Bank 0 0×0F ISR ADIF R/W AD23 (PC2) AD22 (P94) AD21 (P95) 24 to 1 Analog switch AD3 (P90) VDD VREF ADC (Successive Approximation) Power Down Start to Convert Fosc/4 AD2 (P91) Fosc/16 Fosc/32 Fosc/64 AD1 (P92) 4 to 1 MUX AD0 (P93) ADIC1 ADIC2 ADIC3 ADIC4 0~23 3 2 1 0 ADCR 5 4 ADCR 5 ISR 11 10 9 8 7 6 5 4 3 2 1 0 ADCR 7 5 6 6 ADICH IMR DATA BUS Figure 6-8 ADC Functional Block Diagram 46 · Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller It is a 12-bit successive approximation type AD converter. The upper side of analog reference voltage can select either internal VDD or external input pin P84 (VREF) by setting the ADREF bit in ADCR2. 6.6.2 ADC Data Register When the A/D conversion is complete, the result is loaded to the ADDH (4-bit) and ADDL (8-bit). The START/END bit is cleared, and the ADIF is set. 6.6.3 A/D Sampling Time The accuracy, linearity, and speed of the successive approximation by A/D converter are dependent on the properties of the ADC. The source impedance and the internal sampling impedance directly affect the time required to charge the sample holding capacitor. The application program controls the length of the sampling time to meet the specified accuracy. Generally speaking, the program should wait for 2 µs for each K of the analog source impedance and at least 2 µs for the low-impedance source. The maximum recommended impedance for the analog source is 10K at Vdd =3.3V. After the analog input channel is selected, this acquisition time must be done before A/D conversion can be started. 6.6.4 A/D Conversion Time ADCK0 and ADCK1 select the conversion time (Tct), in terms of instruction cycles. This allows the MCU to run at maximum frequency without sacrificing accuracy of A/D conversion. For the EM78P507N EM78P507N, the conversion time per bit is about 4µs. The table below shows the relationship between Tct and the maximum operating frequencies. ADCK1:0 Operation Mode Maximum Frequency (Fc) Maximum Conversion Rate per Bit Maximum Conversion Rate 00 Fc/4 1 MHz 250kHz (4 µs) 48 µs (20.83kHz) 01 Fc/16 4 MHz 250kHz (4 µs) 48 µs (20.83kHz) 10 Fc/32 8 MHz 250kHz (4 µs) 48 µs (20.83kHz) 11 Fc/64 16 MHz 250kHz (4 µs) 48 µs (20.83kHz) Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) · 47 EM78P507N EM78P507N 8-Bit Microcontroller 6.7 SPI (Serial Peripheral Interface) 6.7.1 Registers for SPI Circuit R_BANK Addr. Bank 0 0X0D 0x0E Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SPIS DORD TD1 TD0 - OD3 OD4 - RBF R/W R/W R/W R/W CES SPIE SRO SSE SDOC R/W R/W R/W R/W R/W R/W R/W SRB7 SRB6 SRB5 SRB4 SRB3 SRB2 SRB1 SRB0 R R R R R R R SWB7 SWB6 SWB5 SWB4 SWB3 SWB2 SWB1 SWB0 R/W Bank 3 0X0C Bit 5 R Bank 3 0X0B Bit 6 R/W Bank 3 0X0A Bit 7 R/W Bank 3 Name R/W R/W R/W R/W R/W R/W R/W SPIC SPIR SPIW IMR R SBRS2 SBRS1 SBRS0 SPIE R/W Bank 0 0x0F ISR SPIF R/W 6.7.2 Overview and Features Overview: Figures 7-9a and 7-9b below show how the EM78P507N EM78P507N communicates with other devices through the SPI module. If the EM78P507N EM78P507N is a Master controller, it sends a clock through the SCK pin. A couple of 8-bit data are transmitted and received at the same time. However, if the EM78P507N EM78P507N is defined as a Slave, its SCK pin could be programmed as an input pin. Data will continue to be shifted based on both the clock rate and the selected edge. You can also set the SPIS Bit 7 (DORD) to determine the SPI transmission order, the SPIC Bit 3 (SDOC) to control the SO pin after serial data output status, and the SPIS Bit 6 (TD1) & Bit 5 (TD0) to determine the SO status output delay times. Features: Operation in either Master mode or Slave mode Full duplex, 3-wire synchronous communication Programmable baud rates of communication Programming clock polarity (RD Bit 7) Interrupt flag available for the read buffer full SPI transmission order After serial data output SDO status select SDO status output delay time Up to 8 MHz bit frequency (maximum) 48 · Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller SDO SPIW SPIW Reg Reg SPIR Reg SPIW SPIW Reg Reg SPIR Reg /SS SDI SPIS Reg SPI Module SCK Master Device Slave Device Figure 6-9a SPI Master/Slave Communication SDI SDO SCK /SS VDD Master P70 P71 P72 P73 SDO SDI SCK /SS SDO SDI SCK /SS SDO SDI SCK /SS SDO SDI SCK /SS Slave Device 1 Slave Device 2 Slave Device 3 Slave Device 4 Figure 6-9b SPI Single-Master and Multi-Slave Configurations Product Specification (V1.0) 04.16.2010 (This specification is subject to change without further notice) · 49 EM78P507N EM78P507N 8-Bit Microcontroller 6.7.3 SPI Functional Block Diagrams Read RBF SPIIF Write SPIR SSE reg SPIW reg Set to 1 Buffer Full Detector SPIS shift right reg SI SPIC reg SO Edge Select SBR0 ~SBR2 /SS / Noise Filter SBR2~SBR0 SS Clock Select Prescaler 2, 4, 8, 16, 32 Fosc Edge Select SCK TMR2 CES Figure 6-9c SPI General Functional Block Diagram SPI SPI Read Register (0X0D) 7~0 SPIW / SS SPI Write Register (0X0E) 8-1 MUX SPI mode select Register 2 1 0 SPIC SO SI Shift Clock SPI Shift Buffer FOSC 7 6 4 5 4 SPIC SPIC 3 0 ISR SPIS 7~0 SPIR DATA Bus Figure 6-9d SPI Transmission Functional Block Diagram 50 · Product Specification (V1.0) 04.02.1610 (This specification is subject to change without further notice) EM78P507N EM78P507N 8-Bit Microcontroller Listed below are the function descriptions of each block depicted in Figures 6-9c and 6-9d above. It also explains how to carry out the SPI communication with the relevant signals. PA4/SDI: Serial Data In PA5/SDO: Serial Data Out PA6/SCK: Serial Clock PA7//SS: /Slave Select (Option). This pin (/SS) may be required in Slave mode RBF: Set by Buffer Full Detector Buffer Full Detector: Set to "1" when an 8-bit shifting is completed. SSE: Loads the data in SPIS register, and begin to shift. The SSE bit will be kept at "1" if communication is still undergoing. This flag must be cleared as the shifting is completed. Users can determine if the next write attempt is available. SPIS reg.: Shifting byte in and out. The MSB is shifted first. Both the SPIR and the SPIW registers are shifted at the same time. Once data are written, SPIS starts transmission/reception. The data received will be moved to the SPIR register as the shifting of the 8-bit data is completed. The RBF (Read Buff