NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Type | Ordering |
| ECL-100K-SWGM-100 | Engineered Components Company | Waveform Generator |
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| ECL-100K-SWGM-110 | Engineered Components Company | Waveform Generator |
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| ECL-100K-SWGM-120 | Engineered Components Company | Waveform Generator |
1 pages, |
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| ECL-100K-SWGM-130 | Engineered Components Company | Waveform Generator |
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| ECL-100K-SWGM-140 | Engineered Components Company | Waveform Generator |
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| ECL-100K-SWGM-150 | Engineered Components Company | Waveform Generator |
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| ECL-100K-SWGM-160 | Engineered Components Company | Waveform Generator |
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| ECL-100K-SWGM-170 | Engineered Components Company | Waveform Generator |
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| ECL-100K-SWGM-190 | Engineered Components Company | Waveform Generator |
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| ECL-100K-SWGM-200 | Engineered Components Company | Waveform Generator |
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| Catalog Datasheet Results | Type | Document Tags |
| Abstract: ECL-1OOK-DFMM 190 190 Mhz ECL-100K-DFMM-85 85 Mhz ECL-100K DFMM 200 200 Mhz ECL-100K-DFMM-90 90 Mhz ECL-100K DFMM 210 210 Mhz ECL-100K DFMM 95 95 Mhz ECL-100K-DFMM-220 220 Mhz ECL-1 OOK-DFMM-100 OOK-DFMM-100 100 Mhz ECL-1OOK-DFMM 230 230 Mhz ECL-100K DFMM 110 110 Mhz ECL-100K-DFMM-240 240 Mhz ECL-100K-DFMM-120 120 Mhz , ECL-100K DFMM 130 1 30 Mhz ECL-100K DFMM-55 DFMM-55 55 Mhz ECL-1OOK-DFMM 140 140 Mhz ECL-100K-DFMM 60 60 Mhz ECL-1OOK-DFMM-1 50 150 Mhz ECL-100K DFMM-65 DFMM-65 65 Mhz ECL-1OOK-DFMM 160 160 Mhz ECL-100K-DFMM 70 70 Mhz ... | OCR Scan |
2 pages, |
ECL100K digital frequency multiplier ECL100K abstract |
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| Abstract: ECL100K INPUT > BUFFER X Y I > ECL 100K INPUT > BUFFER DELAY LINE Î I - - - V] DELAY LINE ECL100K OUTPUT BUFFER X Y ECL100K > OUTPUT BUFFER 1-F - î in2 4 Vcc E OUT2 _I 6 ... | OCR Scan |
1 pages, |
L552 EL552-4 EL552-3 EL552-2 EL552-15 EL552-12 EL552-11 EL552 EL552 abstract |
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| Abstract: ECL-10CK-SWGM-55 ECL-10CK-SWGM-55 55 MHz ECL-100K-SWGM-140 14C MHz ECL-100K-SWGM-60 60 MHz ECL-100K-SWGM-150 150 MHz ECL-100K-SWGM-"5 65 MHz ECL-10CK-SWGM-160 ECL-10CK-SWGM-160 160 MHz ECL- 100K-SWGM-70 100K-SWGM-70 70 MHz ECL-100K-SWGM-170 170 MHz ECL-100K-SWGM-75 75 MHz ECL-10CK-SWGM-180 ECL-10CK-SWGM-180 180 MHz ECL-100K-SWGM-80 80 MHz ECL-10CK-SWGM-190 ECL-10CK-SWGM-190 190 MHz , ECL-100K-SWGM-9S 95 MHz ECL-100K-SWGM-220 220 MHz ECL-10CK-SWGM-100 ECL-10CK-SWGM-100 100 MHz ECL-100K-SWGM-23O 230 MHz , DETAIL IS SHOWN BELOW .600 «-.800 - -^ -1- V OUT OUT e ECL-100K- SWGM- - V IN Ve ~r .780 J_ ... | OCR Scan |
1 pages, |
ECL-100K-SWGM-60 ECL-100K-SWGM-170 ECL-100K-SWGM-150 ECL-100K-SWGM-140 cip8 datasheet abstract |
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| Abstract: 5000-gate /;PB6350 PB6350. Both are compatible with ECL-10KH ECL-10KH, ECL-100K, or LSTTL logic. These application-specific , typical (F/0 = 1;L=0 mm) - ECL-10KH ECL-10KH, ECL-100K, or LSTTL compatible - 100% burn-in, all units - ECL-3A , pPB6350 Comments Integration (gate) 4000 5000 1 cell = 3.1 gates I/O interlace ECL-100K ECL-100K ECL-10KH ECL-10KH ECL-10KH ECL-10KH LSTTL LSTTL Power supply voltages Vee -4.5 V ±0.5 V -4.5 V ±0.5 V ECL-100K , Unit Power supply (EGL-10KH EGL-10KH) (ECL-100K) Vee -5.72 -5.0 -5.2 -4.5 -4.68 -4.0 V V Power supply Vt -2.1 ... | OCR Scan |
12 pages, |
ECL-10KH 208PGA PB6350 T-42-IH3 PB6340 ECL-100K T-42-IH3 abstract |
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| Abstract: ECL OUTPUTS OHW (ECL100k outputs) These characteristics apply when the relevant output is , ns ECL INPUTS STM16 STM16(15:0) and FP (ECL100k inputs with 50k pulldown resistors) Parameter , RT 1k VTT INPUT BIAS GENERATOR VREF VEE -5V Single Ended DC Coupled (ECL100k , ) GND VCC RDB ALE WRB VEE GND N/C SCRIB B1ENB FP GND Levels Type ECL100k ECL100k ECL100k ECL100k Input Input Resistor Input 75 Output 75 Output 75 Output ... | Original |
19 pages, |
SSSB153 SSSB149 PE-65507 G703 STM16 SSSB153 abstract |
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| Abstract: LTXD LOOPBACK RCVDA RCVDAB TESTB VEE FLTR GND BGFLTR VEE · ECL100k compatible 155.52MBit/s , differential ECL100k outputs SRDATA and RBCLK. The retimed data is converted from bit serial to byte parallel , rate, i.e. nominally 19.44MHz. LTXD ECL100k data input for Loopback operation. SDI, SDIB , SRDATA, SRDATAB Differential ECL100k data outputs for the Retimed Serial Data in NRZ format. RBCLK, RBCLKB Differential ECL100k 155.52MHz Clock outputs. RBCLK and RBCLKB are the clock outputs associated ... | Original |
16 pages, |
SSSB151 PE-65507 10n 500V capacitor SSSB151 abstract |
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| Abstract: frequency capacitors. All power supply and ground pins must be connected. The clock input is ECL100K , ECL100K gate with a 50 Ohm termination resistor to -2V mounted close to the clock pin. At frequencies , frequency set, input enable and reset inputs are ECL100K compatible, and when very fast frequency hopping is , TERMINATING RESISTOR X- -2 V FSO ECL100K INPUT , F1 KS E11 E10 D11 A6 B3 SP2002 SP2002 E2 L6 F10 B7 C10 B11 A10 BIO A8 B8 BS A4 B1 B2 A3 ECL100K ... | OCR Scan |
6 pages, |
triangle wave application note SP2002AAC SP2002 FS23 ECL100K 400M fs2d 350/400MHZ SP2002 abstract |
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| Abstract: to make any signal pin compatible with ECL 10K, ECL100K, TTL or CMOS. Customisation is accomplished , Three layer metallisation All peripheral cells fully programmable ECL 10K , ECL100K, TTL, CMOS I/O , Differential Input 2 p PEXDI 2.4 - ECL10K ECL10K Differential Output 2 p PEXDO 4.8 - ECL100K Input 1 p PECI 2.4 - ECL100K Buffer Output 1 p PECO 48 - ECL100K Inverting Output 1 p PECOIM 48 - ECL100K Differential Input 2 p PECDI 2 4 - ECL100K Differential Output 2 p PECDO 48 - TTL I/O 3-state 1 p PTIOZ 40 7.0 CMOS ... | OCR Scan |
8 pages, |
sp93802 ECL100K ELA61000 ELA62000 ELA63000 mdf 24 peco II plessey S 1979 SL-2541 SL254 SL2541 CMOS dual D-FLIPFLOP SIC 850 inverter rs FLIPFLOP SCHEMATIC ELA60000 ECL100K ELA60000 abstract |
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| Abstract: CMOS compatible byte-wide STM1 input ports SSSB152 SSSB152 DATE CODE · Byte-wide ECL100k compatible , POUT pins are ECL100k compatible Clock and Framing Signals A set of Clock and Framing signals are generated by the SSSB152 SSSB152 from the 155.52MHz clock supplied to the device through the differential ECL100k , STM64 STM64 application. The SYNCAO and SYNCAI pins are ECL100k compatible. The delay inside the SSSB152 SSSB152 from , Configuration Control Interface ECL Inputs SCRB ECL100k compatible control input for the scrambling circuit. ... | Original |
23 pages, |
STM64 STM16 SSSB152 SSSB151 SSSB148 44Mbyte SSSB152 abstract |
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| Abstract: capabilities: 70 ECL. - DC Parameters: See ECL-100K Logic Table on Page 6. Delay Total Increment Delay ... | OCR Scan |
1 pages, |
eel -16-2005 100KECL DDU-18 100KECL abstract |
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| Abstract: Coxa profiCe ECL 100 K COMPATIBLE ARE WAVE TOR MODULE # ECL 100K input and outputs # Output wavetrain can be started in sync with random events # 16-pin DIP package (.280 high) # Available in frequencies from 50 MHz to 250 MHz # Output frequencies controlled to within ±2% # High fan-out capacity design notes The "DIP Series" Gated Square Wave Generator Modules developed by Engineered Components Company have been designed to provide an ECL 100K square wave output at frequencies from 50 ... | OCR Scan |
2 pages, |
ECL-100K-SWGM-55 ecl 100k datasheet abstract |
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| Abstract: PRELIMINARY ECL DIGITAL DELAY LINES -5-41-5 - ECL 10K INTERFACED -5-41-5 - ECL 100K INTERFACED FEATURES TYPE E105 - ECL 10K 5 TAP Tap Delay (nS) 5 30 15 4 25 Pulse Spacing 5X Total Delay -1.0V provided by open emitter ECL 10K gate 5.2 VDC ECL 10K, -4.5 VDC ECL 100K 6 Ground (VCC) 3 14 4 13 Tap Delay (nS) 8 5 9 6 10 7 11 8 12 6 7 4 8 5 64 3 5 4 56 2 4 3 48 Output#1 Pin# 3 2 3 ... | Original |
1 pages, |
SCHEMAT E105 E103 E1008 E1004 E1001 RCD Components ecl 10K datasheet abstract |
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| Abstract: BLOCK DIAGRAM IS SHOWN BELOW IN-i 12 Vee 9 -I OUT1 8 -t ÜÜT1 ECL 100K INPUT BUFFER DELAY LINE ECL 100K OUTPUT BUFFER X V X Y ECL100K INPUT BUFFER DELAY LINE ECL 100K OUTPUT BUFFER 1 IN2 Y r 4 Vcc F 5 0UÏ2 0 6 UDT2 MECHANICAL DETAIL IS SHOWN BELOW .875 .700--^ IN, VpOUTj OUT^ DECLDL-2-_ in2 voutoout- .325 .060. TYP. efc2 8-138 made inslousa I- X.030 _L .100 typ. .050 typ.-- i .1601.030 -T -»-.020 dia. typ. .350 typ. .250 typ TEST CONDITONS 1. All ... | OCR Scan |
1 pages, |
ECL100K datasheet abstract |
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| Abstract: Technology 2.5 GHz minimum clock frequency ECL100k compatible parallel data inputs 50 differential serial , PARALLEL LOAD INPUTS D15 to D0 and ICK (ECL100k inputs) Parameter Symbol Conditions Input High , (155MHz) CLOCK OUTPUTS TCK and SCK (ECL100k outputs) These characteristics apply when the relevant , CKB (ECL100k compatible inputs, but internally biased through 1k to 1.32v to allow AC coupling , data inputs are ECL100k compatible, and have onboard terminating resistors of 50 to the 2V supply. ... | Original |
12 pages, |
STM16 SSSB148 ECL100K C 5387 IN4145 SSSB148 abstract |
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| Abstract: ÜÜT1 ECL 100K INPUT BUFFER DELAY LINE ECL 100K OUTPUT BUFFER X V X Y ECL100K INPUT BUFFER ... | OCR Scan |
2 pages, |
ECL100K marking ACY datasheet abstract |
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| Abstract: E-SAN ELECTRONIC CO LTD 24E ß a Active Delay Line (ECL 100K Series Interface) 3037MG2 3037MG2 00DG0S7 00DG0S7 L, i 90E Series 24 Pin Dip Package • 8 Tap Output I Specifications: • Operating Temp. Range • Storage Temp. • Vee • Logic 1 Output • Logic 0 Output • Rise Time (20% to 80%) • 100K ECL input and output 0°C to 85°C - 55°C to + 125°C - 4.5Vdc ±5% - 1 .025Vdc min - 1 .620Vdc max 2ns max. Test Conditions: • Input pulse Amplitude : -1.0V (-0.75V to -1.75V) Pulse width Pulse Spacing Time ... | OCR Scan |
1 pages, |
Esan 620VDC 3037MG2 00DG0S7 3037MG2 abstract |
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| Abstract: DC parameters: See ECL-100K Logic Table on Page 6. o J~I n h n JT .015 TYP. 100TYP 100TYP.-*- ... | OCR Scan |
1 pages, |
MDU-14 MDU-14 abstract |
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| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
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| I/O Cells Input Cells Differential and non differential input cells are available. The input cells perform the following voltage level conversions : Input Core Macro type Pad Macro ECL 100K CML IBI01EH IBI01EH IBI01EH IBI01EH, S IBI02EH IBI02EH IBI02EH IBI02EH, S IBI04EH IBI04EH IBI04EH IBI04EH, S PIECL CML2 IBI03EH IBI03EH IBI03EH IBI03EH, S Line Reciver CML IDIF02EH IDIF02EH IDIF02EH IDIF02EH, S IDIF03EH IDIF03EH IDIF03EH IDIF03EH, S : Input Core Macro type Pad Macro ECL 100K CML MXOUT50CEH MXOUT50CEH MXOUT50CEH MXOUT50CEH ORIOUT50CEH ORIOUT50CEH ORIOUT50CEH ORIOUT50CEH OUT50 OUT50 OUT50 OUT50 www.datasheetarchive.com/files/siemens/products/39/fl_ioc.htm |
Siemens | 26/02/1998 | 4.17 Kb | HTM | fl_ioc.htm |
| I/O Cells Input Cells Differential and non differential input cells are available. The input cells perform the following voltage level conversions : Input Core Macro type Pad Macro ECL 100K CML IBI01EH IBI01EH IBI01EH IBI01EH, S IBI02EH IBI02EH IBI02EH IBI02EH, S IBI04EH IBI04EH IBI04EH IBI04EH, S PIECL CML2 IBI03EH IBI03EH IBI03EH IBI03EH, S Line Reciver CML IDIF02EH IDIF02EH IDIF02EH IDIF02EH, S IDIF03EH IDIF03EH IDIF03EH IDIF03EH, S : Input Core Macro type Pad Macro ECL 100K CML MXOUT50CEH MXOUT50CEH MXOUT50CEH MXOUT50CEH ORIOUT50CEH ORIOUT50CEH ORIOUT50CEH ORIOUT50CEH OUT50 OUT50 OUT50 OUT50 www.datasheetarchive.com/files/infineon/products/39/fl_ioc.htm |
Infineon | 26/11/1998 | 4.14 Kb | HTM | fl_ioc.htm |
| * Library of digital logic: ECL 10K and 100K * Copyright Cadence Design Systems, Inc. 2002 All Rights Reserved. * * * $Revision: 1.2 $ * $Author: HIRASUNA $ * $Date: 11 May 2000 13:26:32 $ * * * ECL 10K LOGIC * * Created 07/17/91 (jjr, tdn) * *$ *- * ECL Output 50 ohm termination/load * * muw 07/16/91 Created .subckt ECL_10K_LOAD_50 A + optional: VTT =$G_ECL_10K_VTT VCC2=$G_ECL_10K_VCC2 www.datasheetarchive.com/files/spicemodels/misc/dig_ecl.lib |
Spice Models | 07/08/2009 | 142.23 Kb | LIB | dig_ecl.lib |
| * Library of digital logic: ECL 10K and 100K * Copyright OrCAD, Inc. 1998 All Rights Reserved. * Release date: January 1994 * $Revision: 1.14 $ * $Author: RPEREZ $ * $Date: 17 Apr 1998 11:11:12 $ * * * ECL 10K LOGIC * * Created 07/17/91 (jjr, tdn) * *$ *- * ECL Output 50 ohm termination/load * * muw 07/16/91 Created .subckt ECL_10K_LOAD_50 A + optional: VTT =$G_ECL_10K_VTT VCC2=$G_ECL www.datasheetarchive.com/files/spicemodels/misc/spice_model_cd/mixed part list/spice-models-collection/dig_ecl.lib |
Spice Models | 29/07/2012 | 142.14 Kb | LIB | dig_ecl.lib |
| ECL 100K www.datasheetarchive.com/files/infineon/wwwinf~1.com/produc~1/pro~1743.htm |
Infineon | 26/10/2000 | 19.5 Kb | HTM | pro~1743.htm |
| ECL 100K www.datasheetarchive.com/files/infineon/wwwinf~1.com/produc~1/pro~1744.htm |
Infineon | 26/10/2000 | 19.51 Kb | HTM | pro~1744.htm |
| Obsolete ECL 100K No Line Receiver No TTL No TTL (single power supply) No 3,3 V Bi www.datasheetarchive.com/files/infineon/wwwinf~1.com/produc~1/para~410.htm |
Infineon | 19/10/2000 | 10.87 Kb | HTM | para~410.htm |
| Obsolete ECL 100K No TTL No TTL (single power supply) No 3,3 V BiCMOS No CML (open www.datasheetarchive.com/files/infineon/wwwinf~1.com/produc~1/para~411.htm |
Infineon | 19/10/2000 | 10.88 Kb | HTM | para~411.htm |
| * DIGITAL LIBRARY ECL10K ECL10K ECL10K ECL10K and ECL100K * * The Global Setting DIGDRVZ may need to be set to a higher value * than the default value of 20K. The input pulldown resistors of * each part are at 50K which would display a high impedance state * instead of a 0. Setting the DIGDRVZ to 200K should solve this. * * - 10100 - * Quad 2-Input Nor Gate With Strobe * * The MECL Data Book, 1993, Motorola Pages 3-3 to 3-4 * bss 12 www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/ecl.lib |
Spice Models | 18/04/2010 | 183.71 Kb | LIB | ecl.lib |
| {REF} R3 VEE AGND 1E9 V4 VTT AGND {REFTT} R4 VTT AGND 1E9 R5 AGND 0 1m .ends *ECL 100K POWER SUPPLY SUBCIRCUIT* .subckt ECL_100K_PWR AGND + optional: VCC1=$G_ECL_100K_VCC1 VCC2=$G_ECL_100K_VCC2 + VEE=$G_ECL_100K_VEE VTT=$G_ECL_100K_VTT + params: VOLT1=0 VOLT2=0 REF=-4 www.datasheetarchive.com/files/spicemodels/misc/modelos/spice_complete/digio.lib |
Spice Models | 18/04/2010 | 79.04 Kb | LIB | digio.lib |
| Part | Manufacturer | Description | Shortform Datasheet | Ordering |
| ECL100K-DFMM100 | Engineered Components Company | Miscellaneous Digital Circuit - Digital Freq. Multiplier | |
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| ECL100K-DFMM110 | Engineered Components Company | Miscellaneous Digital Circuit - Digital Freq. Multiplier | |
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| ECL100K-DFMM120 | Engineered Components Company | Miscellaneous Digital Circuit - Digital Freq. Multiplier | |
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| ECL100K-DFMM130 | Engineered Components Company | Miscellaneous Digital Circuit - Digital Freq. Multiplier | |
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| ECL100K-DFMM140 | Engineered Components Company | Miscellaneous Digital Circuit - Digital Freq. Multiplier | |
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| ECL100K-DFMM150 | Engineered Components Company | Miscellaneous Digital Circuit - Digital Freq. Multiplier | |
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| ECL100K-DFMM160 | Engineered Components Company | Miscellaneous Digital Circuit - Digital Freq. Multiplier | |
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| ECL100K-DFMM170 | Engineered Components Company | Miscellaneous Digital Circuit - Digital Freq. Multiplier | |
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| ECL100K-DFMM180 | Engineered Components Company | Miscellaneous Digital Circuit - Digital Freq. Multiplier | |
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| ECL100K-DFMM190 | Engineered Components Company | Miscellaneous Digital Circuit - Digital Freq. Multiplier | |
| PCA Electronics Part | Industry Part | Manufacturer |
| EPA199-X Buy | ECL100K-LDM(X) Buy | ECC |