NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
NEW DATABASE - 350 MILLION DATASHEETS FROM 8500 MANUFACTURERS
| Part | Manufacturer | Description | Samples | Ordering |
| MAX9381ESA-TG068 | Maxim Integrated Products | ECL/PECL DIFFERENTIAL DATA AND CLOCK D FLIP-F | 
|
|
|
| SN100KT5574NT | Texas Instruments | Octal ECL-to-TTL Translator With D-type Edge-Triggered Flip-Flops And 3-State OU 24-PDIP 0 to 70 |
|
|
|
| SN100KT5574DW | Texas Instruments | Octal ECL-to-TTL Translator With D-type Edge-Triggered Flip-Flops And 3-State OU 24-SOIC 0 to 70 |
|
|
|
| SN10KHT5574DW | Texas Instruments | Octal ECL-to-TTL Translator With D-Type Edge-Triggered Flip-Flops and 3-State Outputs 24-SOIC 0 to 70 |
|
|
|
| SN10KHT5578DW | Texas Instruments | Octal TTL-To-ECL Translator With D-Type Edge-Triggered Flip-Flops and Output Enable 24-SOIC 0 to 70 |
|
|
| Catalog Datasheet Results | Type | Document Tags |
| Abstract: SG388/D Rev. 4, May-2002 Master Components Selector Guide Master Components Selector Guide , Representative ON Semiconductor Website: http://onsemi.com SG388/D 05/02 SG388 SG388 REV 4 ON , Power Products SG388/D Rev. 4, MayÂ2002 © SCILLC, 2002 Previous Edition © 2001 "All Rights , Semiconductor brochure, BRD8011/D, for information on Tape & Reel. http://onsemi.com 3 http , see the Analog Switch Brochure, BRD8007/D available online at http://www.onsemi.com, or from the ... | Original |
314 pages, |
TL494 AC-DC CONVERTER MMFT3055VLT1 UC2842 DIP-8 TI design smps 500 watt TL494 UNDERVOLTAGE SENSING CIRCUIT tsop5 NCP6334 SG3526 tip122 tip127 mosfet audio amp TRANSISTOR MPS2112 smps with uc3842 and tl431 dc motor speed control tl494 UC3842 smps design with TL431 SG388/D SG388/D abstract |
|
|||
| Abstract: Buffer ECL/PECL Differential Receiver ECL/PECL D Flip Flop with Set and Reset ECL/PECL � 2 Divider ECL/PECL 2:1 Multiplexer ECL/PECL Quint Differential Line Receiver ECL/PECL 4-bit D Flip-Flop ECL , ECL/PECL � 4 Divider ECL/PECL 2:1 Multiplexer Packages D, T, N D, T, N D, T, N D, T, N D, T , AZ100EL16VO AZ100EL16VO AZ100LVEL16VR AZ100LVEL16VR AZ100LVEL16VT AZ100LVEL16VT AZ100LVEL16VV AZ100LVEL16VV AZP81 AZP81 AZP92 AZP92 AZP94 AZP94 AZV99 AZV99 AZ12010 AZ12010 Function ECL/PECL Oscillator Gain Stage and Buffer with Enable Packages T, U, L, N, XP, XR ECL/PECL Oscillator ... | Original |
5 pages, |
AZ100LVEL16VV AZ100LVEL16 AZ100LVEL16VR AZ100LVEL16VT AZ100EL16VO AZ12010 AZP81 AZP92 AZP94 AZV99 AZ100LVEL11 1 TO 4 CLOCK BUFFER 8-pin SOIC dual flip flop 8-pin AZ100EL16VO abstract |
|
|||
| Abstract: counter frequency is over 180 MHz or easy frequency increase to over 250 MHz with the 95H29 95H29 JK Flip Flop , Features include assertion inputs and outputs on each of the 4 master slave counting flip flop. Terminal , SEPARATE NON-STANDARD ECL LOGIC FUNCTIONS -4 DUAL AND GATES • HIGHER SYSTEM RELIABILITY AND LOWER COST BY , COUNT AND POWER C„ â- A„ â- B„ , D = A, 2 2 3 3 A, B, o-i =EX Cfc 1 IMI -0 P„ P, P3 CE Tc ... | OCR Scan |
1 pages, |
95H29 95H10 95H00 ECL D flip flop BCD 8421 synchronous counter using flip flip digital clock using logic gates digital clock using gates synchronous counter using 4 flip flip 95H10 abstract |
|
|||
| Abstract: SK10/100EL31W SK10/100EL31W D Flip - Flop with Set and Reset HIGH-PERFORMANCE PRODUCTS Description Features · The SK10/100EL31W SK10/100EL31W is a D Flip-Flop with Set and Reset. The device is fully compatible with the , : Level 1. · · · · · · · · · PinDescription Pin Q, Q* S D CLK R Functional Block Diagram S 8 1 2 D Truth Table 7 Q D 6 3 Q* R S R CLK Q L H X X X Flip Flop CLK Data Outputs Set Data Input Clock Input Reset VCC S ... | Original |
5 pages, |
ECL D flip flop E131 SK10/100EL31W MC10/ 100EL31 MC10/100LVEL31 SK10/100EL31W abstract |
|
|||
| Abstract: DUAL D FLIP FLC SYNCHRONOUS OPERATION D TABLE TRUTH TABLES ASYNCHRONOUS OPERATION SD CD TABLE FD DUAL D FLIP FLOP d °ft+1) L L H H SD = CD = LOW (t+1) = Time after positive going clock , undetermined s D VCC , =1 VCC 2 = 16 VEE -8 pfeñ -f£>1 TO OTHEP FLIP FLOP Note that this diagram , F95231 F95231 HIGH SPEED DUAL D FLIP-FLOP DESCRIPTION - The F95231 F95231 contains two master/slave D type , LOW, the slave is held steady and the information on the D input is permitted to enter the master. The ... | OCR Scan |
4 pages, |
F95231 F95231 abstract |
|
|||
| Abstract: MC100LVEL29 MC100LVEL29 3.3V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset Description The MC100LVEL29 MC100LVEL29 is a dual master-slave flip flop. The device features fully differential Data , the state will be random based on how the flip flop powers up. Both flip flops feature asynchronous , Note AND8020/D - Termination of ECL Logic Devices.) http://onsemi.com 4 MC100LVEL29 MC100LVEL29 ORDERING , Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D - ECL Clock Distribution ... | Original |
6 pages, |
MC100LVEL29DW MC100LVEL29 MC100EL29 MC100LVEL29 abstract |
|
|||
| Abstract: MC100LVEL29 MC100LVEL29 3.3V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset Description The MC100LVEL29 MC100LVEL29 is a dual master-slave flip flop. The device features fully differential Data , the state will be random based on how the flip flop powers up. Both flip flops feature asynchronous , Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.) http://onsemi.com 4 , Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D - ECL Clock ... | Original |
6 pages, |
MC100LVEL29DW MC100LVEL29 MC100EL29 ECL D flip flop MC100LVEL29 abstract |
|
|||
| Abstract: MC100EL29 MC100EL29 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset Description The MC100EL29 MC100EL29 is a dual master-slave flip flop. The device features fully differential Data and Clock , , however the state will be random based on how the flip flop powers up. Both flip flops feature , TABLE PIN FUNCTION S* D* CLK* Q Q ECL Differential Data Inputs ECL Reset Inputs , (See Application Note AND8020/D - Termination of ECL Logic Devices.) http://onsemi.com 4 ... | Original |
6 pages, |
MC100EL29 MC100EL29 abstract |
|
|||
| Abstract: delays are for each gating level of a more complex logic function (i.e. D flip/flop, 4 to 1 mux, etc. , NOTES: 1. Logic cell delays are for each gate level of a more complex logic function (i.e. D flip/flop , lFPD' Internal equivalent gate delay .9 .9 nS fmaxt Max internal flip/flop toggle frequency 250 , DEVICE SPECIFICATION 004958 Q/^cf APPLIED MICRO CIRCUITS CORPORATION Q700 SERIES ECL/TTL , circuit requirements. VERY HIGH SPEED 0.5 to 0.9 ns average gate delay within the internal array. ECL & ... | OCR Scan |
8 pages, |
VCC-650 Q700 ECL10K AMCC Q700 Q720 Logic TTL military summary Q710 datasheet abstract |
|
|||
| Abstract: gating level of a more complex logic function (i.e. D flip/flop, 4 to 1 mux, etc.) INPUT/OUTPUT , for each gate level of a more complex logic function (i.e. D flip/flop, 4 to 1 mux, etc.) 2. Standard , .9 nS fmaxt Max internal flip/flop toggle frequency 250 250 MHz lPZH Enable time to high , DEVICE SPECIFICATION 004958 Q/^cf APPLIED MICRO CIRCUITS CORPORATION Q700 SERIES ECL/TTL , circuit requirements. VERY HIGH SPEED 0.5 to 0.9 ns average gate delay within the internal array. ECL & ... | OCR Scan |
8 pages, |
TTL 1980 Q700 ecl10k 10125 ecl to ttl Q710 Q720 datasheet abstract |
|
|||
| Abstract | Saved from | Date Saved | File Size | Type | Download |
| Over 1.1 million files (1986-2013): html articles, reference designs, gerber files, chemical content, spice models, programs, code, pricing, images, circuits, parametric data, RoHS data, cross references, pcns, military data, and more. Please note that due to their age, these files do not always format correctly in modern browsers. Disclaimer. |
|||||
| V ECL Quad D Flip Flop with Set, Reset, and Differential Clock Flip-Flop MC100EP52 MC100EP52 MC100EP52 MC100EP52 3.3V / 5V ECL Differential Data and Clock D Flip-Flop NB4L52 NB4L52 NB4L52 NB4L52 2.5 to 5.5V ECL D-Flip-flop w/Differential Reset & Input Termination MC100EP31 MC100EP31 MC100EP31 MC100EP31 3.3V / 5V ECL D Flip-Flop with Set and Reset MC100EP29 MC100EP29 MC100EP29 MC100EP29 3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset www.datasheetarchive.com/files/on-semiconductor/html/ds/13_datamanagement.html |
On Semiconductor | 28/08/2008 | 23.04 Kb | HTML | 13_datamanagement.html |
| 3.3V / 5V ECL D Flip-Flop with Set and Reset MC10EP31/D (158.0kB) 9 100 3.3V / 5V ECL Differential Data and Clock D Flip Flop MC10EP52/D (162.0kB) 6 .3V / 5V ECL JK Flip Flop MC10EP35/D (157.0kB) 5 100 3.3V 3.3V / 5V ECL Quad D Flip Flop with Set, Reset, and Differential Clock MC10EP131/D (164.0k ECL D Flip-Flop with Set and Reset MC100LVEL31/D (136.0kB) 3 100 www.datasheetarchive.com/files/on-semiconductor/taxonomy/differentiallogic.htm |
On Semiconductor | 28/09/2007 | 88.06 Kb | HTM | differentiallogic.htm |
| mc100el52;so8;MC100EL52 MC100EL52 MC100EL52 MC100EL52;100K ECL differential D-Flip-Flop;100K ECL differential D-Flip-Flop;MECL 100k Series;MECL 100k Serie;ON-Semiconductor;mc mc100e131;plcc28;MC100E131 MC100E131 MC100E131 MC100E131, SY100E131 SY100E131 SY100E131 SY100E131;100K ECL 4 Bit D-Flip-Flop;100K ECL 4 Bit D-Flip-Flop;MECL 100k Series;MECL 100k Serie;ON-Semiconductor, Synergy;mc www.datasheetarchive.com/download/48664731-299145ZC/bae65022linux.tgz |
Kaleidoscope | 22/08/2005 | 11421.08 Kb | TGZ | bae65022linux.tgz |
| mc100el52;so8;MC100EL52 MC100EL52 MC100EL52 MC100EL52;100K ECL differential D-Flip-Flop;100K ECL differential D-Flip-Flop;MECL 100k Series;MECL 100k Serie;ON-Semiconductor;mc mc100e131;plcc28;MC100E131 MC100E131 MC100E131 MC100E131, SY100E131 SY100E131 SY100E131 SY100E131;100K ECL 4 Bit D-Flip-Flop;100K ECL 4 Bit D-Flip-Flop;MECL 100k Series;MECL 100k Serie;ON-Semiconductor, Synergy;mc www.datasheetarchive.com/download/48664731-299145ZC/bae65022linux.tgz |
Kaleidoscope | 22/08/2005 | 11421.08 Kb | TGZ | bae65022linux.tgz |
| OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS13A SDZS13A SDZS13A SDZS13A - APRIL 1990 -FLOPS & OUTPUT ENABLE Product Family: D-TYPE FLIP-FLOPS Device Functionality: OCTAL TTL-TO-ECL Data Sheet Abstract: SN100KT5578 SN100KT5578 SN100KT5578 SN100KT5578:OCTAL TTL-TO-ECL TRANSLATOR W/ D-TYPE EDGE-TRIGGERED FLIP bus-oriented receiversand transmitters. The eight flip-flops of the '5578 are edge-triggered D-typeflip-flops the D inputs. The output-control input doesnot affect the internal operations of the flip-flops. Old www.datasheetarchive.com/files/texas-instruments/sc/psheets/abstract/datasht/sdzs13a.htm |
Texas Instruments | 01/06/1998 | 5.79 Kb | HTM | sdzs13a.htm |
| Data Sheet Abstract: SN100KT5574 SN100KT5574 SN100KT5574 SN100KT5574:OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS ECL-TO-TTLTRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS features 100K : OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OU Product Family: D-TYPE FLIP-FLOPS Device Functionality: OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND eight flip-flops of the SN100KT5574 SN100KT5574 SN100KT5574 SN100KT5574 are edge-triggered D-typeflip-flops. On the positive transition of www.datasheetarchive.com/files/texas-instruments/sc/psheets/abstract/datasht/sdzs009.htm |
Texas Instruments | 01/06/1998 | 6.17 Kb | HTM | sdzs009.htm |
| ,clock drivers, and bus-oriented receivers and transmitters. The eight flip-flops of the '5578 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic SN100KT5578 SN100KT5578 SN100KT5578 SN100KT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS13A SDZS13A SDZS13A SDZS13A - APRIL 1990 - REVISED OCTOBER 1990 features operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are off www.datasheetarchive.com/files/texas-instruments/data/html/sdzs13a.htm |
Texas Instruments | 28/08/1997 | 1.76 Kb | HTM | sdzs13a.htm |
| and transmitters. The eight flip-flops of the Â'5578 are edge-triggered D-type flip-flops. On the SN10KHT5578 SN10KHT5578 SN10KHT5578 SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014 SDZS014 SDZS014 SDZS014 Â- APRIL 1990 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs Flow-Through Architecture inputs. The output-control input does not affect the internal operations of the flip-flops. Old www.datasheetarchive.com/files/texas-instruments/data/html/sdzs014.htm |
Texas Instruments | 17/11/1997 | 1.9 Kb | HTM | sdzs014.htm |
| SN100 SN100 SN100 SN100 T5574 T5574 T5574 T5574 OCTAL ECL-TO-TTLTRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS features 100K Compatible ECL drivers, and bus-oriented receivers and transmitters. The eight flip-flops of the SN100KT5574 SN100KT5574 SN100KT5574 SN100KT5574 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are off www.datasheetarchive.com/files/texas-instruments/data/html/sdzs009.htm |
Texas Instruments | 28/08/1997 | 2.28 Kb | HTM | sdzs009.htm |
| and transmitters. The eight flip-flops of the Â'5578 are edge-triggered D-type flip-flops. On the SN10KHT5578 SN10KHT5578 SN10KHT5578 SN10KHT5578 OCTAL TTL-TO-ECL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND OUTPUT ENABLE SDZS014 SDZS014 SDZS014 SDZS014 Â- APRIL 1990 10KH Compatible TTL Clock and ECL Control Inputs Noninverting Outputs Flow-Through Architecture inputs. The output-control input does not affect the internal operations of the flip-flops. Old www.datasheetarchive.com/files/texas-instruments/data/html/sdzs014-v1.htm |
Texas Instruments | 26/08/1997 | 1.9 Kb | HTM | sdzs014-v1.htm |