E2U0039-16-X3 MSM6997H MSM7543 MSM7702 MSM6932B/6933B MSM6962/6963 MSM6982/6983 - Datasheet Archive

 

¡ Semiconductor Single Supply PCM CODEC Application Notes ¡ Semiconductor Single Supply PCM CODEC Application Notes

 

E2U0039-16-X3 E2U0039-16-X3 ¡ Semiconductor Single Supply PCM CODEC Application Notes ¡ Semiconductor Single Supply PCM CODEC Application Notes CONTENTS 1. Differences in the electrical characteristics between conventional dual supply CODEC and the single supply CODEC. 2. Dynamic range of the single supply CODEC. 3. Output amplitude of CODEC to which another codec having a different dynamic range is interfaced. 4. Power saving mode. 5. Power down mode. 6. The states of output pins in power down mode and power saving mode. 7. Analog output noise in power down mode and power saving mode. 8. Burst mode clock. 9. Interface between the device input and a microphone signal output. 10. Interface between the device output and a speaker signal input. 11. Example of a circuit connected to a 4-wire communication (telephone) line. 10 813 Single Supply PCM CODEC Application Notes ¡ Semiconductor DESCRIPTION 1. Table of Difference in Electrical Characteristics Between the Dual Supply CODEC and the Single Supply CODEC Dual Supply CODEC Ex. MSM6997H MSM6997H 5 V Single Supply CODEC 3 V Single Supply CODEC Ex. MSM7543 MSM7543 Ex. MSM7702 MSM7702 +5 V ±5% ­5 V ±5% 68 mW typ. 110 mW max. +5 V ±5% 2.7 V to 3.8 V 20 mW typ. 32 mW max. 15 mW typ. Signal Level (0 dBm0) 1.227 Vrms (+4 dBm) 0.6007 Vrms (­2.2 dBm) Transmit Receive Signal Ground 0V VDD/2 VDD/2 Transmit ­79 dBm0p typ. ­75 dBm0p spec. ­74 dBm0p typ. ­70 dBm0p spec. ­72 dBm0p typ. ­68 dBm0p spec. Receive ­84 dBm0p typ. ­75 dBm0p spec. ­78 dBm0p typ. ­75 dBm0p spec. ­76.5 dBm0p typ. ­74 dBm0p spec. Transmit/Receive Asynchronous Operation Enable Both BCLOCK and SYNC can be separated in transmit and receive. Disable BCLOCK is used for both transmit and receive. Disable BCLOCK is used for both transmit and receive. Usable BCLOCK Frequency 64 kHz to 2048 kHz Value specified in catalog Value specified in catalog MSM6932B/6933B MSM6932B/6933B MSM6962/6963 MSM6962/6963 MSM6982/6983 MSM6982/6983 MSM6996 MSM6996 MSM6998/6999 MSM6998/6999 MSM6810/6811 MSM6810/6811 MSM6812/6813 MSM6812/6813 MSM6814/6815 MSM6814/6815 MSM7508B/7509B MSM7508B/7509B MSM7578/7579 MSM7578/7579 MSM7543/7544 MSM7543/7544 MSM7507 MSM7507 MSM7533/7534 MSM7533/7534 MSM7502 MSM7502 MSM7705 MSM7705 MSM6895/6896 MSM6895/6896 MSM7503 MSM7503 MSM7566/7567 MSM7566/7567 MSM7541/7542 MSM7541/7542 MSM7704 MSM7704 MSM7717 MSM7717 MSM7716 MSM7716 Power Supply Voltage Power Consumption Idle Channel Noise Names of the Products Families Note: 10 814 0.35 Vrms 0.50 Vrms There is no difference in other characteristics between the three types of CODEC listed above. ¡ Semiconductor Single Supply PCM CODEC Application Notes 2. Dynamic Range of Single Supply CODEC (1) Absolute level Conventional CODEC (±5 V power supplies in the MSM6997 MSM6997 series) 0 dBm0 = +4.0 dBm = 1.227 Vrms 5 V single supply CODEC (in the MSM7508B MSM7508B, MSM7543 MSM7543) 0 dBm0 = ­2.2 dBm = 0.6007 Vrms 3 V single supply CODEC (in the MSM7541 MSM7541) 0 dBm0 = ­6.9 dBm = 0.35 Vrms (transmit) 0 dBm0 = ­3.8 dBm = 0.5 Vrms (receive) 5 V single supply CODEC (MSM7533/7534 MSM7533/7534) 0 dBm0 = 0.8 dBm = 0.85 Vrms (2) Maximum output amplitude Conventional dual supply CODEC (MSM6997/6998 MSM6997/6998) Vmax = 2 ¥ ÷2 ¥ ÷2 ¥ 1.227 = 4.9 VPP Maximum amplitude : Vmax = 4.9 VPP 5 V single supply CODEC (MSM7543/7544 MSM7543/7544, MSM7508B/7509B MSM7508B/7509B) Vmax = 2 ¥ ÷2 ¥ ÷2 ¥ 0.6007 = 2.4 VPP Maximum amplitude : Vmax = 2.4 VPP As described above, the output amplitude of 5 V single supply CODEC series is approximately half the level of the dual supply CODEC. 3 V single supply CODEC (MSM7541/7542 MSM7541/7542, MSM7566/7567 MSM7566/7567, MSM7702 MSM7702, MSM7717 MSM7717, MSM7704 MSM7704) (Transmit side) Vmax = 2 ¥ ÷2 ¥ ÷2 ¥ 0.35 = 1.4 VPP Maximum amplitude : Vmax = 1.4 VPP (Receive side) Vmax = 2 ¥ ÷2 ¥ ÷2 ¥ 0.5 = 2.0 VPP Maximum amplitude : Vmax = 2.0 VPP 5 V single supply 2ch/4ch CODEC (MSM7533/7534 MSM7533/7534, MSM7705 MSM7705) Vmax = 2 ¥ ÷2 ¥ ÷2 ¥ 0.85 = 3.4 VPP Maximum amplitude : Vmax = 3.4 VPP 10 Note: As described above, the dynamic range of a 3 V single supply CODEC is different between the transmit side and the receive side. 815 Single Supply PCM CODEC Application Notes ¡ Semiconductor 3. Output Amplitude of CODEC Connected to Another CODEC with a Different Dynamic Range Example 1. When the 3 V single supply CODEC is interfaced with the 5 V single supply CODEC. MSM7541 MSM7541 0.7 Vo-p input 1.0 Vo-p output AIN PCMOUT VFRO PCMIN MSM7543 MSM7543 PCMIN VFRO PCMOUT AIN 1.2 Vo-p output 1.2 Vo-p input Example 2. When the 3 V single supply CODEC is interfaced with the dual supply CODEC. MSM7541 MSM7541 0.7 Vo-p input 1.0 Vo-p output AIN VFRO MSM6997 MSM6997 PCMOUT PCMIN PCMIN AOUT PCMOUT 2.45 Vo-p output AIN 2.45 Vo-p input Example 3. When the 5 V single supply CODEC is interfaced with the dual supply CODEC. MSM7543 MSM7543 1.2 Vo-p input 1.2 Vo-p output Note: 10 816 AIN VFRO PCMOUT PCMIN MSM6997 MSM6997 PCMIN PCMOUT In the above figures, the input gain is assumed to be one. AOUT 2.45 Vo-p output AIN 2.45 Vo-p input ¡ Semiconductor Single Supply PCM CODEC Application Notes 4. Power Save Mode The single supply CODEC automatically enters power save mode based on the following conditions. Case 1. When the XSYNC, RSYNC or BCLOCK signal is set to digital "1" or digital "0". Case 2. When the XSYNC or RSYNC signal has a lot of jitter. In case 1 and case 2, the internal PLL and the analog circuit with the exception of the reference voltage source go in to a power down state. This state is called Power save mode. XSYNC/RSYNC PWD (Internal Signal) 2 to 10 ms PLL Lock-in Time 1 ms DPWD (Internal Signal) PWD : Internal circuit signal which sets the PLL and analog circuit with the exception of the reference voltage circuit to the power down state. DPWD : Delayed PWD. The states of PCMOUT and the analog output do not become stable soon after the entire device goes in to the power on state. To avoid an unstable state, the DPWD signal inside the device is fixed at digital "1" for about 1 ms after locking of PLL, and the states of PCMOUT and the analog output are fixed. This description applies to MSM7508B/7509B MSM7508B/7509B. In the case of / 7717/7705/7702/7704/7578/7579, the RSYNC signal is not monitored and only the BCLOCK, and XSYNC signals are monitored. Note : If the power source contains noise pulses, and the amplitude of the noise is great, the PLL may go in to an asynchronous state and the device may go to power save mode. 817 10 Single Supply PCM CODEC Application Notes ¡ Semiconductor 5. Power Down Mode Common to all 3 V single supply and 5 V single supply CODEC. When digital "0" is input to the power down signal input pin (PDN), all of the analog circuits including the PLL and the reference voltage circuit go in to a power down state. PDN PWD (Internal Signal) 1 ms DPWD (Internal Signal) 5.1 Setup time from power down mode to operation mode. The locking of the internal PLL circuit takes a long time to setup. It usually takes 2 ms to 10 ms, depending on device variations. The device starts within a maximum of 10 ms. 10 818 ¡ Semiconductor Single Supply PCM CODEC Application Notes 6. The State of the Output Pin in Power Save Mode and Power Down Mode PCMOUT, PCM data output pins (applicable to all types of device) These pins are open. PCM DATA "0" PCMOUT OFF DPWD (Digital "0") DG (0 V) SG (applicable to all types of device) The pin is undefined when in high impedance. SGC (applicable to all types of device) The output voltage is 1/2 VDD. The output resistance is approximately 500 kW. VDD SGC AG 10 819 Single Supply PCM CODEC Application Notes ¡ Semiconductor The state of each analog output pin differs depending on the type of device, as shown below. Power Save Mode Product Name Power Down Mode GSX MSM7508B/7509B MSM7508B/7509B VFRO AOUT AOUT­/AOUT+ GSX VFRO AOUT AOUT­/AOUT+ Hz - HR SG - Hz - HR SG - MSM7578/7579 MSM7578/7579 HR AG - SG - HR AG - HR SG - MSM7543/7544 MSM7543/7544 Hz HR AG - Hz Hz HR AG - Hz MSM7507 MSM7507 HR AG SG - SG HR AG HR SG - Hz MSM7541/7542 MSM7541/7542 HR AG HR AG - Hz HR AG HR AG - Hz MSM7566/7567 MSM7566/7567 HR AG Hz - SG HR AG Hz - HR SG MSM7533/7534 MSM7533/7534 HR AG - SG - HR AG - HR SG - MSM7702 MSM7702 Hz - SG - Hz - HR SG - MSM7704 MSM7704 Hz - SG - Hz - HR SG - MSM7717 MSM7717 HR AG Hz - OP HR AG SG - Hz MSM7705 MSM7705 HR AG - SG - HR AG - SG - Hz HR AG HR SG SG OP 10 820 : High impedance : Connected to AG with several 10 kW : Connected to SGC with several 10 kW : Output the SG voltage with 100 W or less : Operating ¡ Semiconductor Single Supply PCM CODEC Application Notes 7. Analog Noise Dependent Upon the Power Down/Power Save States AOUT (MSM7508B/7509B MSM7508B/7509B) PWD Power Save/Down Mode 5 ms SG AOUT Noise is output 5 ms after the rising edge of DPWD signal. Noise level : ­30 dBm0 to ­40 dBm0 Noise frequency : 1 kHz to 2 kHz This noise level is lower than those of the MSM7541/7542/7543/7544 MSM7541/7542/7543/7544 product families. The noise level in MSM7566/7567/7533/7534/7507/7702/7578/7579 is lower still. AOUT+/AOUT­ (MSM7541/7542/7543/7544 MSM7541/7542/7543/7544) Power Save/Down Mode PWD 5 ms AOUT+/AOUT­ Noise Similar to the MSM7508B/7509B MSM7508B/7509B SG AG Comparatively High Noise Jitter noise is likely to be generated at the syncronizing signal in the wireless system in particular, but when jitter noises continue for 500 ns or more, even if communication is in progress, the device may enter power save mode. At that time, AOUT outputs noise. Generally in a device like the CODEC, it is difficult to design a device free from a noise. With the MSM7541/7542/7543/7544 MSM7541/7542/7543/7544 series, the noise generated is higher than in the MSM7508B MSM7508B and MSM7509B MSM7509B. With the MSM7541/7542/7543/7544 MSM7541/7542/7543/7544 series, the control of power saving by the RSYNC is not provided because noise is easily generated at RSYNC. 10 821 Single Supply PCM CODEC Application Notes ¡ Semiconductor 8. The Burst Mode Clock In the single supply series CODEC, the device can be operated by a burst mode clock. BCLOCK 1 2 3 4 5 6 7 8 9 1 2 3 4 5 XSYNC/RSYNC 125 ms Sync Signal Pulse Width : Min. 1 bit clock : Max. (Number of clocks in burst mode)­1 Bit clocks 1 to 8 are used for PCM data transfer, bit clock 9 is used for starting the internal operation of the CODEC, so that at least 9 bits are needed (except an operation at 64 kHz). When the bit clock frequency is 64 kbps, 8 bit clocks are required, for the device to operate, but this is not a burst mode clock operation. In this case the maximum cycle time of a synchronizing signal is 100 ms (exactly 109.375 ms). When the bit clock signal BCLOCK stops, the device goes to power save mode. A BCLOCK SYNC 1 2 1 3 4 9 2 Whether or not the bit clock and the SYNC signal exist at the same time is monitored at each SYNC signal timing at the rising edge of the bit clocks. In the above figure, the BCLOCK signal does not exist at the point "A", so the device is operating in power save mode. Practically, the device goes to power save mode after a certain time elapses from the point "A". 10 822 ¡ Semiconductor Single Supply PCM CODEC Application Notes 9. Interfaces Between the Device Input and a Microphone Output According to the analog input specified for MSM7543 MSM7543, the maximum input level of the MSM7543 MSM7543 GSX pin is 1.2 Vo-p and the +3 dBm0 digital pattern is output from the PCMOUT pin. Normally the gain of the average speed level is set to ­15 dBm0 for voice devices, which is equivalent to the signal level of 0.15 Vo-p for the MSM7543 MSM7543 GSX pin (0.088 Vo-p at the MSM7541 MSM7541). If the average signal level from a microphone unit is X Vo-p, the gain required for the analog input of the MSM7543 MSM7543 is as shown below. G = 20 log 0.151/X 151/X dB Since the maximum input amplifier gain can be set to +20 dB, if the above value of gain G is lower than +20 dB, only the gain setting of the input amplifier is required. But if the value of G is higher than +20 dB, a microphone preamplifier must be added. Fig. 1 shows an example of a circuit with a preamplifier added. +5 V 5+5 V 5+5 V 10 W Zenor 10 mF 5.1 kW VDD AIN­ 51 kW GSX AIN+ SG MIC. Unit MIC. Amplifier 1 mF to 10 mF (Connect if needed) Figure 1 Note : In Fig. 1, the amplifier gain of the MSM7543 MSM7543 analog input is assumed to be +20 dB, and a resistance of 10 W and a capacitance of 10 mF should be connected to the power supply for decoupling use if needed. 10 823 Single Supply PCM CODEC Application Notes ¡ Semiconductor 10. Interface Between the Device Output and a Speaker Input The MSM7543 MSM7543 analog output has the minimum differential output load resistance of 1.2 kW. This value is defined to assure an output amplitude of AOUT+/AOUT­ and the total distortion at the level of the catalog. If the requirements usage are satisfied, the value of the load resistance may be less than 1.2 kW. The direct driving of a dynamic type speaker having an impedance of less than 1.2 kW should be tested by the user. An example of a peripheral circuit when using the device to drive a speaker directly is shown in Fig. 2. An example of a peripheral circuit when adding a preamplifier to the device is shown in Fig. 3. VFRO Maximum output amplitude at VFRO : 1.2 Vo-p R1 : 51 kW R2 : 51 kW C1 and C2 are for adjustment of frequency characteristics. When the f-characteristic is flat, C1 : 0.1 mF C2 : Not used C3 is used for preventing the DC-current between AOUT+ and AOUT­. C3 : 47 mF C1 R1 PWI C2 R2 AOUT­ AOUT+ C3 Figure 2 In Fig. 2 the gain setting is defined at 0 dB, but if an output level of a speaker is higher in this state, a resistor should be connected in series with the capacitor C3. The characteristics of output amplitude and harmonic distortion are improved, as a consequence of converting this resistance. R3 : 51 kW R4 : Should be adjusted. VFRO R3 R4 6 3 AOUT­ AOUT+ 10 Refer to the data sheet prepared by the National Semiconductor Co., for the peripheral circuit of LM386 LM386. +5 V PWI 5 2 4 0V 7 LM386 LM386 Figure 3 824 ¡ Semiconductor Single Supply PCM CODEC Application Notes 11. An Example of a Circuit Connected to a Telephone Line MSM7543/7544 MSM7543/7544 0.1 mF 51 kW AIN­ Line PCMOUT R1 Transformer 0V GSX 300 W AOUT+ Line Transformer PCMIN AOUT­ 300 W Note : The value of R1 in the above diagram is 600 W, but a resistor between 550 W and 600 W is used for a transformer coil resistance. 10 825