E2000 CK505 CK410 32-KB E2160 E2140 E2200 E2220 E2180 IA-32 LGA775 TESTHI8/FC42 - Datasheet Archive

 

Processor E2000 Series Datasheet March 2008 Document Number: 316981-005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION

 

Intel® Pentium® Dual-Core Desktop Processor E2000 E2000 Series Datasheet March 2008 Document Number: 316981-005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/ processor_number for details. Intel® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software configurations. See http://www.intel.com/technology/intel64/index.htm for more information including details on which processors support Intel 64, or consult with your system vendor for more information. Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality. The Intel® Pentium® Dual-Core Desktop processor E2000 E2000 series may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Not all specified units of this processor support Thermal Monitor 2, Enhanced HALT State and Enhanced Intel SpeedStep® Technology. See the Processor Spec Finder at http://processorfinder.intel.com or contact your Intel representative for more information." Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Intel, Pentium, Intel SpeedStep, Intel Core, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2007­2008 Intel Corporation. 2 Datasheet Contents 1 Introduction . 9 1.1 Terminology . 9 1.1.1 Processor Terminology . 10 1.2 References . 11 2 Electrical Specifications . 13 2.1 Power and Ground Lands. 13 2.2 Decoupling Guidelines . 13 2.2.1 VCC Decoupling . 13 2.2.2 Vtt Decoupling . 13 2.2.3 FSB Decoupling. 14 2.3 Voltage Identification . 14 2.4 Market Segment Identification (MSID) . 16 2.5 Reserved, Unused, and TESTHI Signals . 16 2.6 Voltage and Current Specification . 17 2.6.1 Absolute Maximum and Minimum Ratings . 17 2.6.2 DC Voltage and Current Specification . 19 2.6.3 Vcc Overshoot . 21 2.6.4 Die Voltage Validation . 22 2.7 Signaling Specifications. 22 2.7.1 FSB Signal Groups. 23 2.7.2 CMOS and Open Drain Signals . 24 2.7.3 Processor DC Specifications . 25 2.7.3.1 GTL+ Front Side Bus Specifications . 26 2.8 Clock Specifications . 28 2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking . 28 2.8.2 FSB Frequency Select Signals (BSEL[2:0]). 28 2.8.3 Phase Lock Loop (PLL) and Filter . 29 2.8.4 BCLK[1:0] Specifications (CK505 CK505 based Platforms) . 29 2.8.5 BCLK[1:0] Specifications (CK410 CK410 based Platforms) . 31 2.9 PECI DC Specifications . 32 3 Package Mechanical Specifications . 33 3.1 Package Mechanical Drawing. 33 3.2 Processor Component Keep-Out Zones . 37 3.3 Package Loading Specifications . 37 3.4 Package Handling Guidelines. 37 3.5 Package Insertion Specifications. 38 3.6 Processor Mass Specification . 38 3.7 Processor Materials. 38 3.8 Processor Markings. 38 3.9 Processor Land Coordinates . 39 4 Land Listing and Signal Descriptions . 41 4.1 Processor Land Assignments . 41 4.2 Alphabetical Signals Reference . 64 5 Thermal Specifications and Design Considerations . 73 5.1 Processor Thermal Specifications . 73 5.1.1 Thermal Specifications . 73 5.1.2 Thermal Metrology . 77 5.2 Processor Thermal Features . 77 5.2.1 Thermal Monitor. 77 Datasheet 3 5.3 5.4 5.2.2 Thermal Monitor 2 .78 5.2.3 On-Demand Mode .79 5.2.4 PROCHOT# Signal .80 5.2.5 THERMTRIP# Signal .80 Thermal Diode.81 Platform Environment Control Interface (PECI) .83 5.4.1 Introduction .83 5.4.1.1 Key Difference with Legacy Diode-Based Thermal Management .83 5.4.2 PECI Specifications .85 5.4.2.1 PECI Device Address.85 5.4.2.2 PECI Command Support .85 5.4.2.3 PECI Fault Handling Requirements .85 5.4.2.4 PECI GetTemp0() Error Code Support .85 6 Features .87 6.1 Power-On Configuration Options .87 6.2 Clock Control and Low Power States .88 6.2.1 Normal State .88 6.2.2 HALT and Extended HALT Powerdown States .88 6.2.2.1 HALT Powerdown State .89 6.2.2.2 Extended HALT Powerdown State .89 6.2.3 Stop Grant and Extended Stop Grant States .89 6.2.3.1 Stop-Grant State.90 6.2.3.2 Extended Stop Grant State .90 6.2.4 Extended HALT Snoop State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State.90 6.2.4.1 HALT Snoop State, Stop Grant Snoop State .90 6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State.91 6.3 Enhanced Intel SpeedStep® Technology .91 7 Boxed Processor Specifications.93 7.1 Mechanical Specifications .94 7.1.1 Boxed Processor Cooling Solution Dimensions.94 7.1.2 Boxed Processor Fan Heatsink Weight .96 7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly .96 7.2 Electrical Requirements .96 7.2.1 Fan Heatsink Power Supply .96 7.3 Thermal Specifications.98 7.3.1 Boxed Processor Cooling Requirements.98 7.3.2 Fan Speed Control Operation (Intel® Pentium® Dual-Core Desktop Processor E2000 E2000 Series) . 100 8 Debug Tools Specifications . 103 8.1 Logic Analyzer Interface (LAI) . 103 8.1.1 Mechanical Considerations . 103 8.1.2 Electrical Considerations . 103 4 Datasheet Figures 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Datasheet VCC Static and Transient Tolerance for Processors. 21 VCC Overshoot Example Waveform . 22 Differential Clock Waveform . 30 Differential Clock Crosspoint Specification . 30 Differential Measurements. 30 Differential Clock Crosspoint Specification . 31 Processor Package Assembly Sketch . 33 Processor Package Drawing Sheet 1 of 3 . 34 Processor Package Drawing Sheet 2 of 3 . 35 Processor Package Drawing Sheet 3 of 3 . 36 Processor Top-Side Markings Example . 38 Processor Land Coordinates and Quadrants, Top View . 39 land-out Diagram (Top View ­ Left Side) . 42 land-out Diagram (Top View ­ Right Side) . 43 Thermal Profile (Intel® Pentium® Dual-Core Processors with CPUID = 06F2h). 75 Thermal Profile (Intel® Pentium® Dual-Core Processors with CPUID = 06FDh) . 76 Case Temperature (TC) Measurement Location . 77 Thermal Monitor 2 Frequency and Voltage Ordering . 79 Processor PECI Topology . 83 Conceptual Fan Control on PECI-Based Platforms . 84 Conceptual Fan Control on Thermal Diode-Based Platforms. 84 Processor Low Power State Machine . 88 Mechanical Representation of the Boxed Processor . 93 Space Requirements for the Boxed Processor (Side View). 94 Space Requirements for the Boxed Processor (Top View). 95 Space Requirements for the Boxed Processor (Overall View) . 95 Boxed Processor Fan Heatsink Power Cable Connector Description . 97 Baseboard Power Header Placement Relative to Processor Socket . 98 Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view) . 99 Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View). 99 Boxed Processor Fan Heatsink Set Points. 100 5 Tables 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 6 References .11 Voltage Identification Definition .15 Market Segment Selection Truth Table for MSID[1:0], , , .16 Absolute Maximum and Minimum Ratings .18 Voltage and Current Specifications.19 VCC Static and Transient Tolerance for Processors .20 VCC Overshoot Specifications.21 FSB Signal Groups .23 Signal Characteristics.24 Signal Reference Voltages .24 GTL+ Signal Group DC Specifications .25 Open Drain and TAP Output Signal Group DC Specifications .25 CMOS Signal Group DC Specifications.26 GTL+ Bus Voltage Definitions .27 Core Frequency to FSB Multiplier Configuration.28 BSEL[2:0] Frequency Table for BCLK[1:0] .29 Front Side Bus Differential BCLK Specifications .29 Front Side Bus Differential BCLK Specifications .31 PECI DC Electrical Limits .32 Processor Loading Specifications.37 Package Handling Guidelines.37 Processor Materials .38 Alphabetical Land Assignments.44 Numerical Land Assignment .54 Signal Description.64 Processor Thermal Specifications .74 Thermal Profile (Intel® Pentium® Dual-Core Processors with CPUID = 06F2h) .75 Thermal Profile (Intel® Pentium® Dual-Core Processors with CPUID = 06FDh) .76 Thermal "Diode" Parameters using Diode Model .81 Thermal "Diode" Parameters using Transistor Model .82 Thermal Diode Interface .82 GetTemp0() Error Codes .85 Power-On Configuration Option Signals .87 Fan Heatsink Power and Signal Specifications .97 Fan Heatsink Power and Signal Specifications . 101 Datasheet Intel® Pentium® Dual-Core Desktop Processor E2000 E2000 Series · Available at 2.4 GHz, 2.2 GHz, 2.0 GHz, 1.80 GHz, and 1.60 GHz · Enhanced Intel SpeedStep® Technology · Supports Intel® 64 architecture · Supports Execute Disable Bit capability · Binary compatible with applications running on previous members of the Intel microprocessor line · FSB frequency at 800 MHz · · · · Advance Dynamic Execution Very deep out-of-order execution Enhanced branch prediction Optimized for 32-bit applications running on advanced 32-bit operating systems · · · · · · · · · Two 32-KB 32-KB Level 1 data caches 1 MB Advanced Smart Cache Advanced Digital Media Boost Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance Power Management capabilities System Management mode Multiple low-power states 8-way cache associativity provides improved cache hit rate on load/store operations 775-land Package The Intel Pentium® Dual-Core desktop processor E2000 E2000 series deliver Intel's advanced, powerful processors for desktop PCs. The processor is designed to deliver performance across applications and usages where end-users can truly appreciate and experience the performance. These applications include Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and multitasking user environments. Intel® 64 architecture enables the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture. The processor supporting Enhanced Intel SpeedStep® technology allows tradeoffs to be made between performance and power consumption. The Intel Pentium® Dual-Core desktop processor E2000 E2000 series also includes the Execute Disable Bit capability. This feature, combined with a supported operating system, allows memory to be marked as executable or non-executable. §§ Datasheet 7 Revision History Revision Number -001 -002 Description · Initial release Date June 2007 ® ® · Added specifications for Intel · Added specifications for Intel® Pentium® Dual-Core Desktop processor E2160 E2160 and E2140 E2140 for a second thermal profile (See Table 26) September 2007 -004 · Added specifications for Intel® Pentium® Dual-Core Desktop processor E2200 E2200 December 2007 -005 · Added specifications for Intel® Pentium® Dual-Core Desktop processor E2220 E2220 March 2008 -003 Pentium Dual-Core Desktop processor E2180 E2180 August 2007 §§ 8 Datasheet Introduction 1 Introduction The Intel® Pentium® Dual-Core Desktop processor E2000 E2000 series combines the performance of the current generation of desktop products with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems. These dual-core processors are based on 65 nm process technology. They are 64-bit processors that maintain compatibility with IA-32 IA-32 software. The Intel® Pentium® Dual-Core Desktop processor E2000 E2000 series uses Flip-Chip Land Grid Array (FC-LGA6) package technology, and plugs into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the LGA775 LGA775 socket. Note: In this document, unless otherwise specified, the Intel® Pentium® Dual-Core Desktop processor E2000 E2000 series refers to Intel® Pentium® Dual-Core Desktop processor E2220 E2220, E2200 E2200, E2180 E2180, E2160 E2160, and E2140 E2140. Note: In this document, unless otherwise specified, the Intel® Pentium® Dual-Core Desktop processor E2000 E2000 series is referred to as "processor." The processor supports advanced technologies including Execute Disable Bit, Intel® 64 architecture, and Enhanced Intel SpeedStep® technology. The processor's front side bus (FSB) uses a split-transaction, deferred reply protocol like the Intel® Pentium® 4 processor. The FSB uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "doubleclocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 8.5 GB/s. Intel will enable support components for the processor including heatsink, heatsink retention mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling. The processor includes an address bus power-down capability which removes power from the address and data signals when the FSB is not in use. This feature is always enabled on the processor. 1.1 Terminology A `#' symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the `#' symbol implies that the signal is inverted. For example, D[3:0] = `HLHL' refers to a hex `A', and D[3:0]# = `LHLH' also refers to a hex `A' (H= High logic level, L= Low logic level). Front Side Bus" refers to the interface between the processor and system core logic (a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O. Datasheet 9 Introduction 1.1.1 Processor Terminology Commonly used terms are explained here for clarification: · Intel® Pentium® Dual-Core Desktop processor E2000 E2000 series - Dual core processor in the FC-LGA6 package with a 1 MB L2 cache. · Processor - For this document, the term processor is the generic form of the Intel® Pentium® Dual-Core Desktop processor E2000 E2000 series. The processor is a single package that contains one or more execution units. · Keep-out zone - The area on or near the processor that system design can not use. · Processor core - Processor core die with integrated L2 cache. · LGA775 LGA775 socket - The processors mate with the system board through a surface mount, 775-land, LGA socket. · Integrated heat spreader (IHS) -A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface. · Retention mechanism (RM) - Since the LGA775 LGA775 socket does not include any mechanical features for heatsink attach, a retention mechanism is required. Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket. · FSB (Front Side Bus) - The electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB. · Storage conditions - Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks. Upon exposure to "free air"(i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material. · Functional operation - Refers to normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical and thermal are satisfied. · Execute Disable Bit - The Execute Disable bit allows memory to be marked as executable or non-executable, when combined with a supporting operating system. If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system. See the Intel® Architecture Software Developer's Manual for more detailed information. · Intel® 64 Architecture - An enhancement to Intel's IA-32 IA-32 architecture, allowing the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture. Further details on Intel 64 architecture and programming model can be found in the Intel Extended Memory 64 Technology Software Developer Guide at http://developer.intel.com/technology/ 64bitextensions/. · Enhanced Intel SpeedStep® Technology - Enhanced Intel SpeedStep technology allows trade-offs to be made between performance and power consumptions, based on processor utilization. This may lower average power consumption (in conjunction with OS support). 10 Datasheet Introduction 1.2 References Material and concepts available in the following documents may be beneficial when reading this document. Table 1. References Document Location Intel® Pentium® Dual-Core Desktop Processor E2000 E2000 Series Specification Update http://www.intel.com// design/processor/ specupdt/316982.htm Intel® CoreTM2 Duo Processor and Intel® Pentium® Dual Core Thermal and Mechanical Design Guidelines http://www.intel.com/ design/processor/ designex/317804.htm Intel® Pentium® D Processor, Intel® Pentium® Processor Extreme Edition, Intel® Pentium® 4 Processor, and Intel® CoreTM2 Duo Extreme Processor Thermal and Mechanical Design Guidelines. http://www.intel.com/ design/pentiumXE/ designex/306830.htm Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 LGA775 Socket http://www.intel.com/ design/processor/ applnots/313214.htm http://intel.com/ design/Pentium4/ guides/302666.htm LGA775 LGA775 Socket Mechanical Design Guide Intel® 64 and IA-32 IA-32 Architecture Software Developer's Manuals Intel® 64 and IA-32 IA-32 Architecture Software Developer's Manual Volume 1: Basic Architecture Intel® 64 and IA-32 IA-32 Architecture Software Developer's Manual Volume 2A: Instruction Set Reference Manual A­M Intel® 64 and IA-32 IA-32 Architecture Software Developer's Manual Volume 2B: Instruction Set Reference Manual, N­Z http://www.intel.com/ products/processor/ manuals/ Intel® 64 and IA-32 IA-32 Architecture Software Developer's Manual Volume 3A: System Programming Guide Intel® 64 and IA-32 IA-32 Architecture Software Developer's Manual Volume 3B: System Programming Guide §§ Datasheet 11 Introduction 12 Datasheet Electrical Specifications 2 Electrical Specifications This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided. 2.1 Power and Ground Lands The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to VCC, while all VSS lands must be connected to a system ground plane. The processor VCC lands must be supplied the voltage determined by the Voltage IDentification (VID) lands. The signals denoted as VTT provide termination for the front side bus and power to the I/O buffers. A separate supply must be implemented for these lands, that meets the VTT specifications outlined in Table 5. 2.2 Decoupling Guidelines Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings. This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate. Larger bulk storage (CBULK), such as electrolytic or aluminum-polymer capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications listed in Table 5. Failure to do so can result in timing violations or reduced lifetime of the component. 2.2.1 VCC Decoupling VCC regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications. This includes bulk capacitance with low effective series resistance (ESR) to keep the voltage rail within specifications during large swings in load current. In addition, ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity. Consult the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 LGA775 Socket for further information. 2.2.2 VTT Decoupling Decoupling must be provided on the motherboard. Decoupling solutions must be sized to meet the expected load. To ensure compliance with the specifications, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors. Datasheet 13 Electrical Specifications 2.2.3 FSB Decoupling The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package. However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation. 2.3 Voltage Identification The Voltage Identification (VID) specification for the processor is defined by the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 LGA775 Socket. The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor VCC pins (see Section 2.6.3 for VCC overshoot specifications). Refer to Table 13 for the DC specifications for these signals. Voltages for each processor frequency is provided in Table 5. Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings. This is reflected by the VID Range values provided in Table 5. Refer to the Intel® Pentium® Dual-Core Desktop Processor E2000 E2000 Series Specification Update for further details on specific valid core frequency and VID values of the processor. Note this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep® Technology, or Enhanced HALT State). The processor uses six voltage identification signals, VID[6:1], to support automatic selection of power supply voltages. Table 2 specifies the voltage level corresponding to the state of VID[6:1]. A `1' in this table refers to a high voltage level and a `0' refers to a low voltage level. If the processor socket is empty (VID[6:1] = 111111), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. The Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 LGA775 Socket defines VID [7:0], VID7 and VID0 are not used on the processor; VID0 and VID7 are strapped to VSS on the processor package. VID0 and VID7 must be connected to the VR controller for compatibility with future processors. The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (VCC). This will represent a DC shift in the load line. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target core voltage. Transitions above the specified VID are not permitted. Table 5 includes VID step sizes and DC shift ranges. Minimum and maximum voltages must be maintained as shown in Table 6 and Figure 1 as measured across the VCC_SENSE and VSS_SENSE lands. The VRM or VRD used must be capable of regulating its output to the value defined by the new VID. DC specifications for dynamic VID transitions are included in Table 5 and Table 6. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 LGA775 Socket for further details. 14 Datasheet Electrical Specifications Table 2. Voltage Identification Definition VID6 VID5 1 1 1 1 0 1 0.8500 0 1 1 1 1 0 1.2375 1 1 1 1 0 0 0.8625 0 1 1 1 0 1 1.2500 1 1 1 0 1 1 0.8750 0 1 1 1 0 0 1.2625 1 1 1 0 1 0 0.8875 0 1 1 0 1 1 1.2750 1 1 1 0 0 1 0.9000 0 1 1 0 1 0 1.2875 1 1 1 0 0 0 0.9125 0 1 1 0 0 1 1.3000 1 1 0 1 1 1 0.9250 0 1 1 0 0 0 1.3125 1 1 0 1 1 0 0.9375 0 1 0 1 1 1 1.3250 1 1 0 1 0 1 0.9500 0 1 0 1 1 0 1.3375 1 1 0 1 0 0 0.9625 0 1 0 1 0 1 1.3500 1 1 0 0 1 1 0.9750 0 1 0 1 0 0 1.3625 1 1 0 0 1 0 0.9875 0 1 0 0 1 1 1.3750 1 1 0 0 0 1 1.0000 0 1 0 0 1 0 1.3875 1 1 0 0 0 0 1.0125 0 1 0 0 0 1 1.4000 1 0 1 1 1 1 1.0250 0 1 0 0 0 0 1.4125 1 0 1 1 1 0 1.0375 0 0 1 1 1 1 1.4250 1 0 1 1 0 1 1.0500 0 0 1 1 1 0 1.4375 1 0 1 1 0 0 1.0625 0 0 1 1 0 1 1.4500 1 0 1 0 1 1 1.0750 0 0 1 1 0 0 1.4625 1 0 1 0 1 0 1.0875 0 0 1 0 1 1 1.4750 1 0 1 0 0 1 1.1000 0 0 1 0 1 0 1.4875 1 0 1 0 0 0 1.1125 0 0 1 0 0 1 1.5000 1 0 0 1 1 1 1.1250 0 0 1 0 0 0 1.5125 1 0 0 1 1 0 1.1375 0 0 0 1 1 1 1.5250 1 0 0 1 0 1 1.1500 0 0 0 1 1 0 1.5375 1 0 0 1 0 0 1.1625 0 0 0 1 0 1 1.5500 1 0 0 0 1 1 1.1750 0 0 0 1 0 0 1.5625 1 0 0 0 1 0 1.1875 0 0 0 0 1 1 1.5750 1 0 0 0 0 1 1.2000 0 0 0 0 1 0 1.5875 1 0 0 0 0 0 1.2125 0 0 0 0 0 1 1.6000 0 1 1 1 1 1 1.2250 0 0 0 0 0 0 OFF Datasheet VID4 VID3 VID2 VID1 VCC_MAX VID6 VID5 VID4 VID3 VID2 VID1 VCC_MAX 15 Electrical Specifications 2.4 Market Segment Identification (MSID) The MSID[1:0] signals may be used as outputs to determine the Market Segment of the processor. Table 3 provides details regarding the state of MSID[1:0]. A circuit can be used to prevent 130 W TDP processors from booting on boards optimized for 65 W TDP. Table 3. Market Segment Selection Truth Table for MSID[1:0]1, 2, 3, 4 MSID1 MSID0 Description 0 0 Intel® Pentium® Dual-Core Desktop processor E2000 E2000 series 0 1 Reserved 1 0 Reserved 1 1 Reserved NOTES: 1. The MSID[1:0] signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying. Circuitry on the motherboard may use these signals to identify the processor installed. 2. These signals are not connected to the processor die. 3. A logic 0 is achieved by pulling the signal to ground on the package. 4. A logic 1 is achieved by leaving the signal as a no connect on the package. 2.5 Reserved, Unused, and TESTHI Signals All RESERVED lands must remain unconnected. Connection of these lands to VCC, VSS, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See Chapter 4 for a land listing of the processor and the location of all RESERVED lands. In a system level design, on-die termination has been included by the processor to allow signals to be terminated within the processor silicon. Most unused GTL+ inputs should be left as no connects as GTL+ termination is provided on the processor silicon. However, see Table 8 for details on GTL+ signals that do not include on-die termination. Unused active high inputs, should be connected through a resistor to ground (VSS). Unused outputs can be left unconnected, however this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ± 20% of the impedance of the motherboard trace for front side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the same value as the on-die termination resistors (RTT). For details, see Table 14. TAP and CMOS signals do not include on-die termination. Inputs and used outputs must be terminated on the motherboard. Unused outputs may be terminated on the motherboard or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. All TESTHI[13:0] lands should be individually connected to VTT via a pull-up resistor that matches the nominal trace impedance. 16 Datasheet Electrical Specifications The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group: · TESTHI[1:0] · TESTHI[7:2] · TESTHI8/FC42 TESTHI8/FC42 ­ cannot be grouped with other TESTHI signals · TESTHI9/FC43 TESTHI9/FC43 ­ cannot be grouped with other TESTHI signals · TESTHI10 TESTHI10 ­ cannot be grouped with other TESTHI signals · TESTHI11 TESTHI11 ­ cannot be grouped with other TESTHI signals · TESTHI12/FC44 TESTHI12/FC44 ­ cannot be grouped with other TESTHI signals · TESTHI13 TESTHI13 ­ cannot be grouped with other TESTHI signals However, use of boundary scan test will not be functional if these lands are connected together. For optimum noise margin, all pull-up resistor values used for TESTHI[13:0] lands should have a resistance value within ± 20% of the impedance of the board transmission line traces. For example, if the nominal trace impedance is 50 , then a value between 40 and 60 should be used. 2.6 Voltage and Current Specification 2.6.1 Absolute Maximum and Minimum Ratings Table 4 specifies absolute maximum and minimum ratings only and lie outside the functional limits of the processor. Within functional operation limits, functionality and long-term reliability can be expected. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits. At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded. Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields. Datasheet 17 Electrical Specifications Table 4. Absolute Maximum and Minimum Ratings Symbol Parameter Min Max Unit Notes1, 2 VCC Core voltage with respect to VSS ­0.3 1.55 V - VTT FSB termination voltage with respect to VSS ­0.3 1.55 V - TC Processor case temperature See Chapter 5 See Chapter 5 °C - TSTORAGE Processor storage temperature ­40 85 °C 3, 4, 5 NOTES: 1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied. 2. Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor. 3. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long-term reliability of the device. For functional operation, refer to the processor case temperature specifications. 4. This rating applies to the processor and does not include any tray or packaging. 5. Failure to adhere to this specification can affect the long term reliability of the processor. 18 Datasheet Electrical Specifications 2.6.2 DC Voltage and Current Specification Table 5. Voltage and Current Specifications Symbol VID Range Parameter Min VID 2.4 GHz E2200 E2200 2.2 GHz E2180 E2180 2.0 GHz E2160 E2160 1.5 V Refer to Table 6 and Table 1 V Default VCC voltage for initial power up VCCPLL PLL VCC Processor Number 4, 5, 6 V - - 1.10 - - 5% 1.50 + 5% - - VCC for 775_VR_CONFIG_06 E2220 E2220 2.2 GHz E2180 E2180 2.0 GHz 75 1.8 GHz 75 E2140 E2140 ITT 2.4 GHz E2200 E2200 E2160 E2160 VTT_OUT_LEFT and VTT_OUT_RIGHT ICC 2 1.6 GHz VCC_BOOT VTT Notes1, 1.8 GHz E2140 E2140 ICC Unit VCC for 775_VR_CONFIG_06 E2220 E2220 VCC Max 3 0.8500 Processor Number Typ 1.6 GHz 75 FSB termination voltage (DC + AC specifications) DC Current that may be drawn from VTT_OUT_LEFT and VTT_OUT_RIGHT per pin ICC for VTT supply before VCC stable ICC for VTT supply after VCC stable 75 75 A 7 1.14 1.20 1.26 V 8 - - 580 mA 9 - - A 10 4.5 4.6 ICC_VCCPLL ICC for PLL land - - 130 mA ICC_GTLREF ICC for GTLREF - - 200 A NOTES: 1. Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at a later date. 2. Adherence to the voltage specifications for the processor are required to ensure reliable processor operation. 3. Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Note this differs from the VID employed by the processor during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep® technology, or Extended HALT State). 4. These voltages are targets only. A variable voltage source should exist on systems in the event that a different voltage is required. See Section 2.3 and Table 2 for more information. 5. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 M minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe. 6. Refer to Table 6 and Figure 1 for the minimum, typical, and maximum VCC allowed for a given current. The processor should not be subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current. 7. ICC_MAX specification is based on the VCC_MAX loadline. Refer to Figure 1 for details. 8. VTT must be provided via a separate voltage source and not be connected to VCC. This specification is measured at the land. 9. Baseboard bandwidth is limited to 20 MHz. 10.This is maximum total current drawn from VTT plane by only the processor. This specification does not include the current coming from RTT (through the signal line). Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 LGA775 Socket to determine the total ITT drawn by the system. This parameter is based on design characterization and is not tested. Datasheet 19 Electrical Specifications Table 6. VCC Static and Transient Tolerance for Processors Voltage Deviation from VID Setting (V)1, 2, 3, 4 ICC (A) Maximum Voltage 1.30 m Typical Voltage 1.425 m Minimum Voltage 1.55 m 0 0.000 -0.019 -0.038 5 -0.007 -0.026 -0.046 10 -0.013 -0.033 -0.054 15 -0.020 -0.040 -0.061 20 -0.026 -0.048 -0.069 25 -0.033 -0.055 -0.077 30 -0.039 -0.062 -0.085 35 -0.046 -0.069 -0.092 40 -0.052 -0.076 -0.100 45 -0.059 -0.083 -0.108 50 -0.065 -0.090 -0.116 55 -0.072 -0.097 -0.123 60 -0.078 -0.105 -0.131 65 -0.085 -0.112 -0.139 70 -0.091 -0.119 -0.147 75 -0.098 -0.126 -0.154 NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.6.3. 2. This table is intended to aid in reading discrete points on Figure 1. 3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 LGA775 Socket for socket loadline guidelines and VR implementation details. 4. Adherence to this loadline specification is required to ensure reliable processor operation. 20 Datasheet Electrical Specifications Figure 1. VCC Static and Transient Tolerance for Processors ICC (A) 0 10 VID ­ 0.000 VID ­ 0.013 20 40 30 VID ­ 0.025 50 60 70 VCC Maximum VID ­ 0.038 VID ­ 0.050 VID ­ 0.063 VCC (V) VID ­ 0.075 VID ­ 0.088 VCC Typical VID ­ 0.100 VID ­ 0.113 VCC Minimum VID ­ 0.125 VID ­ 0.138 VID ­ 0.150 VID ­ 0.163 NOTES: 1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in Section 2.6.3. 2. This loadline specification shows the deviation from the VID set point. 3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For Desktop LGA775 LGA775 Socket for socket loadline guidelines and VR implementation details. 2.6.3 VCC Overshoot The processor can tolerate short transient overshoot events where VCC exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the maximum allowable overshoot voltage). The time duration of the overshoot event must not exceed TOS_MAX (TOS_MAX is the maximum allowable time duration above VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands. Table 7. VCC Overshoot Specifications Symbol Parameter Min Max Unit Figure Notes VOS_MAX Magnitude of VCC overshoot above VID - 50 mV 2 1 TOS_MAX Time duration of VCC overshoot above VID - 25 s 2 1 NOTES: 1. Adherence to these specifications is required to ensure reliable processor operation. Datasheet 21 Electrical Specifications Figure 2. VCC Overshoot Example Waveform Example Overshoot Waveform VOS Voltage [V] VID + 0.050 VID - 0.000 TOS 0 5 10 15 20 25 Time [us] TOS: Overshoot time above VID VOS: Overshoot above VID NOTES: 1. VOS is measured overshoot voltage. 2. TOS is measured time duration above VID. 2.6.4 Die Voltage Validation Overshoot events on processor must meet the specifications in Table 7 when measured across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to 100 MHz bandwidth limit. 2.7 Signaling Specifications Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates. Platforms implement a termination voltage level for GTL+ signals defined as VTT. Because platforms implement separate power planes for each processor (and chipset), separate VCC and VTT supplies are necessary. This configuration allows for improved noise tolerance as processor frequency increases. Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families. The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the motherboard (see Table 14 for GTLREF specifications). Termination resistors (RTT) for GTL+ signals are provided on the processor silicon and are terminated to VTT. Intel chipsets will also provide on-die termination, thus eliminating the need to terminate the bus on the motherboard for most GTL+ signals. 22 Datasheet Electrical Specifications 2.7.1 FSB Signal Groups The front side bus signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers, which use GTLREF[1:0] as a reference level. In this document, the term "GTL+ Input" refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly, "GTL+ Output" refers to the GTL+ output group as well as the GTL+ I/O group when driving. With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the clock cycle. Table 8 identifies which signals are common clock, source synchronous, and asynchronous. Table 8. FSB Signal Groups Signal Group Signals1 Type GTL+ Common Clock Input Synchronous to BCLK[1:0] BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY# GTL+ Common Clock I/O Synchronous to BCLK[1:0] ADS#, BNR#, BPM[5:0]#, BR0#, DBSY#, DRDY#, HIT#, HITM#, LOCK# Signals Associated Strobe REQ[4:0]#, GTL+ Source Synchronous I/O Synchronous to assoc. strobe A[35:17]# A[16:3]#3 3 ADSTB0# ADSTB1# DSTBP1#, DSTBN1# D[47:32]#, DBI2# DSTBP2#, DSTBN2# D[63:48]#, DBI3# Synchronous to BCLK[1:0] DSTBP0#, DSTBN0# D[31:16]#, DBI1# GTL+ Strobes D[15:0]#, DBI0# DSTBP3#, DSTBN3# ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]# CMOS A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, STPCLK#, PWRGOOD, TCK, TDI, TMS, TRST#, BSEL[2:0], VID[6:1] Open Drain Output FERR#/PBE#, IERR#, THERMTRIP#, TDO Open Drain Input/Output PROCHOT#4 FSB Clock Power/Other Clock BCLK[1:0], ITP_CLK[1:0]2 VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA, GTLREF[1:0], COMP[8,3:0], RESERVED, TESTHI[13:0], VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE, VSS_MB_REGULATION, DBR#2, VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL, FCx, PECI, MSID[1:0] NOTES: 1. Refer to Section 4.2 for signal descriptions. 2. In processor systems where no debug port is implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects. Datasheet 23 Electrical Specifications 3. 4. The value of these signals during the active-to-inactive edge of RESET# defines the processor configuration options. See Section 6.1 for details. PROCHOT# signal type is open drain output and CMOS input. . Table 9. Signal Characteristics Signals with RTT Signals with No RTT A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, LOCK#, PROCHOT#, REQ[4:0]#, RS[2:0]#, TRDY# A20M#, BCLK[1:0], BSEL[2:0], COMP[8,3:0], IGNNE#, INIT#, ITP_CLK[1:0], LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#, SMI#, STPCLK#, TESTHI[13:0], VID[6:1], GTLREF[1:0], TCK, TDI, TMS, TRST#, VTT_SEL, MSID[1:0] Open Drain Signals1 THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#, BR0#, TDO, FCx NOTES: 1. Signals that do not have RTT, nor are actively driven to their high-voltage level. . Table 10. Signal Reference Voltages GTLREF BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#, A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#, TRDY# VTT/2 A20M#, LINT0/INTR, LINT1/NMI, IGNNE#, INIT#, PROCHOT#, PWRGOOD1, SMI#, STPCLK#, TCK1, TDI1, TMS1, TRST#1 NOTES: 1. These signals also have hysteresis added to the reference voltage. See Table 12 for more information. 2.7.2 CMOS and Open Drain Signals Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of the CMOS and Open Drain signals are required to be asserted/deasserted for at least four BCLKs in order for the processor to recognize the proper signal state. See Section 2.7.3 for the DC specifications. See Section 6.2 for additional timing requirements for entering and leaving the low power states. 24 Datasheet Electrical Specifications 2.7.3 Processor DC Specifications The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated. Table 11. GTL+ Signal Group DC Specifications Symbol VIL Parameter Notes1 Min Unit -0.10 Input Low Voltage Max GTLREF ­ 0.10 V 2, 3 GTLREF + 0.10 VTT + 0.10 V 4, 5, 3 Output High Voltage VTT ­ 0.10 VTT V 5, 3 IOL Output Low Current N/A VTT_MAX/ [(RTT_MIN)+(2*RON_MIN)] A - ILI Input Leakage Current N/A ± 100 µA 6 ILO Output Leakage Current N/A ± 100 µA 7 RON Buffer On Resistance 10 13 VIH Input High Voltage VOH NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value. 3. The VTT referred to in these specifications is the instantaneous VTT. 4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value. 5. VIH and VOH may experience excursions above VTT. However, input signal drivers must comply with the signal quality specifications. 6. Leakage to VSS with land held at VTT. 7. Leakage to VTT with land held at 300 mV . Table 12. Open Drain and TAP Output Signal Group DC Specifications Symbol VOL Parameter Output Low Voltage Notes1 Min Max Unit 0 0.20 V - VOH Output High Voltage VTT ­ 0.05 VTT + 0.05 V 2 IOL Output Low Current 16 50 mA 3 ILO Output Leakage Current N/A ± 200 µA 4 NOTES: Unless otherwise noted, all specifications in this table apply to all processor frequencies. 1. 2. 3. 4. Datasheet VOH is determined by the value of the external pull-up resister to VTT. Measured at VTT * 0.2. For Vin between 0 and VOH 25 Electrical Specifications . Table 13. CMOS Signal Group DC Specifications Symbol VIL Parameter Input Low Voltage Notes1 Min Max Unit -0.10 VTT * 0.30 V 2, 3 VIH Input High Voltage VTT * 0.70 VTT + 0.10 V 4, 5, 3 VOL Output Low Voltage -0.10 VTT * 0.10 V 3 VOH Output High Voltage 0.90 * VTT VTT + 0.10 V 6, 5, 3 IOL Output Low Current 1.70 4.70 mA 3, 7 IOH Output High Current 1.70 4.70 mA 3, 7 ILI Input Leakage Current N/A ± 100 µA 8 ILO Output Leakage Current N/A ± 100 µA 9 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value. 3. The VTT referred to in these specifications refers to instantaneous VTT. 4. VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value. 5. VIH and VOH may experience excursions above VTT. However, input signal drivers must comply 6. 7. 8. 9. 2.7.3.1 with the signal quality specifications. All outputs are open drain. IOL is measured at 0.10 * VTT. IOH is measured at 0.90 * VTT. Leakage to VSS with land held at VTT. Leakage to VTT with land held at 300 mV. GTL+ Front Side Bus Specifications In most cases, termination resistors are not required as these are integrated into the processor silicon. See Table 9 for details on which GTL+ signals do not include on-die termination. Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF. Table 14 lists the GTLREF specifications. The GTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits. 26 Datasheet Electrical Specifications Table 14. GTL+ Bus Voltage Definitions Symbol Parameter Min Typ Max Units Notes1 GTLREF_PU GTLREF pull up resistor on Intel 975X and 96x Express Chipset family boards 124 * 0.99 124 124 * 1.01 2 GTLREF_PD GTLREF pull down resistor on Intel 975X and 96x Express Chipset family boards 210 * 0.99 210 210 * 1.01 2 GTLREF_PU GTLREF pull up resistor on Intel Series 3 Express Chipset family boards 100 * 0.99 100 100 * 1.01 2 GTLREF_PD GTLREF pull down resistor on Intel Series 3 Express Chipset family boards 200 * 0.99 200 200 * 1.01 2 RTT Termination Resistance 45 50 55 3 COMP[3:0] COMP Resistance 49.40 49.90 50.40 4 COMP8 COMP Resistance 24.65 24.90 25.15 4 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. GTLREF is to be generated from VTT by a voltage divider of 1% resistors (one divider for each GTLEREF land). 3. RTT is the on-die termination resistance measured at VTT/3 of the GTL+ output driver. 4. COMP resistance must be provided on the system board with 1% resistors. COMP[3:0] and COMP8 resistors are to VSS. Datasheet 27 Electrical Specifications 2.8 Clock Specifications 2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor's core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during manufacturing. Refer to Table 15 for the processor supported ratios. The processor uses a differential clocking implementation. For more information on the processor clocking, contact your Intel field representative. Platforms using a CK505 CK505 Clock Synthesizer/Driver should comply with the specifications in Section 2.8.4. Platforms using a CK410 CK410 Clock Synthesizer/Driver should comply with the specifications in Section 2.8.5. Table 15. Core Frequency to FSB Multiplier Configuration Multiplication of System Core Frequency to FSB Frequency Core Frequency (200 MHz BCLK/800 BCLK/800 MHz FSB) 1/6 1.20 GHz - 1/7 1.40 GHz - 1/8 1.60 GHz - 1/9 1.80 GHz - 1/10 2 GHz - 1/11 2.2 GHz - 1/12 2.4 GHz - Notes1, 2 NOTES: 1. Individual processors operate only at or below the rated frequency. 2. Listed frequencies are not necessarily committed production frequencies. 2.8.2 FSB Frequency Select Signals (BSEL[2:0]) The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]). Table 16 defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency. The Intel Pentium Dual-Core Desktop processor E2000 E2000 series operates at a 800 MHz FSB frequency (selected by a 200 MHz BCLK[1:0] frequency). 28 Datasheet Electrical Specifications Table 16. BSEL[2:0] Frequency Table for BCLK[1:0] BSEL2 BSEL1 BSEL0 FSB Frequency L L L RESERVED L L H RESERVED L H H RESERVED L L 200 MHz H L RESERVED H H H RESERVED H L H RESERVED H 2.8.3 H H L L RESERVED Phase Lock Loop (PLL) and Filter An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is used for the PLL. Refer to Table 5 for DC specifications. 2.8.4 BCLK[1:0] Specifications (CK505 CK505 based Platforms) Table 17. Front Side Bus Differential BCLK Specifications Symbol Parameter Min Typ Max Unit Figure Notes1 VL Input Low Voltage -0.30 N/A N/A V 3 2 VH Input High Voltage N/A N/A 1.15 V 3 2 0.300 N/A 0.550 V 3, 4 3,4 5 Range of Crossing Points N/A N/A 0.140 V 3, 4 4 VOS Overshoot N/A N/A 1.4 V 3 6 VUS Undershoot -0.300 N/A N/A V 3 6 Differential Output Swing 0.300 N/A N/A V 5 7 Input Leakage Current -5 N/A 5 A Pad Capacitance .95 1.2 1.45 pF VCROSS(abs) VCROSS VSWING ILI Cpad Absolute Crossing Point 8 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. "Steady state" voltage, not including overshoot or undershoot. 3. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1. 4. VHavg is the statistical average of the VH measured by the oscilloscope. 5. The crossing point must meet the absolute and relative crossing point specifications simultaneously. 6. Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as the absolute value of the minimum voltage. 7. Measurement taken from differential waveform. 8. Cpad includes die capacitance only. No package parasitics are included. Datasheet 29 Electrical Specifications Figure 3. Differential Clock Waveform CLK 0 VCROSS Median + 75 mV VCROSS median VCROSS VCROSS Max 550 mV VCROSS VCROSS Min 300 mV Median - 75 mV CLK 1 High Time median Low Time Period Figure 4. Differential Clock Crosspoint Specification 650 Crossing Point (mV) 600 550 550 mV 500 450 550 + 0.5 (VHavg - 700) 400 300 + 0.5 (VHavg - 700) 350 300 250 300 mV 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg (mV) Figure 5. Differential Measurements Slew_rise Slew _fall +150 mV 0.0V -150 mV +150mV V_swing 0.0V -150mV Diff 30 Datasheet Electrical Specifications 2.8.5 BCLK[1:0] Specifications (CK410 CK410 based Platforms) Table 18. Front Side Bus Differential BCLK Specifications Symbol Min Parameter Typ Max Unit Figure Notes1 VL Input Low Voltage -0.150 0.00 0 N/A V 3 - VH Input High Voltage 0.660 0.70 0 0.850 V 3 - VCROSS(abs) Absolute Crossing Point 0.250 N/A 0.550 V 3, 4 2, 3 VCROSS(rel) Relative Crossing Point 0.250 + 0.5(VHavg ­ 0.700) N/A 0.550 + 0.5(VHavg ­ 0.700) V 3, 4 4, 3, 5 VCROSS Range of Crossing Points N/A N/A 0.140 V 3, 4 - VOS Overshoot N/A N/A VH + 0.3 V 3 6 VUS Undershoot -0.300 N/A N/A V 3 7 VRBM Ringback Margin 0.200 N/A N/A V 3 8 VTM Threshold Region VCROSS ­ 0.100 N/A VCROSS + 0.100 V 3 9 NOTES: 1. Unless otherwise noted, all specifications in this table apply to all processor frequencies. 2. Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 equals the falling edge of BCLK1. The crossing point must meet the absolute and relative crossing point specifications simultaneously. VHavg is the statistical average of the VH measured by the oscilloscope. VHavg can be measured directly using "Vtop" on Agilent* oscilloscopes and "High" on Tektronix* oscilloscopes. vershoot is defined as the absolute value of the maximum voltage. Undershoot is defined as the absolute value of the minimum voltage. Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback and the maximum Falling Edge Ringback. 9. Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis. 3. 4. 5. 6. 7. 8. Figure 6. Differential Clock Crosspoint Specification 650 Crossing Point (mV) 600 550 550 mV 500 450 550 + 0.5 (VHavg - 700) 400 250 + 0.5 (VHavg - 700) 350 300 250 250 mV 200 660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850 VHavg (mV) Datasheet 31 Electrical Specifications 2.9 PECI DC Specifications PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors (may also include chipset components in the future) and external thermal monitoring devices. The processor contains Digital Thermal Sensors (DTS) distributed throughout die. These sensors are implemented as analog-to-digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature. PECI provides an interface to relay the highest DTS temperature within a die to external management devices for thermal/ fan speed control. More detailed information is available in the Platform Environment Control Interface (PECI) Specification. Table 19. PECI DC Electrical Limits Symbol Vin Vhysteresis Definition and Conditions Units VTT - V Notes1 V 0.1 * VTT Hysteresis Max -0.15 Input Voltage Range Min 2 Vn Negative-edge threshold voltage 0.275 * VTT 0.500 * VTT V Vp Positive-edge threshold voltage 0.550 * VTT 0.762 * VTT V -6.0 N/A mA (VOL = 0.25 * VTT) 0.5 1.0 mA Ileak+ High impedance state leakage to VTT N/A 50 µA 3 Ileak- High impedance leakage to GND N/A 10 µA 3 Cbus Bus capacitance per node N/A 10 pF 4 0.1 * VTT - Vp-p Isource Isink Vnoise High level output source (VOH = 0.75 * VTT) Low level output sink Signal noise immunity above 300 MHz NOTES: 1. VTT supplies the PECI interface. PECI behavior does not affect VTT min/max specifications. Refer to Table 4 for VTT specifications. 2. The input buffers use a Schmitt-triggered input design for improved noise immunity. 3. The leakage specification applies to powered devices on the PECI bus. 4. One node is counted for each client and one node for the system host. Extended trace lengths might appear as additional nodes. §§ 32 Datasheet Package Mechanical Specifications 3 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for processor component thermal solutions, such as a heatsink. Figure 7 shows a sketch of the processor package components and how they are assembled together. Refer to the LGA775 LGA775 Socket Mechanical Design Guide for complete details on the LGA775 LGA775 socket. The package components shown in Figure 7 include the following: · · · · · Figure 7. Integrated Heat Spreader (IHS) Thermal Interface Material (TIM) Processor core (die) Package substrate Capacitors Processor Package Assembly Sketch Core (die) TIM IHS Substrate Capacitors LGA775 LGA775 Socket System Board Processor_Pkg_Assembly_775 NOTE: 1. Socket and system board are included for reference and are not part of processor package. 3.1 Package Mechanical Drawing The package mechanical drawings are shown in Figure 8 and Figure 9. The drawings include dimensions necessary to design a thermal solution for the processor. These dimensions include: · · · · · · · Datasheet Package reference with tolerances (total height, length, width, etc.) IHS parallelism and tilt Land dimensions Top-side and back-side component keep-out dimensions Reference datums All drawing dimensions are in mm [in]. Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and Mechanical Design Guidelines (see Section 1.2). 33 Package Mechanical Specifications Figure 8. 34 Processor Package Drawing Sheet 1 of 3 Datasheet Package Mechanical Specifications Figure 9. Datasheet Processor Package Drawing Sheet 2 of 3 35 Package Mechanical Specifications Figure 10. 36 Processor Package Drawing Sheet 3 of 3 Datasheet Package Mechanical Specifications 3.2 Processor Component Keep-Out Zones The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the topside or land-side of the package substrate. See Figure 8 and Figure 9 for keep-out zones. The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep-in. 3.3 Package Loading Specifications Table 20 provides dynamic and static load specifications for the processor package. These mechanical maximum load limits should not be exceeded during heatsink assembly, shipping conditions, or standard use condition. Also, any mechanical system or component testing should not exceed the maximum limits. The processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solution. The minimum loading specification must be maintained by any thermal and mechanical solutions. . Table 20. Processor Loading Specifications Parameter Minimum Maximum Notes Static 80 N [17 lbf] 311 N [70 lbf] 1, 2, 3 Dynamic - 756 N [170 lbf] 1, 3, 4 NOTES: 1. These specifications apply to uniform compressive loading in a direction normal to the processor IHS. 2. This is the maximum force that can be applied by a heatsink retention clip. The clip must also provide the minimum specified load on the processor package. 3. These specifications are based on limited testing for design characterization. Loading limits are for the package only and do not include the limits of the processor socket. 4. Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement. 3.4 Package Handling Guidelines Table 21 includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal. Table 21. Package Handling Guidelines Parameter Maximum Recommended Notes Shear 311 N [70 lbf] 1, 2 Tensile 111 N [25 lbf] 2, 3 Torque 3.95 N-m [35 lbf-in] 2, 4 NOTES: 1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface. 2. These guidelines are based on limited testing for design characterization. 3. A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface. 4. A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top surface. Datasheet 37 Package Mechanical Specifications 3.5 Package Insertion Specifications The processor can be inserted into and removed from a LGA775 LGA775 socket 15 times. The socket should meet the LGA775 LGA775 requirements detailed in the LGA775 LGA775 Socket Mechanical Design Guide. 3.6 Processor Mass Specification The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package. 3.7 Processor Materials Table 22 lists some of the package components and associated materials. Table 22. Processor Materials Component Material Integrated Heat Spreader (IHS) Fiber Reinforced Resin Substrate Lands 3.8 Nickel Plated Copper Substrate Gold Plated Copper Processor Markings Figure 11 shows the topside markings on the processors. This diagram aids in the identification of the processor. Figure 11. Processor Top-Side Markings Example INTEL M ©'05 E2160 E2160 PENTIUM® DUAL-CORE SLxxx [COO] 1.80GHZ/1M/800/06 80GHZ/1M/800/06 [FPO] e4 ATPO S/N 38 Datasheet Package Mechanical Specifications 3.9 Processor Land Coordinates Figure 12 shows the top view of the processor land coordinates. The coordinates are referred to throughout the document to identify processor lands. . Figure 12. Processor Land Coordinates and Quadrants, Top View VCC / VSS 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A AN AM AL AK AJ AH AG AF AE AD AC AB AA Y W V U T R P N M L K J H G F E D C B A Preliminary Socket 775 Quadrants Top View Address/ Common Clock/ Async 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 VTT / Clocks Data §§ Datasheet 39 Package Mechanical Specifications 40 Datasheet Land Listing and Signal Descriptions 4 Land Listing and Signal Descriptions This chapter provides the processor land assignment and signal descriptions. 4.1 Processor Land Assignments This section contains the land listings for the processor. The land-out footprint is shown in Figure 13 and Figure 14. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array (top view). Table 23 provides a list of processor lands ordered alphabetically by land (signal) name. Table 24 provides a list of processor lands ordered by land number. Datasheet 41 Land Listing and Signal Descriptions Figure 13. land-out Diagram (Top View ­ Left Side) 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AM VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AL VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AK VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AJ VSS VSS VSS VSS VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AH VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AG VCC VCC VCC VCC VCC VCC VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AF VSS VSS VSS VSS VSS VSS VSS VSS VCC VCC VSS VCC VCC VSS VSS VCC AE VSS VSS VSS VSS VSS VSS VSS VCC VCC VCC VSS VCC VCC VSS VSS VCC AD VCC VCC VCC VCC VCC VCC VCC VCC AC VCC VCC VCC VCC VCC VCC VCC VCC AB VSS VSS VSS VSS VSS VSS VSS VSS AA VSS VSS VSS VSS VSS VSS VSS VSS Y VCC VCC VCC VCC VCC VCC VCC VCC W VCC VCC VCC VCC VCC VCC VCC VCC AN V VSS VSS VSS VSS VSS VSS VSS VSS U VCC VCC VCC VCC VCC VCC VCC VCC T VCC VCC VCC VCC VCC VCC VCC VCC R VSS VSS VSS VSS VSS VSS VSS VSS P VSS VSS VSS VSS VSS VSS VSS VSS N VCC VCC VCC VCC VCC VCC VCC VCC M VCC VCC VCC VCC VCC VCC VCC VCC L VSS VSS VSS VSS VSS VSS VSS VSS K VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC FC34 FC31 VCC BSEL1 FC15 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS FC33 FC32 BSEL2 J H G BSEL0 BCLK1 TESTHI4 TESTHI5 TESTHI3 TESTHI6 RESET# D47# D44# DSTBN2# DSTBP2# D35# D36# D32# D31# F RSVD BCLK0 VTT_SEL TESTHI0 TESTHI2 TESTHI7 RSVD VSS D43# D41# VSS D38# D37# VSS D30# E FC26 VSS VSS VSS VSS FC10 RSVD D45# D42# VSS D40# D39# VSS D34# D33# VTT VTT VTT VTT VTT VSS VCCPLL D46# VSS D48# DBI2# VSS D49# RSVD VSS D VTT C VTT VTT VTT VTT VTT VSS VSS D58# DBI3# VSS D54# DSTBP3# VSS D51# B VTT VTT VTT VTT VTT VTT VSS VSSA D63# D59# VSS D60# D57# VSS D55# D53# A VTT VTT VTT VTT VTT VTT FC23 VCCA D62# VSS RSVD D61# VSS D56# DSTBN3# VSS 30 42 VTT VCCIO PLL 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Datasheet Land Listing and Signal Descriptions Figure 14. 14 13 land-out Diagram (Top View ­ Right Side) 12 11 10 9 8 7 6 5 4 3 2 1 VSS_MB_ REGULATION VCC_MB_ REGULATION VSS_ SENSE VCC_ SENSE VSS VSS AN AM VCC VSS VCC VCC VSS VCC VCC VID_SELE CT VCC VSS VCC VCC VSS VCC VCC VID7 FC40 VID6 VSS VID2 VID0 VSS VCC VSS VCC VCC VSS VCC VCC VSS VID3 VID1 VID5 VRDSEL PROCHOT# THERMDA AL VCC VSS VCC VCC VSS VCC VCC VSS FC8 VSS VID4 ITP_CLK0 VSS THERMDC AK VCC VSS VCC VCC VSS VCC VCC VSS A35# A34# VSS ITP_CLK1 BPM0# BPM1# AJ VCC VSS VCC VCC VSS VCC VCC VSS VSS A33# A32# VSS RSVD VSS AH VCC VSS VCC VCC VSS VCC VCC VSS A29# A31# A30# BPM5# BPM3# TRST# AG VCC VSS VCC VCC VSS VCC VCC VSS VSS A27# A28# VSS BPM4# TDO AF VCC VSS VCC VCC VSS VCC SKTOCC# VSS RSVD VSS RSVD FC18 VSS TCK AE VCC VSS A22# ADSTB1# VSS FC36 BPM2# TDI AD VCC VSS VSS A25# RSVD VSS DBR# TMS AC VCC VSS A17# A24# A26# FC37 IERR# VSS AB VCC VSS VSS A23# A21# VSS FC39 VTT_OUT_ RIGHT AA VCC VSS A19# VSS A20# FC17 VSS FC0 Y TESTHI1 TESTHI12/ TESTHI12/ FC44 MSID0 W VCC VSS A18# A16# VSS VCC VCC VSS VSS A14# A15# VSS RSVD MSID1 V VSS A10# A12# A13# FC30 FC29 FC28 U VCC VSS VSS A9# A11# VSS FC4 COMP1 T VCC VSS ADSTB0# VSS A8# FERR#/ PBE# VSS COMP3 R VCC VSS A4# RSVD VSS INIT# SMI# TESTHI11 TESTHI11 P VCC VSS VSS RSVD RSVD VSS IGNNE# PWRGOOD N VCC VSS REQ2# A5# A7# STPCLK# THERMTRIP# VSS M VCC VSS VSS A3# A6# VSS TESTHI13 TESTHI13 LINT1 L VCC VSS REQ3# VSS REQ0# A20M# VSS LINT0 K J VCC VCC VCC VCC VCC VCC VCC VSS REQ4# REQ1# VSS FC22 FC3 VTT_OUT_ LEFT VSS VSS VSS VSS VSS VSS VSS VSS VSS TESTHI10 TESTHI10 FC35 VSS GTLREF1 GTLREF0 D29# D27# DSTBN1# DBI1# FC38 D16# BPRI# DEFER# RSVD PECI TESTHI9/ FC43 TESTHI8/ FC42 COMP2 FC27 H G D28# VSS D24# D23# VSS D18# D17# VSS FC21 RS1# VSS BR0# FC5 F VSS D26# DSTBP1# VSS D21# D19# VSS RSVD RSVD FC20 HITM# TRDY# VSS E RSVD D25# VSS D15# D22# VSS D12# D20# VSS VSS HIT# VSS ADS# RSVD D52# VSS D14# D11# VSS FC38 DSTBN0# VSS D3# D1# VSS LOCK# BNR# DRDY# VSS VSS COMP8 D13# VSS D10# DSTBP0# VSS D6# D5# VSS D0# RS0# DBSY# D50# COMP0 VSS D9# D8# VSS DBI0# D7# VSS D4# D2# RS2# VSS 14 13 12 11 10 9 8 7 6 5 4 3 2 Datasheet D C B A 1 43 Land Listing and Signal Descriptions Table 23. Land Name Alphabetical Land Assignments Land Signal Buffer # Type Table 23. Direction Land Name Alphabetical Land Assignments Land Signal Buffer # Type Direction A3# L5 Source Synch Input/Output BNR# C2 Common Clock Input/Output A4# P6 Source Synch Input/Output BPM0# AJ2 Common Clock Input/Output A5# M5 Source Synch Input/Output BPM1# AJ1 Common Clock Input/Output A6# L4 Source Synch Input/Output BPM2# AD2 Common Clock Input/Output A7# M4 Source Synch Input/Output BPM3# AG2 Common Clock Input/Output A8# R4 Source Synch Input/Output BPM4# AF2 Common Clock Input/Output A9# T5 Source Synch Input/Output BPM5# AG3 A10# U6 Source Synch Input/Output BPRI# G8 Common Clock A11# T4 Source Synch Input/Output BR0# F3 Common Clock Input/Output A12# U5 Source Synch Input/Output BSEL0 G29 A13# U4 Source Synch Input/Output BSEL1 A14# V5 Source Synch Input/Output BSEL2 A15# V4 Source Synch Input/Output COMP0 A13 Power/Other Input A16# W5 Source Synch Input/Output COMP1 T1 Power/Other Input A17# AB6 Source Synch Input/Output COMP2 G2 Power/Other Input A18# W6 Source Synch Input/Output COMP3 R1 Power/Other Input A19# Y6 Source Synch Input/Output COMP8 B13 Power/Other Input A20# Y4 Source Synch Input/Output D0# B4 Source Synch Input/Output A20M# K3 Asynch CMOS A21# AA4 A22# A23# Input Common Clock Input/Output Input Power/Other Output H30 Power/Other Output G30 Power/Other Output D1# C5 Source Synch Input/Output Source Synch Input/Output D2# A4 Source Synch Input/Output AD6 Source Synch Input/Output D3# C6 Source Synch Input/Output AA5 Source Synch Input/Output D4# A5 Source Synch Input/Output A24# AB5 Source Synch Input/Output D5# B6 Source Synch Input/Output A25# AC5 Source Synch Input/Output D6# B7 Source Synch Input/Output A26# AB4 Source Synch Input/Output D7# A7 Source Synch Input/Output A27# AF5 Source Synch Input/Output D8# A10 Source Synch Input/Output A28# AF4 Source Synch Input/Output D9# A11 Source Synch Input/Output A29# AG6 Source Synch Input/Output D10# B10 Source Synch Input/Output A30# AG4 Source Synch Input/Output D11# C11 Source Synch Input/Output A31# AG5 Source Synch Input/Output D12# D8 Source Synch Input/Output A32# AH4 Source Synch Input/Output D13# B12 Source Synch Input/Output A33# AH5 Source Synch Input/Output D14# C12 Source Synch Input/Output A34# AJ5 Source Synch Input/Output D15# D11 Source Synch Input/Output A35# AJ6 Source Synch Input/Output D16# G9 Source Synch Input/Output ADS# Common Clock Input/Output D17# F8 Source Synch Input/Output R6 Source Synch Input/Output D18# F9 Source Synch Input/Output ADSTB1# AD5 Source Synch Input/Output D19# E9 Source Synch Input/Output BCLK0 F28 Clock Input D20# D7 Source Synch Input/Output BCLK1 44 D2 ADSTB0# G28 Clock Input D21# E10 Source Synch Input/Output Datasheet Land Listing and Signal Descriptions Table 23. Land Name Alphabetical Land Assignments Land Signal Buffer # Type Direction Table 23. Land Name Alphabetical Land Assignments Land Signal Buffer # Type Direction D22# D10 Source Synch Input/Output D61# A19 Source Synch Input/Output D23# F11 Source Synch Input/Output D62# A22 Source Synch Input/Output D24# F12 Source Synch Input/Output D63# B22 Source Synch Input/Output D25# D13 Source Synch Input/Output DBI0# A8 Source Synch Input/Output D26# E13 Source Synch Input/Output DBI1# G11 Source Synch Input/Output D27# G13 Source Synch Input/Output DBI2# D19 Source Synch Input/Output D28# F14 Source Synch Input/Output DBI3# C20 Source Synch Input/Output D29# G14 Source Synch Input/Output DBR# AC2 D30# F15 Source Synch Input/Output DBSY# B2 D31# G15 Source Synch Input/Output DEFER# G7 Common Clock D32# G16 Source Synch Input/Output DRDY# C1 Common Clock Input/Output D33# E15 Source Synch Input/Output DSTBN0# C8 Source Synch Input/Output D34# E16 Source Synch Input/Output DSTBN1# G12 Source Synch Input/Output D35# G18 Source Synch Input/Output DSTBN2# G20 Source Synch Input/Output D36# G17 Source Synch Input/Output DSTBN3# A16 Source Synch Input/Output D37# F17 Source Synch Input/Output DSTBP0# B9 Source Synch Input/Output D38# F18 Source Synch Input/Output DSTBP1# E12 Source Synch Input/Output D39# E18 Source Synch Input/Output DSTBP2# G19 Source Synch Input/Output D40# E19 Source Synch Input/Output DSTBP3# C17 Source Synch Input/Output Power/Other D41# F20 Source Synch Input/Output FC0 Y1 E21 Source Synch Input/Output FC3 J2 Input Power/Other D42# Power/Other D43# F21 Source Synch Input/Output FC4 T2 Power/Other D44# G21 Source Synch Input/Output FC5 F2 Power/Other D45# E22 Source Synch Input/Output FC8 AK6 Power/Other D46# D22 Source Synch Input/Output FC10 E24 Power/Other D47# G22 Source Synch Input/Output FC15 H29 Power/Other D48# D20 Source Synch Input/Output FC17 Y3 Power/Other D49# D17 Source Synch Input/Output FC18 AE3 Power/Other D50# A14 Source Synch Input/Output FC20 E5 Power/Other D51# C15 Source Synch Input/Output FC21 F6 Power/Other D52# C14 Source Synch Input/Output FC22 J3 Power/Other D53# B15 Source Synch Input/Output FC23 A24 Power/Other D54# C18 Source Synch Input/Output FC26 E29 Power/Other D55# B16 Source Synch Input/Output FC27 G1 Power/Other D56# A17 Source Synch Input/Output FC28 U1 Power/Other D57# B18 Source Synch Input/Output FC29 U2 Power/Other D58# C21 Source Synch Input/Output FC30 U3 Power/Other D59# B21 Source Synch Input/Output FC31 J16 Power/Other D60# Datasheet Output Common Clock Input/Output B19 Source Synch Input/Output FC32 H15 Power/Other 45 Land Listing and Signal Descriptions Table 23. Land Name Alphabetical Land Assignments Land Signal Buffer # Type Table 23. Direction Land Name Alphabetical Land Assignments Land Signal Buffer # Type FC33 H16 Power/Other RESERVED D16 FC34 J17 Power/Other RESERVED E23 FC35 H4 Power/Other RESERVED E6 FC36 AD3 Power/Other RESERVED E7 FC37 AB3 Power/Other RESERVED F23 FC38 G10 Power/Other RESERVED Direction F29 FC38 C9 Power/Other RESERVED G6 FC39 AA2 Power/Other RESERVED N4 FC40 AM6 Power/Other RESERVED N5 FERR#/PBE# R3 Asynch CMOS Output RESERVED P5 GTLREF0 H1 Power/Other Input RESERVED V2 GTLREF1 H2 Power/Other Input RESET# G23 Common Clock Input HIT# D4 Common Clock Input/Output RS0# B3 Common Clock Input HITM# E4 Common Clock Input/Output RS1# F5 Common Clock Input IERR# AB2 Asynch CMOS Output RS2# A3 Common Clock Input IGNNE# N2 Asynch CMOS Input SKTOCC# AE8 Power/Other Output INIT# P3 Asynch CMOS Input SMI# P2 Asynch CMOS Input ITP_CLK0 AK3 TAP Input STPCLK# M3 Asynch CMOS Input ITP_CLK1 AJ3 TAP Input TCK AE1 TAP Input LINT0 K1 Asynch CMOS Input TDI AD1 TAP Input Asynch CMOS Input LINT1 L1 LOCK# C3 MSID0 W1 Power/Other MSID1 V1 Power/Other Power/Other TDO AF1 TAP Output TESTHI0 F26 Power/Other Input Output TESTHI1 W3 Power/Other Input Output TESTHI10 TESTHI10 H5 Power/Other Input Input/Output TESTHI11 TESTHI11 P1 Power/Other Input Asynch CMOS Input/Output TESTHI12/ TESTHI12/ FC44 W2 Power/Other Input Common Clock Input/Output PECI G5 PROCHOT# AL2 PWRGOOD N1 Power/Other REQ0# K4 Source Synch Input/Output Input REQ1# Source Synch Input/Output M6 Source Synch Input/Output REQ3# K6 Source Synch Input/Output REQ4# J6 Source Synch Input/Output RESERVED A20 RESERVED AC4 RESERVED AE4 RESERVED AE6 RESERVED AH2 RESERVED D1 RESERVED 46 J5 REQ2# D14 TESTHI13 TESTHI13 L2 Power/Other Input TESTHI2 F25 Power/Other Input TESTHI3 G25 Power/Other Input TESTHI4 G27 Power/Other Input TESTHI5 G26 Power/Other Input TESTHI6 G24 Power/Other Input TESTHI7 F24 Power/Other Input TESTHI8/FC42 TESTHI8/FC42 G3 Power/Other Input Input TESTHI9/FC43 TESTHI9/FC43 G4 Power/Other THERMDA AL1 Power/Other THERMDC AK1 Power/Other THERMTRIP# M2 Asynch CMOS Output TMS AC1 TAP Input Datasheet Land Listing and Signal Descriptions Table 23. Land Name Alphabetical Land Assignments Land Signal Buffer # Type Table 23. Alphabetical Land Assignments Land Signal Buffer # Type Direction Land Name Common Clock Input VCC AF22 Power/Other Input TRDY# E3 TRST# AG1 TAP VCC AF8 Power/Other VCC AA8 Power/Other VCC AF9 Power/Other VCC AB8 Power/Other VCC AG11 Power/Other VCC AC23 Power/Other VCC AG12 Power/Other VCC AC24 Power/Other VCC AG14 Power/Other VCC AC25 Power/Other VCC AG15 Power/Other V