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HDB36-24-91SE-059 TE Connectivity Ltd BR AWY PL ASM visit Digikey
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E2 hdb3

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E1 HDB3

Abstract: pin diagram 14 demultiplexer data streams from the E2 intermediary stream. · If the LIU provides HDB3 decoding, NRZ data and , DHDNI DHHDB3C HDB3 Decoder Within the E2 and E3 standards, there are four extra bits used for , The SXT6234 E-Rate Multiplexer offers a simple and economic approach to building E1/E2, E2/E3 and E1 , , E2, and E3 specifications. The ITU-T was formerly known as the Consultive Committee for , Level Number System 1 E1 30 2.048 2 E2 120 8.448 3 E3 480 34.368
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SDB6234 E1 HDB3 pin diagram 14 demultiplexer multiplexing e1 frame to e3 frame HDB3 to nrz 16 line to 4 line coder multiplexer HDB3 E2 16-E1/E3 16E1/E3

LDB6234

Abstract: HDB3 LXT6234, E1/E2 Stage · If the tributary LIU does not perform HDB3 decoding, then the signals are routed , and clock to the LXT6234 1.7.4.2 LXT6234, E3/E2 Stage · If the LIU does not do HDB3 decoding , . 5 E2 Standard , . 9 1.7.2.2 LXT6234, E1/E2 Stage , .12 1.7.4.2 LXT6234, E3/E2 Stage
Intel
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AN9501 LDB6234 HDB3 HDB3 decoder E2 liu multiplexing demultiplexing e2 e3 multiplexing e2 frame e3

HDB3 E2

Abstract: multiplexing e1 frame to e3 frame Multiplexer/Demultiplexer SXT6234, E3/E2 STAGE · If the LIU does not do HDB3 decoding then the signals are , Tributary #1 Tributary #2 Tributary #3 Tributary #4 DHDNI DHHDB3C HDB3 Decoder Within the E2 , approach to building E1/E2, E2/E3 and E1/E3 multiplexers and demultiplexers. This application note , ) standardized the E1, E2, and E3 specifications. The ITU-T was formerly known as the Consultive Committee for , E2 120 8.448 3 E3 480 34.368 4 E4 1920 139.264 Speech 16
Level One Communications
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1 into 12 demultiplexer circuit diagram 1 into 16 demultiplexer circuit diagram using 1 i design 16 bit demultiplexer introduction crystal oscillator 8.448 1 into 4 demultiplexer circuit diagram HDB3 can use where

HDB3 AMI ENCODER DECODER

Abstract: multiplexing e1 frame to e3 frame Multiplexer can also serve as a five channel HDB3 coder and decoder. Applications n E1/E2 Multiplexer (2/8 , negative RZ data.) 5.1.2 LXT6234, E1/E2 Stage · The LXT6234 may interface with either HDB3 or , Multiplexer, stage E2/E3. 1. Datasheet If the HDB3 decoder is on the line interface unit (LIU). 17 , four E1 channels into an E2 frame; and the G.751 recommendation for multiplexing four E2 channels into an E3 frame. The LXT6234 E-Rate Multiplexer also encodes and decodes HDB3 zero suppression line
Intel
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LXT6234QE HDB3 AMI ENCODER DECODER Frame structure for Multiplexing of four E2 streams into E3 stream multiplexer 30 pin circuit diagram of 64-1 multiplexer intel 4e2 100-P

16 line to 4 line coder multiplexer

Abstract: Frame structure for Multiplexing of four E1 streams into E2 stream LXT6234 can also function as a stand alone five-channel HDB3 transcoder. E1/E2 Multiplexer (2/8 Mbit , HDB3 E1 E2 E3 4 4 DLNRZO[1:4] DLCO[1:4] DHNRZI Demultiplexer DHDMXC DNAT And , Stage LXT6234, E1/E2 Stage · The LXT6234 may interface with either HDB3 or non-HDB3 coded signals , into an E2 frame; and the G.751 recommendation for multiplexing four E2 channels into an E3 frame. The LXT6234 E-Rate Multiplexer also encodes and decodes HDB3 zero suppression line coding used on E1
Intel
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Frame structure for Multiplexing of four E1 streams into E2 stream LEVEL ONE COMMUNICATIONS E2 hdb3 mais E1 AMI HDB3 decoder 500E LXT305/332 PDS-6234-7/99-2

circuit diagram of 64-1 multiplexer

Abstract: E1 AMI HDB3 decoder ; formerly known as CCITT): G.742 recommendation for multiplexing four E1 channels into an E2 frame; and the G.751 recommendation for multiplexing four E2 channels into an E3 frame. The SXT6234 E-Rate Multiplexer also encodes and decodes HDB3 zero suppression line coding used on E1, E2, and E3 signals. The coder and decoder input/output pins are externally accessible, allowing either HDB3 or NRZ , HDB3 transcoder. E1/E2 Multiplexer (2/8 Mbit/s) E2/E3 Multiplexer (8/34 Mbit/s) E1/E3 Multiplexer
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multiplexer/14052B multiplexing demultiplexing e2

E1 HDB3

Abstract: 16 line to 4 line coder multiplexer .742 recommendation for multi plexi ng four E1 channel s into an E2 frame; and the G.751 recommendation for mul tiplexing four E2 channels into an E3 frame. The SXT6234 E-Rate Multi plexer al so encodes and decodes HDB3 zero suppression line coding used on E1, E2, and E3 signals. The coder and decoder input/output pins are external ly accessible, allowing either HDB3 or NRZ (non-return-to-zero) I/O to the mul tiplexer. The SXT6234 E-Rate Mul tiplexer can also serve as a five channel HDB3 coder and decoder. ·
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micron lable information multiplexor 2 inputs NOTES ON MULTIPLEXER nrz to hdb3 demul

aux-04

Abstract: LXT6234 can also function as a stand alone five-channel HDB3 transcoder. E1/E2 Multiplexer (2/8 Mbit , Glossary AIS AMI CCITT CODEC HDB3 El E2 E3 FIFO ITU NRZ PCB RZ 12 Alarm Indication , LXT6234, E1/E2 Stage â'¢ The LXT6234 may interface with either HDB3 or non-HDB3 coded signals. Data from , into an E2 frame; and the G.751 recommendation for multiplexing four E2 channels into an E3 frame. The LXT6234 E-Rate Multiplexer also encodes and decodes HDB3 zero suppression line coding used on E l
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aux-04

circuit diagram of 64-1 multiplexer

Abstract: 16 line to 4 line coder multiplexer SXT6234 can also function as a stand alone five-channel HDB3 transcoder. E1/E2 Multiplexer (2/8 Mbit , Side Block Diagram AIS AMI CCITT CODEC HDB3 E1 E2 E3 4 4 DLNRZO[1:4] DLCO[1:4 , four E1 channels into an E2 frame; and the G.751 recommendation for multiplexing four E2 channels into an E3 frame. The SXT6234 E-Rate Multiplexer also encodes and decodes HDB3 zero suppression line coding used on E1, E2, and E3 signals. The coder and decoder input/output pins are externally
Level One Communications
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SXT6234QE D-85774

HDB3 E2

Abstract: LDB6208 E2AIS and , E2NAT bits setting MU X RX CH1 RX CH1 IN HDB3 ENC E2 Tx Ch1 AUX in Ch2 AUX in Ch3 AUX in Ch4 AUX in ME2AIS in ME2NAT in JP6 E2 Input & Output LXT332 HDB3 , Cable HDB3 DEC E2 Rx JP5 AUX Channel, E2AIS and E2NAT bits out monitors 1.2 E12 , circuit and includes all supporting circuitry for E1 and E2 multiplexer/ demultiplexer applications. The , input and output signals. JP1 is for E1 I/O and JP6 is for E2 I/O. JP4 is for Local Loop Back and
Intel
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LDB6208 74F74 74HC14 HEADER14P LXT332QE XR5683 e2 mux IC 74HC14 DATA SHEET 2048KH SOIC-14 8448KH

HD b3c

Abstract: DLC12 ): G .742 recom m endation for m ultiplexing four E l channels into an E2 fram e; and the G.751 recom m endation for m ultiplexing four E2 chan nels into an E3 frame. The SX T6234 E-Rate M ultiplexer also encodes and decodes HDB3 zero suppression line coding used on E l, E2, and E3 signals. The coder and decoder input/output pins are externally accessible, allow ing either HDB3 or N RZ (non-return-to-zero) I , SX T 6234 can also function as a stand alone five-channel HDB3 transcoder. E1/E2 M ultiplexer (2/8
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HD b3c DLC12 11DB3 mc 3375 XT6234 SXT6234QC T305/332 S-T6234-0496-5K

PV 1153

Abstract: I2864 he N R Z data is sent to a tributary o f th e E -R ate M ultiplexer, stage E2/E3. 1. If the HDB3 , ITU or for proprietary use. Five independent HDB3 C O D E C s allow M ultiplexer I/O in either H D B3 or N R Z form ats. T he SX T6234 can also function as a stand alone five-channel HDB3 transcoder , ultiplexing four E l channels into an E2 fram e; and the G.751 recom m endation for m ultiplexing four E2 , suppression line coding used on E l, E2, and E3 signals. T he coder and decoder input/ output pins are
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PV 1153 I2864 DLDP02 z04 e3 C55D DS-SXT6234-0296-1K

HD b3c

Abstract: ): G.742 recommendation for multiplexing four E l channels into an E2 frame; and the G.751 recommendation for multiplexing four E2 chan­ nels into an E3 frame. The SXT6234 E-Rate Multiplexer also encodes and decodes H D B3 zero suppression line coding used on E l, E2, and E3 signals. The coder and , D B3 or N R Z formats. The SXT6234 can also function as a stand alone five-channel HDB3 transcoder. Applications NOTE â'¢ E1/E2 Multiplexer (2/8 Mbit/s) â'¢ E2/E3 Multiplexer (8/34 Mbit/s) The SXT6234 w
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EFB7446

Abstract: HDB3 E2 - input E2 16 Receive HDB3 + input IN 5 Inhibition input BE 6 Transmission Binary input BB 8 Binary loop input HE 7 Transmission clock input HRG 14 Regenerated clock input SI 3 Transmission HDB3 , voltage ±5 V. â'¢ Low power CMOS. BLOCK DIAGRAM BINARY DATA- INHIBITION . TRANSMISSION CODER HDB3 + - HDB3 - _ SAMPLING CLOCK BINARY LOOPING - RECEPTION |,2|-DECODER REGENERATED CLOCK BINARY DATA , SUFFIX PLASTIC PACKAGE PIN ASSIGNMENT VDD C 3 E2 HD C 2 15 3 El S1 C 3 14 3 HRG S2 C 4 13 D ER
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EFB7446 binary coder HDB3 coding Thomson ceramic capacitor CB-79 240780F MO//30

G753

Abstract: g745 .753 (34368 kbit/s) · Line side interface: - Rail or NRZ · HDB3 codec for rail I/O The E2/E3F can be , is clocked into the E2/E3F on negative transitions of the clock signal RCK/RCKL. The HDB3 codec for , Leased Circuits. An optional HDB3 codec is provided for the two CCITT line rates. TXC-21037, E2/E3F-MRT , E2/E3F Device 8-, 34 Mbit/s Framer TXC-03701 DATA SHEET FEATURES DESCRIPTION The E2/E3 Framer (E2/E3F) is a CMOS VLSI device that provides the functions needed to frame a wideband payload to
TranSwitch
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G753 g745 RS-232

XT305

Abstract: IT T); G .742 recom m endation for m ultiplexing four E l channels into an E2 fram e; and the G.751 recom m endation for m ultiplexing four E2 channels into an E3 fram e. T he SX T6234 E -R ate M ultiplexer also encodes and d ecodes H DB3 zero suppression line coding used on E l, E2, and E3 signals. T he , or for p ro p ri etary use. Five independent HDB3 C O D E C s allow M ultiplexer I/O in either H D B , Clocks Loss Of Signal (LOS) Service Channels / AIS HDB3 Data input Clock 4 Tributary NRZ Data Inputs 4
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XT305
Abstract: ® MT90732 CMOS E2/E3 Framer (E2/E3F) Advance Information Features · Framer for CCITT , side interface - Dual rail or NRZ HDB3 codec for dual rail I/O Terminal side interface - , +85°C Description The MT90732 E2/E3 Framer (E2/E3F) is a CMOS VLSI device that provides the , .753. The E2/E3 Framer interfaces to line circuitry with either dual rail or NRZ signals. On the terminal , without a microprocessor. When interfaced with a microprocessor, the E2/E3 Framer provides an 8byte memory Zarlink Semiconductor
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MT90732AP

HDB3 E2

Abstract: nrz to hdb3 MT90732 CMOS E2/E3 Framer (E2/E3F) ® Advance Information Features · · · · · · , .751 (34368 kbit/s) - G.753 (34368 kbit/s) Line side interface - Dual rail or NRZ HDB3 codec for dual rail , 68 Pin PLCC -40°C to +85°C Description The MT90732 E2/E3 Framer (E2/E3F) is a CMOS VLSI device , . G.742, G.745, G.751, or G.753. The E2/E3 Framer interfaces to line circuitry with either dual rail , E2/E3 Framer provides an 8byte memory map for control, performance counters and alarm status. The
Zarlink Semiconductor
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HDB3 to nrz e2

e2 framer g742

Abstract: http://products.zarlink.com/obsolete_products/ ® MT90732 CMOS E2/E3 Framer (E2/E3F) Advance , .751 (34368 kbit/s) - G.753 (34368 kbit/s) Line side interface - Dual rail or NRZ HDB3 codec for dual rail I/O , MT90732AP 68 Pin PLCC -40°C to +85°C Description The MT90732 E2/E3 Framer (E2/E3F) is a CMOS VLSI device , .742, G.745, G.751, or G.753. The E2/E3 Framer interfaces to line circuitry with either dual rail or NRZ , be operated with or without a microprocessor. When interfaced with a microprocessor, the E2/E3 Framer
Mitel Semiconductor
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e2 framer g742

G753

Abstract: 0 Features · M ITEL CMOS MT90732 E2/E3 Framer (E2/E3F) Advance Information , or NRZ HDB3 codec for dual rail I/O Terminal side interface - Nibble-parallel - Bit-serial Transmit , rdering Info rm a tio n MT90732AP 68 Pin PLCC -40°C to +85°C D escrip tion The MT90732 E2/E3 Framer (E2/E3F) is a CMOS VLSI device that provides the functions needed to frame a wideband payload to one of four CCITT Recommendations. G.742, G.745, G.751, or G.753. The E2/E3 Framer interfaces to line
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